1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // CS42L43 SPI Controller Driver
4 //
5 // Copyright (C) 2022-2023 Cirrus Logic, Inc. and
6 // Cirrus Logic International Semiconductor Ltd.
7
8 #include <linux/acpi.h>
9 #include <linux/array_size.h>
10 #include <linux/bits.h>
11 #include <linux/bitfield.h>
12 #include <linux/cleanup.h>
13 #include <linux/device.h>
14 #include <linux/errno.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/gpio/machine.h>
17 #include <linux/gpio/property.h>
18 #include <linux/mfd/cs42l43.h>
19 #include <linux/mfd/cs42l43-regs.h>
20 #include <linux/module.h>
21 #include <linux/of.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/property.h>
25 #include <linux/regmap.h>
26 #include <linux/spi/spi.h>
27 #include <linux/units.h>
28
29 #define CS42L43_FIFO_SIZE 16
30 #define CS42L43_SPI_ROOT_HZ 49152000
31 #define CS42L43_SPI_MAX_LENGTH 65532
32
33 enum cs42l43_spi_cmd {
34 CS42L43_WRITE,
35 CS42L43_READ
36 };
37
38 struct cs42l43_spi {
39 struct device *dev;
40 struct regmap *regmap;
41 struct spi_controller *ctlr;
42 };
43
44 static const unsigned int cs42l43_clock_divs[] = {
45 2, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
46 };
47
48 static struct spi_board_info amp_info_template = {
49 .modalias = "cs35l56",
50 .max_speed_hz = 11 * HZ_PER_MHZ,
51 .mode = SPI_MODE_0,
52 };
53
cs42l43_spi_tx(struct regmap * regmap,const u8 * buf,unsigned int len)54 static int cs42l43_spi_tx(struct regmap *regmap, const u8 *buf, unsigned int len)
55 {
56 const u8 *end = buf + len;
57 u32 val = 0;
58 int ret;
59
60 while (buf < end) {
61 const u8 *block = min(buf + CS42L43_FIFO_SIZE, end);
62
63 while (buf < block) {
64 const u8 *word = min(buf + sizeof(u32), block);
65 int pad = (buf + sizeof(u32)) - word;
66
67 while (buf < word) {
68 val >>= BITS_PER_BYTE;
69 val |= FIELD_PREP(GENMASK(31, 24), *buf);
70
71 buf++;
72 }
73
74 val >>= pad * BITS_PER_BYTE;
75
76 regmap_write(regmap, CS42L43_TX_DATA, val);
77 }
78
79 regmap_write(regmap, CS42L43_TRAN_CONFIG8, CS42L43_SPI_TX_DONE_MASK);
80
81 ret = regmap_read_poll_timeout(regmap, CS42L43_TRAN_STATUS1,
82 val, (val & CS42L43_SPI_TX_REQUEST_MASK),
83 1000, 5000);
84 if (ret)
85 return ret;
86 }
87
88 return 0;
89 }
90
cs42l43_spi_rx(struct regmap * regmap,u8 * buf,unsigned int len)91 static int cs42l43_spi_rx(struct regmap *regmap, u8 *buf, unsigned int len)
92 {
93 u8 *end = buf + len;
94 u32 val;
95 int ret;
96
97 while (buf < end) {
98 u8 *block = min(buf + CS42L43_FIFO_SIZE, end);
99
100 ret = regmap_read_poll_timeout(regmap, CS42L43_TRAN_STATUS1,
101 val, (val & CS42L43_SPI_RX_REQUEST_MASK),
102 1000, 5000);
103 if (ret)
104 return ret;
105
106 while (buf < block) {
107 u8 *word = min(buf + sizeof(u32), block);
108
109 ret = regmap_read(regmap, CS42L43_RX_DATA, &val);
110 if (ret)
111 return ret;
112
113 while (buf < word) {
114 *buf = FIELD_GET(GENMASK(7, 0), val);
115
116 val >>= BITS_PER_BYTE;
117 buf++;
118 }
119 }
120
121 regmap_write(regmap, CS42L43_TRAN_CONFIG8, CS42L43_SPI_RX_DONE_MASK);
122 }
123
124 return 0;
125 }
126
cs42l43_transfer_one(struct spi_controller * ctlr,struct spi_device * spi,struct spi_transfer * tfr)127 static int cs42l43_transfer_one(struct spi_controller *ctlr, struct spi_device *spi,
128 struct spi_transfer *tfr)
129 {
130 struct cs42l43_spi *priv = spi_controller_get_devdata(spi->controller);
131 int i, ret = -EINVAL;
132
133 for (i = 0; i < ARRAY_SIZE(cs42l43_clock_divs); i++) {
134 if (CS42L43_SPI_ROOT_HZ / cs42l43_clock_divs[i] <= tfr->speed_hz)
135 break;
136 }
137
138 if (i == ARRAY_SIZE(cs42l43_clock_divs))
139 return -EINVAL;
140
141 regmap_write(priv->regmap, CS42L43_SPI_CLK_CONFIG1, i);
142
143 if (tfr->tx_buf) {
144 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG3, CS42L43_WRITE);
145 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG4, tfr->len - 1);
146 } else if (tfr->rx_buf) {
147 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG3, CS42L43_READ);
148 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG5, tfr->len - 1);
149 }
150
151 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG1, CS42L43_SPI_START_MASK);
152
153 if (tfr->tx_buf)
154 ret = cs42l43_spi_tx(priv->regmap, (const u8 *)tfr->tx_buf, tfr->len);
155 else if (tfr->rx_buf)
156 ret = cs42l43_spi_rx(priv->regmap, (u8 *)tfr->rx_buf, tfr->len);
157
158 return ret;
159 }
160
cs42l43_set_cs(struct spi_device * spi,bool is_high)161 static void cs42l43_set_cs(struct spi_device *spi, bool is_high)
162 {
163 struct cs42l43_spi *priv = spi_controller_get_devdata(spi->controller);
164
165 regmap_write(priv->regmap, CS42L43_SPI_CONFIG2, !is_high);
166 }
167
cs42l43_prepare_message(struct spi_controller * ctlr,struct spi_message * msg)168 static int cs42l43_prepare_message(struct spi_controller *ctlr, struct spi_message *msg)
169 {
170 struct cs42l43_spi *priv = spi_controller_get_devdata(ctlr);
171 struct spi_device *spi = msg->spi;
172 unsigned int spi_config1 = 0;
173
174 /* select another internal CS, which doesn't exist, so CS 0 is not used */
175 if (spi_get_csgpiod(spi, 0))
176 spi_config1 |= 1 << CS42L43_SPI_SS_SEL_SHIFT;
177 if (spi->mode & SPI_CPOL)
178 spi_config1 |= CS42L43_SPI_CPOL_MASK;
179 if (spi->mode & SPI_CPHA)
180 spi_config1 |= CS42L43_SPI_CPHA_MASK;
181 if (spi->mode & SPI_3WIRE)
182 spi_config1 |= CS42L43_SPI_THREE_WIRE_MASK;
183
184 regmap_write(priv->regmap, CS42L43_SPI_CONFIG1, spi_config1);
185
186 return 0;
187 }
188
cs42l43_prepare_transfer_hardware(struct spi_controller * ctlr)189 static int cs42l43_prepare_transfer_hardware(struct spi_controller *ctlr)
190 {
191 struct cs42l43_spi *priv = spi_controller_get_devdata(ctlr);
192 int ret;
193
194 ret = regmap_write(priv->regmap, CS42L43_BLOCK_EN2, CS42L43_SPI_MSTR_EN_MASK);
195 if (ret)
196 dev_err(priv->dev, "Failed to enable SPI controller: %d\n", ret);
197
198 return ret;
199 }
200
cs42l43_unprepare_transfer_hardware(struct spi_controller * ctlr)201 static int cs42l43_unprepare_transfer_hardware(struct spi_controller *ctlr)
202 {
203 struct cs42l43_spi *priv = spi_controller_get_devdata(ctlr);
204 int ret;
205
206 ret = regmap_write(priv->regmap, CS42L43_BLOCK_EN2, 0);
207 if (ret)
208 dev_err(priv->dev, "Failed to disable SPI controller: %d\n", ret);
209
210 return ret;
211 }
212
cs42l43_spi_max_length(struct spi_device * spi)213 static size_t cs42l43_spi_max_length(struct spi_device *spi)
214 {
215 return CS42L43_SPI_MAX_LENGTH;
216 }
217
cs42l43_get_speaker_id_gpios(struct cs42l43_spi * priv,int * result)218 static int cs42l43_get_speaker_id_gpios(struct cs42l43_spi *priv, int *result)
219 {
220 struct gpio_descs *descs;
221 u32 spkid;
222 int i, ret;
223
224 descs = gpiod_get_array_optional(priv->dev, "spk-id", GPIOD_IN);
225 if (!descs)
226 return 0;
227 else if (IS_ERR(descs))
228 return PTR_ERR(descs);
229
230 spkid = 0;
231 for (i = 0; i < descs->ndescs; i++) {
232 ret = gpiod_get_value_cansleep(descs->desc[i]);
233 if (ret < 0)
234 goto err;
235
236 spkid |= (ret << i);
237 }
238
239 dev_dbg(priv->dev, "spk-id-gpios = %d\n", spkid);
240 *result = spkid;
241 err:
242 gpiod_put_array(descs);
243
244 return ret;
245 }
246
cs42l43_find_xu_node(struct fwnode_handle * fwnode)247 static struct fwnode_handle *cs42l43_find_xu_node(struct fwnode_handle *fwnode)
248 {
249 static const u32 func_smart_amp = 0x1;
250 struct fwnode_handle *child_fwnode, *ext_fwnode;
251 u32 function;
252 int ret;
253
254 fwnode_for_each_child_node(fwnode, child_fwnode) {
255 acpi_handle handle = ACPI_HANDLE_FWNODE(child_fwnode);
256
257 ret = acpi_get_local_address(handle, &function);
258 if (ret || function != func_smart_amp)
259 continue;
260
261 ext_fwnode = fwnode_get_named_child_node(child_fwnode,
262 "mipi-sdca-function-expansion-subproperties");
263 if (!ext_fwnode)
264 continue;
265
266 fwnode_handle_put(child_fwnode);
267
268 return ext_fwnode;
269 }
270
271 return NULL;
272 }
273
cs42l43_create_bridge_amp(struct cs42l43_spi * priv,const char * const name,int cs,int spkid)274 static struct spi_board_info *cs42l43_create_bridge_amp(struct cs42l43_spi *priv,
275 const char * const name,
276 int cs, int spkid)
277 {
278 struct property_entry *props = NULL;
279 struct software_node *swnode;
280 struct spi_board_info *info;
281
282 if (spkid >= 0) {
283 props = devm_kcalloc(priv->dev, 2, sizeof(*props), GFP_KERNEL);
284 if (!props)
285 return NULL;
286
287 *props = PROPERTY_ENTRY_U32("cirrus,speaker-id", spkid);
288 }
289
290 swnode = devm_kmalloc(priv->dev, sizeof(*swnode), GFP_KERNEL);
291 if (!swnode)
292 return NULL;
293
294 *swnode = SOFTWARE_NODE(name, props, NULL);
295
296 info = devm_kmemdup(priv->dev, &_info_template,
297 sizeof(amp_info_template), GFP_KERNEL);
298 if (!info)
299 return NULL;
300
301 info->chip_select = cs;
302 info->swnode = swnode;
303
304 return info;
305 }
306
cs42l43_release_of_node(void * data)307 static void cs42l43_release_of_node(void *data)
308 {
309 fwnode_handle_put(data);
310 }
311
cs42l43_spi_probe(struct platform_device * pdev)312 static int cs42l43_spi_probe(struct platform_device *pdev)
313 {
314 struct cs42l43 *cs42l43 = dev_get_drvdata(pdev->dev.parent);
315 struct cs42l43_spi *priv;
316 struct fwnode_handle *fwnode = dev_fwnode(cs42l43->dev);
317 struct fwnode_handle *xu_fwnode __free(fwnode_handle) = cs42l43_find_xu_node(fwnode);
318 int nsidecars = 0;
319 int spkid = -EINVAL;
320 int ret;
321
322 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
323 if (!priv)
324 return -ENOMEM;
325
326 priv->ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*priv->ctlr));
327 if (!priv->ctlr)
328 return -ENOMEM;
329
330 spi_controller_set_devdata(priv->ctlr, priv);
331
332 priv->dev = &pdev->dev;
333 priv->regmap = cs42l43->regmap;
334
335 priv->ctlr->prepare_message = cs42l43_prepare_message;
336 priv->ctlr->prepare_transfer_hardware = cs42l43_prepare_transfer_hardware;
337 priv->ctlr->unprepare_transfer_hardware = cs42l43_unprepare_transfer_hardware;
338 priv->ctlr->transfer_one = cs42l43_transfer_one;
339 priv->ctlr->set_cs = cs42l43_set_cs;
340 priv->ctlr->max_transfer_size = cs42l43_spi_max_length;
341 priv->ctlr->mode_bits = SPI_3WIRE | SPI_MODE_X_MASK;
342 priv->ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX;
343 priv->ctlr->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
344 SPI_BPW_MASK(32);
345 priv->ctlr->min_speed_hz = CS42L43_SPI_ROOT_HZ /
346 cs42l43_clock_divs[ARRAY_SIZE(cs42l43_clock_divs) - 1];
347 priv->ctlr->max_speed_hz = CS42L43_SPI_ROOT_HZ / cs42l43_clock_divs[0];
348 priv->ctlr->use_gpio_descriptors = true;
349 priv->ctlr->auto_runtime_pm = true;
350
351 ret = devm_pm_runtime_enable(priv->dev);
352 if (ret)
353 return ret;
354
355 pm_runtime_idle(priv->dev);
356
357 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG6, CS42L43_FIFO_SIZE - 1);
358 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG7, CS42L43_FIFO_SIZE - 1);
359
360 // Disable Watchdog timer and enable stall
361 regmap_write(priv->regmap, CS42L43_SPI_CONFIG3, 0);
362 regmap_write(priv->regmap, CS42L43_SPI_CONFIG4, CS42L43_SPI_STALL_ENA_MASK);
363
364 if (is_of_node(fwnode)) {
365 fwnode = fwnode_get_named_child_node(fwnode, "spi");
366 ret = devm_add_action_or_reset(priv->dev, cs42l43_release_of_node, fwnode);
367 if (ret)
368 return ret;
369 } else {
370 fwnode_property_read_u32(xu_fwnode, "01fa-sidecar-instances", &nsidecars);
371 }
372
373 /*
374 * Depending on the value of nsidecars we either create a software node
375 * or assign an fwnode. We don't want software node to be attached to
376 * the default one. That's why we need to clear the SPI controller fwnode
377 * first.
378 */
379 device_set_node(&priv->ctlr->dev, NULL);
380
381 if (nsidecars) {
382 struct software_node_ref_args args[] = {
383 SOFTWARE_NODE_REFERENCE(fwnode, 0, GPIO_ACTIVE_LOW),
384 SOFTWARE_NODE_REFERENCE(&swnode_gpio_undefined),
385 };
386 struct property_entry props[] = {
387 PROPERTY_ENTRY_REF_ARRAY("cs-gpios", args),
388 { }
389 };
390
391 ret = fwnode_property_read_u32(xu_fwnode, "01fa-spk-id-val", &spkid);
392 if (!ret) {
393 dev_dbg(priv->dev, "01fa-spk-id-val = %d\n", spkid);
394 } else if (ret != -EINVAL) {
395 return dev_err_probe(priv->dev, ret, "Failed to get spk-id-val\n");
396 } else {
397 ret = cs42l43_get_speaker_id_gpios(priv, &spkid);
398 if (ret < 0)
399 return dev_err_probe(priv->dev, ret,
400 "Failed to get spk-id-gpios\n");
401 }
402
403 ret = device_create_managed_software_node(&priv->ctlr->dev, props, NULL);
404 if (ret)
405 return dev_err_probe(priv->dev, ret, "Failed to add swnode\n");
406 } else {
407 device_set_node(&priv->ctlr->dev, fwnode);
408 }
409
410 ret = devm_spi_register_controller(priv->dev, priv->ctlr);
411 if (ret)
412 return dev_err_probe(priv->dev, ret,
413 "Failed to register SPI controller\n");
414
415 if (nsidecars) {
416 struct spi_board_info *ampl_info;
417 struct spi_board_info *ampr_info;
418
419 ampl_info = cs42l43_create_bridge_amp(priv, "cs35l56-left", 0, spkid);
420 if (!ampl_info)
421 return -ENOMEM;
422
423 ampr_info = cs42l43_create_bridge_amp(priv, "cs35l56-right", 1, spkid);
424 if (!ampr_info)
425 return -ENOMEM;
426
427 if (!spi_new_device(priv->ctlr, ampl_info))
428 return dev_err_probe(priv->dev, -ENODEV,
429 "Failed to create left amp slave\n");
430
431 if (!spi_new_device(priv->ctlr, ampr_info))
432 return dev_err_probe(priv->dev, -ENODEV,
433 "Failed to create right amp slave\n");
434 }
435
436 return 0;
437 }
438
439 static const struct platform_device_id cs42l43_spi_id_table[] = {
440 { .name = "cs42l43-spi" },
441 { }
442 };
443 MODULE_DEVICE_TABLE(platform, cs42l43_spi_id_table);
444
445 static struct platform_driver cs42l43_spi_driver = {
446 .driver = {
447 .name = "cs42l43-spi",
448 },
449 .probe = cs42l43_spi_probe,
450 .id_table = cs42l43_spi_id_table,
451 };
452 module_platform_driver(cs42l43_spi_driver);
453
454 MODULE_IMPORT_NS("GPIO_SWNODE");
455 MODULE_DESCRIPTION("CS42L43 SPI Driver");
456 MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>");
457 MODULE_AUTHOR("Maciej Strozek <mstrozek@opensource.cirrus.com>");
458 MODULE_LICENSE("GPL");
459