1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * HiSilicon SoC MN uncore Hardware event counters support
4 *
5 * Copyright (c) 2025 HiSilicon Technologies Co., Ltd.
6 */
7 #include <linux/cpuhotplug.h>
8 #include <linux/interrupt.h>
9 #include <linux/iopoll.h>
10 #include <linux/irq.h>
11 #include <linux/list.h>
12 #include <linux/property.h>
13
14 #include "hisi_uncore_pmu.h"
15
16 /* Dynamic CPU hotplug state used by MN PMU */
17 static enum cpuhp_state hisi_mn_pmu_online;
18
19 /* MN register definition */
20 #define HISI_MN_DYNAMIC_CTRL_REG 0x400
21 #define HISI_MN_DYNAMIC_CTRL_EN BIT(0)
22 #define HISI_MN_PERF_CTRL_REG 0x408
23 #define HISI_MN_PERF_CTRL_EN BIT(6)
24 #define HISI_MN_INT_MASK_REG 0x800
25 #define HISI_MN_INT_STATUS_REG 0x808
26 #define HISI_MN_INT_CLEAR_REG 0x80C
27 #define HISI_MN_EVENT_CTRL_REG 0x1C00
28 #define HISI_MN_VERSION_REG 0x1C04
29 #define HISI_MN_EVTYPE0_REG 0x1d00
30 #define HISI_MN_EVTYPE_MASK GENMASK(7, 0)
31 #define HISI_MN_CNTR0_REG 0x1e00
32 #define HISI_MN_EVTYPE_REGn(evtype0, n) ((evtype0) + (n) * 4)
33 #define HISI_MN_CNTR_REGn(cntr0, n) ((cntr0) + (n) * 8)
34
35 #define HISI_MN_NR_COUNTERS 4
36 #define HISI_MN_TIMEOUT_US 500U
37
38 struct hisi_mn_pmu_regs {
39 u32 version;
40 u32 dyn_ctrl;
41 u32 perf_ctrl;
42 u32 int_mask;
43 u32 int_clear;
44 u32 int_status;
45 u32 event_ctrl;
46 u32 event_type0;
47 u32 event_cntr0;
48 };
49
50 /*
51 * Each event request takes a certain amount of time to complete. If
52 * we counting the latency related event, we need to wait for the all
53 * requests complete. Otherwise, the value of counter is slightly larger.
54 */
hisi_mn_pmu_counter_flush(struct hisi_pmu * mn_pmu)55 static void hisi_mn_pmu_counter_flush(struct hisi_pmu *mn_pmu)
56 {
57 struct hisi_mn_pmu_regs *reg_info = mn_pmu->dev_info->private;
58 int ret;
59 u32 val;
60
61 val = readl(mn_pmu->base + reg_info->dyn_ctrl);
62 val |= HISI_MN_DYNAMIC_CTRL_EN;
63 writel(val, mn_pmu->base + reg_info->dyn_ctrl);
64
65 ret = readl_poll_timeout_atomic(mn_pmu->base + reg_info->dyn_ctrl,
66 val, !(val & HISI_MN_DYNAMIC_CTRL_EN),
67 1, HISI_MN_TIMEOUT_US);
68 if (ret)
69 dev_warn(mn_pmu->dev, "Counter flush timeout\n");
70 }
71
hisi_mn_pmu_read_counter(struct hisi_pmu * mn_pmu,struct hw_perf_event * hwc)72 static u64 hisi_mn_pmu_read_counter(struct hisi_pmu *mn_pmu,
73 struct hw_perf_event *hwc)
74 {
75 struct hisi_mn_pmu_regs *reg_info = mn_pmu->dev_info->private;
76
77 return readq(mn_pmu->base + HISI_MN_CNTR_REGn(reg_info->event_cntr0, hwc->idx));
78 }
79
hisi_mn_pmu_write_counter(struct hisi_pmu * mn_pmu,struct hw_perf_event * hwc,u64 val)80 static void hisi_mn_pmu_write_counter(struct hisi_pmu *mn_pmu,
81 struct hw_perf_event *hwc, u64 val)
82 {
83 struct hisi_mn_pmu_regs *reg_info = mn_pmu->dev_info->private;
84
85 writeq(val, mn_pmu->base + HISI_MN_CNTR_REGn(reg_info->event_cntr0, hwc->idx));
86 }
87
hisi_mn_pmu_write_evtype(struct hisi_pmu * mn_pmu,int idx,u32 type)88 static void hisi_mn_pmu_write_evtype(struct hisi_pmu *mn_pmu, int idx, u32 type)
89 {
90 struct hisi_mn_pmu_regs *reg_info = mn_pmu->dev_info->private;
91 u32 val;
92
93 /*
94 * Select the appropriate event select register.
95 * There are 2 32-bit event select registers for the
96 * 8 hardware counters, each event code is 8-bit wide.
97 */
98 val = readl(mn_pmu->base + HISI_MN_EVTYPE_REGn(reg_info->event_type0, idx / 4));
99 val &= ~(HISI_MN_EVTYPE_MASK << HISI_PMU_EVTYPE_SHIFT(idx));
100 val |= (type << HISI_PMU_EVTYPE_SHIFT(idx));
101 writel(val, mn_pmu->base + HISI_MN_EVTYPE_REGn(reg_info->event_type0, idx / 4));
102 }
103
hisi_mn_pmu_start_counters(struct hisi_pmu * mn_pmu)104 static void hisi_mn_pmu_start_counters(struct hisi_pmu *mn_pmu)
105 {
106 struct hisi_mn_pmu_regs *reg_info = mn_pmu->dev_info->private;
107 u32 val;
108
109 val = readl(mn_pmu->base + reg_info->perf_ctrl);
110 val |= HISI_MN_PERF_CTRL_EN;
111 writel(val, mn_pmu->base + reg_info->perf_ctrl);
112 }
113
hisi_mn_pmu_stop_counters(struct hisi_pmu * mn_pmu)114 static void hisi_mn_pmu_stop_counters(struct hisi_pmu *mn_pmu)
115 {
116 struct hisi_mn_pmu_regs *reg_info = mn_pmu->dev_info->private;
117 u32 val;
118
119 val = readl(mn_pmu->base + reg_info->perf_ctrl);
120 val &= ~HISI_MN_PERF_CTRL_EN;
121 writel(val, mn_pmu->base + reg_info->perf_ctrl);
122
123 hisi_mn_pmu_counter_flush(mn_pmu);
124 }
125
hisi_mn_pmu_enable_counter(struct hisi_pmu * mn_pmu,struct hw_perf_event * hwc)126 static void hisi_mn_pmu_enable_counter(struct hisi_pmu *mn_pmu,
127 struct hw_perf_event *hwc)
128 {
129 struct hisi_mn_pmu_regs *reg_info = mn_pmu->dev_info->private;
130 u32 val;
131
132 val = readl(mn_pmu->base + reg_info->event_ctrl);
133 val |= BIT(hwc->idx);
134 writel(val, mn_pmu->base + reg_info->event_ctrl);
135 }
136
hisi_mn_pmu_disable_counter(struct hisi_pmu * mn_pmu,struct hw_perf_event * hwc)137 static void hisi_mn_pmu_disable_counter(struct hisi_pmu *mn_pmu,
138 struct hw_perf_event *hwc)
139 {
140 struct hisi_mn_pmu_regs *reg_info = mn_pmu->dev_info->private;
141 u32 val;
142
143 val = readl(mn_pmu->base + reg_info->event_ctrl);
144 val &= ~BIT(hwc->idx);
145 writel(val, mn_pmu->base + reg_info->event_ctrl);
146 }
147
hisi_mn_pmu_enable_counter_int(struct hisi_pmu * mn_pmu,struct hw_perf_event * hwc)148 static void hisi_mn_pmu_enable_counter_int(struct hisi_pmu *mn_pmu,
149 struct hw_perf_event *hwc)
150 {
151 struct hisi_mn_pmu_regs *reg_info = mn_pmu->dev_info->private;
152 u32 val;
153
154 val = readl(mn_pmu->base + reg_info->int_mask);
155 val &= ~BIT(hwc->idx);
156 writel(val, mn_pmu->base + reg_info->int_mask);
157 }
158
hisi_mn_pmu_disable_counter_int(struct hisi_pmu * mn_pmu,struct hw_perf_event * hwc)159 static void hisi_mn_pmu_disable_counter_int(struct hisi_pmu *mn_pmu,
160 struct hw_perf_event *hwc)
161 {
162 struct hisi_mn_pmu_regs *reg_info = mn_pmu->dev_info->private;
163 u32 val;
164
165 val = readl(mn_pmu->base + reg_info->int_mask);
166 val |= BIT(hwc->idx);
167 writel(val, mn_pmu->base + reg_info->int_mask);
168 }
169
hisi_mn_pmu_get_int_status(struct hisi_pmu * mn_pmu)170 static u32 hisi_mn_pmu_get_int_status(struct hisi_pmu *mn_pmu)
171 {
172 struct hisi_mn_pmu_regs *reg_info = mn_pmu->dev_info->private;
173
174 return readl(mn_pmu->base + reg_info->int_status);
175 }
176
hisi_mn_pmu_clear_int_status(struct hisi_pmu * mn_pmu,int idx)177 static void hisi_mn_pmu_clear_int_status(struct hisi_pmu *mn_pmu, int idx)
178 {
179 struct hisi_mn_pmu_regs *reg_info = mn_pmu->dev_info->private;
180
181 writel(BIT(idx), mn_pmu->base + reg_info->int_clear);
182 }
183
184 static struct attribute *hisi_mn_pmu_format_attr[] = {
185 HISI_PMU_FORMAT_ATTR(event, "config:0-7"),
186 NULL
187 };
188
189 static const struct attribute_group hisi_mn_pmu_format_group = {
190 .name = "format",
191 .attrs = hisi_mn_pmu_format_attr,
192 };
193
194 static struct attribute *hisi_mn_pmu_events_attr[] = {
195 HISI_PMU_EVENT_ATTR(req_eobarrier_num, 0x00),
196 HISI_PMU_EVENT_ATTR(req_ecbarrier_num, 0x01),
197 HISI_PMU_EVENT_ATTR(req_dvmop_num, 0x02),
198 HISI_PMU_EVENT_ATTR(req_dvmsync_num, 0x03),
199 HISI_PMU_EVENT_ATTR(req_retry_num, 0x04),
200 HISI_PMU_EVENT_ATTR(req_writenosnp_num, 0x05),
201 HISI_PMU_EVENT_ATTR(req_readnosnp_num, 0x06),
202 HISI_PMU_EVENT_ATTR(snp_dvm_num, 0x07),
203 HISI_PMU_EVENT_ATTR(snp_dvmsync_num, 0x08),
204 HISI_PMU_EVENT_ATTR(l3t_req_dvm_num, 0x09),
205 HISI_PMU_EVENT_ATTR(l3t_req_dvmsync_num, 0x0A),
206 HISI_PMU_EVENT_ATTR(mn_req_dvm_num, 0x0B),
207 HISI_PMU_EVENT_ATTR(mn_req_dvmsync_num, 0x0C),
208 HISI_PMU_EVENT_ATTR(pa_req_dvm_num, 0x0D),
209 HISI_PMU_EVENT_ATTR(pa_req_dvmsync_num, 0x0E),
210 HISI_PMU_EVENT_ATTR(snp_dvm_latency, 0x80),
211 HISI_PMU_EVENT_ATTR(snp_dvmsync_latency, 0x81),
212 HISI_PMU_EVENT_ATTR(l3t_req_dvm_latency, 0x82),
213 HISI_PMU_EVENT_ATTR(l3t_req_dvmsync_latency, 0x83),
214 HISI_PMU_EVENT_ATTR(mn_req_dvm_latency, 0x84),
215 HISI_PMU_EVENT_ATTR(mn_req_dvmsync_latency, 0x85),
216 HISI_PMU_EVENT_ATTR(pa_req_dvm_latency, 0x86),
217 HISI_PMU_EVENT_ATTR(pa_req_dvmsync_latency, 0x87),
218 NULL
219 };
220
221 static const struct attribute_group hisi_mn_pmu_events_group = {
222 .name = "events",
223 .attrs = hisi_mn_pmu_events_attr,
224 };
225
226 static const struct attribute_group *hisi_mn_pmu_attr_groups[] = {
227 &hisi_mn_pmu_format_group,
228 &hisi_mn_pmu_events_group,
229 &hisi_pmu_cpumask_attr_group,
230 &hisi_pmu_identifier_group,
231 NULL
232 };
233
234 static const struct hisi_uncore_ops hisi_uncore_mn_ops = {
235 .write_evtype = hisi_mn_pmu_write_evtype,
236 .get_event_idx = hisi_uncore_pmu_get_event_idx,
237 .start_counters = hisi_mn_pmu_start_counters,
238 .stop_counters = hisi_mn_pmu_stop_counters,
239 .enable_counter = hisi_mn_pmu_enable_counter,
240 .disable_counter = hisi_mn_pmu_disable_counter,
241 .enable_counter_int = hisi_mn_pmu_enable_counter_int,
242 .disable_counter_int = hisi_mn_pmu_disable_counter_int,
243 .write_counter = hisi_mn_pmu_write_counter,
244 .read_counter = hisi_mn_pmu_read_counter,
245 .get_int_status = hisi_mn_pmu_get_int_status,
246 .clear_int_status = hisi_mn_pmu_clear_int_status,
247 };
248
hisi_mn_pmu_dev_init(struct platform_device * pdev,struct hisi_pmu * mn_pmu)249 static int hisi_mn_pmu_dev_init(struct platform_device *pdev,
250 struct hisi_pmu *mn_pmu)
251 {
252 struct hisi_mn_pmu_regs *reg_info;
253 int ret;
254
255 hisi_uncore_pmu_init_topology(mn_pmu, &pdev->dev);
256
257 if (mn_pmu->topo.scl_id < 0)
258 return dev_err_probe(&pdev->dev, -EINVAL,
259 "Failed to read MN scl id\n");
260
261 if (mn_pmu->topo.index_id < 0)
262 return dev_err_probe(&pdev->dev, -EINVAL,
263 "Failed to read MN index id\n");
264
265 mn_pmu->base = devm_platform_ioremap_resource(pdev, 0);
266 if (IS_ERR(mn_pmu->base))
267 return dev_err_probe(&pdev->dev, PTR_ERR(mn_pmu->base),
268 "Failed to ioremap resource\n");
269
270 ret = hisi_uncore_pmu_init_irq(mn_pmu, pdev);
271 if (ret)
272 return ret;
273
274 mn_pmu->dev_info = device_get_match_data(&pdev->dev);
275 if (!mn_pmu->dev_info)
276 return -ENODEV;
277
278 mn_pmu->pmu_events.attr_groups = mn_pmu->dev_info->attr_groups;
279 mn_pmu->counter_bits = mn_pmu->dev_info->counter_bits;
280 mn_pmu->check_event = mn_pmu->dev_info->check_event;
281 mn_pmu->num_counters = HISI_MN_NR_COUNTERS;
282 mn_pmu->ops = &hisi_uncore_mn_ops;
283 mn_pmu->dev = &pdev->dev;
284 mn_pmu->on_cpu = -1;
285
286 reg_info = mn_pmu->dev_info->private;
287 mn_pmu->identifier = readl(mn_pmu->base + reg_info->version);
288
289 return 0;
290 }
291
hisi_mn_pmu_remove_cpuhp(void * hotplug_node)292 static void hisi_mn_pmu_remove_cpuhp(void *hotplug_node)
293 {
294 cpuhp_state_remove_instance_nocalls(hisi_mn_pmu_online, hotplug_node);
295 }
296
hisi_mn_pmu_unregister(void * pmu)297 static void hisi_mn_pmu_unregister(void *pmu)
298 {
299 perf_pmu_unregister(pmu);
300 }
301
hisi_mn_pmu_probe(struct platform_device * pdev)302 static int hisi_mn_pmu_probe(struct platform_device *pdev)
303 {
304 struct hisi_pmu *mn_pmu;
305 char *name;
306 int ret;
307
308 mn_pmu = devm_kzalloc(&pdev->dev, sizeof(*mn_pmu), GFP_KERNEL);
309 if (!mn_pmu)
310 return -ENOMEM;
311
312 platform_set_drvdata(pdev, mn_pmu);
313
314 ret = hisi_mn_pmu_dev_init(pdev, mn_pmu);
315 if (ret)
316 return ret;
317
318 name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "hisi_scl%d_mn%d",
319 mn_pmu->topo.scl_id, mn_pmu->topo.index_id);
320 if (!name)
321 return -ENOMEM;
322
323 ret = cpuhp_state_add_instance(hisi_mn_pmu_online, &mn_pmu->node);
324 if (ret)
325 return dev_err_probe(&pdev->dev, ret, "Failed to register cpu hotplug\n");
326
327 ret = devm_add_action_or_reset(&pdev->dev, hisi_mn_pmu_remove_cpuhp, &mn_pmu->node);
328 if (ret)
329 return ret;
330
331 hisi_pmu_init(mn_pmu, THIS_MODULE);
332
333 ret = perf_pmu_register(&mn_pmu->pmu, name, -1);
334 if (ret)
335 return dev_err_probe(mn_pmu->dev, ret, "Failed to register MN PMU\n");
336
337 return devm_add_action_or_reset(&pdev->dev, hisi_mn_pmu_unregister, &mn_pmu->pmu);
338 }
339
340 static struct hisi_mn_pmu_regs hisi_mn_v1_pmu_regs = {
341 .version = HISI_MN_VERSION_REG,
342 .dyn_ctrl = HISI_MN_DYNAMIC_CTRL_REG,
343 .perf_ctrl = HISI_MN_PERF_CTRL_REG,
344 .int_mask = HISI_MN_INT_MASK_REG,
345 .int_clear = HISI_MN_INT_CLEAR_REG,
346 .int_status = HISI_MN_INT_STATUS_REG,
347 .event_ctrl = HISI_MN_EVENT_CTRL_REG,
348 .event_type0 = HISI_MN_EVTYPE0_REG,
349 .event_cntr0 = HISI_MN_CNTR0_REG,
350 };
351
352 static const struct hisi_pmu_dev_info hisi_mn_v1 = {
353 .attr_groups = hisi_mn_pmu_attr_groups,
354 .counter_bits = 48,
355 .check_event = HISI_MN_EVTYPE_MASK,
356 .private = &hisi_mn_v1_pmu_regs,
357 };
358
359 static const struct acpi_device_id hisi_mn_pmu_acpi_match[] = {
360 { "HISI0222", (kernel_ulong_t) &hisi_mn_v1 },
361 { }
362 };
363 MODULE_DEVICE_TABLE(acpi, hisi_mn_pmu_acpi_match);
364
365 static struct platform_driver hisi_mn_pmu_driver = {
366 .driver = {
367 .name = "hisi_mn_pmu",
368 .acpi_match_table = hisi_mn_pmu_acpi_match,
369 /*
370 * We have not worked out a safe bind/unbind process,
371 * Forcefully unbinding during sampling will lead to a
372 * kernel panic, so this is not supported yet.
373 */
374 .suppress_bind_attrs = true,
375 },
376 .probe = hisi_mn_pmu_probe,
377 };
378
hisi_mn_pmu_module_init(void)379 static int __init hisi_mn_pmu_module_init(void)
380 {
381 int ret;
382
383 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "perf/hisi/mn:online",
384 hisi_uncore_pmu_online_cpu,
385 hisi_uncore_pmu_offline_cpu);
386 if (ret < 0) {
387 pr_err("hisi_mn_pmu: Failed to setup MN PMU hotplug: %d\n", ret);
388 return ret;
389 }
390 hisi_mn_pmu_online = ret;
391
392 ret = platform_driver_register(&hisi_mn_pmu_driver);
393 if (ret)
394 cpuhp_remove_multi_state(hisi_mn_pmu_online);
395
396 return ret;
397 }
398 module_init(hisi_mn_pmu_module_init);
399
hisi_mn_pmu_module_exit(void)400 static void __exit hisi_mn_pmu_module_exit(void)
401 {
402 platform_driver_unregister(&hisi_mn_pmu_driver);
403 cpuhp_remove_multi_state(hisi_mn_pmu_online);
404 }
405 module_exit(hisi_mn_pmu_module_exit);
406
407 MODULE_IMPORT_NS("HISI_PMU");
408 MODULE_DESCRIPTION("HiSilicon SoC MN uncore PMU driver");
409 MODULE_LICENSE("GPL");
410 MODULE_AUTHOR("Junhao He <hejunhao3@huawei.com>");
411