1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * es8328.c -- ES8328 ALSA SoC Audio driver 4 * 5 * Copyright 2014 Sutajio Ko-Usagi PTE LTD 6 * 7 * Author: Sean Cross <xobs@kosagi.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/module.h> 13 #include <linux/pm.h> 14 #include <linux/regmap.h> 15 #include <linux/slab.h> 16 #include <linux/regulator/consumer.h> 17 #include <sound/core.h> 18 #include <sound/initval.h> 19 #include <sound/pcm.h> 20 #include <sound/pcm_params.h> 21 #include <sound/soc.h> 22 #include <sound/tlv.h> 23 #include "es8328.h" 24 25 static const unsigned int rates_12288[] = { 26 8000, 12000, 16000, 24000, 32000, 48000, 96000, 27 }; 28 29 static const int ratios_12288[] = { 30 10, 7, 6, 4, 3, 2, 0, 31 }; 32 33 static const struct snd_pcm_hw_constraint_list constraints_12288 = { 34 .count = ARRAY_SIZE(rates_12288), 35 .list = rates_12288, 36 }; 37 38 static const unsigned int rates_11289[] = { 39 8018, 11025, 22050, 44100, 88200, 40 }; 41 42 static const int ratios_11289[] = { 43 9, 7, 4, 2, 0, 44 }; 45 46 static const struct snd_pcm_hw_constraint_list constraints_11289 = { 47 .count = ARRAY_SIZE(rates_11289), 48 .list = rates_11289, 49 }; 50 51 /* regulator supplies for sgtl5000, VDDD is an optional external supply */ 52 enum sgtl5000_regulator_supplies { 53 DVDD, 54 AVDD, 55 PVDD, 56 HPVDD, 57 ES8328_SUPPLY_NUM 58 }; 59 60 /* vddd is optional supply */ 61 static const char * const supply_names[ES8328_SUPPLY_NUM] = { 62 "DVDD", 63 "AVDD", 64 "PVDD", 65 "HPVDD", 66 }; 67 68 #define ES8328_RATES (SNDRV_PCM_RATE_192000 | \ 69 SNDRV_PCM_RATE_96000 | \ 70 SNDRV_PCM_RATE_88200 | \ 71 SNDRV_PCM_RATE_8000_48000) 72 #define ES8328_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 73 SNDRV_PCM_FMTBIT_S18_3LE | \ 74 SNDRV_PCM_FMTBIT_S20_3LE | \ 75 SNDRV_PCM_FMTBIT_S24_LE | \ 76 SNDRV_PCM_FMTBIT_S32_LE) 77 78 struct es8328_priv { 79 struct regmap *regmap; 80 struct clk *clk; 81 int playback_fs; 82 bool deemph; 83 int mclkdiv2; 84 const struct snd_pcm_hw_constraint_list *sysclk_constraints; 85 const int *mclk_ratios; 86 bool provider; 87 struct regulator_bulk_data supplies[ES8328_SUPPLY_NUM]; 88 }; 89 90 /* 91 * ES8328 Controls 92 */ 93 94 static const char * const adcpol_txt[] = {"Normal", "L Invert", "R Invert", 95 "L + R Invert"}; 96 static SOC_ENUM_SINGLE_DECL(adcpol, 97 ES8328_ADCCONTROL6, 6, adcpol_txt); 98 99 static const DECLARE_TLV_DB_SCALE(play_tlv, -3000, 100, 0); 100 static const DECLARE_TLV_DB_SCALE(dac_adc_tlv, -9600, 50, 0); 101 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0); 102 static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 300, 0); 103 104 static const struct { 105 int rate; 106 unsigned int val; 107 } deemph_settings[] = { 108 { 0, ES8328_DACCONTROL6_DEEMPH_OFF }, 109 { 32000, ES8328_DACCONTROL6_DEEMPH_32k }, 110 { 44100, ES8328_DACCONTROL6_DEEMPH_44_1k }, 111 { 48000, ES8328_DACCONTROL6_DEEMPH_48k }, 112 }; 113 114 static int es8328_set_deemph(struct snd_soc_component *component) 115 { 116 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); 117 int val, i, best; 118 119 /* 120 * If we're using deemphasis select the nearest available sample 121 * rate. 122 */ 123 if (es8328->deemph) { 124 best = 0; 125 for (i = 1; i < ARRAY_SIZE(deemph_settings); i++) { 126 if (abs(deemph_settings[i].rate - es8328->playback_fs) < 127 abs(deemph_settings[best].rate - es8328->playback_fs)) 128 best = i; 129 } 130 131 val = deemph_settings[best].val; 132 } else { 133 val = ES8328_DACCONTROL6_DEEMPH_OFF; 134 } 135 136 dev_dbg(component->dev, "Set deemphasis %d\n", val); 137 138 return snd_soc_component_update_bits(component, ES8328_DACCONTROL6, 139 ES8328_DACCONTROL6_DEEMPH_MASK, val); 140 } 141 142 static int es8328_get_deemph(struct snd_kcontrol *kcontrol, 143 struct snd_ctl_elem_value *ucontrol) 144 { 145 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 146 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); 147 148 ucontrol->value.integer.value[0] = es8328->deemph; 149 return 0; 150 } 151 152 static int es8328_put_deemph(struct snd_kcontrol *kcontrol, 153 struct snd_ctl_elem_value *ucontrol) 154 { 155 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 156 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); 157 unsigned int deemph = ucontrol->value.integer.value[0]; 158 int ret; 159 160 if (deemph > 1) 161 return -EINVAL; 162 163 if (es8328->deemph == deemph) 164 return 0; 165 166 es8328->deemph = deemph; 167 ret = es8328_set_deemph(component); 168 if (ret < 0) 169 return ret; 170 171 return 1; 172 } 173 174 175 176 static const struct snd_kcontrol_new es8328_snd_controls[] = { 177 SOC_DOUBLE_R_TLV("Capture Digital Volume", 178 ES8328_ADCCONTROL8, ES8328_ADCCONTROL9, 179 0, 0xc0, 1, dac_adc_tlv), 180 SOC_SINGLE("Capture ZC Switch", ES8328_ADCCONTROL7, 6, 1, 0), 181 182 SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0, 183 es8328_get_deemph, es8328_put_deemph), 184 185 SOC_ENUM("Capture Polarity", adcpol), 186 187 SOC_SINGLE_TLV("Left Mixer Left Bypass Volume", 188 ES8328_DACCONTROL17, 3, 7, 1, bypass_tlv), 189 SOC_SINGLE_TLV("Left Mixer Right Bypass Volume", 190 ES8328_DACCONTROL19, 3, 7, 1, bypass_tlv), 191 SOC_SINGLE_TLV("Right Mixer Left Bypass Volume", 192 ES8328_DACCONTROL18, 3, 7, 1, bypass_tlv), 193 SOC_SINGLE_TLV("Right Mixer Right Bypass Volume", 194 ES8328_DACCONTROL20, 3, 7, 1, bypass_tlv), 195 196 SOC_DOUBLE_R_TLV("PCM Volume", 197 ES8328_LDACVOL, ES8328_RDACVOL, 198 0, ES8328_DACVOL_MAX, 1, dac_adc_tlv), 199 200 SOC_DOUBLE_R_TLV("Output 1 Playback Volume", 201 ES8328_LOUT1VOL, ES8328_ROUT1VOL, 202 0, ES8328_OUT1VOL_MAX, 0, play_tlv), 203 204 SOC_DOUBLE_R_TLV("Output 2 Playback Volume", 205 ES8328_LOUT2VOL, ES8328_ROUT2VOL, 206 0, ES8328_OUT2VOL_MAX, 0, play_tlv), 207 208 SOC_DOUBLE_TLV("Mic PGA Volume", ES8328_ADCCONTROL1, 209 4, 0, 8, 0, mic_tlv), 210 }; 211 212 /* 213 * DAPM Controls 214 */ 215 216 static const char * const es8328_line_texts[] = { 217 "Line 1", "Line 2", "PGA", "Differential"}; 218 219 static const struct soc_enum es8328_lline_enum = 220 SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 3, 221 ARRAY_SIZE(es8328_line_texts), 222 es8328_line_texts); 223 static const struct snd_kcontrol_new es8328_left_line_controls = 224 SOC_DAPM_ENUM("Route", es8328_lline_enum); 225 226 static const struct soc_enum es8328_rline_enum = 227 SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 0, 228 ARRAY_SIZE(es8328_line_texts), 229 es8328_line_texts); 230 static const struct snd_kcontrol_new es8328_right_line_controls = 231 SOC_DAPM_ENUM("Route", es8328_rline_enum); 232 233 /* Left Mixer */ 234 static const struct snd_kcontrol_new es8328_left_mixer_controls[] = { 235 SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL17, 6, 1, 0), 236 SOC_DAPM_SINGLE("Right Playback Switch", ES8328_DACCONTROL18, 7, 1, 0), 237 SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL18, 6, 1, 0), 238 }; 239 240 /* Right Mixer */ 241 static const struct snd_kcontrol_new es8328_right_mixer_controls[] = { 242 SOC_DAPM_SINGLE("Left Playback Switch", ES8328_DACCONTROL19, 7, 1, 0), 243 SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL19, 6, 1, 0), 244 SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL20, 6, 1, 0), 245 }; 246 247 static const char * const es8328_pga_sel[] = { 248 "Line 1", "Line 2", "Line 3", "Differential"}; 249 250 /* Left PGA Mux */ 251 static const struct soc_enum es8328_lpga_enum = 252 SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 6, 253 ARRAY_SIZE(es8328_pga_sel), 254 es8328_pga_sel); 255 static const struct snd_kcontrol_new es8328_left_pga_controls = 256 SOC_DAPM_ENUM("Route", es8328_lpga_enum); 257 258 /* Right PGA Mux */ 259 static const struct soc_enum es8328_rpga_enum = 260 SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 4, 261 ARRAY_SIZE(es8328_pga_sel), 262 es8328_pga_sel); 263 static const struct snd_kcontrol_new es8328_right_pga_controls = 264 SOC_DAPM_ENUM("Route", es8328_rpga_enum); 265 266 /* Differential Mux */ 267 static const char * const es8328_diff_sel[] = {"Line 1", "Line 2"}; 268 static SOC_ENUM_SINGLE_DECL(diffmux, 269 ES8328_ADCCONTROL3, 7, es8328_diff_sel); 270 static const struct snd_kcontrol_new es8328_diffmux_controls = 271 SOC_DAPM_ENUM("Route", diffmux); 272 273 /* Mono ADC Mux */ 274 static const char * const es8328_mono_mux[] = {"Stereo", "Mono (Left)", 275 "Mono (Right)", "Digital Mono"}; 276 static SOC_ENUM_SINGLE_DECL(monomux, 277 ES8328_ADCCONTROL3, 3, es8328_mono_mux); 278 static const struct snd_kcontrol_new es8328_monomux_controls = 279 SOC_DAPM_ENUM("Route", monomux); 280 281 static const struct snd_soc_dapm_widget es8328_dapm_widgets[] = { 282 SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0, 283 &es8328_diffmux_controls), 284 SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0, 285 &es8328_monomux_controls), 286 SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0, 287 &es8328_monomux_controls), 288 289 SND_SOC_DAPM_MUX("Left PGA Mux", ES8328_ADCPOWER, 290 ES8328_ADCPOWER_AINL_OFF, 1, 291 &es8328_left_pga_controls), 292 SND_SOC_DAPM_MUX("Right PGA Mux", ES8328_ADCPOWER, 293 ES8328_ADCPOWER_AINR_OFF, 1, 294 &es8328_right_pga_controls), 295 296 SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0, 297 &es8328_left_line_controls), 298 SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0, 299 &es8328_right_line_controls), 300 301 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ES8328_ADCPOWER, 302 ES8328_ADCPOWER_ADCR_OFF, 1), 303 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ES8328_ADCPOWER, 304 ES8328_ADCPOWER_ADCL_OFF, 1), 305 306 SND_SOC_DAPM_SUPPLY("Mic Bias", ES8328_ADCPOWER, 307 ES8328_ADCPOWER_MIC_BIAS_OFF, 1, NULL, 0), 308 SND_SOC_DAPM_SUPPLY("Mic Bias Gen", ES8328_ADCPOWER, 309 ES8328_ADCPOWER_ADC_BIAS_GEN_OFF, 1, NULL, 0), 310 311 SND_SOC_DAPM_SUPPLY("DAC STM", ES8328_CHIPPOWER, 312 ES8328_CHIPPOWER_DACSTM_RESET, 1, NULL, 0), 313 SND_SOC_DAPM_SUPPLY("ADC STM", ES8328_CHIPPOWER, 314 ES8328_CHIPPOWER_ADCSTM_RESET, 1, NULL, 0), 315 316 SND_SOC_DAPM_SUPPLY("DAC DIG", ES8328_CHIPPOWER, 317 ES8328_CHIPPOWER_DACDIG_OFF, 1, NULL, 0), 318 SND_SOC_DAPM_SUPPLY("ADC DIG", ES8328_CHIPPOWER, 319 ES8328_CHIPPOWER_ADCDIG_OFF, 1, NULL, 0), 320 321 SND_SOC_DAPM_SUPPLY("DAC DLL", ES8328_CHIPPOWER, 322 ES8328_CHIPPOWER_DACDLL_OFF, 1, NULL, 0), 323 SND_SOC_DAPM_SUPPLY("ADC DLL", ES8328_CHIPPOWER, 324 ES8328_CHIPPOWER_ADCDLL_OFF, 1, NULL, 0), 325 326 SND_SOC_DAPM_SUPPLY("ADC Vref", ES8328_CHIPPOWER, 327 ES8328_CHIPPOWER_ADCVREF_OFF, 1, NULL, 0), 328 SND_SOC_DAPM_SUPPLY("DAC Vref", ES8328_CHIPPOWER, 329 ES8328_CHIPPOWER_DACVREF_OFF, 1, NULL, 0), 330 331 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", ES8328_DACPOWER, 332 ES8328_DACPOWER_RDAC_OFF, 1), 333 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", ES8328_DACPOWER, 334 ES8328_DACPOWER_LDAC_OFF, 1), 335 336 SND_SOC_DAPM_MIXER("Left Mixer", ES8328_DACCONTROL17, 7, 0, 337 &es8328_left_mixer_controls[0], 338 ARRAY_SIZE(es8328_left_mixer_controls)), 339 SND_SOC_DAPM_MIXER("Right Mixer", ES8328_DACCONTROL20, 7, 0, 340 &es8328_right_mixer_controls[0], 341 ARRAY_SIZE(es8328_right_mixer_controls)), 342 343 SND_SOC_DAPM_PGA("Right Out 2", ES8328_DACPOWER, 344 ES8328_DACPOWER_ROUT2_ON, 0, NULL, 0), 345 SND_SOC_DAPM_PGA("Left Out 2", ES8328_DACPOWER, 346 ES8328_DACPOWER_LOUT2_ON, 0, NULL, 0), 347 SND_SOC_DAPM_PGA("Right Out 1", ES8328_DACPOWER, 348 ES8328_DACPOWER_ROUT1_ON, 0, NULL, 0), 349 SND_SOC_DAPM_PGA("Left Out 1", ES8328_DACPOWER, 350 ES8328_DACPOWER_LOUT1_ON, 0, NULL, 0), 351 352 SND_SOC_DAPM_OUTPUT("LOUT1"), 353 SND_SOC_DAPM_OUTPUT("ROUT1"), 354 SND_SOC_DAPM_OUTPUT("LOUT2"), 355 SND_SOC_DAPM_OUTPUT("ROUT2"), 356 357 SND_SOC_DAPM_INPUT("LINPUT1"), 358 SND_SOC_DAPM_INPUT("LINPUT2"), 359 SND_SOC_DAPM_INPUT("RINPUT1"), 360 SND_SOC_DAPM_INPUT("RINPUT2"), 361 }; 362 363 static const struct snd_soc_dapm_route es8328_dapm_routes[] = { 364 365 { "Left Line Mux", "Line 1", "LINPUT1" }, 366 { "Left Line Mux", "Line 2", "LINPUT2" }, 367 { "Left Line Mux", "PGA", "Left PGA Mux" }, 368 { "Left Line Mux", "Differential", "Differential Mux" }, 369 370 { "Right Line Mux", "Line 1", "RINPUT1" }, 371 { "Right Line Mux", "Line 2", "RINPUT2" }, 372 { "Right Line Mux", "PGA", "Right PGA Mux" }, 373 { "Right Line Mux", "Differential", "Differential Mux" }, 374 375 { "Left PGA Mux", "Line 1", "LINPUT1" }, 376 { "Left PGA Mux", "Line 2", "LINPUT2" }, 377 { "Left PGA Mux", "Differential", "Differential Mux" }, 378 379 { "Right PGA Mux", "Line 1", "RINPUT1" }, 380 { "Right PGA Mux", "Line 2", "RINPUT2" }, 381 { "Right PGA Mux", "Differential", "Differential Mux" }, 382 383 { "Differential Mux", "Line 1", "LINPUT1" }, 384 { "Differential Mux", "Line 1", "RINPUT1" }, 385 { "Differential Mux", "Line 2", "LINPUT2" }, 386 { "Differential Mux", "Line 2", "RINPUT2" }, 387 388 { "Left ADC Mux", "Stereo", "Left PGA Mux" }, 389 { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" }, 390 { "Left ADC Mux", "Digital Mono", "Left PGA Mux" }, 391 392 { "Right ADC Mux", "Stereo", "Right PGA Mux" }, 393 { "Right ADC Mux", "Mono (Right)", "Right PGA Mux" }, 394 { "Right ADC Mux", "Digital Mono", "Right PGA Mux" }, 395 396 { "Left ADC", NULL, "Left ADC Mux" }, 397 { "Right ADC", NULL, "Right ADC Mux" }, 398 399 { "ADC DIG", NULL, "ADC STM" }, 400 { "ADC DIG", NULL, "ADC Vref" }, 401 { "ADC DIG", NULL, "ADC DLL" }, 402 403 { "Left ADC", NULL, "ADC DIG" }, 404 { "Right ADC", NULL, "ADC DIG" }, 405 406 { "Mic Bias", NULL, "Mic Bias Gen" }, 407 408 { "LINPUT1", NULL, "Mic Bias" }, 409 { "RINPUT1", NULL, "Mic Bias" }, 410 { "LINPUT2", NULL, "Mic Bias" }, 411 { "RINPUT2", NULL, "Mic Bias" }, 412 413 { "Left Mixer", NULL, "Left DAC" }, 414 { "Left Mixer", "Left Bypass Switch", "Left Line Mux" }, 415 { "Left Mixer", "Right Playback Switch", "Right DAC" }, 416 { "Left Mixer", "Right Bypass Switch", "Right Line Mux" }, 417 418 { "Right Mixer", "Left Playback Switch", "Left DAC" }, 419 { "Right Mixer", "Left Bypass Switch", "Left Line Mux" }, 420 { "Right Mixer", NULL, "Right DAC" }, 421 { "Right Mixer", "Right Bypass Switch", "Right Line Mux" }, 422 423 { "DAC DIG", NULL, "DAC STM" }, 424 { "DAC DIG", NULL, "DAC Vref" }, 425 { "DAC DIG", NULL, "DAC DLL" }, 426 427 { "Left DAC", NULL, "DAC DIG" }, 428 { "Right DAC", NULL, "DAC DIG" }, 429 430 { "Left Out 1", NULL, "Left Mixer" }, 431 { "LOUT1", NULL, "Left Out 1" }, 432 { "Right Out 1", NULL, "Right Mixer" }, 433 { "ROUT1", NULL, "Right Out 1" }, 434 435 { "Left Out 2", NULL, "Left Mixer" }, 436 { "LOUT2", NULL, "Left Out 2" }, 437 { "Right Out 2", NULL, "Right Mixer" }, 438 { "ROUT2", NULL, "Right Out 2" }, 439 }; 440 441 static int es8328_mute(struct snd_soc_dai *dai, int mute, int direction) 442 { 443 return snd_soc_component_update_bits(dai->component, ES8328_DACCONTROL3, 444 ES8328_DACCONTROL3_DACMUTE, 445 mute ? ES8328_DACCONTROL3_DACMUTE : 0); 446 } 447 448 static int es8328_startup(struct snd_pcm_substream *substream, 449 struct snd_soc_dai *dai) 450 { 451 struct snd_soc_component *component = dai->component; 452 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); 453 454 if (es8328->provider && es8328->sysclk_constraints) 455 snd_pcm_hw_constraint_list(substream->runtime, 0, 456 SNDRV_PCM_HW_PARAM_RATE, 457 es8328->sysclk_constraints); 458 459 return 0; 460 } 461 462 static int es8328_hw_params(struct snd_pcm_substream *substream, 463 struct snd_pcm_hw_params *params, 464 struct snd_soc_dai *dai) 465 { 466 struct snd_soc_component *component = dai->component; 467 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); 468 int ret; 469 int i; 470 int reg; 471 int wl; 472 int ratio; 473 474 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 475 reg = ES8328_DACCONTROL2; 476 else 477 reg = ES8328_ADCCONTROL5; 478 479 if (es8328->provider) { 480 if (!es8328->sysclk_constraints) { 481 dev_err(component->dev, "No MCLK configured\n"); 482 return -EINVAL; 483 } 484 485 for (i = 0; i < es8328->sysclk_constraints->count; i++) 486 if (es8328->sysclk_constraints->list[i] == 487 params_rate(params)) 488 break; 489 490 if (i == es8328->sysclk_constraints->count) { 491 dev_err(component->dev, 492 "LRCLK %d unsupported with current clock\n", 493 params_rate(params)); 494 return -EINVAL; 495 } 496 ratio = es8328->mclk_ratios[i]; 497 } else { 498 ratio = 0; 499 es8328->mclkdiv2 = 0; 500 } 501 502 ret = snd_soc_component_update_bits(component, ES8328_MASTERMODE, 503 ES8328_MASTERMODE_MCLKDIV2, 504 es8328->mclkdiv2 ? 505 ES8328_MASTERMODE_MCLKDIV2 : 0); 506 if (ret < 0) 507 return ret; 508 509 switch (params_width(params)) { 510 case 16: 511 wl = 3; 512 break; 513 case 18: 514 wl = 2; 515 break; 516 case 20: 517 wl = 1; 518 break; 519 case 24: 520 wl = 0; 521 break; 522 case 32: 523 wl = 4; 524 break; 525 default: 526 return -EINVAL; 527 } 528 529 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 530 ret = snd_soc_component_update_bits(component, ES8328_DACCONTROL1, 531 ES8328_DACCONTROL1_DACWL_MASK, 532 wl << ES8328_DACCONTROL1_DACWL_SHIFT); 533 if (ret < 0) 534 return ret; 535 536 es8328->playback_fs = params_rate(params); 537 ret = es8328_set_deemph(component); 538 if (ret < 0) 539 return ret; 540 } else { 541 ret = snd_soc_component_update_bits(component, ES8328_ADCCONTROL4, 542 ES8328_ADCCONTROL4_ADCWL_MASK, 543 wl << ES8328_ADCCONTROL4_ADCWL_SHIFT); 544 if (ret < 0) 545 return ret; 546 } 547 548 ret = snd_soc_component_update_bits(component, reg, ES8328_RATEMASK, ratio); 549 if (ret < 0) 550 return ret; 551 return 0; 552 } 553 554 static int es8328_set_sysclk(struct snd_soc_dai *codec_dai, 555 int clk_id, unsigned int freq, int dir) 556 { 557 struct snd_soc_component *component = codec_dai->component; 558 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); 559 int mclkdiv2 = 0; 560 unsigned int round_freq; 561 562 /* 563 * Allow a small tolerance for frequencies within 100hz. Note 564 * this value is chosen arbitrarily. 565 */ 566 round_freq = DIV_ROUND_CLOSEST(freq, 100) * 100; 567 568 switch (round_freq) { 569 case 0: 570 es8328->sysclk_constraints = NULL; 571 es8328->mclk_ratios = NULL; 572 break; 573 case 22579200: 574 mclkdiv2 = 1; 575 fallthrough; 576 case 11289600: 577 es8328->sysclk_constraints = &constraints_11289; 578 es8328->mclk_ratios = ratios_11289; 579 break; 580 case 24576000: 581 mclkdiv2 = 1; 582 fallthrough; 583 case 12288000: 584 es8328->sysclk_constraints = &constraints_12288; 585 es8328->mclk_ratios = ratios_12288; 586 break; 587 default: 588 return -EINVAL; 589 } 590 591 es8328->mclkdiv2 = mclkdiv2; 592 return 0; 593 } 594 595 static int es8328_set_dai_fmt(struct snd_soc_dai *codec_dai, 596 unsigned int fmt) 597 { 598 struct snd_soc_component *component = codec_dai->component; 599 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); 600 int ret; 601 u8 dac_mode = 0; 602 u8 adc_mode = 0; 603 604 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 605 case SND_SOC_DAIFMT_CBP_CFP: 606 /* Master serial port mode, with BCLK generated automatically */ 607 ret = snd_soc_component_update_bits(component, ES8328_MASTERMODE, 608 ES8328_MASTERMODE_MSC, 609 ES8328_MASTERMODE_MSC); 610 if (ret < 0) 611 return ret; 612 es8328->provider = true; 613 break; 614 case SND_SOC_DAIFMT_CBC_CFC: 615 /* Slave serial port mode */ 616 ret = snd_soc_component_update_bits(component, ES8328_MASTERMODE, 617 ES8328_MASTERMODE_MSC, 0); 618 if (ret < 0) 619 return ret; 620 es8328->provider = false; 621 break; 622 default: 623 return -EINVAL; 624 } 625 626 /* interface format */ 627 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 628 case SND_SOC_DAIFMT_I2S: 629 dac_mode |= ES8328_DACCONTROL1_DACFORMAT_I2S; 630 adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_I2S; 631 break; 632 case SND_SOC_DAIFMT_RIGHT_J: 633 dac_mode |= ES8328_DACCONTROL1_DACFORMAT_RJUST; 634 adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_RJUST; 635 break; 636 case SND_SOC_DAIFMT_LEFT_J: 637 dac_mode |= ES8328_DACCONTROL1_DACFORMAT_LJUST; 638 adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_LJUST; 639 break; 640 default: 641 return -EINVAL; 642 } 643 644 /* clock inversion */ 645 if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) 646 return -EINVAL; 647 648 ret = snd_soc_component_update_bits(component, ES8328_DACCONTROL1, 649 ES8328_DACCONTROL1_DACFORMAT_MASK, 650 dac_mode); 651 if (ret < 0) 652 return ret; 653 654 ret = snd_soc_component_update_bits(component, ES8328_ADCCONTROL4, 655 ES8328_ADCCONTROL4_ADCFORMAT_MASK, 656 adc_mode); 657 if (ret < 0) 658 return ret; 659 660 return 0; 661 } 662 663 static int es8328_set_bias_level(struct snd_soc_component *component, 664 enum snd_soc_bias_level level) 665 { 666 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 667 int ret; 668 669 switch (level) { 670 case SND_SOC_BIAS_ON: 671 break; 672 673 case SND_SOC_BIAS_PREPARE: 674 /* VREF, VMID=2x50k, digital enabled */ 675 ret = snd_soc_component_write(component, ES8328_CHIPPOWER, 0); 676 if (ret < 0) 677 return ret; 678 679 ret = snd_soc_component_update_bits(component, ES8328_CONTROL1, 680 ES8328_CONTROL1_VMIDSEL_MASK | 681 ES8328_CONTROL1_ENREF, 682 ES8328_CONTROL1_VMIDSEL_50k | 683 ES8328_CONTROL1_ENREF); 684 if (ret < 0) 685 return ret; 686 break; 687 688 case SND_SOC_BIAS_STANDBY: 689 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) { 690 ret = snd_soc_component_update_bits(component, ES8328_CONTROL1, 691 ES8328_CONTROL1_VMIDSEL_MASK | 692 ES8328_CONTROL1_ENREF, 693 ES8328_CONTROL1_VMIDSEL_5k | 694 ES8328_CONTROL1_ENREF); 695 if (ret < 0) 696 return ret; 697 698 /* Charge caps */ 699 msleep(100); 700 } 701 702 ret = snd_soc_component_write(component, ES8328_CONTROL2, 703 ES8328_CONTROL2_OVERCURRENT_ON | 704 ES8328_CONTROL2_THERMAL_SHUTDOWN_ON); 705 if (ret < 0) 706 return ret; 707 708 /* VREF, VMID=2*500k, digital stopped */ 709 ret = snd_soc_component_update_bits(component, ES8328_CONTROL1, 710 ES8328_CONTROL1_VMIDSEL_MASK | 711 ES8328_CONTROL1_ENREF, 712 ES8328_CONTROL1_VMIDSEL_500k | 713 ES8328_CONTROL1_ENREF); 714 if (ret < 0) 715 return ret; 716 break; 717 718 case SND_SOC_BIAS_OFF: 719 ret = snd_soc_component_update_bits(component, ES8328_CONTROL1, 720 ES8328_CONTROL1_VMIDSEL_MASK | 721 ES8328_CONTROL1_ENREF, 722 0); 723 if (ret < 0) 724 return ret; 725 break; 726 } 727 return 0; 728 } 729 730 static const struct snd_soc_dai_ops es8328_dai_ops = { 731 .startup = es8328_startup, 732 .hw_params = es8328_hw_params, 733 .mute_stream = es8328_mute, 734 .set_sysclk = es8328_set_sysclk, 735 .set_fmt = es8328_set_dai_fmt, 736 .no_capture_mute = 1, 737 }; 738 739 static struct snd_soc_dai_driver es8328_dai = { 740 .name = "es8328-hifi-analog", 741 .playback = { 742 .stream_name = "Playback", 743 .channels_min = 2, 744 .channels_max = 2, 745 .rates = ES8328_RATES, 746 .formats = ES8328_FORMATS, 747 }, 748 .capture = { 749 .stream_name = "Capture", 750 .channels_min = 2, 751 .channels_max = 2, 752 .rates = ES8328_RATES, 753 .formats = ES8328_FORMATS, 754 }, 755 .ops = &es8328_dai_ops, 756 .symmetric_rate = 1, 757 }; 758 759 static int es8328_suspend(struct snd_soc_component *component) 760 { 761 struct es8328_priv *es8328; 762 int ret; 763 764 es8328 = snd_soc_component_get_drvdata(component); 765 766 clk_disable_unprepare(es8328->clk); 767 768 ret = regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), 769 es8328->supplies); 770 if (ret) { 771 dev_err(component->dev, "unable to disable regulators\n"); 772 return ret; 773 } 774 return 0; 775 } 776 777 static int es8328_resume(struct snd_soc_component *component) 778 { 779 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); 780 int ret; 781 782 ret = clk_prepare_enable(es8328->clk); 783 if (ret) { 784 dev_err(component->dev, "unable to enable clock\n"); 785 return ret; 786 } 787 788 ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies), 789 es8328->supplies); 790 if (ret) { 791 dev_err(component->dev, "unable to enable regulators\n"); 792 goto err_clk; 793 } 794 795 regcache_mark_dirty(es8328->regmap); 796 ret = regcache_sync(es8328->regmap); 797 if (ret) { 798 dev_err(component->dev, "unable to sync regcache\n"); 799 goto err_regulators; 800 } 801 802 return 0; 803 804 err_regulators: 805 regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), es8328->supplies); 806 err_clk: 807 clk_disable_unprepare(es8328->clk); 808 return ret; 809 } 810 811 static int es8328_component_probe(struct snd_soc_component *component) 812 { 813 struct es8328_priv *es8328; 814 int ret; 815 816 es8328 = snd_soc_component_get_drvdata(component); 817 818 ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies), 819 es8328->supplies); 820 if (ret) { 821 dev_err(component->dev, "unable to enable regulators\n"); 822 return ret; 823 } 824 825 /* Setup clocks */ 826 es8328->clk = devm_clk_get(component->dev, NULL); 827 if (IS_ERR(es8328->clk)) { 828 dev_err(component->dev, "codec clock missing or invalid\n"); 829 ret = PTR_ERR(es8328->clk); 830 goto clk_fail; 831 } 832 833 ret = clk_prepare_enable(es8328->clk); 834 if (ret) { 835 dev_err(component->dev, "unable to prepare codec clk\n"); 836 goto clk_fail; 837 } 838 839 return 0; 840 841 clk_fail: 842 regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), 843 es8328->supplies); 844 return ret; 845 } 846 847 static void es8328_remove(struct snd_soc_component *component) 848 { 849 struct es8328_priv *es8328; 850 851 es8328 = snd_soc_component_get_drvdata(component); 852 853 clk_disable_unprepare(es8328->clk); 854 855 regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), 856 es8328->supplies); 857 } 858 859 const struct regmap_config es8328_regmap_config = { 860 .reg_bits = 8, 861 .val_bits = 8, 862 .max_register = ES8328_REG_MAX, 863 .cache_type = REGCACHE_MAPLE, 864 .use_single_read = true, 865 .use_single_write = true, 866 }; 867 EXPORT_SYMBOL_GPL(es8328_regmap_config); 868 869 static const struct snd_soc_component_driver es8328_component_driver = { 870 .probe = es8328_component_probe, 871 .remove = es8328_remove, 872 .suspend = es8328_suspend, 873 .resume = es8328_resume, 874 .set_bias_level = es8328_set_bias_level, 875 .controls = es8328_snd_controls, 876 .num_controls = ARRAY_SIZE(es8328_snd_controls), 877 .dapm_widgets = es8328_dapm_widgets, 878 .num_dapm_widgets = ARRAY_SIZE(es8328_dapm_widgets), 879 .dapm_routes = es8328_dapm_routes, 880 .num_dapm_routes = ARRAY_SIZE(es8328_dapm_routes), 881 .suspend_bias_off = 1, 882 .idle_bias_on = 1, 883 .use_pmdown_time = 1, 884 .endianness = 1, 885 }; 886 887 int es8328_probe(struct device *dev, struct regmap *regmap) 888 { 889 struct es8328_priv *es8328; 890 int ret; 891 int i; 892 893 if (IS_ERR(regmap)) 894 return PTR_ERR(regmap); 895 896 es8328 = devm_kzalloc(dev, sizeof(*es8328), GFP_KERNEL); 897 if (es8328 == NULL) 898 return -ENOMEM; 899 900 es8328->regmap = regmap; 901 902 for (i = 0; i < ARRAY_SIZE(es8328->supplies); i++) 903 es8328->supplies[i].supply = supply_names[i]; 904 905 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(es8328->supplies), 906 es8328->supplies); 907 if (ret) { 908 dev_err(dev, "unable to get regulators\n"); 909 return ret; 910 } 911 912 dev_set_drvdata(dev, es8328); 913 914 return devm_snd_soc_register_component(dev, 915 &es8328_component_driver, &es8328_dai, 1); 916 } 917 EXPORT_SYMBOL_GPL(es8328_probe); 918 919 MODULE_DESCRIPTION("ASoC ES8328 driver"); 920 MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>"); 921 MODULE_LICENSE("GPL"); 922