1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/property.h> 31 #include <linux/netdevice.h> 32 #include <linux/gpio/consumer.h> 33 #include <linux/phylink.h> 34 #include <net/dsa.h> 35 36 #include "chip.h" 37 #include "devlink.h" 38 #include "global1.h" 39 #include "global2.h" 40 #include "hwtstamp.h" 41 #include "phy.h" 42 #include "port.h" 43 #include "ptp.h" 44 #include "serdes.h" 45 #include "smi.h" 46 #include "tcam.h" 47 #include "tcflower.h" 48 49 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 50 { 51 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 52 dev_err(chip->dev, "Switch registers lock not held!\n"); 53 dump_stack(); 54 } 55 } 56 57 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 58 { 59 int err; 60 61 assert_reg_lock(chip); 62 63 err = mv88e6xxx_smi_read(chip, addr, reg, val); 64 if (err) 65 return err; 66 67 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 68 addr, reg, *val); 69 70 return 0; 71 } 72 73 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 74 { 75 int err; 76 77 assert_reg_lock(chip); 78 79 err = mv88e6xxx_smi_write(chip, addr, reg, val); 80 if (err) 81 return err; 82 83 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 84 addr, reg, val); 85 86 return 0; 87 } 88 89 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 90 u16 mask, u16 val) 91 { 92 const unsigned long timeout = jiffies + msecs_to_jiffies(50); 93 u16 data; 94 int err; 95 int i; 96 97 /* There's no bus specific operation to wait for a mask. Even 98 * if the initial poll takes longer than 50ms, always do at 99 * least one more attempt. 100 */ 101 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) { 102 err = mv88e6xxx_read(chip, addr, reg, &data); 103 if (err) 104 return err; 105 106 if ((data & mask) == val) 107 return 0; 108 109 if (i < 2) 110 cpu_relax(); 111 else 112 usleep_range(1000, 2000); 113 } 114 115 err = mv88e6xxx_read(chip, addr, reg, &data); 116 if (err) 117 return err; 118 119 if ((data & mask) == val) 120 return 0; 121 122 dev_err(chip->dev, "Timeout while waiting for switch\n"); 123 return -ETIMEDOUT; 124 } 125 126 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 127 int bit, int val) 128 { 129 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 130 val ? BIT(bit) : 0x0000); 131 } 132 133 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 134 { 135 struct mv88e6xxx_mdio_bus *mdio_bus; 136 137 mdio_bus = list_first_entry_or_null(&chip->mdios, 138 struct mv88e6xxx_mdio_bus, list); 139 if (!mdio_bus) 140 return NULL; 141 142 return mdio_bus->bus; 143 } 144 145 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 146 { 147 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 148 unsigned int n = d->hwirq; 149 150 chip->g1_irq.masked |= (1 << n); 151 } 152 153 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 154 { 155 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 156 unsigned int n = d->hwirq; 157 158 chip->g1_irq.masked &= ~(1 << n); 159 } 160 161 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 162 { 163 unsigned int nhandled = 0; 164 unsigned int sub_irq; 165 unsigned int n; 166 u16 reg; 167 u16 ctl1; 168 int err; 169 170 mv88e6xxx_reg_lock(chip); 171 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 172 mv88e6xxx_reg_unlock(chip); 173 174 if (err) 175 goto out; 176 177 do { 178 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 179 if (reg & (1 << n)) { 180 sub_irq = irq_find_mapping(chip->g1_irq.domain, 181 n); 182 handle_nested_irq(sub_irq); 183 ++nhandled; 184 } 185 } 186 187 mv88e6xxx_reg_lock(chip); 188 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 189 if (err) 190 goto unlock; 191 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 192 unlock: 193 mv88e6xxx_reg_unlock(chip); 194 if (err) 195 goto out; 196 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 197 } while (reg & ctl1); 198 199 out: 200 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 201 } 202 203 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 204 { 205 struct mv88e6xxx_chip *chip = dev_id; 206 207 return mv88e6xxx_g1_irq_thread_work(chip); 208 } 209 210 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 211 { 212 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 213 214 mv88e6xxx_reg_lock(chip); 215 } 216 217 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 218 { 219 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 220 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 221 u16 reg; 222 int err; 223 224 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 225 if (err) 226 goto out; 227 228 reg &= ~mask; 229 reg |= (~chip->g1_irq.masked & mask); 230 231 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 232 if (err) 233 goto out; 234 235 out: 236 mv88e6xxx_reg_unlock(chip); 237 } 238 239 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 240 .name = "mv88e6xxx-g1", 241 .irq_mask = mv88e6xxx_g1_irq_mask, 242 .irq_unmask = mv88e6xxx_g1_irq_unmask, 243 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 244 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 245 }; 246 247 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 248 unsigned int irq, 249 irq_hw_number_t hwirq) 250 { 251 struct mv88e6xxx_chip *chip = d->host_data; 252 253 irq_set_chip_data(irq, d->host_data); 254 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 255 irq_set_noprobe(irq); 256 257 return 0; 258 } 259 260 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 261 .map = mv88e6xxx_g1_irq_domain_map, 262 .xlate = irq_domain_xlate_twocell, 263 }; 264 265 /* To be called with reg_lock held */ 266 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 267 { 268 int irq, virq; 269 u16 mask; 270 271 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 272 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 273 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 274 275 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 276 virq = irq_find_mapping(chip->g1_irq.domain, irq); 277 irq_dispose_mapping(virq); 278 } 279 280 irq_domain_remove(chip->g1_irq.domain); 281 } 282 283 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 284 { 285 /* 286 * free_irq must be called without reg_lock taken because the irq 287 * handler takes this lock, too. 288 */ 289 free_irq(chip->irq, chip); 290 291 mv88e6xxx_reg_lock(chip); 292 mv88e6xxx_g1_irq_free_common(chip); 293 mv88e6xxx_reg_unlock(chip); 294 } 295 296 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 297 { 298 int err, irq, virq; 299 u16 reg, mask; 300 301 chip->g1_irq.nirqs = chip->info->g1_irqs; 302 chip->g1_irq.domain = irq_domain_create_simple( 303 NULL, chip->g1_irq.nirqs, 0, 304 &mv88e6xxx_g1_irq_domain_ops, chip); 305 if (!chip->g1_irq.domain) 306 return -ENOMEM; 307 308 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 309 irq_create_mapping(chip->g1_irq.domain, irq); 310 311 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 312 chip->g1_irq.masked = ~0; 313 314 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 315 if (err) 316 goto out_mapping; 317 318 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 319 320 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 321 if (err) 322 goto out_disable; 323 324 /* Reading the interrupt status clears (most of) them */ 325 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 326 if (err) 327 goto out_disable; 328 329 return 0; 330 331 out_disable: 332 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 333 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 334 335 out_mapping: 336 for (irq = 0; irq < 16; irq++) { 337 virq = irq_find_mapping(chip->g1_irq.domain, irq); 338 irq_dispose_mapping(virq); 339 } 340 341 irq_domain_remove(chip->g1_irq.domain); 342 343 return err; 344 } 345 346 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 347 { 348 static struct lock_class_key lock_key; 349 static struct lock_class_key request_key; 350 int err; 351 352 err = mv88e6xxx_g1_irq_setup_common(chip); 353 if (err) 354 return err; 355 356 /* These lock classes tells lockdep that global 1 irqs are in 357 * a different category than their parent GPIO, so it won't 358 * report false recursion. 359 */ 360 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 361 362 snprintf(chip->irq_name, sizeof(chip->irq_name), 363 "mv88e6xxx-%s", dev_name(chip->dev)); 364 365 mv88e6xxx_reg_unlock(chip); 366 err = request_threaded_irq(chip->irq, NULL, 367 mv88e6xxx_g1_irq_thread_fn, 368 IRQF_ONESHOT | IRQF_SHARED, 369 chip->irq_name, chip); 370 mv88e6xxx_reg_lock(chip); 371 if (err) 372 mv88e6xxx_g1_irq_free_common(chip); 373 374 return err; 375 } 376 377 static void mv88e6xxx_irq_poll(struct kthread_work *work) 378 { 379 struct mv88e6xxx_chip *chip = container_of(work, 380 struct mv88e6xxx_chip, 381 irq_poll_work.work); 382 mv88e6xxx_g1_irq_thread_work(chip); 383 384 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 385 msecs_to_jiffies(100)); 386 } 387 388 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 389 { 390 int err; 391 392 err = mv88e6xxx_g1_irq_setup_common(chip); 393 if (err) 394 return err; 395 396 kthread_init_delayed_work(&chip->irq_poll_work, 397 mv88e6xxx_irq_poll); 398 399 chip->kworker = kthread_run_worker(0, "%s", dev_name(chip->dev)); 400 if (IS_ERR(chip->kworker)) 401 return PTR_ERR(chip->kworker); 402 403 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 404 msecs_to_jiffies(100)); 405 406 return 0; 407 } 408 409 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 410 { 411 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 412 kthread_destroy_worker(chip->kworker); 413 414 mv88e6xxx_reg_lock(chip); 415 mv88e6xxx_g1_irq_free_common(chip); 416 mv88e6xxx_reg_unlock(chip); 417 } 418 419 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 420 int port, phy_interface_t interface) 421 { 422 int err; 423 424 if (chip->info->ops->port_set_rgmii_delay) { 425 err = chip->info->ops->port_set_rgmii_delay(chip, port, 426 interface); 427 if (err && err != -EOPNOTSUPP) 428 return err; 429 } 430 431 if (chip->info->ops->port_set_cmode) { 432 err = chip->info->ops->port_set_cmode(chip, port, 433 interface); 434 if (err && err != -EOPNOTSUPP) 435 return err; 436 } 437 438 return 0; 439 } 440 441 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 442 int link, int speed, int duplex, int pause, 443 phy_interface_t mode) 444 { 445 int err; 446 447 if (!chip->info->ops->port_set_link) 448 return 0; 449 450 /* Port's MAC control must not be changed unless the link is down */ 451 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 452 if (err) 453 return err; 454 455 if (chip->info->ops->port_set_speed_duplex) { 456 err = chip->info->ops->port_set_speed_duplex(chip, port, 457 speed, duplex); 458 if (err && err != -EOPNOTSUPP) 459 goto restore_link; 460 } 461 462 if (chip->info->ops->port_set_pause) { 463 err = chip->info->ops->port_set_pause(chip, port, pause); 464 if (err) 465 goto restore_link; 466 } 467 468 err = mv88e6xxx_port_config_interface(chip, port, mode); 469 restore_link: 470 if (chip->info->ops->port_set_link(chip, port, link)) 471 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 472 473 return err; 474 } 475 476 static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port) 477 { 478 return port >= chip->info->internal_phys_offset && 479 port < chip->info->num_internal_phys + 480 chip->info->internal_phys_offset; 481 } 482 483 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 484 { 485 u16 reg; 486 int err; 487 488 /* The 88e6250 family does not have the PHY detect bit. Instead, 489 * report whether the port is internal. 490 */ 491 if (chip->info->family == MV88E6XXX_FAMILY_6250) 492 return mv88e6xxx_phy_is_internal(chip, port); 493 494 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 495 if (err) { 496 dev_err(chip->dev, 497 "p%d: %s: failed to read port status\n", 498 port, __func__); 499 return err; 500 } 501 502 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 503 } 504 505 static const u8 mv88e6185_phy_interface_modes[] = { 506 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII, 507 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII, 508 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII, 509 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII, 510 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX, 511 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX, 512 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII, 513 }; 514 515 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 516 struct phylink_config *config) 517 { 518 u8 cmode = chip->ports[port].cmode; 519 520 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 521 522 if (mv88e6xxx_phy_is_internal(chip, port)) { 523 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 524 } else { 525 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 526 mv88e6185_phy_interface_modes[cmode]) 527 __set_bit(mv88e6185_phy_interface_modes[cmode], 528 config->supported_interfaces); 529 530 config->mac_capabilities |= MAC_1000FD; 531 } 532 } 533 534 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 535 struct phylink_config *config) 536 { 537 u8 cmode = chip->ports[port].cmode; 538 539 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 540 mv88e6185_phy_interface_modes[cmode]) 541 __set_bit(mv88e6185_phy_interface_modes[cmode], 542 config->supported_interfaces); 543 544 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 545 MAC_1000FD; 546 } 547 548 static const u8 mv88e6xxx_phy_interface_modes[] = { 549 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII, 550 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII, 551 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII, 552 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII, 553 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII, 554 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX, 555 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX, 556 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII, 557 /* higher interface modes are not needed here, since ports supporting 558 * them are writable, and so the supported interfaces are filled in the 559 * corresponding .phylink_set_interfaces() implementation below 560 */ 561 }; 562 563 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported) 564 { 565 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) && 566 mv88e6xxx_phy_interface_modes[cmode]) 567 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported); 568 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII) 569 phy_interface_set_rgmii(supported); 570 } 571 572 static void 573 mv88e6250_setup_supported_interfaces(struct mv88e6xxx_chip *chip, int port, 574 struct phylink_config *config) 575 { 576 unsigned long *supported = config->supported_interfaces; 577 int err; 578 u16 reg; 579 580 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 581 if (err) { 582 dev_err(chip->dev, "p%d: failed to read port status\n", port); 583 return; 584 } 585 586 switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) { 587 case MV88E6250_PORT_STS_PORTMODE_MII_10_HALF_PHY: 588 case MV88E6250_PORT_STS_PORTMODE_MII_100_HALF_PHY: 589 case MV88E6250_PORT_STS_PORTMODE_MII_10_FULL_PHY: 590 case MV88E6250_PORT_STS_PORTMODE_MII_100_FULL_PHY: 591 __set_bit(PHY_INTERFACE_MODE_REVMII, supported); 592 break; 593 594 case MV88E6250_PORT_STS_PORTMODE_MII_HALF: 595 case MV88E6250_PORT_STS_PORTMODE_MII_FULL: 596 __set_bit(PHY_INTERFACE_MODE_MII, supported); 597 break; 598 599 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL_PHY: 600 case MV88E6250_PORT_STS_PORTMODE_MII_200_RMII_FULL_PHY: 601 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_HALF_PHY: 602 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL_PHY: 603 __set_bit(PHY_INTERFACE_MODE_REVRMII, supported); 604 break; 605 606 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL: 607 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL: 608 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 609 break; 610 611 case MV88E6250_PORT_STS_PORTMODE_MII_100_RGMII: 612 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 613 break; 614 615 default: 616 dev_err(chip->dev, 617 "p%d: invalid port mode in status register: %04x\n", 618 port, reg); 619 } 620 } 621 622 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 623 struct phylink_config *config) 624 { 625 if (!mv88e6xxx_phy_is_internal(chip, port)) 626 mv88e6250_setup_supported_interfaces(chip, port, config); 627 628 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 629 } 630 631 static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 632 struct phylink_config *config) 633 { 634 unsigned long *supported = config->supported_interfaces; 635 636 /* Translate the default cmode */ 637 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 638 639 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 640 MAC_1000FD; 641 } 642 643 static int mv88e63xx_get_port_serdes_cmode(struct mv88e6xxx_chip *chip, int port) 644 { 645 u16 reg, val; 646 int err; 647 648 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 649 if (err) 650 return err; 651 652 /* If PHY_DETECT is zero, then we are not in auto-media mode */ 653 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT)) 654 return 0xf; 655 656 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT; 657 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, val); 658 if (err) 659 return err; 660 661 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &val); 662 if (err) 663 return err; 664 665 /* Restore PHY_DETECT value */ 666 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); 667 if (err) 668 return err; 669 670 return val & MV88E6XXX_PORT_STS_CMODE_MASK; 671 } 672 673 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 674 struct phylink_config *config) 675 { 676 unsigned long *supported = config->supported_interfaces; 677 int err, cmode; 678 679 /* Translate the default cmode */ 680 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 681 682 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 683 MAC_1000FD; 684 685 /* Port 4 supports automedia if the serdes is associated with it. */ 686 if (port == 4) { 687 err = mv88e6352_g2_scratch_port_has_serdes(chip, port); 688 if (err < 0) 689 dev_err(chip->dev, "p%d: failed to read scratch\n", 690 port); 691 if (err <= 0) 692 return; 693 694 cmode = mv88e63xx_get_port_serdes_cmode(chip, port); 695 if (cmode < 0) 696 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 697 port); 698 else 699 mv88e6xxx_translate_cmode(cmode, supported); 700 } 701 } 702 703 static void mv88e632x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 704 struct phylink_config *config) 705 { 706 unsigned long *supported = config->supported_interfaces; 707 int cmode; 708 709 /* Translate the default cmode */ 710 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 711 712 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 713 MAC_1000FD; 714 715 /* Port 0/1 are serdes only ports */ 716 if (port == 0 || port == 1) { 717 cmode = mv88e63xx_get_port_serdes_cmode(chip, port); 718 if (cmode < 0) 719 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 720 port); 721 else 722 mv88e6xxx_translate_cmode(cmode, supported); 723 } 724 } 725 726 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 727 struct phylink_config *config) 728 { 729 unsigned long *supported = config->supported_interfaces; 730 731 /* Translate the default cmode */ 732 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 733 734 /* No ethtool bits for 200Mbps */ 735 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 736 MAC_1000FD; 737 738 /* The C_Mode field is programmable on port 5 */ 739 if (port == 5) { 740 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 741 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 742 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 743 744 config->mac_capabilities |= MAC_2500FD; 745 } 746 } 747 748 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 749 struct phylink_config *config) 750 { 751 unsigned long *supported = config->supported_interfaces; 752 753 /* Translate the default cmode */ 754 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 755 756 /* No ethtool bits for 200Mbps */ 757 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 758 MAC_1000FD; 759 760 /* The C_Mode field is programmable on ports 9 and 10 */ 761 if (port == 9 || port == 10) { 762 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 763 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 764 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 765 766 config->mac_capabilities |= MAC_2500FD; 767 } 768 } 769 770 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 771 struct phylink_config *config) 772 { 773 unsigned long *supported = config->supported_interfaces; 774 775 mv88e6390_phylink_get_caps(chip, port, config); 776 777 /* For the 6x90X, ports 2-7 can be in automedia mode. 778 * (Note that 6x90 doesn't support RXAUI nor XAUI). 779 * 780 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is 781 * configured for 1000BASE-X, SGMII or 2500BASE-X. 782 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is 783 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 784 * 785 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is 786 * configured for 1000BASE-X, SGMII or 2500BASE-X. 787 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is 788 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 789 * 790 * For now, be permissive (as the old code was) and allow 1000BASE-X 791 * on ports 2..7. 792 */ 793 if (port >= 2 && port <= 7) 794 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 795 796 /* The C_Mode field can also be programmed for 10G speeds */ 797 if (port == 9 || port == 10) { 798 __set_bit(PHY_INTERFACE_MODE_XAUI, supported); 799 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported); 800 801 config->mac_capabilities |= MAC_10000FD; 802 } 803 } 804 805 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 806 struct phylink_config *config) 807 { 808 unsigned long *supported = config->supported_interfaces; 809 bool is_6191x = 810 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 811 bool is_6361 = 812 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361; 813 814 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 815 816 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 817 MAC_1000FD; 818 819 /* The C_Mode field can be programmed for ports 0, 9 and 10 */ 820 if (port == 0 || port == 9 || port == 10) { 821 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 822 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 823 824 /* 6191X supports >1G modes only on port 10 */ 825 if (!is_6191x || port == 10) { 826 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 827 config->mac_capabilities |= MAC_2500FD; 828 829 /* 6361 only supports up to 2500BaseX */ 830 if (!is_6361) { 831 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported); 832 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported); 833 __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); 834 config->mac_capabilities |= MAC_5000FD | 835 MAC_10000FD; 836 } 837 } 838 } 839 840 if (port == 0) { 841 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 842 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 843 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported); 844 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported); 845 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported); 846 } 847 } 848 849 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, 850 struct phylink_config *config) 851 { 852 struct mv88e6xxx_chip *chip = ds->priv; 853 854 mv88e6xxx_reg_lock(chip); 855 chip->info->ops->phylink_get_caps(chip, port, config); 856 mv88e6xxx_reg_unlock(chip); 857 858 if (mv88e6xxx_phy_is_internal(chip, port)) { 859 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 860 config->supported_interfaces); 861 /* Internal ports with no phy-mode need GMII for PHYLIB */ 862 __set_bit(PHY_INTERFACE_MODE_GMII, 863 config->supported_interfaces); 864 } 865 } 866 867 static struct phylink_pcs * 868 mv88e6xxx_mac_select_pcs(struct phylink_config *config, 869 phy_interface_t interface) 870 { 871 struct dsa_port *dp = dsa_phylink_to_port(config); 872 struct mv88e6xxx_chip *chip = dp->ds->priv; 873 struct phylink_pcs *pcs = NULL; 874 875 if (chip->info->ops->pcs_ops) 876 pcs = chip->info->ops->pcs_ops->pcs_select(chip, dp->index, 877 interface); 878 879 return pcs; 880 } 881 882 static int mv88e6xxx_mac_prepare(struct phylink_config *config, 883 unsigned int mode, phy_interface_t interface) 884 { 885 struct dsa_port *dp = dsa_phylink_to_port(config); 886 struct mv88e6xxx_chip *chip = dp->ds->priv; 887 int port = dp->index; 888 int err = 0; 889 890 /* In inband mode, the link may come up at any time while the link 891 * is not forced down. Force the link down while we reconfigure the 892 * interface mode. 893 */ 894 if (mode == MLO_AN_INBAND && 895 chip->ports[port].interface != interface && 896 chip->info->ops->port_set_link) { 897 mv88e6xxx_reg_lock(chip); 898 err = chip->info->ops->port_set_link(chip, port, 899 LINK_FORCED_DOWN); 900 mv88e6xxx_reg_unlock(chip); 901 } 902 903 return err; 904 } 905 906 static void mv88e6xxx_mac_config(struct phylink_config *config, 907 unsigned int mode, 908 const struct phylink_link_state *state) 909 { 910 struct dsa_port *dp = dsa_phylink_to_port(config); 911 struct mv88e6xxx_chip *chip = dp->ds->priv; 912 int port = dp->index; 913 int err = 0; 914 915 mv88e6xxx_reg_lock(chip); 916 917 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) { 918 err = mv88e6xxx_port_config_interface(chip, port, 919 state->interface); 920 if (err && err != -EOPNOTSUPP) 921 goto err_unlock; 922 } 923 924 err_unlock: 925 mv88e6xxx_reg_unlock(chip); 926 927 if (err && err != -EOPNOTSUPP) 928 dev_err(chip->dev, "p%d: failed to configure MAC/PCS\n", port); 929 } 930 931 static int mv88e6xxx_mac_finish(struct phylink_config *config, 932 unsigned int mode, phy_interface_t interface) 933 { 934 struct dsa_port *dp = dsa_phylink_to_port(config); 935 struct mv88e6xxx_chip *chip = dp->ds->priv; 936 int port = dp->index; 937 int err = 0; 938 939 /* Undo the forced down state above after completing configuration 940 * irrespective of its state on entry, which allows the link to come 941 * up in the in-band case where there is no separate SERDES. Also 942 * ensure that the link can come up if the PPU is in use and we are 943 * in PHY mode (we treat the PPU as an effective in-band mechanism.) 944 */ 945 mv88e6xxx_reg_lock(chip); 946 947 if (chip->info->ops->port_set_link && 948 ((mode == MLO_AN_INBAND && 949 chip->ports[port].interface != interface) || 950 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) 951 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 952 953 mv88e6xxx_reg_unlock(chip); 954 955 chip->ports[port].interface = interface; 956 957 return err; 958 } 959 960 static void mv88e6xxx_mac_link_down(struct phylink_config *config, 961 unsigned int mode, 962 phy_interface_t interface) 963 { 964 struct dsa_port *dp = dsa_phylink_to_port(config); 965 struct mv88e6xxx_chip *chip = dp->ds->priv; 966 const struct mv88e6xxx_ops *ops; 967 int port = dp->index; 968 int err = 0; 969 970 ops = chip->info->ops; 971 972 mv88e6xxx_reg_lock(chip); 973 /* Force the link down if we know the port may not be automatically 974 * updated by the switch or if we are using fixed-link mode. 975 */ 976 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 977 mode == MLO_AN_FIXED) && ops->port_sync_link) 978 err = ops->port_sync_link(chip, port, mode, false); 979 980 if (!err && ops->port_set_speed_duplex) 981 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, 982 DUPLEX_UNFORCED); 983 mv88e6xxx_reg_unlock(chip); 984 985 if (err) 986 dev_err(chip->dev, 987 "p%d: failed to force MAC link down\n", port); 988 } 989 990 static void mv88e6xxx_mac_link_up(struct phylink_config *config, 991 struct phy_device *phydev, 992 unsigned int mode, phy_interface_t interface, 993 int speed, int duplex, 994 bool tx_pause, bool rx_pause) 995 { 996 struct dsa_port *dp = dsa_phylink_to_port(config); 997 struct mv88e6xxx_chip *chip = dp->ds->priv; 998 const struct mv88e6xxx_ops *ops; 999 int port = dp->index; 1000 int err = 0; 1001 1002 ops = chip->info->ops; 1003 1004 mv88e6xxx_reg_lock(chip); 1005 /* Configure and force the link up if we know that the port may not 1006 * automatically updated by the switch or if we are using fixed-link 1007 * mode. 1008 */ 1009 if (!mv88e6xxx_port_ppu_updates(chip, port) || 1010 mode == MLO_AN_FIXED) { 1011 if (ops->port_set_speed_duplex) { 1012 err = ops->port_set_speed_duplex(chip, port, 1013 speed, duplex); 1014 if (err && err != -EOPNOTSUPP) 1015 goto error; 1016 } 1017 1018 if (ops->port_sync_link) 1019 err = ops->port_sync_link(chip, port, mode, true); 1020 } 1021 error: 1022 mv88e6xxx_reg_unlock(chip); 1023 1024 if (err && err != -EOPNOTSUPP) 1025 dev_err(chip->dev, 1026 "p%d: failed to configure MAC link up\n", port); 1027 } 1028 1029 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 1030 { 1031 int err; 1032 1033 if (!chip->info->ops->stats_snapshot) 1034 return -EOPNOTSUPP; 1035 1036 mv88e6xxx_reg_lock(chip); 1037 err = chip->info->ops->stats_snapshot(chip, port); 1038 mv88e6xxx_reg_unlock(chip); 1039 1040 return err; 1041 } 1042 1043 #define MV88E6XXX_HW_STAT_MAPPER(_fn) \ 1044 _fn(in_good_octets, 8, 0x00, STATS_TYPE_BANK0), \ 1045 _fn(in_bad_octets, 4, 0x02, STATS_TYPE_BANK0), \ 1046 _fn(in_unicast, 4, 0x04, STATS_TYPE_BANK0), \ 1047 _fn(in_broadcasts, 4, 0x06, STATS_TYPE_BANK0), \ 1048 _fn(in_multicasts, 4, 0x07, STATS_TYPE_BANK0), \ 1049 _fn(in_pause, 4, 0x16, STATS_TYPE_BANK0), \ 1050 _fn(in_undersize, 4, 0x18, STATS_TYPE_BANK0), \ 1051 _fn(in_fragments, 4, 0x19, STATS_TYPE_BANK0), \ 1052 _fn(in_oversize, 4, 0x1a, STATS_TYPE_BANK0), \ 1053 _fn(in_jabber, 4, 0x1b, STATS_TYPE_BANK0), \ 1054 _fn(in_rx_error, 4, 0x1c, STATS_TYPE_BANK0), \ 1055 _fn(in_fcs_error, 4, 0x1d, STATS_TYPE_BANK0), \ 1056 _fn(out_octets, 8, 0x0e, STATS_TYPE_BANK0), \ 1057 _fn(out_unicast, 4, 0x10, STATS_TYPE_BANK0), \ 1058 _fn(out_broadcasts, 4, 0x13, STATS_TYPE_BANK0), \ 1059 _fn(out_multicasts, 4, 0x12, STATS_TYPE_BANK0), \ 1060 _fn(out_pause, 4, 0x15, STATS_TYPE_BANK0), \ 1061 _fn(excessive, 4, 0x11, STATS_TYPE_BANK0), \ 1062 _fn(collisions, 4, 0x1e, STATS_TYPE_BANK0), \ 1063 _fn(deferred, 4, 0x05, STATS_TYPE_BANK0), \ 1064 _fn(single, 4, 0x14, STATS_TYPE_BANK0), \ 1065 _fn(multiple, 4, 0x17, STATS_TYPE_BANK0), \ 1066 _fn(out_fcs_error, 4, 0x03, STATS_TYPE_BANK0), \ 1067 _fn(late, 4, 0x1f, STATS_TYPE_BANK0), \ 1068 _fn(hist_64bytes, 4, 0x08, STATS_TYPE_BANK0), \ 1069 _fn(hist_65_127bytes, 4, 0x09, STATS_TYPE_BANK0), \ 1070 _fn(hist_128_255bytes, 4, 0x0a, STATS_TYPE_BANK0), \ 1071 _fn(hist_256_511bytes, 4, 0x0b, STATS_TYPE_BANK0), \ 1072 _fn(hist_512_1023bytes, 4, 0x0c, STATS_TYPE_BANK0), \ 1073 _fn(hist_1024_max_bytes, 4, 0x0d, STATS_TYPE_BANK0), \ 1074 _fn(sw_in_discards, 4, 0x10, STATS_TYPE_PORT), \ 1075 _fn(sw_in_filtered, 2, 0x12, STATS_TYPE_PORT), \ 1076 _fn(sw_out_filtered, 2, 0x13, STATS_TYPE_PORT), \ 1077 _fn(in_discards, 4, 0x00, STATS_TYPE_BANK1), \ 1078 _fn(in_filtered, 4, 0x01, STATS_TYPE_BANK1), \ 1079 _fn(in_accepted, 4, 0x02, STATS_TYPE_BANK1), \ 1080 _fn(in_bad_accepted, 4, 0x03, STATS_TYPE_BANK1), \ 1081 _fn(in_good_avb_class_a, 4, 0x04, STATS_TYPE_BANK1), \ 1082 _fn(in_good_avb_class_b, 4, 0x05, STATS_TYPE_BANK1), \ 1083 _fn(in_bad_avb_class_a, 4, 0x06, STATS_TYPE_BANK1), \ 1084 _fn(in_bad_avb_class_b, 4, 0x07, STATS_TYPE_BANK1), \ 1085 _fn(tcam_counter_0, 4, 0x08, STATS_TYPE_BANK1), \ 1086 _fn(tcam_counter_1, 4, 0x09, STATS_TYPE_BANK1), \ 1087 _fn(tcam_counter_2, 4, 0x0a, STATS_TYPE_BANK1), \ 1088 _fn(tcam_counter_3, 4, 0x0b, STATS_TYPE_BANK1), \ 1089 _fn(in_da_unknown, 4, 0x0e, STATS_TYPE_BANK1), \ 1090 _fn(in_management, 4, 0x0f, STATS_TYPE_BANK1), \ 1091 _fn(out_queue_0, 4, 0x10, STATS_TYPE_BANK1), \ 1092 _fn(out_queue_1, 4, 0x11, STATS_TYPE_BANK1), \ 1093 _fn(out_queue_2, 4, 0x12, STATS_TYPE_BANK1), \ 1094 _fn(out_queue_3, 4, 0x13, STATS_TYPE_BANK1), \ 1095 _fn(out_queue_4, 4, 0x14, STATS_TYPE_BANK1), \ 1096 _fn(out_queue_5, 4, 0x15, STATS_TYPE_BANK1), \ 1097 _fn(out_queue_6, 4, 0x16, STATS_TYPE_BANK1), \ 1098 _fn(out_queue_7, 4, 0x17, STATS_TYPE_BANK1), \ 1099 _fn(out_cut_through, 4, 0x18, STATS_TYPE_BANK1), \ 1100 _fn(out_octets_a, 4, 0x1a, STATS_TYPE_BANK1), \ 1101 _fn(out_octets_b, 4, 0x1b, STATS_TYPE_BANK1), \ 1102 _fn(out_management, 4, 0x1f, STATS_TYPE_BANK1), \ 1103 /* */ 1104 1105 #define MV88E6XXX_HW_STAT_ENTRY(_string, _size, _reg, _type) \ 1106 { #_string, _size, _reg, _type } 1107 static const struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 1108 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENTRY) 1109 }; 1110 1111 #define MV88E6XXX_HW_STAT_ENUM(_string, _size, _reg, _type) \ 1112 MV88E6XXX_HW_STAT_ID_ ## _string 1113 enum mv88e6xxx_hw_stat_id { 1114 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENUM) 1115 }; 1116 1117 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 1118 const struct mv88e6xxx_hw_stat *s, 1119 int port, u16 bank1_select, 1120 u16 histogram) 1121 { 1122 u32 low; 1123 u32 high = 0; 1124 u16 reg = 0; 1125 int err; 1126 u64 value; 1127 1128 switch (s->type) { 1129 case STATS_TYPE_PORT: 1130 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 1131 if (err) 1132 return U64_MAX; 1133 1134 low = reg; 1135 if (s->size == 4) { 1136 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 1137 if (err) 1138 return U64_MAX; 1139 low |= ((u32)reg) << 16; 1140 } 1141 break; 1142 case STATS_TYPE_BANK1: 1143 reg = bank1_select; 1144 fallthrough; 1145 case STATS_TYPE_BANK0: 1146 reg |= s->reg | histogram; 1147 mv88e6xxx_g1_stats_read(chip, reg, &low); 1148 if (s->size == 8) 1149 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 1150 break; 1151 default: 1152 return U64_MAX; 1153 } 1154 value = (((u64)high) << 32) | low; 1155 return value; 1156 } 1157 1158 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 1159 uint8_t **data, int types) 1160 { 1161 const struct mv88e6xxx_hw_stat *stat; 1162 int i; 1163 1164 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1165 stat = &mv88e6xxx_hw_stats[i]; 1166 if (stat->type & types) 1167 ethtool_puts(data, stat->string); 1168 } 1169 } 1170 1171 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 1172 uint8_t **data) 1173 { 1174 mv88e6xxx_stats_get_strings(chip, data, 1175 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 1176 } 1177 1178 static void mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 1179 uint8_t **data) 1180 { 1181 mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 1182 } 1183 1184 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 1185 uint8_t **data) 1186 { 1187 mv88e6xxx_stats_get_strings(chip, data, 1188 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 1189 } 1190 1191 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 1192 "atu_member_violation", 1193 "atu_miss_violation", 1194 "atu_full_violation", 1195 "vtu_member_violation", 1196 "vtu_miss_violation", 1197 }; 1198 1199 static void mv88e6xxx_atu_vtu_get_strings(uint8_t **data) 1200 { 1201 unsigned int i; 1202 1203 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 1204 ethtool_puts(data, mv88e6xxx_atu_vtu_stats_strings[i]); 1205 } 1206 1207 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 1208 u32 stringset, uint8_t *data) 1209 { 1210 struct mv88e6xxx_chip *chip = ds->priv; 1211 1212 if (stringset != ETH_SS_STATS) 1213 return; 1214 1215 mv88e6xxx_reg_lock(chip); 1216 1217 if (chip->info->ops->stats_get_strings) 1218 chip->info->ops->stats_get_strings(chip, &data); 1219 1220 if (chip->info->ops->serdes_get_strings) 1221 chip->info->ops->serdes_get_strings(chip, port, &data); 1222 1223 mv88e6xxx_atu_vtu_get_strings(&data); 1224 1225 mv88e6xxx_reg_unlock(chip); 1226 } 1227 1228 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1229 int types) 1230 { 1231 const struct mv88e6xxx_hw_stat *stat; 1232 int i, j; 1233 1234 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1235 stat = &mv88e6xxx_hw_stats[i]; 1236 if (stat->type & types) 1237 j++; 1238 } 1239 return j; 1240 } 1241 1242 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1243 { 1244 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1245 STATS_TYPE_PORT); 1246 } 1247 1248 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1249 { 1250 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1251 } 1252 1253 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1254 { 1255 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1256 STATS_TYPE_BANK1); 1257 } 1258 1259 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1260 { 1261 struct mv88e6xxx_chip *chip = ds->priv; 1262 int serdes_count = 0; 1263 int count = 0; 1264 1265 if (sset != ETH_SS_STATS) 1266 return 0; 1267 1268 mv88e6xxx_reg_lock(chip); 1269 if (chip->info->ops->stats_get_sset_count) 1270 count = chip->info->ops->stats_get_sset_count(chip); 1271 if (count < 0) 1272 goto out; 1273 1274 if (chip->info->ops->serdes_get_sset_count) 1275 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1276 port); 1277 if (serdes_count < 0) { 1278 count = serdes_count; 1279 goto out; 1280 } 1281 count += serdes_count; 1282 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1283 1284 out: 1285 mv88e6xxx_reg_unlock(chip); 1286 1287 return count; 1288 } 1289 1290 static size_t mv88e6095_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1291 const struct mv88e6xxx_hw_stat *stat, 1292 uint64_t *data) 1293 { 1294 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0, 1295 MV88E6XXX_G1_STATS_OP_HIST_RX); 1296 return 1; 1297 } 1298 1299 static size_t mv88e6250_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1300 const struct mv88e6xxx_hw_stat *stat, 1301 uint64_t *data) 1302 { 1303 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0, 1304 MV88E6XXX_G1_STATS_OP_HIST_RX); 1305 return 1; 1306 } 1307 1308 static size_t mv88e6320_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1309 const struct mv88e6xxx_hw_stat *stat, 1310 uint64_t *data) 1311 { 1312 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1313 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1314 MV88E6XXX_G1_STATS_OP_HIST_RX); 1315 return 1; 1316 } 1317 1318 static size_t mv88e6390_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1319 const struct mv88e6xxx_hw_stat *stat, 1320 uint64_t *data) 1321 { 1322 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1323 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1324 0); 1325 return 1; 1326 } 1327 1328 static size_t mv88e6xxx_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1329 const struct mv88e6xxx_hw_stat *stat, 1330 uint64_t *data) 1331 { 1332 int ret = 0; 1333 1334 if (!(stat->type & chip->info->stats_type)) 1335 return 0; 1336 1337 if (chip->info->ops->stats_get_stat) { 1338 mv88e6xxx_reg_lock(chip); 1339 ret = chip->info->ops->stats_get_stat(chip, port, stat, data); 1340 mv88e6xxx_reg_unlock(chip); 1341 } 1342 1343 return ret; 1344 } 1345 1346 static size_t mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1347 uint64_t *data) 1348 { 1349 const struct mv88e6xxx_hw_stat *stat; 1350 size_t i, j; 1351 1352 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1353 stat = &mv88e6xxx_hw_stats[i]; 1354 j += mv88e6xxx_stats_get_stat(chip, port, stat, &data[j]); 1355 } 1356 return j; 1357 } 1358 1359 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1360 uint64_t *data) 1361 { 1362 *data++ = chip->ports[port].atu_member_violation; 1363 *data++ = chip->ports[port].atu_miss_violation; 1364 *data++ = chip->ports[port].atu_full_violation; 1365 *data++ = chip->ports[port].vtu_member_violation; 1366 *data++ = chip->ports[port].vtu_miss_violation; 1367 } 1368 1369 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1370 uint64_t *data) 1371 { 1372 size_t count; 1373 1374 count = mv88e6xxx_stats_get_stats(chip, port, data); 1375 1376 mv88e6xxx_reg_lock(chip); 1377 if (chip->info->ops->serdes_get_stats) { 1378 data += count; 1379 count = chip->info->ops->serdes_get_stats(chip, port, data); 1380 } 1381 data += count; 1382 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1383 mv88e6xxx_reg_unlock(chip); 1384 } 1385 1386 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1387 uint64_t *data) 1388 { 1389 struct mv88e6xxx_chip *chip = ds->priv; 1390 int ret; 1391 1392 ret = mv88e6xxx_stats_snapshot(chip, port); 1393 if (ret < 0) 1394 return; 1395 1396 mv88e6xxx_get_stats(chip, port, data); 1397 } 1398 1399 static void mv88e6xxx_get_eth_mac_stats(struct dsa_switch *ds, int port, 1400 struct ethtool_eth_mac_stats *mac_stats) 1401 { 1402 struct mv88e6xxx_chip *chip = ds->priv; 1403 int ret; 1404 1405 ret = mv88e6xxx_stats_snapshot(chip, port); 1406 if (ret < 0) 1407 return; 1408 1409 #define MV88E6XXX_ETH_MAC_STAT_MAP(_id, _member) \ 1410 mv88e6xxx_stats_get_stat(chip, port, \ 1411 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \ 1412 &mac_stats->stats._member) 1413 1414 MV88E6XXX_ETH_MAC_STAT_MAP(out_unicast, FramesTransmittedOK); 1415 MV88E6XXX_ETH_MAC_STAT_MAP(single, SingleCollisionFrames); 1416 MV88E6XXX_ETH_MAC_STAT_MAP(multiple, MultipleCollisionFrames); 1417 MV88E6XXX_ETH_MAC_STAT_MAP(in_unicast, FramesReceivedOK); 1418 MV88E6XXX_ETH_MAC_STAT_MAP(in_fcs_error, FrameCheckSequenceErrors); 1419 MV88E6XXX_ETH_MAC_STAT_MAP(out_octets, OctetsTransmittedOK); 1420 MV88E6XXX_ETH_MAC_STAT_MAP(deferred, FramesWithDeferredXmissions); 1421 MV88E6XXX_ETH_MAC_STAT_MAP(late, LateCollisions); 1422 MV88E6XXX_ETH_MAC_STAT_MAP(in_good_octets, OctetsReceivedOK); 1423 MV88E6XXX_ETH_MAC_STAT_MAP(out_multicasts, MulticastFramesXmittedOK); 1424 MV88E6XXX_ETH_MAC_STAT_MAP(out_broadcasts, BroadcastFramesXmittedOK); 1425 MV88E6XXX_ETH_MAC_STAT_MAP(excessive, FramesWithExcessiveDeferral); 1426 MV88E6XXX_ETH_MAC_STAT_MAP(in_multicasts, MulticastFramesReceivedOK); 1427 MV88E6XXX_ETH_MAC_STAT_MAP(in_broadcasts, BroadcastFramesReceivedOK); 1428 1429 #undef MV88E6XXX_ETH_MAC_STAT_MAP 1430 1431 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.MulticastFramesXmittedOK; 1432 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.BroadcastFramesXmittedOK; 1433 mac_stats->stats.FramesReceivedOK += mac_stats->stats.MulticastFramesReceivedOK; 1434 mac_stats->stats.FramesReceivedOK += mac_stats->stats.BroadcastFramesReceivedOK; 1435 } 1436 1437 static void mv88e6xxx_get_rmon_stats(struct dsa_switch *ds, int port, 1438 struct ethtool_rmon_stats *rmon_stats, 1439 const struct ethtool_rmon_hist_range **ranges) 1440 { 1441 static const struct ethtool_rmon_hist_range rmon_ranges[] = { 1442 { 64, 64 }, 1443 { 65, 127 }, 1444 { 128, 255 }, 1445 { 256, 511 }, 1446 { 512, 1023 }, 1447 { 1024, 65535 }, 1448 {} 1449 }; 1450 struct mv88e6xxx_chip *chip = ds->priv; 1451 int ret; 1452 1453 ret = mv88e6xxx_stats_snapshot(chip, port); 1454 if (ret < 0) 1455 return; 1456 1457 #define MV88E6XXX_RMON_STAT_MAP(_id, _member) \ 1458 mv88e6xxx_stats_get_stat(chip, port, \ 1459 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \ 1460 &rmon_stats->stats._member) 1461 1462 MV88E6XXX_RMON_STAT_MAP(in_undersize, undersize_pkts); 1463 MV88E6XXX_RMON_STAT_MAP(in_oversize, oversize_pkts); 1464 MV88E6XXX_RMON_STAT_MAP(in_fragments, fragments); 1465 MV88E6XXX_RMON_STAT_MAP(in_jabber, jabbers); 1466 MV88E6XXX_RMON_STAT_MAP(hist_64bytes, hist[0]); 1467 MV88E6XXX_RMON_STAT_MAP(hist_65_127bytes, hist[1]); 1468 MV88E6XXX_RMON_STAT_MAP(hist_128_255bytes, hist[2]); 1469 MV88E6XXX_RMON_STAT_MAP(hist_256_511bytes, hist[3]); 1470 MV88E6XXX_RMON_STAT_MAP(hist_512_1023bytes, hist[4]); 1471 MV88E6XXX_RMON_STAT_MAP(hist_1024_max_bytes, hist[5]); 1472 1473 #undef MV88E6XXX_RMON_STAT_MAP 1474 1475 *ranges = rmon_ranges; 1476 } 1477 1478 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1479 { 1480 struct mv88e6xxx_chip *chip = ds->priv; 1481 int len; 1482 1483 len = 32 * sizeof(u16); 1484 if (chip->info->ops->serdes_get_regs_len) 1485 len += chip->info->ops->serdes_get_regs_len(chip, port); 1486 1487 return len; 1488 } 1489 1490 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1491 struct ethtool_regs *regs, void *_p) 1492 { 1493 struct mv88e6xxx_chip *chip = ds->priv; 1494 int err; 1495 u16 reg; 1496 u16 *p = _p; 1497 int i; 1498 1499 regs->version = chip->info->prod_num; 1500 1501 memset(p, 0xff, 32 * sizeof(u16)); 1502 1503 mv88e6xxx_reg_lock(chip); 1504 1505 for (i = 0; i < 32; i++) { 1506 1507 err = mv88e6xxx_port_read(chip, port, i, ®); 1508 if (!err) 1509 p[i] = reg; 1510 } 1511 1512 if (chip->info->ops->serdes_get_regs) 1513 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1514 1515 mv88e6xxx_reg_unlock(chip); 1516 } 1517 1518 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1519 struct ethtool_keee *e) 1520 { 1521 /* Nothing to do on the port's MAC */ 1522 return 0; 1523 } 1524 1525 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1526 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1527 { 1528 struct dsa_switch *ds = chip->ds; 1529 struct dsa_switch_tree *dst = ds->dst; 1530 struct dsa_port *dp, *other_dp; 1531 bool found = false; 1532 u16 pvlan; 1533 1534 /* dev is a physical switch */ 1535 if (dev <= dst->last_switch) { 1536 list_for_each_entry(dp, &dst->ports, list) { 1537 if (dp->ds->index == dev && dp->index == port) { 1538 /* dp might be a DSA link or a user port, so it 1539 * might or might not have a bridge. 1540 * Use the "found" variable for both cases. 1541 */ 1542 found = true; 1543 break; 1544 } 1545 } 1546 /* dev is a virtual bridge */ 1547 } else { 1548 list_for_each_entry(dp, &dst->ports, list) { 1549 unsigned int bridge_num = dsa_port_bridge_num_get(dp); 1550 1551 if (!bridge_num) 1552 continue; 1553 1554 if (bridge_num + dst->last_switch != dev) 1555 continue; 1556 1557 found = true; 1558 break; 1559 } 1560 } 1561 1562 /* Prevent frames from unknown switch or virtual bridge */ 1563 if (!found) 1564 return 0; 1565 1566 /* Frames from DSA links and CPU ports can egress any local port */ 1567 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1568 return mv88e6xxx_port_mask(chip); 1569 1570 pvlan = 0; 1571 1572 /* Frames from standalone user ports can only egress on the 1573 * upstream port. 1574 */ 1575 if (!dsa_port_bridge_dev_get(dp)) 1576 return BIT(dsa_switch_upstream_port(ds)); 1577 1578 /* Frames from bridged user ports can egress any local DSA 1579 * links and CPU ports, as well as any local member of their 1580 * bridge group. 1581 */ 1582 dsa_switch_for_each_port(other_dp, ds) 1583 if (other_dp->type == DSA_PORT_TYPE_CPU || 1584 other_dp->type == DSA_PORT_TYPE_DSA || 1585 dsa_port_bridge_same(dp, other_dp)) 1586 pvlan |= BIT(other_dp->index); 1587 1588 return pvlan; 1589 } 1590 1591 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1592 { 1593 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1594 1595 /* prevent frames from going back out of the port they came in on */ 1596 output_ports &= ~BIT(port); 1597 1598 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1599 } 1600 1601 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1602 u8 state) 1603 { 1604 struct mv88e6xxx_chip *chip = ds->priv; 1605 int err; 1606 1607 mv88e6xxx_reg_lock(chip); 1608 err = mv88e6xxx_port_set_state(chip, port, state); 1609 mv88e6xxx_reg_unlock(chip); 1610 1611 if (err) 1612 dev_err(ds->dev, "p%d: failed to update state\n", port); 1613 } 1614 1615 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1616 { 1617 int err; 1618 1619 if (chip->info->ops->ieee_pri_map) { 1620 err = chip->info->ops->ieee_pri_map(chip); 1621 if (err) 1622 return err; 1623 } 1624 1625 if (chip->info->ops->ip_pri_map) { 1626 err = chip->info->ops->ip_pri_map(chip); 1627 if (err) 1628 return err; 1629 } 1630 1631 return 0; 1632 } 1633 1634 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1635 { 1636 struct dsa_switch *ds = chip->ds; 1637 int target, port; 1638 int err; 1639 1640 if (!chip->info->global2_addr) 1641 return 0; 1642 1643 /* Initialize the routing port to the 32 possible target devices */ 1644 for (target = 0; target < 32; target++) { 1645 port = dsa_routing_port(ds, target); 1646 if (port == ds->num_ports) 1647 port = 0x1f; 1648 1649 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1650 if (err) 1651 return err; 1652 } 1653 1654 if (chip->info->ops->set_cascade_port) { 1655 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1656 err = chip->info->ops->set_cascade_port(chip, port); 1657 if (err) 1658 return err; 1659 } 1660 1661 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1662 if (err) 1663 return err; 1664 1665 return 0; 1666 } 1667 1668 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1669 { 1670 /* Clear all trunk masks and mapping */ 1671 if (chip->info->global2_addr) 1672 return mv88e6xxx_g2_trunk_clear(chip); 1673 1674 return 0; 1675 } 1676 1677 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1678 { 1679 if (chip->info->ops->rmu_disable) 1680 return chip->info->ops->rmu_disable(chip); 1681 1682 return 0; 1683 } 1684 1685 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1686 { 1687 if (chip->info->ops->pot_clear) 1688 return chip->info->ops->pot_clear(chip); 1689 1690 return 0; 1691 } 1692 1693 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1694 { 1695 if (chip->info->ops->mgmt_rsvd2cpu) 1696 return chip->info->ops->mgmt_rsvd2cpu(chip); 1697 1698 return 0; 1699 } 1700 1701 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1702 { 1703 int err; 1704 1705 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1706 if (err) 1707 return err; 1708 1709 /* The chips that have a "learn2all" bit in Global1, ATU 1710 * Control are precisely those whose port registers have a 1711 * Message Port bit in Port Control 1 and hence implement 1712 * ->port_setup_message_port. 1713 */ 1714 if (chip->info->ops->port_setup_message_port) { 1715 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1716 if (err) 1717 return err; 1718 } 1719 1720 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1721 } 1722 1723 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1724 { 1725 int port; 1726 int err; 1727 1728 if (!chip->info->ops->irl_init_all) 1729 return 0; 1730 1731 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1732 /* Disable ingress rate limiting by resetting all per port 1733 * ingress rate limit resources to their initial state. 1734 */ 1735 err = chip->info->ops->irl_init_all(chip, port); 1736 if (err) 1737 return err; 1738 } 1739 1740 return 0; 1741 } 1742 1743 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1744 { 1745 if (chip->info->ops->set_switch_mac) { 1746 u8 addr[ETH_ALEN]; 1747 1748 eth_random_addr(addr); 1749 1750 return chip->info->ops->set_switch_mac(chip, addr); 1751 } 1752 1753 return 0; 1754 } 1755 1756 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1757 { 1758 struct dsa_switch_tree *dst = chip->ds->dst; 1759 struct dsa_switch *ds; 1760 struct dsa_port *dp; 1761 u16 pvlan = 0; 1762 1763 if (!mv88e6xxx_has_pvt(chip)) 1764 return 0; 1765 1766 /* Skip the local source device, which uses in-chip port VLAN */ 1767 if (dev != chip->ds->index) { 1768 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1769 1770 ds = dsa_switch_find(dst->index, dev); 1771 dp = ds ? dsa_to_port(ds, port) : NULL; 1772 if (dp && dp->lag) { 1773 /* As the PVT is used to limit flooding of 1774 * FORWARD frames, which use the LAG ID as the 1775 * source port, we must translate dev/port to 1776 * the special "LAG device" in the PVT, using 1777 * the LAG ID (one-based) as the port number 1778 * (zero-based). 1779 */ 1780 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1781 port = dsa_port_lag_id_get(dp) - 1; 1782 } 1783 } 1784 1785 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1786 } 1787 1788 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1789 { 1790 int dev, port; 1791 int err; 1792 1793 if (!mv88e6xxx_has_pvt(chip)) 1794 return 0; 1795 1796 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1797 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1798 */ 1799 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1800 if (err) 1801 return err; 1802 1803 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1804 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1805 err = mv88e6xxx_pvt_map(chip, dev, port); 1806 if (err) 1807 return err; 1808 } 1809 } 1810 1811 return 0; 1812 } 1813 1814 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port, 1815 u16 fid) 1816 { 1817 if (dsa_to_port(chip->ds, port)->lag) 1818 /* Hardware is incapable of fast-aging a LAG through a 1819 * regular ATU move operation. Until we have something 1820 * more fancy in place this is a no-op. 1821 */ 1822 return -EOPNOTSUPP; 1823 1824 return mv88e6xxx_g1_atu_remove(chip, fid, port, false); 1825 } 1826 1827 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1828 { 1829 struct mv88e6xxx_chip *chip = ds->priv; 1830 int err; 1831 1832 mv88e6xxx_reg_lock(chip); 1833 err = mv88e6xxx_port_fast_age_fid(chip, port, 0); 1834 mv88e6xxx_reg_unlock(chip); 1835 1836 if (err) 1837 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n", 1838 port, err); 1839 } 1840 1841 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1842 { 1843 if (!mv88e6xxx_max_vid(chip)) 1844 return 0; 1845 1846 return mv88e6xxx_g1_vtu_flush(chip); 1847 } 1848 1849 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1850 struct mv88e6xxx_vtu_entry *entry) 1851 { 1852 int err; 1853 1854 if (!chip->info->ops->vtu_getnext) 1855 return -EOPNOTSUPP; 1856 1857 memset(entry, 0, sizeof(*entry)); 1858 1859 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1860 entry->valid = false; 1861 1862 err = chip->info->ops->vtu_getnext(chip, entry); 1863 1864 if (entry->vid != vid) 1865 entry->valid = false; 1866 1867 return err; 1868 } 1869 1870 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1871 int (*cb)(struct mv88e6xxx_chip *chip, 1872 const struct mv88e6xxx_vtu_entry *entry, 1873 void *priv), 1874 void *priv) 1875 { 1876 struct mv88e6xxx_vtu_entry entry = { 1877 .vid = mv88e6xxx_max_vid(chip), 1878 .valid = false, 1879 }; 1880 int err; 1881 1882 if (!chip->info->ops->vtu_getnext) 1883 return -EOPNOTSUPP; 1884 1885 do { 1886 err = chip->info->ops->vtu_getnext(chip, &entry); 1887 if (err) 1888 return err; 1889 1890 if (!entry.valid) 1891 break; 1892 1893 err = cb(chip, &entry, priv); 1894 if (err) 1895 return err; 1896 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1897 1898 return 0; 1899 } 1900 1901 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1902 struct mv88e6xxx_vtu_entry *entry) 1903 { 1904 if (!chip->info->ops->vtu_loadpurge) 1905 return -EOPNOTSUPP; 1906 1907 return chip->info->ops->vtu_loadpurge(chip, entry); 1908 } 1909 1910 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1911 { 1912 *fid = find_first_zero_bit(chip->fid_bitmap, MV88E6XXX_N_FID); 1913 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1914 return -ENOSPC; 1915 1916 /* Clear the database */ 1917 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1918 } 1919 1920 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, 1921 struct mv88e6xxx_stu_entry *entry) 1922 { 1923 if (!chip->info->ops->stu_loadpurge) 1924 return -EOPNOTSUPP; 1925 1926 return chip->info->ops->stu_loadpurge(chip, entry); 1927 } 1928 1929 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip) 1930 { 1931 struct mv88e6xxx_stu_entry stu = { 1932 .valid = true, 1933 .sid = 0 1934 }; 1935 1936 if (!mv88e6xxx_has_stu(chip)) 1937 return 0; 1938 1939 /* Make sure that SID 0 is always valid. This is used by VTU 1940 * entries that do not make use of the STU, e.g. when creating 1941 * a VLAN upper on a port that is also part of a VLAN 1942 * filtering bridge. 1943 */ 1944 return mv88e6xxx_stu_loadpurge(chip, &stu); 1945 } 1946 1947 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid) 1948 { 1949 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 }; 1950 struct mv88e6xxx_mst *mst; 1951 1952 __set_bit(0, busy); 1953 1954 list_for_each_entry(mst, &chip->msts, node) 1955 __set_bit(mst->stu.sid, busy); 1956 1957 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID); 1958 1959 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0; 1960 } 1961 1962 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid) 1963 { 1964 struct mv88e6xxx_mst *mst, *tmp; 1965 int err; 1966 1967 /* If the SID is zero, it is for a VLAN mapped to the default MSTI, 1968 * and mv88e6xxx_stu_setup() made sure it is always present, and thus, 1969 * should not be removed here. 1970 * 1971 * If the chip lacks STU support, numerically the "sid" variable will 1972 * happen to also be zero, but we don't want to rely on that fact, so 1973 * we explicitly test that first. In that case, there is also nothing 1974 * to do here. 1975 */ 1976 if (!mv88e6xxx_has_stu(chip) || !sid) 1977 return 0; 1978 1979 list_for_each_entry_safe(mst, tmp, &chip->msts, node) { 1980 if (mst->stu.sid != sid) 1981 continue; 1982 1983 if (!refcount_dec_and_test(&mst->refcnt)) 1984 return 0; 1985 1986 mst->stu.valid = false; 1987 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1988 if (err) { 1989 refcount_set(&mst->refcnt, 1); 1990 return err; 1991 } 1992 1993 list_del(&mst->node); 1994 kfree(mst); 1995 return 0; 1996 } 1997 1998 return -ENOENT; 1999 } 2000 2001 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br, 2002 u16 msti, u8 *sid) 2003 { 2004 struct mv88e6xxx_mst *mst; 2005 int err, i; 2006 2007 if (!mv88e6xxx_has_stu(chip)) { 2008 err = -EOPNOTSUPP; 2009 goto err; 2010 } 2011 2012 if (!msti) { 2013 *sid = 0; 2014 return 0; 2015 } 2016 2017 list_for_each_entry(mst, &chip->msts, node) { 2018 if (mst->br == br && mst->msti == msti) { 2019 refcount_inc(&mst->refcnt); 2020 *sid = mst->stu.sid; 2021 return 0; 2022 } 2023 } 2024 2025 err = mv88e6xxx_sid_get(chip, sid); 2026 if (err) 2027 goto err; 2028 2029 mst = kzalloc_obj(*mst); 2030 if (!mst) { 2031 err = -ENOMEM; 2032 goto err; 2033 } 2034 2035 INIT_LIST_HEAD(&mst->node); 2036 refcount_set(&mst->refcnt, 1); 2037 mst->br = br; 2038 mst->msti = msti; 2039 mst->stu.valid = true; 2040 mst->stu.sid = *sid; 2041 2042 /* The bridge starts out all ports in the disabled state. But 2043 * a STU state of disabled means to go by the port-global 2044 * state. So we set all user port's initial state to blocking, 2045 * to match the bridge's behavior. 2046 */ 2047 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 2048 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ? 2049 MV88E6XXX_PORT_CTL0_STATE_BLOCKING : 2050 MV88E6XXX_PORT_CTL0_STATE_DISABLED; 2051 2052 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 2053 if (err) 2054 goto err_free; 2055 2056 list_add_tail(&mst->node, &chip->msts); 2057 return 0; 2058 2059 err_free: 2060 kfree(mst); 2061 err: 2062 return err; 2063 } 2064 2065 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port, 2066 const struct switchdev_mst_state *st) 2067 { 2068 struct dsa_port *dp = dsa_to_port(ds, port); 2069 struct mv88e6xxx_chip *chip = ds->priv; 2070 struct mv88e6xxx_mst *mst; 2071 u8 state; 2072 int err; 2073 2074 if (!mv88e6xxx_has_stu(chip)) 2075 return -EOPNOTSUPP; 2076 2077 switch (st->state) { 2078 case BR_STATE_DISABLED: 2079 case BR_STATE_BLOCKING: 2080 case BR_STATE_LISTENING: 2081 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 2082 break; 2083 case BR_STATE_LEARNING: 2084 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 2085 break; 2086 case BR_STATE_FORWARDING: 2087 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2088 break; 2089 default: 2090 return -EINVAL; 2091 } 2092 2093 list_for_each_entry(mst, &chip->msts, node) { 2094 if (mst->br == dsa_port_bridge_dev_get(dp) && 2095 mst->msti == st->msti) { 2096 if (mst->stu.state[port] == state) 2097 return 0; 2098 2099 mst->stu.state[port] = state; 2100 mv88e6xxx_reg_lock(chip); 2101 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 2102 mv88e6xxx_reg_unlock(chip); 2103 return err; 2104 } 2105 } 2106 2107 return -ENOENT; 2108 } 2109 2110 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 2111 u16 vid) 2112 { 2113 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 2114 struct mv88e6xxx_chip *chip = ds->priv; 2115 struct mv88e6xxx_vtu_entry vlan; 2116 int err; 2117 2118 /* DSA and CPU ports have to be members of multiple vlans */ 2119 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) 2120 return 0; 2121 2122 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2123 if (err) 2124 return err; 2125 2126 if (!vlan.valid) 2127 return 0; 2128 2129 dsa_switch_for_each_user_port(other_dp, ds) { 2130 struct net_device *other_br; 2131 2132 if (vlan.member[other_dp->index] == 2133 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2134 continue; 2135 2136 if (dsa_port_bridge_same(dp, other_dp)) 2137 break; /* same bridge, check next VLAN */ 2138 2139 other_br = dsa_port_bridge_dev_get(other_dp); 2140 if (!other_br) 2141 continue; 2142 2143 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 2144 port, vlan.vid, other_dp->index, netdev_name(other_br)); 2145 return -EOPNOTSUPP; 2146 } 2147 2148 return 0; 2149 } 2150 2151 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 2152 { 2153 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2154 struct net_device *br = dsa_port_bridge_dev_get(dp); 2155 struct mv88e6xxx_port *p = &chip->ports[port]; 2156 u16 pvid = MV88E6XXX_VID_STANDALONE; 2157 bool drop_untagged = false; 2158 int err; 2159 2160 if (br) { 2161 if (br_vlan_enabled(br)) { 2162 pvid = p->bridge_pvid.vid; 2163 drop_untagged = !p->bridge_pvid.valid; 2164 } else { 2165 pvid = MV88E6XXX_VID_BRIDGED; 2166 } 2167 } 2168 2169 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 2170 if (err) 2171 return err; 2172 2173 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 2174 } 2175 2176 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 2177 bool vlan_filtering, 2178 struct netlink_ext_ack *extack) 2179 { 2180 struct mv88e6xxx_chip *chip = ds->priv; 2181 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 2182 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 2183 int err; 2184 2185 if (!mv88e6xxx_max_vid(chip)) 2186 return -EOPNOTSUPP; 2187 2188 mv88e6xxx_reg_lock(chip); 2189 2190 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 2191 if (err) 2192 goto unlock; 2193 2194 err = mv88e6xxx_port_commit_pvid(chip, port); 2195 if (err) 2196 goto unlock; 2197 2198 unlock: 2199 mv88e6xxx_reg_unlock(chip); 2200 2201 return err; 2202 } 2203 2204 static int 2205 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 2206 const struct switchdev_obj_port_vlan *vlan) 2207 { 2208 struct mv88e6xxx_chip *chip = ds->priv; 2209 int err; 2210 2211 if (!mv88e6xxx_max_vid(chip)) 2212 return -EOPNOTSUPP; 2213 2214 /* If the requested port doesn't belong to the same bridge as the VLAN 2215 * members, do not support it (yet) and fallback to software VLAN. 2216 */ 2217 mv88e6xxx_reg_lock(chip); 2218 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 2219 mv88e6xxx_reg_unlock(chip); 2220 2221 return err; 2222 } 2223 2224 static int mv88e6xxx_port_db_get(struct mv88e6xxx_chip *chip, 2225 const unsigned char *addr, u16 vid, 2226 u16 *fid, struct mv88e6xxx_atu_entry *entry) 2227 { 2228 struct mv88e6xxx_vtu_entry vlan; 2229 int err; 2230 2231 /* Ports have two private address databases: one for when the port is 2232 * standalone and one for when the port is under a bridge and the 2233 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 2234 * address database to remain 100% empty, so we never load an ATU entry 2235 * into a standalone port's database. Therefore, translate the null 2236 * VLAN ID into the port's database used for VLAN-unaware bridging. 2237 */ 2238 if (vid == 0) { 2239 *fid = MV88E6XXX_FID_BRIDGED; 2240 } else { 2241 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2242 if (err) 2243 return err; 2244 2245 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 2246 if (!vlan.valid) 2247 return -EOPNOTSUPP; 2248 2249 *fid = vlan.fid; 2250 } 2251 2252 entry->state = 0; 2253 ether_addr_copy(entry->mac, addr); 2254 eth_addr_dec(entry->mac); 2255 2256 return mv88e6xxx_g1_atu_getnext(chip, *fid, entry); 2257 } 2258 2259 static bool mv88e6xxx_port_db_find(struct mv88e6xxx_chip *chip, 2260 const unsigned char *addr, u16 vid) 2261 { 2262 struct mv88e6xxx_atu_entry entry; 2263 u16 fid; 2264 int err; 2265 2266 err = mv88e6xxx_port_db_get(chip, addr, vid, &fid, &entry); 2267 if (err) 2268 return false; 2269 2270 return entry.state && ether_addr_equal(entry.mac, addr); 2271 } 2272 2273 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 2274 const unsigned char *addr, u16 vid, 2275 u8 state) 2276 { 2277 struct mv88e6xxx_atu_entry entry; 2278 u16 fid; 2279 int err; 2280 2281 err = mv88e6xxx_port_db_get(chip, addr, vid, &fid, &entry); 2282 if (err) 2283 return err; 2284 2285 /* Initialize a fresh ATU entry if it isn't found */ 2286 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 2287 memset(&entry, 0, sizeof(entry)); 2288 ether_addr_copy(entry.mac, addr); 2289 } 2290 2291 /* Purge the ATU entry only if no port is using it anymore */ 2292 if (!state) { 2293 entry.portvec &= ~BIT(port); 2294 if (!entry.portvec) 2295 entry.state = 0; 2296 } else { 2297 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 2298 entry.portvec = BIT(port); 2299 else 2300 entry.portvec |= BIT(port); 2301 2302 entry.state = state; 2303 } 2304 2305 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 2306 } 2307 2308 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 2309 const struct mv88e6xxx_policy *policy) 2310 { 2311 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 2312 enum mv88e6xxx_policy_action action = policy->action; 2313 const u8 *addr = policy->addr; 2314 u16 vid = policy->vid; 2315 u8 state; 2316 int err; 2317 int id; 2318 2319 if (!chip->info->ops->port_set_policy) 2320 return -EOPNOTSUPP; 2321 2322 switch (mapping) { 2323 case MV88E6XXX_POLICY_MAPPING_DA: 2324 case MV88E6XXX_POLICY_MAPPING_SA: 2325 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2326 state = 0; /* Dissociate the port and address */ 2327 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2328 is_multicast_ether_addr(addr)) 2329 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 2330 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2331 is_unicast_ether_addr(addr)) 2332 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 2333 else 2334 return -EOPNOTSUPP; 2335 2336 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2337 state); 2338 if (err) 2339 return err; 2340 break; 2341 default: 2342 return -EOPNOTSUPP; 2343 } 2344 2345 /* Skip the port's policy clearing if the mapping is still in use */ 2346 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2347 idr_for_each_entry(&chip->policies, policy, id) 2348 if (policy->port == port && 2349 policy->mapping == mapping && 2350 policy->action != action) 2351 return 0; 2352 2353 return chip->info->ops->port_set_policy(chip, port, mapping, action); 2354 } 2355 2356 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 2357 struct ethtool_rx_flow_spec *fs) 2358 { 2359 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 2360 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 2361 enum mv88e6xxx_policy_mapping mapping; 2362 enum mv88e6xxx_policy_action action; 2363 struct mv88e6xxx_policy *policy; 2364 u16 vid = 0; 2365 u8 *addr; 2366 int err; 2367 int id; 2368 2369 if (fs->location != RX_CLS_LOC_ANY) 2370 return -EINVAL; 2371 2372 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 2373 action = MV88E6XXX_POLICY_ACTION_DISCARD; 2374 else 2375 return -EOPNOTSUPP; 2376 2377 switch (fs->flow_type & ~FLOW_EXT) { 2378 case ETHER_FLOW: 2379 if (!is_zero_ether_addr(mac_mask->h_dest) && 2380 is_zero_ether_addr(mac_mask->h_source)) { 2381 mapping = MV88E6XXX_POLICY_MAPPING_DA; 2382 addr = mac_entry->h_dest; 2383 } else if (is_zero_ether_addr(mac_mask->h_dest) && 2384 !is_zero_ether_addr(mac_mask->h_source)) { 2385 mapping = MV88E6XXX_POLICY_MAPPING_SA; 2386 addr = mac_entry->h_source; 2387 } else { 2388 /* Cannot support DA and SA mapping in the same rule */ 2389 return -EOPNOTSUPP; 2390 } 2391 break; 2392 default: 2393 return -EOPNOTSUPP; 2394 } 2395 2396 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 2397 if (fs->m_ext.vlan_tci != htons(0xffff)) 2398 return -EOPNOTSUPP; 2399 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 2400 } 2401 2402 idr_for_each_entry(&chip->policies, policy, id) { 2403 if (policy->port == port && policy->mapping == mapping && 2404 policy->action == action && policy->vid == vid && 2405 ether_addr_equal(policy->addr, addr)) 2406 return -EEXIST; 2407 } 2408 2409 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 2410 if (!policy) 2411 return -ENOMEM; 2412 2413 fs->location = 0; 2414 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 2415 GFP_KERNEL); 2416 if (err) { 2417 devm_kfree(chip->dev, policy); 2418 return err; 2419 } 2420 2421 memcpy(&policy->fs, fs, sizeof(*fs)); 2422 ether_addr_copy(policy->addr, addr); 2423 policy->mapping = mapping; 2424 policy->action = action; 2425 policy->port = port; 2426 policy->vid = vid; 2427 2428 err = mv88e6xxx_policy_apply(chip, port, policy); 2429 if (err) { 2430 idr_remove(&chip->policies, fs->location); 2431 devm_kfree(chip->dev, policy); 2432 return err; 2433 } 2434 2435 return 0; 2436 } 2437 2438 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 2439 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 2440 { 2441 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2442 struct mv88e6xxx_chip *chip = ds->priv; 2443 struct mv88e6xxx_policy *policy; 2444 int err; 2445 int id; 2446 2447 mv88e6xxx_reg_lock(chip); 2448 2449 switch (rxnfc->cmd) { 2450 case ETHTOOL_GRXCLSRLCNT: 2451 rxnfc->data = 0; 2452 rxnfc->data |= RX_CLS_LOC_SPECIAL; 2453 rxnfc->rule_cnt = 0; 2454 idr_for_each_entry(&chip->policies, policy, id) 2455 if (policy->port == port) 2456 rxnfc->rule_cnt++; 2457 err = 0; 2458 break; 2459 case ETHTOOL_GRXCLSRULE: 2460 err = -ENOENT; 2461 policy = idr_find(&chip->policies, fs->location); 2462 if (policy) { 2463 memcpy(fs, &policy->fs, sizeof(*fs)); 2464 err = 0; 2465 } 2466 break; 2467 case ETHTOOL_GRXCLSRLALL: 2468 rxnfc->data = 0; 2469 rxnfc->rule_cnt = 0; 2470 idr_for_each_entry(&chip->policies, policy, id) 2471 if (policy->port == port) 2472 rule_locs[rxnfc->rule_cnt++] = id; 2473 err = 0; 2474 break; 2475 default: 2476 err = -EOPNOTSUPP; 2477 break; 2478 } 2479 2480 mv88e6xxx_reg_unlock(chip); 2481 2482 return err; 2483 } 2484 2485 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2486 struct ethtool_rxnfc *rxnfc) 2487 { 2488 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2489 struct mv88e6xxx_chip *chip = ds->priv; 2490 struct mv88e6xxx_policy *policy; 2491 int err; 2492 2493 mv88e6xxx_reg_lock(chip); 2494 2495 switch (rxnfc->cmd) { 2496 case ETHTOOL_SRXCLSRLINS: 2497 err = mv88e6xxx_policy_insert(chip, port, fs); 2498 break; 2499 case ETHTOOL_SRXCLSRLDEL: 2500 err = -ENOENT; 2501 policy = idr_remove(&chip->policies, fs->location); 2502 if (policy) { 2503 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2504 err = mv88e6xxx_policy_apply(chip, port, policy); 2505 devm_kfree(chip->dev, policy); 2506 } 2507 break; 2508 default: 2509 err = -EOPNOTSUPP; 2510 break; 2511 } 2512 2513 mv88e6xxx_reg_unlock(chip); 2514 2515 return err; 2516 } 2517 2518 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2519 u16 vid) 2520 { 2521 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2522 u8 broadcast[ETH_ALEN]; 2523 2524 eth_broadcast_addr(broadcast); 2525 2526 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2527 } 2528 2529 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2530 { 2531 int port; 2532 int err; 2533 2534 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2535 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2536 struct net_device *brport; 2537 2538 if (dsa_is_unused_port(chip->ds, port)) 2539 continue; 2540 2541 brport = dsa_port_to_bridge_port(dp); 2542 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2543 /* Skip bridged user ports where broadcast 2544 * flooding is disabled. 2545 */ 2546 continue; 2547 2548 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2549 if (err) 2550 return err; 2551 } 2552 2553 return 0; 2554 } 2555 2556 struct mv88e6xxx_port_broadcast_sync_ctx { 2557 int port; 2558 bool flood; 2559 }; 2560 2561 static int 2562 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2563 const struct mv88e6xxx_vtu_entry *vlan, 2564 void *_ctx) 2565 { 2566 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2567 u8 broadcast[ETH_ALEN]; 2568 u8 state; 2569 2570 if (ctx->flood) 2571 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2572 else 2573 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2574 2575 eth_broadcast_addr(broadcast); 2576 2577 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2578 vlan->vid, state); 2579 } 2580 2581 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2582 bool flood) 2583 { 2584 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2585 .port = port, 2586 .flood = flood, 2587 }; 2588 struct mv88e6xxx_vtu_entry vid0 = { 2589 .vid = 0, 2590 }; 2591 int err; 2592 2593 /* Update the port's private database... */ 2594 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2595 if (err) 2596 return err; 2597 2598 /* ...and the database for all VLANs. */ 2599 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2600 &ctx); 2601 } 2602 2603 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2604 u16 vid, u8 member, bool warn) 2605 { 2606 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2607 struct mv88e6xxx_vtu_entry vlan; 2608 int i, err; 2609 2610 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2611 if (err) 2612 return err; 2613 2614 if (!vlan.valid) { 2615 memset(&vlan, 0, sizeof(vlan)); 2616 2617 if (vid == MV88E6XXX_VID_STANDALONE) 2618 vlan.policy = true; 2619 2620 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2621 if (err) 2622 return err; 2623 2624 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2625 if (i == port) 2626 vlan.member[i] = member; 2627 else 2628 vlan.member[i] = non_member; 2629 2630 vlan.vid = vid; 2631 vlan.valid = true; 2632 2633 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2634 if (err) 2635 return err; 2636 2637 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2638 if (err) 2639 return err; 2640 } else if (vlan.member[port] != member) { 2641 vlan.member[port] = member; 2642 2643 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2644 if (err) 2645 return err; 2646 } else if (warn) { 2647 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2648 port, vid); 2649 } 2650 2651 /* Record FID used in SW FID map */ 2652 bitmap_set(chip->fid_bitmap, vlan.fid, 1); 2653 2654 return 0; 2655 } 2656 2657 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2658 const struct switchdev_obj_port_vlan *vlan, 2659 struct netlink_ext_ack *extack) 2660 { 2661 struct mv88e6xxx_chip *chip = ds->priv; 2662 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2663 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2664 struct mv88e6xxx_port *p = &chip->ports[port]; 2665 bool warn; 2666 u8 member; 2667 int err; 2668 2669 if (!vlan->vid) 2670 return 0; 2671 2672 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2673 if (err) 2674 return err; 2675 2676 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2677 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2678 else if (untagged) 2679 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2680 else 2681 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2682 2683 /* net/dsa/user.c will call dsa_port_vlan_add() for the affected port 2684 * and then the CPU port. Do not warn for duplicates for the CPU port. 2685 */ 2686 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2687 2688 mv88e6xxx_reg_lock(chip); 2689 2690 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2691 if (err) { 2692 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2693 vlan->vid, untagged ? 'u' : 't'); 2694 goto out; 2695 } 2696 2697 if (pvid) { 2698 p->bridge_pvid.vid = vlan->vid; 2699 p->bridge_pvid.valid = true; 2700 2701 err = mv88e6xxx_port_commit_pvid(chip, port); 2702 if (err) 2703 goto out; 2704 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2705 /* The old pvid was reinstalled as a non-pvid VLAN */ 2706 p->bridge_pvid.valid = false; 2707 2708 err = mv88e6xxx_port_commit_pvid(chip, port); 2709 if (err) 2710 goto out; 2711 } 2712 2713 out: 2714 mv88e6xxx_reg_unlock(chip); 2715 2716 return err; 2717 } 2718 2719 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2720 int port, u16 vid) 2721 { 2722 struct mv88e6xxx_vtu_entry vlan; 2723 int i, err; 2724 2725 if (!vid) 2726 return 0; 2727 2728 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2729 if (err) 2730 return err; 2731 2732 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2733 * tell switchdev that this VLAN is likely handled in software. 2734 */ 2735 if (!vlan.valid || 2736 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2737 return -EOPNOTSUPP; 2738 2739 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2740 2741 /* keep the VLAN unless all ports are excluded */ 2742 vlan.valid = false; 2743 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2744 if (vlan.member[i] != 2745 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2746 vlan.valid = true; 2747 break; 2748 } 2749 } 2750 2751 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2752 if (err) 2753 return err; 2754 2755 if (!vlan.valid) { 2756 err = mv88e6xxx_mst_put(chip, vlan.sid); 2757 if (err) 2758 return err; 2759 2760 /* Record FID freed in SW FID map */ 2761 bitmap_clear(chip->fid_bitmap, vlan.fid, 1); 2762 } 2763 2764 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2765 } 2766 2767 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2768 const struct switchdev_obj_port_vlan *vlan) 2769 { 2770 struct mv88e6xxx_chip *chip = ds->priv; 2771 struct mv88e6xxx_port *p = &chip->ports[port]; 2772 int err = 0; 2773 u16 pvid; 2774 2775 if (!mv88e6xxx_max_vid(chip)) 2776 return -EOPNOTSUPP; 2777 2778 /* The ATU removal procedure needs the FID to be mapped in the VTU, 2779 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA 2780 * switchdev workqueue to ensure that all FDB entries are deleted 2781 * before we remove the VLAN. 2782 */ 2783 dsa_flush_workqueue(); 2784 2785 mv88e6xxx_reg_lock(chip); 2786 2787 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2788 if (err) 2789 goto unlock; 2790 2791 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2792 if (err) 2793 goto unlock; 2794 2795 if (vlan->vid == pvid) { 2796 p->bridge_pvid.valid = false; 2797 2798 err = mv88e6xxx_port_commit_pvid(chip, port); 2799 if (err) 2800 goto unlock; 2801 } 2802 2803 unlock: 2804 mv88e6xxx_reg_unlock(chip); 2805 2806 return err; 2807 } 2808 2809 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid) 2810 { 2811 struct mv88e6xxx_chip *chip = ds->priv; 2812 struct mv88e6xxx_vtu_entry vlan; 2813 int err; 2814 2815 mv88e6xxx_reg_lock(chip); 2816 2817 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2818 if (err) 2819 goto unlock; 2820 2821 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid); 2822 2823 unlock: 2824 mv88e6xxx_reg_unlock(chip); 2825 2826 return err; 2827 } 2828 2829 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds, 2830 struct dsa_bridge bridge, 2831 const struct switchdev_vlan_msti *msti) 2832 { 2833 struct mv88e6xxx_chip *chip = ds->priv; 2834 struct mv88e6xxx_vtu_entry vlan; 2835 u8 old_sid, new_sid; 2836 int err; 2837 2838 if (!mv88e6xxx_has_stu(chip)) 2839 return -EOPNOTSUPP; 2840 2841 mv88e6xxx_reg_lock(chip); 2842 2843 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan); 2844 if (err) 2845 goto unlock; 2846 2847 if (!vlan.valid) { 2848 err = -EINVAL; 2849 goto unlock; 2850 } 2851 2852 old_sid = vlan.sid; 2853 2854 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid); 2855 if (err) 2856 goto unlock; 2857 2858 if (new_sid != old_sid) { 2859 vlan.sid = new_sid; 2860 2861 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2862 if (err) { 2863 mv88e6xxx_mst_put(chip, new_sid); 2864 goto unlock; 2865 } 2866 } 2867 2868 err = mv88e6xxx_mst_put(chip, old_sid); 2869 2870 unlock: 2871 mv88e6xxx_reg_unlock(chip); 2872 return err; 2873 } 2874 2875 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2876 const unsigned char *addr, u16 vid, 2877 struct dsa_db db) 2878 { 2879 struct mv88e6xxx_chip *chip = ds->priv; 2880 int err; 2881 2882 mv88e6xxx_reg_lock(chip); 2883 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2884 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2885 if (err) 2886 goto out; 2887 2888 if (!mv88e6xxx_port_db_find(chip, addr, vid)) 2889 err = -ENOSPC; 2890 2891 out: 2892 mv88e6xxx_reg_unlock(chip); 2893 2894 return err; 2895 } 2896 2897 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2898 const unsigned char *addr, u16 vid, 2899 struct dsa_db db) 2900 { 2901 struct mv88e6xxx_chip *chip = ds->priv; 2902 int err; 2903 2904 mv88e6xxx_reg_lock(chip); 2905 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2906 mv88e6xxx_reg_unlock(chip); 2907 2908 return err; 2909 } 2910 2911 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2912 u16 fid, u16 vid, int port, 2913 dsa_fdb_dump_cb_t *cb, void *data) 2914 { 2915 struct mv88e6xxx_atu_entry addr; 2916 bool is_static; 2917 int err; 2918 2919 addr.state = 0; 2920 eth_broadcast_addr(addr.mac); 2921 2922 do { 2923 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2924 if (err) 2925 return err; 2926 2927 if (!addr.state) 2928 break; 2929 2930 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2931 continue; 2932 2933 if (!is_unicast_ether_addr(addr.mac)) 2934 continue; 2935 2936 is_static = (addr.state == 2937 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2938 err = cb(addr.mac, vid, is_static, data); 2939 if (err) 2940 return err; 2941 } while (!is_broadcast_ether_addr(addr.mac)); 2942 2943 return err; 2944 } 2945 2946 struct mv88e6xxx_port_db_dump_vlan_ctx { 2947 int port; 2948 dsa_fdb_dump_cb_t *cb; 2949 void *data; 2950 }; 2951 2952 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2953 const struct mv88e6xxx_vtu_entry *entry, 2954 void *_data) 2955 { 2956 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2957 2958 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2959 ctx->port, ctx->cb, ctx->data); 2960 } 2961 2962 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2963 dsa_fdb_dump_cb_t *cb, void *data) 2964 { 2965 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2966 .port = port, 2967 .cb = cb, 2968 .data = data, 2969 }; 2970 u16 fid; 2971 int err; 2972 2973 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2974 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2975 if (err) 2976 return err; 2977 2978 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2979 if (err) 2980 return err; 2981 2982 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2983 } 2984 2985 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2986 dsa_fdb_dump_cb_t *cb, void *data) 2987 { 2988 struct mv88e6xxx_chip *chip = ds->priv; 2989 int err; 2990 2991 mv88e6xxx_reg_lock(chip); 2992 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2993 mv88e6xxx_reg_unlock(chip); 2994 2995 return err; 2996 } 2997 2998 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2999 struct dsa_bridge bridge) 3000 { 3001 struct dsa_switch *ds = chip->ds; 3002 struct dsa_switch_tree *dst = ds->dst; 3003 struct dsa_port *dp; 3004 int err; 3005 3006 list_for_each_entry(dp, &dst->ports, list) { 3007 if (dsa_port_offloads_bridge(dp, &bridge)) { 3008 if (dp->ds == ds) { 3009 /* This is a local bridge group member, 3010 * remap its Port VLAN Map. 3011 */ 3012 err = mv88e6xxx_port_vlan_map(chip, dp->index); 3013 if (err) 3014 return err; 3015 } else { 3016 /* This is an external bridge group member, 3017 * remap its cross-chip Port VLAN Table entry. 3018 */ 3019 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 3020 dp->index); 3021 if (err) 3022 return err; 3023 } 3024 } 3025 } 3026 3027 return 0; 3028 } 3029 3030 /* Treat the software bridge as a virtual single-port switch behind the 3031 * CPU and map in the PVT. First dst->last_switch elements are taken by 3032 * physical switches, so start from beyond that range. 3033 */ 3034 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 3035 unsigned int bridge_num) 3036 { 3037 u8 dev = bridge_num + ds->dst->last_switch; 3038 struct mv88e6xxx_chip *chip = ds->priv; 3039 3040 return mv88e6xxx_pvt_map(chip, dev, 0); 3041 } 3042 3043 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 3044 struct dsa_bridge bridge, 3045 bool *tx_fwd_offload, 3046 struct netlink_ext_ack *extack) 3047 { 3048 struct mv88e6xxx_chip *chip = ds->priv; 3049 int err; 3050 3051 mv88e6xxx_reg_lock(chip); 3052 3053 err = mv88e6xxx_bridge_map(chip, bridge); 3054 if (err) 3055 goto unlock; 3056 3057 err = mv88e6xxx_port_set_map_da(chip, port, true); 3058 if (err) 3059 goto unlock; 3060 3061 err = mv88e6xxx_port_commit_pvid(chip, port); 3062 if (err) 3063 goto unlock; 3064 3065 if (mv88e6xxx_has_pvt(chip)) { 3066 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 3067 if (err) 3068 goto unlock; 3069 3070 *tx_fwd_offload = true; 3071 } 3072 3073 unlock: 3074 mv88e6xxx_reg_unlock(chip); 3075 3076 return err; 3077 } 3078 3079 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 3080 struct dsa_bridge bridge) 3081 { 3082 struct mv88e6xxx_chip *chip = ds->priv; 3083 int err; 3084 3085 mv88e6xxx_reg_lock(chip); 3086 3087 if (bridge.tx_fwd_offload && 3088 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 3089 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 3090 3091 if (mv88e6xxx_bridge_map(chip, bridge) || 3092 mv88e6xxx_port_vlan_map(chip, port)) 3093 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 3094 3095 err = mv88e6xxx_port_set_map_da(chip, port, false); 3096 if (err) 3097 dev_err(ds->dev, 3098 "port %d failed to restore map-DA: %pe\n", 3099 port, ERR_PTR(err)); 3100 3101 err = mv88e6xxx_port_commit_pvid(chip, port); 3102 if (err) 3103 dev_err(ds->dev, 3104 "port %d failed to restore standalone pvid: %pe\n", 3105 port, ERR_PTR(err)); 3106 3107 mv88e6xxx_reg_unlock(chip); 3108 } 3109 3110 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 3111 int tree_index, int sw_index, 3112 int port, struct dsa_bridge bridge, 3113 struct netlink_ext_ack *extack) 3114 { 3115 struct mv88e6xxx_chip *chip = ds->priv; 3116 int err; 3117 3118 if (tree_index != ds->dst->index) 3119 return 0; 3120 3121 mv88e6xxx_reg_lock(chip); 3122 err = mv88e6xxx_pvt_map(chip, sw_index, port); 3123 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 3124 mv88e6xxx_reg_unlock(chip); 3125 3126 return err; 3127 } 3128 3129 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 3130 int tree_index, int sw_index, 3131 int port, struct dsa_bridge bridge) 3132 { 3133 struct mv88e6xxx_chip *chip = ds->priv; 3134 3135 if (tree_index != ds->dst->index) 3136 return; 3137 3138 mv88e6xxx_reg_lock(chip); 3139 if (mv88e6xxx_pvt_map(chip, sw_index, port) || 3140 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 3141 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 3142 mv88e6xxx_reg_unlock(chip); 3143 } 3144 3145 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 3146 { 3147 if (chip->info->ops->reset) 3148 return chip->info->ops->reset(chip); 3149 3150 return 0; 3151 } 3152 3153 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 3154 { 3155 struct gpio_desc *gpiod = chip->reset; 3156 int err; 3157 3158 /* If there is a GPIO connected to the reset pin, toggle it */ 3159 if (gpiod) { 3160 /* If the switch has just been reset and not yet completed 3161 * loading EEPROM, the reset may interrupt the I2C transaction 3162 * mid-byte, causing the first EEPROM read after the reset 3163 * from the wrong location resulting in the switch booting 3164 * to wrong mode and inoperable. 3165 * For this reason, switch families with EEPROM support 3166 * generally wait for EEPROM loads to complete as their pre- 3167 * and post-reset handlers. 3168 */ 3169 if (chip->info->ops->hardware_reset_pre) { 3170 err = chip->info->ops->hardware_reset_pre(chip); 3171 if (err) 3172 dev_err(chip->dev, "pre-reset error: %d\n", err); 3173 } 3174 3175 gpiod_set_value_cansleep(gpiod, 1); 3176 usleep_range(10000, 20000); 3177 gpiod_set_value_cansleep(gpiod, 0); 3178 usleep_range(10000, 20000); 3179 3180 if (chip->info->ops->hardware_reset_post) { 3181 err = chip->info->ops->hardware_reset_post(chip); 3182 if (err) 3183 dev_err(chip->dev, "post-reset error: %d\n", err); 3184 } 3185 } 3186 } 3187 3188 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 3189 { 3190 int i, err; 3191 3192 /* Set all ports to the Disabled state */ 3193 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3194 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 3195 if (err) 3196 return err; 3197 } 3198 3199 /* Wait for transmit queues to drain, 3200 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 3201 */ 3202 usleep_range(2000, 4000); 3203 3204 return 0; 3205 } 3206 3207 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 3208 { 3209 int err; 3210 3211 err = mv88e6xxx_disable_ports(chip); 3212 if (err) 3213 return err; 3214 3215 mv88e6xxx_hardware_reset(chip); 3216 3217 return mv88e6xxx_software_reset(chip); 3218 } 3219 3220 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 3221 enum mv88e6xxx_frame_mode frame, 3222 enum mv88e6xxx_egress_mode egress, u16 etype) 3223 { 3224 int err; 3225 3226 if (!chip->info->ops->port_set_frame_mode) 3227 return -EOPNOTSUPP; 3228 3229 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 3230 if (err) 3231 return err; 3232 3233 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 3234 if (err) 3235 return err; 3236 3237 if (chip->info->ops->port_set_ether_type) 3238 return chip->info->ops->port_set_ether_type(chip, port, etype); 3239 3240 return 0; 3241 } 3242 3243 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 3244 { 3245 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 3246 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3247 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3248 } 3249 3250 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 3251 { 3252 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 3253 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3254 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3255 } 3256 3257 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 3258 { 3259 return mv88e6xxx_set_port_mode(chip, port, 3260 MV88E6XXX_FRAME_MODE_ETHERTYPE, 3261 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 3262 ETH_P_EDSA); 3263 } 3264 3265 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 3266 { 3267 if (dsa_is_dsa_port(chip->ds, port)) 3268 return mv88e6xxx_set_port_mode_dsa(chip, port); 3269 3270 if (dsa_is_user_port(chip->ds, port)) 3271 return mv88e6xxx_set_port_mode_normal(chip, port); 3272 3273 /* Setup CPU port mode depending on its supported tag format */ 3274 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 3275 return mv88e6xxx_set_port_mode_dsa(chip, port); 3276 3277 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 3278 return mv88e6xxx_set_port_mode_edsa(chip, port); 3279 3280 return -EINVAL; 3281 } 3282 3283 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 3284 { 3285 bool message = dsa_is_dsa_port(chip->ds, port); 3286 3287 return mv88e6xxx_port_set_message_port(chip, port, message); 3288 } 3289 3290 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 3291 { 3292 int err; 3293 3294 if (chip->info->ops->port_set_ucast_flood) { 3295 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 3296 if (err) 3297 return err; 3298 } 3299 if (chip->info->ops->port_set_mcast_flood) { 3300 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 3301 if (err) 3302 return err; 3303 } 3304 3305 return 0; 3306 } 3307 3308 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 3309 enum mv88e6xxx_egress_direction direction, 3310 int port) 3311 { 3312 int err; 3313 3314 if (!chip->info->ops->set_egress_port) 3315 return -EOPNOTSUPP; 3316 3317 err = chip->info->ops->set_egress_port(chip, direction, port); 3318 if (err) 3319 return err; 3320 3321 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 3322 chip->ingress_dest_port = port; 3323 else 3324 chip->egress_dest_port = port; 3325 3326 return 0; 3327 } 3328 3329 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 3330 { 3331 struct dsa_switch *ds = chip->ds; 3332 int upstream_port; 3333 int err; 3334 3335 upstream_port = dsa_upstream_port(ds, port); 3336 if (chip->info->ops->port_set_upstream_port) { 3337 err = chip->info->ops->port_set_upstream_port(chip, port, 3338 upstream_port); 3339 if (err) 3340 return err; 3341 } 3342 3343 if (port == upstream_port) { 3344 if (chip->info->ops->set_cpu_port) { 3345 err = chip->info->ops->set_cpu_port(chip, 3346 upstream_port); 3347 if (err) 3348 return err; 3349 } 3350 3351 err = mv88e6xxx_set_egress_port(chip, 3352 MV88E6XXX_EGRESS_DIR_INGRESS, 3353 upstream_port); 3354 if (err && err != -EOPNOTSUPP) 3355 return err; 3356 3357 err = mv88e6xxx_set_egress_port(chip, 3358 MV88E6XXX_EGRESS_DIR_EGRESS, 3359 upstream_port); 3360 if (err && err != -EOPNOTSUPP) 3361 return err; 3362 } 3363 3364 return 0; 3365 } 3366 3367 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 3368 { 3369 struct fwnode_handle *ports_fwnode; 3370 struct fwnode_handle *port_fwnode; 3371 struct dsa_switch *ds = chip->ds; 3372 struct mv88e6xxx_port *p; 3373 int err; 3374 u16 reg; 3375 u32 val; 3376 3377 p = &chip->ports[port]; 3378 p->chip = chip; 3379 p->port = port; 3380 3381 /* Look up corresponding fwnode if any */ 3382 ports_fwnode = device_get_named_child_node(chip->dev, "ethernet-ports"); 3383 if (!ports_fwnode) 3384 ports_fwnode = device_get_named_child_node(chip->dev, "ports"); 3385 if (ports_fwnode) { 3386 fwnode_for_each_child_node(ports_fwnode, port_fwnode) { 3387 if (fwnode_property_read_u32(port_fwnode, "reg", &val)) 3388 continue; 3389 if (val == port) { 3390 p->fwnode = port_fwnode; 3391 p->fiber = fwnode_property_present(port_fwnode, "sfp"); 3392 break; 3393 } 3394 } 3395 fwnode_handle_put(ports_fwnode); 3396 } else { 3397 dev_dbg(chip->dev, "no ethernet ports node defined for the device\n"); 3398 } 3399 3400 if (chip->info->ops->port_setup_leds) { 3401 err = chip->info->ops->port_setup_leds(chip, port); 3402 if (err && err != -EOPNOTSUPP) 3403 return err; 3404 } 3405 3406 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 3407 SPEED_UNFORCED, DUPLEX_UNFORCED, 3408 PAUSE_ON, PHY_INTERFACE_MODE_NA); 3409 if (err) 3410 return err; 3411 3412 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 3413 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 3414 * tunneling, determine priority by looking at 802.1p and IP 3415 * priority fields (IP prio has precedence), and set STP state 3416 * to Forwarding. 3417 * 3418 * If this is the CPU link, use DSA or EDSA tagging depending 3419 * on which tagging mode was configured. 3420 * 3421 * If this is a link to another switch, use DSA tagging mode. 3422 * 3423 * If this is the upstream port for this switch, enable 3424 * forwarding of unknown unicasts and multicasts. 3425 */ 3426 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 3427 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 3428 /* Forward any IPv4 IGMP or IPv6 MLD frames received 3429 * by a USER port to the CPU port to allow snooping. 3430 */ 3431 if (dsa_is_user_port(ds, port)) 3432 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP; 3433 3434 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 3435 if (err) 3436 return err; 3437 3438 err = mv88e6xxx_setup_port_mode(chip, port); 3439 if (err) 3440 return err; 3441 3442 err = mv88e6xxx_setup_egress_floods(chip, port); 3443 if (err) 3444 return err; 3445 3446 /* Port Control 2: don't force a good FCS, set the MTU size to 3447 * 10222 bytes, disable 802.1q tags checking, don't discard 3448 * tagged or untagged frames on this port, skip destination 3449 * address lookup on user ports, disable ARP mirroring and don't 3450 * send a copy of all transmitted/received frames on this port 3451 * to the CPU. 3452 */ 3453 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port)); 3454 if (err) 3455 return err; 3456 3457 err = mv88e6xxx_setup_upstream_port(chip, port); 3458 if (err) 3459 return err; 3460 3461 /* On chips that support it, set all downstream DSA ports' 3462 * VLAN policy to TRAP. In combination with loading 3463 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this 3464 * provides a better isolation barrier between standalone 3465 * ports, as the ATU is bypassed on any intermediate switches 3466 * between the incoming port and the CPU. 3467 */ 3468 if (dsa_is_downstream_port(ds, port) && 3469 chip->info->ops->port_set_policy) { 3470 err = chip->info->ops->port_set_policy(chip, port, 3471 MV88E6XXX_POLICY_MAPPING_VTU, 3472 MV88E6XXX_POLICY_ACTION_TRAP); 3473 if (err) 3474 return err; 3475 } 3476 3477 /* User ports start out in standalone mode and 802.1Q is 3478 * therefore disabled. On DSA ports, all valid VIDs are always 3479 * loaded in the VTU - therefore, enable 802.1Q in order to take 3480 * advantage of VLAN policy on chips that supports it. 3481 */ 3482 err = mv88e6xxx_port_set_8021q_mode(chip, port, 3483 dsa_is_user_port(ds, port) ? 3484 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED : 3485 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE); 3486 if (err) 3487 return err; 3488 3489 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by 3490 * virtue of the fact that mv88e6xxx_atu_new() will pick it as 3491 * the first free FID. This will be used as the private PVID for 3492 * unbridged ports. Shared (DSA and CPU) ports must also be 3493 * members of this VID, in order to trap all frames assigned to 3494 * it to the CPU. 3495 */ 3496 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE, 3497 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3498 false); 3499 if (err) 3500 return err; 3501 3502 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 3503 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 3504 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 3505 * as the private PVID on ports under a VLAN-unaware bridge. 3506 * Shared (DSA and CPU) ports must also be members of it, to translate 3507 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 3508 * relying on their port default FID. 3509 */ 3510 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 3511 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3512 false); 3513 if (err) 3514 return err; 3515 3516 if (chip->info->ops->port_set_jumbo_size) { 3517 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 3518 if (err) 3519 return err; 3520 } 3521 3522 /* Port Association Vector: disable automatic address learning 3523 * on all user ports since they start out in standalone 3524 * mode. When joining a bridge, learning will be configured to 3525 * match the bridge port settings. Enable learning on all 3526 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 3527 * learning process. 3528 * 3529 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 3530 * and RefreshLocked. I.e. setup standard automatic learning. 3531 */ 3532 if (dsa_is_user_port(ds, port)) 3533 reg = 0; 3534 else 3535 reg = 1 << port; 3536 3537 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 3538 reg); 3539 if (err) 3540 return err; 3541 3542 /* Egress rate control 2: disable egress rate control. */ 3543 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 3544 0x0000); 3545 if (err) 3546 return err; 3547 3548 if (chip->info->ops->port_pause_limit) { 3549 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 3550 if (err) 3551 return err; 3552 } 3553 3554 if (chip->info->ops->port_disable_learn_limit) { 3555 err = chip->info->ops->port_disable_learn_limit(chip, port); 3556 if (err) 3557 return err; 3558 } 3559 3560 if (chip->info->ops->port_disable_pri_override) { 3561 err = chip->info->ops->port_disable_pri_override(chip, port); 3562 if (err) 3563 return err; 3564 } 3565 if (chip->info->ops->port_enable_tcam) { 3566 err = chip->info->ops->port_enable_tcam(chip, port); 3567 if (err) 3568 return err; 3569 } 3570 3571 if (chip->info->ops->port_tag_remap) { 3572 err = chip->info->ops->port_tag_remap(chip, port); 3573 if (err) 3574 return err; 3575 } 3576 3577 if (chip->info->ops->port_egress_rate_limiting) { 3578 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3579 if (err) 3580 return err; 3581 } 3582 3583 if (chip->info->ops->port_setup_message_port) { 3584 err = chip->info->ops->port_setup_message_port(chip, port); 3585 if (err) 3586 return err; 3587 } 3588 3589 /* Port based VLAN map: give each port the same default address 3590 * database, and allow bidirectional communication between the 3591 * CPU and DSA port(s), and the other ports. 3592 */ 3593 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3594 if (err) 3595 return err; 3596 3597 err = mv88e6xxx_port_vlan_map(chip, port); 3598 if (err) 3599 return err; 3600 3601 /* Default VLAN ID and priority: don't set a default VLAN 3602 * ID, and set the default packet priority to zero. 3603 */ 3604 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3605 } 3606 3607 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3608 { 3609 struct mv88e6xxx_chip *chip = ds->priv; 3610 3611 if (chip->info->ops->port_set_jumbo_size) 3612 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3613 else if (chip->info->ops->set_max_frame_size) 3614 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3615 return ETH_DATA_LEN; 3616 } 3617 3618 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3619 { 3620 struct mv88e6xxx_chip *chip = ds->priv; 3621 int ret = 0; 3622 3623 /* For families where we don't know how to alter the MTU, 3624 * just accept any value up to ETH_DATA_LEN 3625 */ 3626 if (!chip->info->ops->port_set_jumbo_size && 3627 !chip->info->ops->set_max_frame_size) { 3628 if (new_mtu > ETH_DATA_LEN) 3629 return -EINVAL; 3630 3631 return 0; 3632 } 3633 3634 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3635 new_mtu += EDSA_HLEN; 3636 3637 mv88e6xxx_reg_lock(chip); 3638 if (chip->info->ops->port_set_jumbo_size) 3639 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3640 else if (chip->info->ops->set_max_frame_size && 3641 dsa_is_cpu_port(ds, port)) 3642 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3643 mv88e6xxx_reg_unlock(chip); 3644 3645 return ret; 3646 } 3647 3648 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3649 unsigned int ageing_time) 3650 { 3651 struct mv88e6xxx_chip *chip = ds->priv; 3652 int err; 3653 3654 mv88e6xxx_reg_lock(chip); 3655 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3656 mv88e6xxx_reg_unlock(chip); 3657 3658 return err; 3659 } 3660 3661 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3662 { 3663 int err; 3664 3665 /* Initialize the statistics unit */ 3666 if (chip->info->ops->stats_set_histogram) { 3667 err = chip->info->ops->stats_set_histogram(chip); 3668 if (err) 3669 return err; 3670 } 3671 3672 return mv88e6xxx_g1_stats_clear(chip); 3673 } 3674 3675 static int mv88e6320_setup_errata(struct mv88e6xxx_chip *chip) 3676 { 3677 u16 dummy; 3678 int err; 3679 3680 /* Workaround for erratum 3681 * 3.3 RGMII timing may be out of spec when transmit delay is enabled 3682 */ 3683 err = mv88e6xxx_port_hidden_write(chip, 0, 0xf, 0x7, 0xe000); 3684 if (err) 3685 return err; 3686 3687 return mv88e6xxx_port_hidden_read(chip, 0, 0xf, 0x7, &dummy); 3688 } 3689 3690 /* Check if the errata has already been applied. */ 3691 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3692 { 3693 int port; 3694 int err; 3695 u16 val; 3696 3697 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3698 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3699 if (err) { 3700 dev_err(chip->dev, 3701 "Error reading hidden register: %d\n", err); 3702 return false; 3703 } 3704 if (val != 0x01c0) 3705 return false; 3706 } 3707 3708 return true; 3709 } 3710 3711 /* The 6390 copper ports have an errata which require poking magic 3712 * values into undocumented hidden registers and then performing a 3713 * software reset. 3714 */ 3715 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3716 { 3717 int port; 3718 int err; 3719 3720 if (mv88e6390_setup_errata_applied(chip)) 3721 return 0; 3722 3723 /* Set the ports into blocking mode */ 3724 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3725 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3726 if (err) 3727 return err; 3728 } 3729 3730 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3731 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3732 if (err) 3733 return err; 3734 } 3735 3736 return mv88e6xxx_software_reset(chip); 3737 } 3738 3739 /* prod_id for switch families which do not have a PHY model number */ 3740 static const u16 family_prod_id_table[] = { 3741 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3742 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3743 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3744 }; 3745 3746 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3747 { 3748 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3749 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3750 u16 prod_id; 3751 u16 val; 3752 int err; 3753 3754 if (!chip->info->ops->phy_read) 3755 return -EOPNOTSUPP; 3756 3757 mv88e6xxx_reg_lock(chip); 3758 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3759 mv88e6xxx_reg_unlock(chip); 3760 3761 /* Some internal PHYs don't have a model number. */ 3762 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3763 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3764 prod_id = family_prod_id_table[chip->info->family]; 3765 if (prod_id) 3766 val |= prod_id >> 4; 3767 } 3768 3769 return err ? err : val; 3770 } 3771 3772 static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad, 3773 int reg) 3774 { 3775 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3776 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3777 u16 val; 3778 int err; 3779 3780 if (!chip->info->ops->phy_read_c45) 3781 return -ENODEV; 3782 3783 mv88e6xxx_reg_lock(chip); 3784 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val); 3785 mv88e6xxx_reg_unlock(chip); 3786 3787 return err ? err : val; 3788 } 3789 3790 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3791 { 3792 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3793 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3794 int err; 3795 3796 if (!chip->info->ops->phy_write) 3797 return -EOPNOTSUPP; 3798 3799 mv88e6xxx_reg_lock(chip); 3800 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3801 mv88e6xxx_reg_unlock(chip); 3802 3803 return err; 3804 } 3805 3806 static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad, 3807 int reg, u16 val) 3808 { 3809 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3810 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3811 int err; 3812 3813 if (!chip->info->ops->phy_write_c45) 3814 return -EOPNOTSUPP; 3815 3816 mv88e6xxx_reg_lock(chip); 3817 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val); 3818 mv88e6xxx_reg_unlock(chip); 3819 3820 return err; 3821 } 3822 3823 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3824 struct device_node *np, 3825 bool external) 3826 { 3827 static int index; 3828 struct mv88e6xxx_mdio_bus *mdio_bus; 3829 struct mii_bus *bus; 3830 int err; 3831 3832 if (external) { 3833 mv88e6xxx_reg_lock(chip); 3834 if (chip->info->family == MV88E6XXX_FAMILY_6393) 3835 err = mv88e6393x_g2_scratch_gpio_set_smi(chip, true); 3836 else 3837 err = mv88e6390_g2_scratch_gpio_set_smi(chip, true); 3838 mv88e6xxx_reg_unlock(chip); 3839 3840 if (err) 3841 return err; 3842 } 3843 3844 bus = mdiobus_alloc_size(sizeof(*mdio_bus)); 3845 if (!bus) 3846 return -ENOMEM; 3847 3848 mdio_bus = bus->priv; 3849 mdio_bus->bus = bus; 3850 mdio_bus->chip = chip; 3851 INIT_LIST_HEAD(&mdio_bus->list); 3852 mdio_bus->external = external; 3853 3854 if (np) { 3855 bus->name = np->full_name; 3856 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3857 } else { 3858 bus->name = "mv88e6xxx SMI"; 3859 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3860 } 3861 3862 bus->read = mv88e6xxx_mdio_read; 3863 bus->write = mv88e6xxx_mdio_write; 3864 bus->read_c45 = mv88e6xxx_mdio_read_c45; 3865 bus->write_c45 = mv88e6xxx_mdio_write_c45; 3866 bus->parent = chip->dev; 3867 bus->phy_mask = ~GENMASK(chip->info->phy_base_addr + 3868 mv88e6xxx_num_ports(chip) - 1, 3869 chip->info->phy_base_addr); 3870 3871 if (!external) { 3872 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3873 if (err) 3874 goto out; 3875 } 3876 3877 err = of_mdiobus_register(bus, np); 3878 if (err) { 3879 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3880 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3881 goto out; 3882 } 3883 3884 if (external) 3885 list_add_tail(&mdio_bus->list, &chip->mdios); 3886 else 3887 list_add(&mdio_bus->list, &chip->mdios); 3888 3889 return 0; 3890 3891 out: 3892 mdiobus_free(bus); 3893 return err; 3894 } 3895 3896 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3897 3898 { 3899 struct mv88e6xxx_mdio_bus *mdio_bus, *p; 3900 struct mii_bus *bus; 3901 3902 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) { 3903 bus = mdio_bus->bus; 3904 3905 if (!mdio_bus->external) 3906 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3907 3908 mdiobus_unregister(bus); 3909 mdiobus_free(bus); 3910 } 3911 } 3912 3913 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip) 3914 { 3915 struct device_node *np = chip->dev->of_node; 3916 struct device_node *child; 3917 int err; 3918 3919 /* Always register one mdio bus for the internal/default mdio 3920 * bus. This maybe represented in the device tree, but is 3921 * optional. 3922 */ 3923 child = of_get_child_by_name(np, "mdio"); 3924 err = mv88e6xxx_mdio_register(chip, child, false); 3925 of_node_put(child); 3926 if (err) 3927 return err; 3928 3929 /* Walk the device tree, and see if there are any other nodes 3930 * which say they are compatible with the external mdio 3931 * bus. 3932 */ 3933 for_each_available_child_of_node(np, child) { 3934 if (of_device_is_compatible( 3935 child, "marvell,mv88e6xxx-mdio-external")) { 3936 err = mv88e6xxx_mdio_register(chip, child, true); 3937 if (err) { 3938 mv88e6xxx_mdios_unregister(chip); 3939 of_node_put(child); 3940 return err; 3941 } 3942 } 3943 } 3944 3945 return 0; 3946 } 3947 3948 static int mv88e6xxx_tcam_setup(struct mv88e6xxx_chip *chip) 3949 { 3950 if (!mv88e6xxx_has_tcam(chip)) 3951 return 0; 3952 3953 return chip->info->ops->tcam_ops->flush_tcam(chip); 3954 } 3955 3956 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3957 { 3958 struct mv88e6xxx_chip *chip = ds->priv; 3959 3960 mv88e6xxx_teardown_devlink_params(ds); 3961 dsa_devlink_resources_unregister(ds); 3962 mv88e6xxx_teardown_devlink_regions_global(ds); 3963 mv88e6xxx_hwtstamp_free(chip); 3964 mv88e6xxx_ptp_free(chip); 3965 mv88e6xxx_flower_teardown(chip); 3966 mv88e6xxx_mdios_unregister(chip); 3967 } 3968 3969 static int mv88e6xxx_setup(struct dsa_switch *ds) 3970 { 3971 struct mv88e6xxx_chip *chip = ds->priv; 3972 u8 cmode; 3973 int err; 3974 int i; 3975 3976 err = mv88e6xxx_mdios_register(chip); 3977 if (err) 3978 return err; 3979 3980 chip->ds = ds; 3981 ds->user_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3982 3983 /* Since virtual bridges are mapped in the PVT, the number we support 3984 * depends on the physical switch topology. We need to let DSA figure 3985 * that out and therefore we cannot set this at dsa_register_switch() 3986 * time. 3987 */ 3988 if (mv88e6xxx_has_pvt(chip)) 3989 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3990 ds->dst->last_switch - 1; 3991 3992 mv88e6xxx_reg_lock(chip); 3993 3994 if (chip->info->ops->setup_errata) { 3995 err = chip->info->ops->setup_errata(chip); 3996 if (err) 3997 goto unlock; 3998 } 3999 4000 /* Cache the cmode of each port. */ 4001 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 4002 if (chip->info->ops->port_get_cmode) { 4003 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 4004 if (err) 4005 goto unlock; 4006 4007 chip->ports[i].cmode = cmode; 4008 } 4009 } 4010 4011 err = mv88e6xxx_vtu_setup(chip); 4012 if (err) 4013 goto unlock; 4014 4015 /* Must be called after mv88e6xxx_vtu_setup (which flushes the 4016 * VTU, thereby also flushing the STU). 4017 */ 4018 err = mv88e6xxx_stu_setup(chip); 4019 if (err) 4020 goto unlock; 4021 4022 /* Setup Switch Port Registers */ 4023 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 4024 if (dsa_is_unused_port(ds, i)) 4025 continue; 4026 4027 /* Prevent the use of an invalid port. */ 4028 if (mv88e6xxx_is_invalid_port(chip, i)) { 4029 dev_err(chip->dev, "port %d is invalid\n", i); 4030 err = -EINVAL; 4031 goto unlock; 4032 } 4033 4034 err = mv88e6xxx_setup_port(chip, i); 4035 if (err) 4036 goto unlock; 4037 } 4038 4039 err = mv88e6xxx_irl_setup(chip); 4040 if (err) 4041 goto unlock; 4042 4043 err = mv88e6xxx_mac_setup(chip); 4044 if (err) 4045 goto unlock; 4046 4047 err = mv88e6xxx_phy_setup(chip); 4048 if (err) 4049 goto unlock; 4050 4051 err = mv88e6xxx_pvt_setup(chip); 4052 if (err) 4053 goto unlock; 4054 4055 err = mv88e6xxx_atu_setup(chip); 4056 if (err) 4057 goto unlock; 4058 4059 err = mv88e6xxx_broadcast_setup(chip, 0); 4060 if (err) 4061 goto unlock; 4062 4063 err = mv88e6xxx_pot_setup(chip); 4064 if (err) 4065 goto unlock; 4066 4067 err = mv88e6xxx_rmu_setup(chip); 4068 if (err) 4069 goto unlock; 4070 4071 err = mv88e6xxx_rsvd2cpu_setup(chip); 4072 if (err) 4073 goto unlock; 4074 4075 err = mv88e6xxx_trunk_setup(chip); 4076 if (err) 4077 goto unlock; 4078 4079 err = mv88e6xxx_devmap_setup(chip); 4080 if (err) 4081 goto unlock; 4082 4083 err = mv88e6xxx_pri_setup(chip); 4084 if (err) 4085 goto unlock; 4086 4087 /* Setup PTP Hardware Clock and timestamping */ 4088 if (chip->info->ptp_support) { 4089 err = mv88e6xxx_ptp_setup(chip); 4090 if (err) 4091 goto unlock; 4092 4093 err = mv88e6xxx_hwtstamp_setup(chip); 4094 if (err) 4095 goto unlock; 4096 } 4097 4098 err = mv88e6xxx_stats_setup(chip); 4099 if (err) 4100 goto unlock; 4101 4102 err = mv88e6xxx_tcam_setup(chip); 4103 if (err) 4104 goto unlock; 4105 4106 unlock: 4107 mv88e6xxx_reg_unlock(chip); 4108 4109 if (err) 4110 goto out_hwtstamp; 4111 4112 /* Have to be called without holding the register lock, since 4113 * they take the devlink lock, and we later take the locks in 4114 * the reverse order when getting/setting parameters or 4115 * resource occupancy. 4116 */ 4117 err = mv88e6xxx_setup_devlink_resources(ds); 4118 if (err) 4119 goto out_hwtstamp; 4120 4121 err = mv88e6xxx_setup_devlink_params(ds); 4122 if (err) 4123 goto out_resources; 4124 4125 err = mv88e6xxx_setup_devlink_regions_global(ds); 4126 if (err) 4127 goto out_params; 4128 4129 return 0; 4130 4131 out_params: 4132 mv88e6xxx_teardown_devlink_params(ds); 4133 out_resources: 4134 dsa_devlink_resources_unregister(ds); 4135 out_hwtstamp: 4136 mv88e6xxx_hwtstamp_free(chip); 4137 mv88e6xxx_ptp_free(chip); 4138 mv88e6xxx_mdios_unregister(chip); 4139 4140 return err; 4141 } 4142 4143 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 4144 { 4145 struct mv88e6xxx_chip *chip = ds->priv; 4146 int err; 4147 4148 if (chip->info->ops->pcs_ops && 4149 chip->info->ops->pcs_ops->pcs_init) { 4150 err = chip->info->ops->pcs_ops->pcs_init(chip, port); 4151 if (err) 4152 return err; 4153 } 4154 4155 return mv88e6xxx_setup_devlink_regions_port(ds, port); 4156 } 4157 4158 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 4159 { 4160 struct mv88e6xxx_chip *chip = ds->priv; 4161 4162 mv88e6xxx_teardown_devlink_regions_port(ds, port); 4163 4164 if (chip->info->ops->pcs_ops && 4165 chip->info->ops->pcs_ops->pcs_teardown) 4166 chip->info->ops->pcs_ops->pcs_teardown(chip, port); 4167 } 4168 4169 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 4170 { 4171 struct mv88e6xxx_chip *chip = ds->priv; 4172 4173 return chip->eeprom_len; 4174 } 4175 4176 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 4177 struct ethtool_eeprom *eeprom, u8 *data) 4178 { 4179 struct mv88e6xxx_chip *chip = ds->priv; 4180 int err; 4181 4182 if (!chip->info->ops->get_eeprom) 4183 return -EOPNOTSUPP; 4184 4185 mv88e6xxx_reg_lock(chip); 4186 err = chip->info->ops->get_eeprom(chip, eeprom, data); 4187 mv88e6xxx_reg_unlock(chip); 4188 4189 if (err) 4190 return err; 4191 4192 eeprom->magic = 0xc3ec4951; 4193 4194 return 0; 4195 } 4196 4197 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 4198 struct ethtool_eeprom *eeprom, u8 *data) 4199 { 4200 struct mv88e6xxx_chip *chip = ds->priv; 4201 int err; 4202 4203 if (!chip->info->ops->set_eeprom) 4204 return -EOPNOTSUPP; 4205 4206 if (eeprom->magic != 0xc3ec4951) 4207 return -EINVAL; 4208 4209 mv88e6xxx_reg_lock(chip); 4210 err = chip->info->ops->set_eeprom(chip, eeprom, data); 4211 mv88e6xxx_reg_unlock(chip); 4212 4213 return err; 4214 } 4215 4216 static const struct mv88e6xxx_ops mv88e6085_ops = { 4217 /* MV88E6XXX_FAMILY_6097 */ 4218 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4219 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4220 .irl_init_all = mv88e6352_g2_irl_init_all, 4221 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4222 .phy_read = mv88e6185_phy_ppu_read, 4223 .phy_write = mv88e6185_phy_ppu_write, 4224 .port_set_link = mv88e6xxx_port_set_link, 4225 .port_sync_link = mv88e6xxx_port_sync_link, 4226 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4227 .port_tag_remap = mv88e6095_port_tag_remap, 4228 .port_set_policy = mv88e6352_port_set_policy, 4229 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4230 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4231 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4232 .port_set_ether_type = mv88e6351_port_set_ether_type, 4233 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4234 .port_pause_limit = mv88e6097_port_pause_limit, 4235 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4236 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4237 .port_get_cmode = mv88e6185_port_get_cmode, 4238 .port_setup_message_port = mv88e6xxx_setup_message_port, 4239 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4240 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4241 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4242 .stats_get_strings = mv88e6095_stats_get_strings, 4243 .stats_get_stat = mv88e6095_stats_get_stat, 4244 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4245 .set_egress_port = mv88e6095_g1_set_egress_port, 4246 .watchdog_ops = &mv88e6097_watchdog_ops, 4247 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4248 .pot_clear = mv88e6xxx_g2_pot_clear, 4249 .ppu_enable = mv88e6185_g1_ppu_enable, 4250 .ppu_disable = mv88e6185_g1_ppu_disable, 4251 .reset = mv88e6185_g1_reset, 4252 .rmu_disable = mv88e6085_g1_rmu_disable, 4253 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4254 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4255 .stu_getnext = mv88e6352_g1_stu_getnext, 4256 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4257 .phylink_get_caps = mv88e6185_phylink_get_caps, 4258 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4259 }; 4260 4261 static const struct mv88e6xxx_ops mv88e6095_ops = { 4262 /* MV88E6XXX_FAMILY_6095 */ 4263 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4264 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4265 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4266 .phy_read = mv88e6185_phy_ppu_read, 4267 .phy_write = mv88e6185_phy_ppu_write, 4268 .port_set_link = mv88e6xxx_port_set_link, 4269 .port_sync_link = mv88e6185_port_sync_link, 4270 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4271 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4272 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4273 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4274 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4275 .port_get_cmode = mv88e6185_port_get_cmode, 4276 .port_setup_message_port = mv88e6xxx_setup_message_port, 4277 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4278 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4279 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4280 .stats_get_strings = mv88e6095_stats_get_strings, 4281 .stats_get_stat = mv88e6095_stats_get_stat, 4282 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4283 .ppu_enable = mv88e6185_g1_ppu_enable, 4284 .ppu_disable = mv88e6185_g1_ppu_disable, 4285 .reset = mv88e6185_g1_reset, 4286 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4287 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4288 .phylink_get_caps = mv88e6095_phylink_get_caps, 4289 .pcs_ops = &mv88e6185_pcs_ops, 4290 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4291 }; 4292 4293 static const struct mv88e6xxx_ops mv88e6097_ops = { 4294 /* MV88E6XXX_FAMILY_6097 */ 4295 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4296 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4297 .irl_init_all = mv88e6352_g2_irl_init_all, 4298 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4299 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4300 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4301 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4302 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4303 .port_set_link = mv88e6xxx_port_set_link, 4304 .port_sync_link = mv88e6185_port_sync_link, 4305 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4306 .port_tag_remap = mv88e6095_port_tag_remap, 4307 .port_set_policy = mv88e6352_port_set_policy, 4308 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4309 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4310 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4311 .port_set_ether_type = mv88e6351_port_set_ether_type, 4312 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4313 .port_pause_limit = mv88e6097_port_pause_limit, 4314 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4315 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4316 .port_get_cmode = mv88e6185_port_get_cmode, 4317 .port_setup_message_port = mv88e6xxx_setup_message_port, 4318 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4319 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4320 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4321 .stats_get_strings = mv88e6095_stats_get_strings, 4322 .stats_get_stat = mv88e6095_stats_get_stat, 4323 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4324 .set_egress_port = mv88e6095_g1_set_egress_port, 4325 .watchdog_ops = &mv88e6097_watchdog_ops, 4326 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4327 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4328 .pot_clear = mv88e6xxx_g2_pot_clear, 4329 .reset = mv88e6352_g1_reset, 4330 .rmu_disable = mv88e6085_g1_rmu_disable, 4331 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4332 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4333 .phylink_get_caps = mv88e6095_phylink_get_caps, 4334 .pcs_ops = &mv88e6185_pcs_ops, 4335 .stu_getnext = mv88e6352_g1_stu_getnext, 4336 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4337 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4338 }; 4339 4340 static const struct mv88e6xxx_ops mv88e6123_ops = { 4341 /* MV88E6XXX_FAMILY_6165 */ 4342 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4343 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4344 .irl_init_all = mv88e6352_g2_irl_init_all, 4345 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4346 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4347 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4348 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4349 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4350 .port_set_link = mv88e6xxx_port_set_link, 4351 .port_sync_link = mv88e6xxx_port_sync_link, 4352 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4353 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4354 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4355 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4356 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4357 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4358 .port_get_cmode = mv88e6185_port_get_cmode, 4359 .port_setup_message_port = mv88e6xxx_setup_message_port, 4360 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4361 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4362 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4363 .stats_get_strings = mv88e6095_stats_get_strings, 4364 .stats_get_stat = mv88e6095_stats_get_stat, 4365 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4366 .set_egress_port = mv88e6095_g1_set_egress_port, 4367 .watchdog_ops = &mv88e6097_watchdog_ops, 4368 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4369 .pot_clear = mv88e6xxx_g2_pot_clear, 4370 .reset = mv88e6352_g1_reset, 4371 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4372 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4373 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4374 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4375 .stu_getnext = mv88e6352_g1_stu_getnext, 4376 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4377 .phylink_get_caps = mv88e6185_phylink_get_caps, 4378 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4379 }; 4380 4381 static const struct mv88e6xxx_ops mv88e6131_ops = { 4382 /* MV88E6XXX_FAMILY_6185 */ 4383 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4384 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4385 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4386 .phy_read = mv88e6185_phy_ppu_read, 4387 .phy_write = mv88e6185_phy_ppu_write, 4388 .port_set_link = mv88e6xxx_port_set_link, 4389 .port_sync_link = mv88e6xxx_port_sync_link, 4390 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4391 .port_tag_remap = mv88e6095_port_tag_remap, 4392 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4393 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4394 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4395 .port_set_ether_type = mv88e6351_port_set_ether_type, 4396 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4397 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4398 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4399 .port_pause_limit = mv88e6097_port_pause_limit, 4400 .port_set_pause = mv88e6185_port_set_pause, 4401 .port_get_cmode = mv88e6185_port_get_cmode, 4402 .port_setup_message_port = mv88e6xxx_setup_message_port, 4403 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4404 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4405 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4406 .stats_get_strings = mv88e6095_stats_get_strings, 4407 .stats_get_stat = mv88e6095_stats_get_stat, 4408 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4409 .set_egress_port = mv88e6095_g1_set_egress_port, 4410 .watchdog_ops = &mv88e6097_watchdog_ops, 4411 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4412 .ppu_enable = mv88e6185_g1_ppu_enable, 4413 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4414 .ppu_disable = mv88e6185_g1_ppu_disable, 4415 .reset = mv88e6185_g1_reset, 4416 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4417 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4418 .phylink_get_caps = mv88e6185_phylink_get_caps, 4419 }; 4420 4421 static const struct mv88e6xxx_ops mv88e6141_ops = { 4422 /* MV88E6XXX_FAMILY_6341 */ 4423 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4424 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4425 .irl_init_all = mv88e6352_g2_irl_init_all, 4426 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4427 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4428 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4429 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4430 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4431 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4432 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4433 .port_set_link = mv88e6xxx_port_set_link, 4434 .port_sync_link = mv88e6xxx_port_sync_link, 4435 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4436 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4437 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4438 .port_tag_remap = mv88e6095_port_tag_remap, 4439 .port_set_policy = mv88e6352_port_set_policy, 4440 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4441 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4442 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4443 .port_set_ether_type = mv88e6351_port_set_ether_type, 4444 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4445 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4446 .port_pause_limit = mv88e6097_port_pause_limit, 4447 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4448 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4449 .port_get_cmode = mv88e6352_port_get_cmode, 4450 .port_set_cmode = mv88e6341_port_set_cmode, 4451 .port_setup_message_port = mv88e6xxx_setup_message_port, 4452 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4453 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4454 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4455 .stats_get_strings = mv88e6320_stats_get_strings, 4456 .stats_get_stat = mv88e6390_stats_get_stat, 4457 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4458 .set_egress_port = mv88e6390_g1_set_egress_port, 4459 .watchdog_ops = &mv88e6390_watchdog_ops, 4460 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4461 .pot_clear = mv88e6xxx_g2_pot_clear, 4462 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4463 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4464 .reset = mv88e6352_g1_reset, 4465 .rmu_disable = mv88e6390_g1_rmu_disable, 4466 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4467 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4468 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4469 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4470 .stu_getnext = mv88e6352_g1_stu_getnext, 4471 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4472 .serdes_get_lane = mv88e6341_serdes_get_lane, 4473 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4474 .gpio_ops = &mv88e6352_gpio_ops, 4475 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4476 .serdes_get_strings = mv88e6390_serdes_get_strings, 4477 .serdes_get_stats = mv88e6390_serdes_get_stats, 4478 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4479 .serdes_get_regs = mv88e6390_serdes_get_regs, 4480 .phylink_get_caps = mv88e6341_phylink_get_caps, 4481 .pcs_ops = &mv88e6390_pcs_ops, 4482 }; 4483 4484 static const struct mv88e6xxx_ops mv88e6161_ops = { 4485 /* MV88E6XXX_FAMILY_6165 */ 4486 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4487 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4488 .irl_init_all = mv88e6352_g2_irl_init_all, 4489 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4490 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4491 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4492 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4493 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4494 .port_set_link = mv88e6xxx_port_set_link, 4495 .port_sync_link = mv88e6xxx_port_sync_link, 4496 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4497 .port_tag_remap = mv88e6095_port_tag_remap, 4498 .port_set_policy = mv88e6352_port_set_policy, 4499 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4500 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4501 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4502 .port_set_ether_type = mv88e6351_port_set_ether_type, 4503 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4504 .port_pause_limit = mv88e6097_port_pause_limit, 4505 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4506 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4507 .port_get_cmode = mv88e6185_port_get_cmode, 4508 .port_setup_message_port = mv88e6xxx_setup_message_port, 4509 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4510 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4511 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4512 .stats_get_strings = mv88e6095_stats_get_strings, 4513 .stats_get_stat = mv88e6095_stats_get_stat, 4514 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4515 .set_egress_port = mv88e6095_g1_set_egress_port, 4516 .watchdog_ops = &mv88e6097_watchdog_ops, 4517 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4518 .pot_clear = mv88e6xxx_g2_pot_clear, 4519 .reset = mv88e6352_g1_reset, 4520 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4521 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4522 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4523 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4524 .stu_getnext = mv88e6352_g1_stu_getnext, 4525 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4526 .avb_ops = &mv88e6165_avb_ops, 4527 .ptp_ops = &mv88e6165_ptp_ops, 4528 .phylink_get_caps = mv88e6185_phylink_get_caps, 4529 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4530 }; 4531 4532 static const struct mv88e6xxx_ops mv88e6165_ops = { 4533 /* MV88E6XXX_FAMILY_6165 */ 4534 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4535 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4536 .irl_init_all = mv88e6352_g2_irl_init_all, 4537 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4538 .phy_read = mv88e6165_phy_read, 4539 .phy_write = mv88e6165_phy_write, 4540 .port_set_link = mv88e6xxx_port_set_link, 4541 .port_sync_link = mv88e6xxx_port_sync_link, 4542 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4543 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4544 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4545 .port_get_cmode = mv88e6185_port_get_cmode, 4546 .port_setup_message_port = mv88e6xxx_setup_message_port, 4547 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4548 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4549 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4550 .stats_get_strings = mv88e6095_stats_get_strings, 4551 .stats_get_stat = mv88e6095_stats_get_stat, 4552 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4553 .set_egress_port = mv88e6095_g1_set_egress_port, 4554 .watchdog_ops = &mv88e6097_watchdog_ops, 4555 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4556 .pot_clear = mv88e6xxx_g2_pot_clear, 4557 .reset = mv88e6352_g1_reset, 4558 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4559 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4560 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4561 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4562 .stu_getnext = mv88e6352_g1_stu_getnext, 4563 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4564 .avb_ops = &mv88e6165_avb_ops, 4565 .ptp_ops = &mv88e6165_ptp_ops, 4566 .phylink_get_caps = mv88e6185_phylink_get_caps, 4567 }; 4568 4569 static const struct mv88e6xxx_ops mv88e6171_ops = { 4570 /* MV88E6XXX_FAMILY_6351 */ 4571 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4572 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4573 .irl_init_all = mv88e6352_g2_irl_init_all, 4574 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4575 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4576 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4577 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4578 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4579 .port_set_link = mv88e6xxx_port_set_link, 4580 .port_sync_link = mv88e6xxx_port_sync_link, 4581 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4582 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4583 .port_tag_remap = mv88e6095_port_tag_remap, 4584 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4585 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4586 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4587 .port_set_ether_type = mv88e6351_port_set_ether_type, 4588 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4589 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4590 .port_pause_limit = mv88e6097_port_pause_limit, 4591 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4592 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4593 .port_get_cmode = mv88e6352_port_get_cmode, 4594 .port_setup_message_port = mv88e6xxx_setup_message_port, 4595 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4596 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4597 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4598 .stats_get_strings = mv88e6095_stats_get_strings, 4599 .stats_get_stat = mv88e6095_stats_get_stat, 4600 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4601 .set_egress_port = mv88e6095_g1_set_egress_port, 4602 .watchdog_ops = &mv88e6097_watchdog_ops, 4603 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4604 .pot_clear = mv88e6xxx_g2_pot_clear, 4605 .reset = mv88e6352_g1_reset, 4606 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4607 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4608 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4609 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4610 .stu_getnext = mv88e6352_g1_stu_getnext, 4611 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4612 .phylink_get_caps = mv88e6351_phylink_get_caps, 4613 }; 4614 4615 static const struct mv88e6xxx_ops mv88e6172_ops = { 4616 /* MV88E6XXX_FAMILY_6352 */ 4617 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4618 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4619 .irl_init_all = mv88e6352_g2_irl_init_all, 4620 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4621 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4622 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4623 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4624 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4625 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4626 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4627 .port_set_link = mv88e6xxx_port_set_link, 4628 .port_sync_link = mv88e6xxx_port_sync_link, 4629 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4630 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4631 .port_tag_remap = mv88e6095_port_tag_remap, 4632 .port_set_policy = mv88e6352_port_set_policy, 4633 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4634 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4635 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4636 .port_set_ether_type = mv88e6351_port_set_ether_type, 4637 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4638 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4639 .port_pause_limit = mv88e6097_port_pause_limit, 4640 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4641 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4642 .port_get_cmode = mv88e6352_port_get_cmode, 4643 .port_setup_leds = mv88e6xxx_port_setup_leds, 4644 .port_setup_message_port = mv88e6xxx_setup_message_port, 4645 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4646 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4647 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4648 .stats_get_strings = mv88e6095_stats_get_strings, 4649 .stats_get_stat = mv88e6095_stats_get_stat, 4650 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4651 .set_egress_port = mv88e6095_g1_set_egress_port, 4652 .watchdog_ops = &mv88e6097_watchdog_ops, 4653 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4654 .pot_clear = mv88e6xxx_g2_pot_clear, 4655 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4656 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4657 .reset = mv88e6352_g1_reset, 4658 .rmu_disable = mv88e6352_g1_rmu_disable, 4659 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4660 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4661 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4662 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4663 .stu_getnext = mv88e6352_g1_stu_getnext, 4664 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4665 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4666 .serdes_get_regs = mv88e6352_serdes_get_regs, 4667 .gpio_ops = &mv88e6352_gpio_ops, 4668 .phylink_get_caps = mv88e6352_phylink_get_caps, 4669 .pcs_ops = &mv88e6352_pcs_ops, 4670 }; 4671 4672 static const struct mv88e6xxx_ops mv88e6175_ops = { 4673 /* MV88E6XXX_FAMILY_6351 */ 4674 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4675 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4676 .irl_init_all = mv88e6352_g2_irl_init_all, 4677 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4678 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4679 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4680 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4681 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4682 .port_set_link = mv88e6xxx_port_set_link, 4683 .port_sync_link = mv88e6xxx_port_sync_link, 4684 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4685 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4686 .port_tag_remap = mv88e6095_port_tag_remap, 4687 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4688 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4689 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4690 .port_set_ether_type = mv88e6351_port_set_ether_type, 4691 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4692 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4693 .port_pause_limit = mv88e6097_port_pause_limit, 4694 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4695 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4696 .port_get_cmode = mv88e6352_port_get_cmode, 4697 .port_setup_message_port = mv88e6xxx_setup_message_port, 4698 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4699 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4700 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4701 .stats_get_strings = mv88e6095_stats_get_strings, 4702 .stats_get_stat = mv88e6095_stats_get_stat, 4703 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4704 .set_egress_port = mv88e6095_g1_set_egress_port, 4705 .watchdog_ops = &mv88e6097_watchdog_ops, 4706 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4707 .pot_clear = mv88e6xxx_g2_pot_clear, 4708 .reset = mv88e6352_g1_reset, 4709 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4710 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4711 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4712 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4713 .stu_getnext = mv88e6352_g1_stu_getnext, 4714 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4715 .phylink_get_caps = mv88e6351_phylink_get_caps, 4716 }; 4717 4718 static const struct mv88e6xxx_ops mv88e6176_ops = { 4719 /* MV88E6XXX_FAMILY_6352 */ 4720 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4721 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4722 .irl_init_all = mv88e6352_g2_irl_init_all, 4723 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4724 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4725 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4726 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4727 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4728 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4729 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4730 .port_set_link = mv88e6xxx_port_set_link, 4731 .port_sync_link = mv88e6xxx_port_sync_link, 4732 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4733 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4734 .port_tag_remap = mv88e6095_port_tag_remap, 4735 .port_set_policy = mv88e6352_port_set_policy, 4736 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4737 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4738 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4739 .port_set_ether_type = mv88e6351_port_set_ether_type, 4740 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4741 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4742 .port_pause_limit = mv88e6097_port_pause_limit, 4743 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4744 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4745 .port_get_cmode = mv88e6352_port_get_cmode, 4746 .port_setup_leds = mv88e6xxx_port_setup_leds, 4747 .port_setup_message_port = mv88e6xxx_setup_message_port, 4748 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4749 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4750 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4751 .stats_get_strings = mv88e6095_stats_get_strings, 4752 .stats_get_stat = mv88e6095_stats_get_stat, 4753 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4754 .set_egress_port = mv88e6095_g1_set_egress_port, 4755 .watchdog_ops = &mv88e6097_watchdog_ops, 4756 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4757 .pot_clear = mv88e6xxx_g2_pot_clear, 4758 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4759 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4760 .reset = mv88e6352_g1_reset, 4761 .rmu_disable = mv88e6352_g1_rmu_disable, 4762 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4763 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4764 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4765 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4766 .stu_getnext = mv88e6352_g1_stu_getnext, 4767 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4768 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4769 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4770 .serdes_get_regs = mv88e6352_serdes_get_regs, 4771 .gpio_ops = &mv88e6352_gpio_ops, 4772 .phylink_get_caps = mv88e6352_phylink_get_caps, 4773 .pcs_ops = &mv88e6352_pcs_ops, 4774 }; 4775 4776 static const struct mv88e6xxx_ops mv88e6185_ops = { 4777 /* MV88E6XXX_FAMILY_6185 */ 4778 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4779 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4780 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4781 .phy_read = mv88e6185_phy_ppu_read, 4782 .phy_write = mv88e6185_phy_ppu_write, 4783 .port_set_link = mv88e6xxx_port_set_link, 4784 .port_sync_link = mv88e6185_port_sync_link, 4785 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4786 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4787 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4788 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4789 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4790 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4791 .port_set_pause = mv88e6185_port_set_pause, 4792 .port_get_cmode = mv88e6185_port_get_cmode, 4793 .port_setup_message_port = mv88e6xxx_setup_message_port, 4794 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4795 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4796 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4797 .stats_get_strings = mv88e6095_stats_get_strings, 4798 .stats_get_stat = mv88e6095_stats_get_stat, 4799 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4800 .set_egress_port = mv88e6095_g1_set_egress_port, 4801 .watchdog_ops = &mv88e6097_watchdog_ops, 4802 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4803 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4804 .ppu_enable = mv88e6185_g1_ppu_enable, 4805 .ppu_disable = mv88e6185_g1_ppu_disable, 4806 .reset = mv88e6185_g1_reset, 4807 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4808 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4809 .phylink_get_caps = mv88e6185_phylink_get_caps, 4810 .pcs_ops = &mv88e6185_pcs_ops, 4811 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4812 }; 4813 4814 static const struct mv88e6xxx_ops mv88e6190_ops = { 4815 /* MV88E6XXX_FAMILY_6390 */ 4816 .setup_errata = mv88e6390_setup_errata, 4817 .irl_init_all = mv88e6390_g2_irl_init_all, 4818 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4819 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4820 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4821 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4822 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4823 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4824 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4825 .port_set_link = mv88e6xxx_port_set_link, 4826 .port_sync_link = mv88e6xxx_port_sync_link, 4827 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4828 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4829 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4830 .port_tag_remap = mv88e6390_port_tag_remap, 4831 .port_set_policy = mv88e6352_port_set_policy, 4832 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4833 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4834 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4835 .port_set_ether_type = mv88e6351_port_set_ether_type, 4836 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4837 .port_pause_limit = mv88e6390_port_pause_limit, 4838 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4839 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4840 .port_get_cmode = mv88e6352_port_get_cmode, 4841 .port_set_cmode = mv88e6390_port_set_cmode, 4842 .port_setup_message_port = mv88e6xxx_setup_message_port, 4843 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4844 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4845 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4846 .stats_get_strings = mv88e6320_stats_get_strings, 4847 .stats_get_stat = mv88e6390_stats_get_stat, 4848 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4849 .set_egress_port = mv88e6390_g1_set_egress_port, 4850 .watchdog_ops = &mv88e6390_watchdog_ops, 4851 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4852 .pot_clear = mv88e6xxx_g2_pot_clear, 4853 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4854 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4855 .reset = mv88e6352_g1_reset, 4856 .rmu_disable = mv88e6390_g1_rmu_disable, 4857 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4858 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4859 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4860 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4861 .stu_getnext = mv88e6390_g1_stu_getnext, 4862 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4863 .serdes_get_lane = mv88e6390_serdes_get_lane, 4864 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4865 .serdes_get_strings = mv88e6390_serdes_get_strings, 4866 .serdes_get_stats = mv88e6390_serdes_get_stats, 4867 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4868 .serdes_get_regs = mv88e6390_serdes_get_regs, 4869 .gpio_ops = &mv88e6352_gpio_ops, 4870 .phylink_get_caps = mv88e6390_phylink_get_caps, 4871 .pcs_ops = &mv88e6390_pcs_ops, 4872 }; 4873 4874 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4875 /* MV88E6XXX_FAMILY_6390 */ 4876 .setup_errata = mv88e6390_setup_errata, 4877 .irl_init_all = mv88e6390_g2_irl_init_all, 4878 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4879 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4880 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4881 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4882 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4883 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4884 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4885 .port_set_link = mv88e6xxx_port_set_link, 4886 .port_sync_link = mv88e6xxx_port_sync_link, 4887 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4888 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4889 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4890 .port_tag_remap = mv88e6390_port_tag_remap, 4891 .port_set_policy = mv88e6352_port_set_policy, 4892 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4893 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4894 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4895 .port_set_ether_type = mv88e6351_port_set_ether_type, 4896 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4897 .port_pause_limit = mv88e6390_port_pause_limit, 4898 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4899 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4900 .port_get_cmode = mv88e6352_port_get_cmode, 4901 .port_set_cmode = mv88e6390x_port_set_cmode, 4902 .port_setup_message_port = mv88e6xxx_setup_message_port, 4903 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4904 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4905 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4906 .stats_get_strings = mv88e6320_stats_get_strings, 4907 .stats_get_stat = mv88e6390_stats_get_stat, 4908 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4909 .set_egress_port = mv88e6390_g1_set_egress_port, 4910 .watchdog_ops = &mv88e6390_watchdog_ops, 4911 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4912 .pot_clear = mv88e6xxx_g2_pot_clear, 4913 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4914 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4915 .reset = mv88e6352_g1_reset, 4916 .rmu_disable = mv88e6390_g1_rmu_disable, 4917 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4918 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4919 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4920 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4921 .stu_getnext = mv88e6390_g1_stu_getnext, 4922 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4923 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4924 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4925 .serdes_get_strings = mv88e6390_serdes_get_strings, 4926 .serdes_get_stats = mv88e6390_serdes_get_stats, 4927 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4928 .serdes_get_regs = mv88e6390_serdes_get_regs, 4929 .gpio_ops = &mv88e6352_gpio_ops, 4930 .phylink_get_caps = mv88e6390x_phylink_get_caps, 4931 .pcs_ops = &mv88e6390_pcs_ops, 4932 }; 4933 4934 static const struct mv88e6xxx_ops mv88e6191_ops = { 4935 /* MV88E6XXX_FAMILY_6390 */ 4936 .setup_errata = mv88e6390_setup_errata, 4937 .irl_init_all = mv88e6390_g2_irl_init_all, 4938 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4939 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4940 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4941 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4942 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4943 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4944 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4945 .port_set_link = mv88e6xxx_port_set_link, 4946 .port_sync_link = mv88e6xxx_port_sync_link, 4947 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4948 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4949 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4950 .port_tag_remap = mv88e6390_port_tag_remap, 4951 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4952 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4953 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4954 .port_set_ether_type = mv88e6351_port_set_ether_type, 4955 .port_pause_limit = mv88e6390_port_pause_limit, 4956 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4957 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4958 .port_get_cmode = mv88e6352_port_get_cmode, 4959 .port_set_cmode = mv88e6390_port_set_cmode, 4960 .port_setup_message_port = mv88e6xxx_setup_message_port, 4961 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4962 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4963 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4964 .stats_get_strings = mv88e6320_stats_get_strings, 4965 .stats_get_stat = mv88e6390_stats_get_stat, 4966 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4967 .set_egress_port = mv88e6390_g1_set_egress_port, 4968 .watchdog_ops = &mv88e6390_watchdog_ops, 4969 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4970 .pot_clear = mv88e6xxx_g2_pot_clear, 4971 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4972 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4973 .reset = mv88e6352_g1_reset, 4974 .rmu_disable = mv88e6390_g1_rmu_disable, 4975 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4976 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4977 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4978 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4979 .stu_getnext = mv88e6390_g1_stu_getnext, 4980 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4981 .serdes_get_lane = mv88e6390_serdes_get_lane, 4982 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4983 .serdes_get_strings = mv88e6390_serdes_get_strings, 4984 .serdes_get_stats = mv88e6390_serdes_get_stats, 4985 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4986 .serdes_get_regs = mv88e6390_serdes_get_regs, 4987 .avb_ops = &mv88e6390_avb_ops, 4988 .ptp_ops = &mv88e6352_ptp_ops, 4989 .phylink_get_caps = mv88e6390_phylink_get_caps, 4990 .pcs_ops = &mv88e6390_pcs_ops, 4991 }; 4992 4993 static const struct mv88e6xxx_ops mv88e6240_ops = { 4994 /* MV88E6XXX_FAMILY_6352 */ 4995 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4996 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4997 .irl_init_all = mv88e6352_g2_irl_init_all, 4998 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4999 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5000 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5001 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5002 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5003 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5004 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5005 .port_set_link = mv88e6xxx_port_set_link, 5006 .port_sync_link = mv88e6xxx_port_sync_link, 5007 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5008 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 5009 .port_tag_remap = mv88e6095_port_tag_remap, 5010 .port_set_policy = mv88e6352_port_set_policy, 5011 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5012 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5013 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5014 .port_set_ether_type = mv88e6351_port_set_ether_type, 5015 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5016 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5017 .port_pause_limit = mv88e6097_port_pause_limit, 5018 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5019 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5020 .port_get_cmode = mv88e6352_port_get_cmode, 5021 .port_setup_leds = mv88e6xxx_port_setup_leds, 5022 .port_setup_message_port = mv88e6xxx_setup_message_port, 5023 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5024 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5025 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5026 .stats_get_strings = mv88e6095_stats_get_strings, 5027 .stats_get_stat = mv88e6095_stats_get_stat, 5028 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5029 .set_egress_port = mv88e6095_g1_set_egress_port, 5030 .watchdog_ops = &mv88e6097_watchdog_ops, 5031 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5032 .pot_clear = mv88e6xxx_g2_pot_clear, 5033 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5034 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5035 .reset = mv88e6352_g1_reset, 5036 .rmu_disable = mv88e6352_g1_rmu_disable, 5037 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5038 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5039 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5040 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5041 .stu_getnext = mv88e6352_g1_stu_getnext, 5042 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5043 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5044 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5045 .serdes_get_regs = mv88e6352_serdes_get_regs, 5046 .gpio_ops = &mv88e6352_gpio_ops, 5047 .avb_ops = &mv88e6352_avb_ops, 5048 .ptp_ops = &mv88e6352_ptp_ops, 5049 .phylink_get_caps = mv88e6352_phylink_get_caps, 5050 .pcs_ops = &mv88e6352_pcs_ops, 5051 }; 5052 5053 static const struct mv88e6xxx_ops mv88e6250_ops = { 5054 /* MV88E6XXX_FAMILY_6250 */ 5055 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 5056 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5057 .irl_init_all = mv88e6352_g2_irl_init_all, 5058 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5059 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5060 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5061 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5062 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5063 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5064 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5065 .port_set_link = mv88e6xxx_port_set_link, 5066 .port_sync_link = mv88e6xxx_port_sync_link, 5067 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5068 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 5069 .port_tag_remap = mv88e6095_port_tag_remap, 5070 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5071 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5072 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5073 .port_set_ether_type = mv88e6351_port_set_ether_type, 5074 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5075 .port_pause_limit = mv88e6097_port_pause_limit, 5076 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5077 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5078 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5079 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 5080 .stats_get_strings = mv88e6250_stats_get_strings, 5081 .stats_get_stat = mv88e6250_stats_get_stat, 5082 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5083 .set_egress_port = mv88e6095_g1_set_egress_port, 5084 .watchdog_ops = &mv88e6250_watchdog_ops, 5085 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5086 .pot_clear = mv88e6xxx_g2_pot_clear, 5087 .hardware_reset_pre = mv88e6250_g1_wait_eeprom_done_prereset, 5088 .hardware_reset_post = mv88e6xxx_g1_wait_eeprom_done, 5089 .reset = mv88e6250_g1_reset, 5090 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5091 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5092 .avb_ops = &mv88e6352_avb_ops, 5093 .ptp_ops = &mv88e6352_ptp_ops, 5094 .phylink_get_caps = mv88e6250_phylink_get_caps, 5095 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 5096 }; 5097 5098 static const struct mv88e6xxx_ops mv88e6290_ops = { 5099 /* MV88E6XXX_FAMILY_6390 */ 5100 .setup_errata = mv88e6390_setup_errata, 5101 .irl_init_all = mv88e6390_g2_irl_init_all, 5102 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5103 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5104 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5105 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5106 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5107 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5108 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5109 .port_set_link = mv88e6xxx_port_set_link, 5110 .port_sync_link = mv88e6xxx_port_sync_link, 5111 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5112 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5113 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5114 .port_tag_remap = mv88e6390_port_tag_remap, 5115 .port_set_policy = mv88e6352_port_set_policy, 5116 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5117 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5118 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5119 .port_set_ether_type = mv88e6351_port_set_ether_type, 5120 .port_pause_limit = mv88e6390_port_pause_limit, 5121 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5122 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5123 .port_get_cmode = mv88e6352_port_get_cmode, 5124 .port_set_cmode = mv88e6390_port_set_cmode, 5125 .port_setup_message_port = mv88e6xxx_setup_message_port, 5126 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5127 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5128 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5129 .stats_get_strings = mv88e6320_stats_get_strings, 5130 .stats_get_stat = mv88e6390_stats_get_stat, 5131 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5132 .set_egress_port = mv88e6390_g1_set_egress_port, 5133 .watchdog_ops = &mv88e6390_watchdog_ops, 5134 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5135 .pot_clear = mv88e6xxx_g2_pot_clear, 5136 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5137 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5138 .reset = mv88e6352_g1_reset, 5139 .rmu_disable = mv88e6390_g1_rmu_disable, 5140 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5141 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5142 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5143 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5144 .stu_getnext = mv88e6390_g1_stu_getnext, 5145 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5146 .serdes_get_lane = mv88e6390_serdes_get_lane, 5147 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5148 .serdes_get_strings = mv88e6390_serdes_get_strings, 5149 .serdes_get_stats = mv88e6390_serdes_get_stats, 5150 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5151 .serdes_get_regs = mv88e6390_serdes_get_regs, 5152 .gpio_ops = &mv88e6352_gpio_ops, 5153 .avb_ops = &mv88e6390_avb_ops, 5154 .ptp_ops = &mv88e6390_ptp_ops, 5155 .phylink_get_caps = mv88e6390_phylink_get_caps, 5156 .pcs_ops = &mv88e6390_pcs_ops, 5157 .tcam_ops = &mv88e6390_tcam_ops, 5158 }; 5159 5160 static const struct mv88e6xxx_ops mv88e6320_ops = { 5161 /* MV88E6XXX_FAMILY_6320 */ 5162 .setup_errata = mv88e6320_setup_errata, 5163 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5164 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5165 .irl_init_all = mv88e6352_g2_irl_init_all, 5166 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5167 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5168 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5169 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5170 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5171 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5172 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5173 .port_set_link = mv88e6xxx_port_set_link, 5174 .port_sync_link = mv88e6xxx_port_sync_link, 5175 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5176 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5177 .port_tag_remap = mv88e6095_port_tag_remap, 5178 .port_set_policy = mv88e6352_port_set_policy, 5179 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5180 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5181 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5182 .port_set_ether_type = mv88e6351_port_set_ether_type, 5183 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5184 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5185 .port_pause_limit = mv88e6097_port_pause_limit, 5186 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5187 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5188 .port_get_cmode = mv88e6352_port_get_cmode, 5189 .port_setup_message_port = mv88e6xxx_setup_message_port, 5190 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5191 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5192 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5193 .stats_get_strings = mv88e6320_stats_get_strings, 5194 .stats_get_stat = mv88e6320_stats_get_stat, 5195 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5196 .set_egress_port = mv88e6095_g1_set_egress_port, 5197 .watchdog_ops = &mv88e6390_watchdog_ops, 5198 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5199 .pot_clear = mv88e6xxx_g2_pot_clear, 5200 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5201 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5202 .reset = mv88e6352_g1_reset, 5203 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5204 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5205 .stu_getnext = mv88e6352_g1_stu_getnext, 5206 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5207 .gpio_ops = &mv88e6352_gpio_ops, 5208 .avb_ops = &mv88e6352_avb_ops, 5209 .ptp_ops = &mv88e6352_ptp_ops, 5210 .phylink_get_caps = mv88e632x_phylink_get_caps, 5211 }; 5212 5213 static const struct mv88e6xxx_ops mv88e6321_ops = { 5214 /* MV88E6XXX_FAMILY_6320 */ 5215 .setup_errata = mv88e6320_setup_errata, 5216 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5217 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5218 .irl_init_all = mv88e6352_g2_irl_init_all, 5219 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5220 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5221 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5222 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5223 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5224 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5225 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5226 .port_set_link = mv88e6xxx_port_set_link, 5227 .port_sync_link = mv88e6xxx_port_sync_link, 5228 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5229 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5230 .port_tag_remap = mv88e6095_port_tag_remap, 5231 .port_set_policy = mv88e6352_port_set_policy, 5232 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5233 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5234 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5235 .port_set_ether_type = mv88e6351_port_set_ether_type, 5236 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5237 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5238 .port_pause_limit = mv88e6097_port_pause_limit, 5239 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5240 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5241 .port_get_cmode = mv88e6352_port_get_cmode, 5242 .port_setup_message_port = mv88e6xxx_setup_message_port, 5243 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5244 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5245 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5246 .stats_get_strings = mv88e6320_stats_get_strings, 5247 .stats_get_stat = mv88e6320_stats_get_stat, 5248 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5249 .set_egress_port = mv88e6095_g1_set_egress_port, 5250 .watchdog_ops = &mv88e6390_watchdog_ops, 5251 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5252 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5253 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5254 .reset = mv88e6352_g1_reset, 5255 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5256 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5257 .stu_getnext = mv88e6352_g1_stu_getnext, 5258 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5259 .gpio_ops = &mv88e6352_gpio_ops, 5260 .avb_ops = &mv88e6352_avb_ops, 5261 .ptp_ops = &mv88e6352_ptp_ops, 5262 .phylink_get_caps = mv88e632x_phylink_get_caps, 5263 }; 5264 5265 static const struct mv88e6xxx_ops mv88e6341_ops = { 5266 /* MV88E6XXX_FAMILY_6341 */ 5267 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5268 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5269 .irl_init_all = mv88e6352_g2_irl_init_all, 5270 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5271 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5272 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5273 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5274 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5275 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5276 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5277 .port_set_link = mv88e6xxx_port_set_link, 5278 .port_sync_link = mv88e6xxx_port_sync_link, 5279 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5280 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 5281 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 5282 .port_tag_remap = mv88e6095_port_tag_remap, 5283 .port_set_policy = mv88e6352_port_set_policy, 5284 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5285 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5286 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5287 .port_set_ether_type = mv88e6351_port_set_ether_type, 5288 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5289 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5290 .port_pause_limit = mv88e6097_port_pause_limit, 5291 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5292 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5293 .port_get_cmode = mv88e6352_port_get_cmode, 5294 .port_set_cmode = mv88e6341_port_set_cmode, 5295 .port_setup_message_port = mv88e6xxx_setup_message_port, 5296 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5297 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5298 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5299 .stats_get_strings = mv88e6320_stats_get_strings, 5300 .stats_get_stat = mv88e6390_stats_get_stat, 5301 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5302 .set_egress_port = mv88e6390_g1_set_egress_port, 5303 .watchdog_ops = &mv88e6390_watchdog_ops, 5304 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5305 .pot_clear = mv88e6xxx_g2_pot_clear, 5306 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5307 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5308 .reset = mv88e6352_g1_reset, 5309 .rmu_disable = mv88e6390_g1_rmu_disable, 5310 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5311 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5312 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5313 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5314 .stu_getnext = mv88e6352_g1_stu_getnext, 5315 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5316 .serdes_get_lane = mv88e6341_serdes_get_lane, 5317 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5318 .gpio_ops = &mv88e6352_gpio_ops, 5319 .avb_ops = &mv88e6390_avb_ops, 5320 .ptp_ops = &mv88e6352_ptp_ops, 5321 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5322 .serdes_get_strings = mv88e6390_serdes_get_strings, 5323 .serdes_get_stats = mv88e6390_serdes_get_stats, 5324 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5325 .serdes_get_regs = mv88e6390_serdes_get_regs, 5326 .phylink_get_caps = mv88e6341_phylink_get_caps, 5327 .pcs_ops = &mv88e6390_pcs_ops, 5328 }; 5329 5330 static const struct mv88e6xxx_ops mv88e6350_ops = { 5331 /* MV88E6XXX_FAMILY_6351 */ 5332 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5333 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5334 .irl_init_all = mv88e6352_g2_irl_init_all, 5335 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5336 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5337 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5338 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5339 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5340 .port_set_link = mv88e6xxx_port_set_link, 5341 .port_sync_link = mv88e6xxx_port_sync_link, 5342 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5343 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5344 .port_tag_remap = mv88e6095_port_tag_remap, 5345 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5346 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5347 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5348 .port_set_ether_type = mv88e6351_port_set_ether_type, 5349 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5350 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5351 .port_pause_limit = mv88e6097_port_pause_limit, 5352 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5353 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5354 .port_get_cmode = mv88e6352_port_get_cmode, 5355 .port_setup_message_port = mv88e6xxx_setup_message_port, 5356 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5357 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5358 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5359 .stats_get_strings = mv88e6095_stats_get_strings, 5360 .stats_get_stat = mv88e6095_stats_get_stat, 5361 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5362 .set_egress_port = mv88e6095_g1_set_egress_port, 5363 .watchdog_ops = &mv88e6097_watchdog_ops, 5364 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5365 .pot_clear = mv88e6xxx_g2_pot_clear, 5366 .reset = mv88e6352_g1_reset, 5367 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5368 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5369 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5370 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5371 .stu_getnext = mv88e6352_g1_stu_getnext, 5372 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5373 .phylink_get_caps = mv88e6351_phylink_get_caps, 5374 }; 5375 5376 static const struct mv88e6xxx_ops mv88e6351_ops = { 5377 /* MV88E6XXX_FAMILY_6351 */ 5378 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5379 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5380 .irl_init_all = mv88e6352_g2_irl_init_all, 5381 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5382 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5383 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5384 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5385 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5386 .port_set_link = mv88e6xxx_port_set_link, 5387 .port_sync_link = mv88e6xxx_port_sync_link, 5388 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5389 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5390 .port_tag_remap = mv88e6095_port_tag_remap, 5391 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5392 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5393 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5394 .port_set_ether_type = mv88e6351_port_set_ether_type, 5395 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5396 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5397 .port_pause_limit = mv88e6097_port_pause_limit, 5398 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5399 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5400 .port_get_cmode = mv88e6352_port_get_cmode, 5401 .port_setup_message_port = mv88e6xxx_setup_message_port, 5402 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5403 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5404 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5405 .stats_get_strings = mv88e6095_stats_get_strings, 5406 .stats_get_stat = mv88e6095_stats_get_stat, 5407 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5408 .set_egress_port = mv88e6095_g1_set_egress_port, 5409 .watchdog_ops = &mv88e6097_watchdog_ops, 5410 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5411 .pot_clear = mv88e6xxx_g2_pot_clear, 5412 .reset = mv88e6352_g1_reset, 5413 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5414 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5415 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5416 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5417 .stu_getnext = mv88e6352_g1_stu_getnext, 5418 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5419 .avb_ops = &mv88e6352_avb_ops, 5420 .ptp_ops = &mv88e6352_ptp_ops, 5421 .phylink_get_caps = mv88e6351_phylink_get_caps, 5422 }; 5423 5424 static const struct mv88e6xxx_ops mv88e6352_ops = { 5425 /* MV88E6XXX_FAMILY_6352 */ 5426 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5427 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5428 .irl_init_all = mv88e6352_g2_irl_init_all, 5429 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5430 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5431 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5432 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5433 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5434 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5435 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5436 .port_set_link = mv88e6xxx_port_set_link, 5437 .port_sync_link = mv88e6xxx_port_sync_link, 5438 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5439 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 5440 .port_tag_remap = mv88e6095_port_tag_remap, 5441 .port_set_policy = mv88e6352_port_set_policy, 5442 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5443 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5444 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5445 .port_set_ether_type = mv88e6351_port_set_ether_type, 5446 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5447 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5448 .port_pause_limit = mv88e6097_port_pause_limit, 5449 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5450 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5451 .port_get_cmode = mv88e6352_port_get_cmode, 5452 .port_setup_leds = mv88e6xxx_port_setup_leds, 5453 .port_setup_message_port = mv88e6xxx_setup_message_port, 5454 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5455 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5456 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5457 .stats_get_strings = mv88e6095_stats_get_strings, 5458 .stats_get_stat = mv88e6095_stats_get_stat, 5459 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5460 .set_egress_port = mv88e6095_g1_set_egress_port, 5461 .watchdog_ops = &mv88e6097_watchdog_ops, 5462 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5463 .pot_clear = mv88e6xxx_g2_pot_clear, 5464 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5465 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5466 .reset = mv88e6352_g1_reset, 5467 .rmu_disable = mv88e6352_g1_rmu_disable, 5468 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5469 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5470 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5471 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5472 .stu_getnext = mv88e6352_g1_stu_getnext, 5473 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5474 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5475 .gpio_ops = &mv88e6352_gpio_ops, 5476 .avb_ops = &mv88e6352_avb_ops, 5477 .ptp_ops = &mv88e6352_ptp_ops, 5478 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 5479 .serdes_get_strings = mv88e6352_serdes_get_strings, 5480 .serdes_get_stats = mv88e6352_serdes_get_stats, 5481 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5482 .serdes_get_regs = mv88e6352_serdes_get_regs, 5483 .phylink_get_caps = mv88e6352_phylink_get_caps, 5484 .pcs_ops = &mv88e6352_pcs_ops, 5485 }; 5486 5487 static const struct mv88e6xxx_ops mv88e6390_ops = { 5488 /* MV88E6XXX_FAMILY_6390 */ 5489 .setup_errata = mv88e6390_setup_errata, 5490 .irl_init_all = mv88e6390_g2_irl_init_all, 5491 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5492 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5493 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5494 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5495 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5496 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5497 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5498 .port_set_link = mv88e6xxx_port_set_link, 5499 .port_sync_link = mv88e6xxx_port_sync_link, 5500 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5501 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5502 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5503 .port_tag_remap = mv88e6390_port_tag_remap, 5504 .port_set_policy = mv88e6352_port_set_policy, 5505 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5506 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5507 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5508 .port_set_ether_type = mv88e6351_port_set_ether_type, 5509 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5510 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5511 .port_pause_limit = mv88e6390_port_pause_limit, 5512 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5513 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5514 .port_get_cmode = mv88e6352_port_get_cmode, 5515 .port_set_cmode = mv88e6390_port_set_cmode, 5516 .port_setup_message_port = mv88e6xxx_setup_message_port, 5517 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5518 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5519 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5520 .stats_get_strings = mv88e6320_stats_get_strings, 5521 .stats_get_stat = mv88e6390_stats_get_stat, 5522 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5523 .set_egress_port = mv88e6390_g1_set_egress_port, 5524 .watchdog_ops = &mv88e6390_watchdog_ops, 5525 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5526 .pot_clear = mv88e6xxx_g2_pot_clear, 5527 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5528 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5529 .reset = mv88e6352_g1_reset, 5530 .rmu_disable = mv88e6390_g1_rmu_disable, 5531 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5532 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5533 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5534 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5535 .stu_getnext = mv88e6390_g1_stu_getnext, 5536 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5537 .serdes_get_lane = mv88e6390_serdes_get_lane, 5538 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5539 .gpio_ops = &mv88e6352_gpio_ops, 5540 .avb_ops = &mv88e6390_avb_ops, 5541 .ptp_ops = &mv88e6390_ptp_ops, 5542 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5543 .serdes_get_strings = mv88e6390_serdes_get_strings, 5544 .serdes_get_stats = mv88e6390_serdes_get_stats, 5545 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5546 .serdes_get_regs = mv88e6390_serdes_get_regs, 5547 .phylink_get_caps = mv88e6390_phylink_get_caps, 5548 .pcs_ops = &mv88e6390_pcs_ops, 5549 .tcam_ops = &mv88e6390_tcam_ops, 5550 }; 5551 5552 static const struct mv88e6xxx_ops mv88e6390x_ops = { 5553 /* MV88E6XXX_FAMILY_6390 */ 5554 .setup_errata = mv88e6390_setup_errata, 5555 .irl_init_all = mv88e6390_g2_irl_init_all, 5556 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5557 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5558 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5559 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5560 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5561 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5562 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5563 .port_set_link = mv88e6xxx_port_set_link, 5564 .port_sync_link = mv88e6xxx_port_sync_link, 5565 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5566 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 5567 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 5568 .port_tag_remap = mv88e6390_port_tag_remap, 5569 .port_set_policy = mv88e6352_port_set_policy, 5570 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5571 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5572 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5573 .port_set_ether_type = mv88e6351_port_set_ether_type, 5574 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5575 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5576 .port_pause_limit = mv88e6390_port_pause_limit, 5577 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5578 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5579 .port_get_cmode = mv88e6352_port_get_cmode, 5580 .port_set_cmode = mv88e6390x_port_set_cmode, 5581 .port_setup_message_port = mv88e6xxx_setup_message_port, 5582 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5583 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5584 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5585 .stats_get_strings = mv88e6320_stats_get_strings, 5586 .stats_get_stat = mv88e6390_stats_get_stat, 5587 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5588 .set_egress_port = mv88e6390_g1_set_egress_port, 5589 .watchdog_ops = &mv88e6390_watchdog_ops, 5590 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5591 .pot_clear = mv88e6xxx_g2_pot_clear, 5592 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5593 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5594 .reset = mv88e6352_g1_reset, 5595 .rmu_disable = mv88e6390_g1_rmu_disable, 5596 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5597 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5598 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5599 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5600 .stu_getnext = mv88e6390_g1_stu_getnext, 5601 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5602 .serdes_get_lane = mv88e6390x_serdes_get_lane, 5603 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5604 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5605 .serdes_get_strings = mv88e6390_serdes_get_strings, 5606 .serdes_get_stats = mv88e6390_serdes_get_stats, 5607 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5608 .serdes_get_regs = mv88e6390_serdes_get_regs, 5609 .gpio_ops = &mv88e6352_gpio_ops, 5610 .avb_ops = &mv88e6390_avb_ops, 5611 .ptp_ops = &mv88e6390_ptp_ops, 5612 .phylink_get_caps = mv88e6390x_phylink_get_caps, 5613 .pcs_ops = &mv88e6390_pcs_ops, 5614 }; 5615 5616 static const struct mv88e6xxx_ops mv88e6393x_ops = { 5617 /* MV88E6XXX_FAMILY_6393 */ 5618 .irl_init_all = mv88e6390_g2_irl_init_all, 5619 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5620 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5621 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5622 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5623 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5624 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5625 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5626 .port_set_link = mv88e6xxx_port_set_link, 5627 .port_sync_link = mv88e6xxx_port_sync_link, 5628 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5629 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 5630 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 5631 .port_tag_remap = mv88e6390_port_tag_remap, 5632 .port_set_policy = mv88e6393x_port_set_policy, 5633 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5634 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5635 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5636 .port_set_ether_type = mv88e6393x_port_set_ether_type, 5637 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5638 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5639 .port_pause_limit = mv88e6390_port_pause_limit, 5640 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5641 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5642 .port_get_cmode = mv88e6352_port_get_cmode, 5643 .port_set_cmode = mv88e6393x_port_set_cmode, 5644 .port_setup_message_port = mv88e6xxx_setup_message_port, 5645 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 5646 .port_enable_tcam = mv88e6xxx_port_enable_tcam, 5647 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5648 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5649 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5650 .stats_get_strings = mv88e6320_stats_get_strings, 5651 .stats_get_stat = mv88e6390_stats_get_stat, 5652 /* .set_cpu_port is missing because this family does not support a global 5653 * CPU port, only per port CPU port which is set via 5654 * .port_set_upstream_port method. 5655 */ 5656 .set_egress_port = mv88e6393x_set_egress_port, 5657 .watchdog_ops = &mv88e6393x_watchdog_ops, 5658 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 5659 .pot_clear = mv88e6xxx_g2_pot_clear, 5660 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5661 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5662 .reset = mv88e6352_g1_reset, 5663 .rmu_disable = mv88e6390_g1_rmu_disable, 5664 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5665 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5666 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5667 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5668 .stu_getnext = mv88e6390_g1_stu_getnext, 5669 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5670 .serdes_get_lane = mv88e6393x_serdes_get_lane, 5671 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5672 /* TODO: serdes stats */ 5673 .gpio_ops = &mv88e6352_gpio_ops, 5674 .avb_ops = &mv88e6390_avb_ops, 5675 .ptp_ops = &mv88e6352_ptp_ops, 5676 .phylink_get_caps = mv88e6393x_phylink_get_caps, 5677 .pcs_ops = &mv88e6393x_pcs_ops, 5678 .tcam_ops = &mv88e6393_tcam_ops, 5679 }; 5680 5681 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 5682 [MV88E6020] = { 5683 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020, 5684 .family = MV88E6XXX_FAMILY_6250, 5685 .name = "Marvell 88E6020", 5686 .num_databases = 64, 5687 /* Ports 2-4 are not routed to pins 5688 * => usable ports 0, 1, 5, 6 5689 */ 5690 .num_ports = 7, 5691 .num_internal_phys = 2, 5692 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5693 .max_vid = 4095, 5694 .port_base_addr = 0x8, 5695 .phy_base_addr = 0x0, 5696 .global1_addr = 0xf, 5697 .global2_addr = 0x7, 5698 .age_time_coeff = 15000, 5699 .g1_irqs = 9, 5700 .g2_irqs = 5, 5701 .stats_type = STATS_TYPE_BANK0, 5702 .atu_move_port_mask = 0xf, 5703 .dual_chip = true, 5704 .ops = &mv88e6250_ops, 5705 }, 5706 5707 [MV88E6071] = { 5708 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071, 5709 .family = MV88E6XXX_FAMILY_6250, 5710 .name = "Marvell 88E6071", 5711 .num_databases = 64, 5712 .num_ports = 7, 5713 .num_internal_phys = 5, 5714 .max_vid = 4095, 5715 .port_base_addr = 0x08, 5716 .phy_base_addr = 0x00, 5717 .global1_addr = 0x0f, 5718 .global2_addr = 0x07, 5719 .age_time_coeff = 15000, 5720 .g1_irqs = 9, 5721 .g2_irqs = 5, 5722 .stats_type = STATS_TYPE_BANK0, 5723 .atu_move_port_mask = 0xf, 5724 .dual_chip = true, 5725 .ops = &mv88e6250_ops, 5726 }, 5727 5728 [MV88E6085] = { 5729 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 5730 .family = MV88E6XXX_FAMILY_6097, 5731 .name = "Marvell 88E6085", 5732 .num_databases = 4096, 5733 .num_macs = 8192, 5734 .num_ports = 10, 5735 .num_internal_phys = 5, 5736 .max_vid = 4095, 5737 .max_sid = 63, 5738 .port_base_addr = 0x10, 5739 .phy_base_addr = 0x0, 5740 .global1_addr = 0x1b, 5741 .global2_addr = 0x1c, 5742 .age_time_coeff = 15000, 5743 .g1_irqs = 8, 5744 .g2_irqs = 10, 5745 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5746 .atu_move_port_mask = 0xf, 5747 .pvt = true, 5748 .multi_chip = true, 5749 .ops = &mv88e6085_ops, 5750 }, 5751 5752 [MV88E6095] = { 5753 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 5754 .family = MV88E6XXX_FAMILY_6095, 5755 .name = "Marvell 88E6095/88E6095F", 5756 .num_databases = 256, 5757 .num_macs = 8192, 5758 .num_ports = 11, 5759 .num_internal_phys = 0, 5760 .max_vid = 4095, 5761 .port_base_addr = 0x10, 5762 .phy_base_addr = 0x0, 5763 .global1_addr = 0x1b, 5764 .global2_addr = 0x1c, 5765 .age_time_coeff = 15000, 5766 .g1_irqs = 8, 5767 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5768 .atu_move_port_mask = 0xf, 5769 .multi_chip = true, 5770 .ops = &mv88e6095_ops, 5771 }, 5772 5773 [MV88E6097] = { 5774 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5775 .family = MV88E6XXX_FAMILY_6097, 5776 .name = "Marvell 88E6097/88E6097F", 5777 .num_databases = 4096, 5778 .num_macs = 8192, 5779 .num_ports = 11, 5780 .num_internal_phys = 8, 5781 .max_vid = 4095, 5782 .max_sid = 63, 5783 .port_base_addr = 0x10, 5784 .phy_base_addr = 0x0, 5785 .global1_addr = 0x1b, 5786 .global2_addr = 0x1c, 5787 .age_time_coeff = 15000, 5788 .g1_irqs = 8, 5789 .g2_irqs = 10, 5790 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5791 .atu_move_port_mask = 0xf, 5792 .pvt = true, 5793 .multi_chip = true, 5794 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5795 .ops = &mv88e6097_ops, 5796 }, 5797 5798 [MV88E6123] = { 5799 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5800 .family = MV88E6XXX_FAMILY_6165, 5801 .name = "Marvell 88E6123", 5802 .num_databases = 4096, 5803 .num_macs = 1024, 5804 .num_ports = 3, 5805 .num_internal_phys = 5, 5806 .max_vid = 4095, 5807 .max_sid = 63, 5808 .port_base_addr = 0x10, 5809 .phy_base_addr = 0x0, 5810 .global1_addr = 0x1b, 5811 .global2_addr = 0x1c, 5812 .age_time_coeff = 15000, 5813 .g1_irqs = 9, 5814 .g2_irqs = 10, 5815 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5816 .atu_move_port_mask = 0xf, 5817 .pvt = true, 5818 .multi_chip = true, 5819 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5820 .ops = &mv88e6123_ops, 5821 }, 5822 5823 [MV88E6131] = { 5824 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5825 .family = MV88E6XXX_FAMILY_6185, 5826 .name = "Marvell 88E6131", 5827 .num_databases = 256, 5828 .num_macs = 8192, 5829 .num_ports = 8, 5830 .num_internal_phys = 0, 5831 .max_vid = 4095, 5832 .port_base_addr = 0x10, 5833 .phy_base_addr = 0x0, 5834 .global1_addr = 0x1b, 5835 .global2_addr = 0x1c, 5836 .age_time_coeff = 15000, 5837 .g1_irqs = 9, 5838 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5839 .atu_move_port_mask = 0xf, 5840 .multi_chip = true, 5841 .ops = &mv88e6131_ops, 5842 }, 5843 5844 [MV88E6141] = { 5845 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5846 .family = MV88E6XXX_FAMILY_6341, 5847 .name = "Marvell 88E6141", 5848 .num_databases = 256, 5849 .num_macs = 2048, 5850 .num_ports = 6, 5851 .num_internal_phys = 5, 5852 .num_gpio = 11, 5853 .max_vid = 4095, 5854 .max_sid = 63, 5855 .port_base_addr = 0x10, 5856 .phy_base_addr = 0x10, 5857 .global1_addr = 0x1b, 5858 .global2_addr = 0x1c, 5859 .age_time_coeff = 3750, 5860 .atu_move_port_mask = 0xf, 5861 .g1_irqs = 9, 5862 .g2_irqs = 10, 5863 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 5864 .pvt = true, 5865 .multi_chip = true, 5866 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5867 .ops = &mv88e6141_ops, 5868 }, 5869 5870 [MV88E6161] = { 5871 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5872 .family = MV88E6XXX_FAMILY_6165, 5873 .name = "Marvell 88E6161", 5874 .num_databases = 4096, 5875 .num_macs = 1024, 5876 .num_ports = 6, 5877 .num_internal_phys = 5, 5878 .max_vid = 4095, 5879 .max_sid = 63, 5880 .port_base_addr = 0x10, 5881 .phy_base_addr = 0x0, 5882 .global1_addr = 0x1b, 5883 .global2_addr = 0x1c, 5884 .age_time_coeff = 15000, 5885 .g1_irqs = 9, 5886 .g2_irqs = 10, 5887 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5888 .atu_move_port_mask = 0xf, 5889 .pvt = true, 5890 .multi_chip = true, 5891 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5892 .ptp_support = true, 5893 .ops = &mv88e6161_ops, 5894 }, 5895 5896 [MV88E6165] = { 5897 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5898 .family = MV88E6XXX_FAMILY_6165, 5899 .name = "Marvell 88E6165", 5900 .num_databases = 4096, 5901 .num_macs = 8192, 5902 .num_ports = 6, 5903 .num_internal_phys = 0, 5904 .max_vid = 4095, 5905 .max_sid = 63, 5906 .port_base_addr = 0x10, 5907 .phy_base_addr = 0x0, 5908 .global1_addr = 0x1b, 5909 .global2_addr = 0x1c, 5910 .age_time_coeff = 15000, 5911 .g1_irqs = 9, 5912 .g2_irqs = 10, 5913 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5914 .atu_move_port_mask = 0xf, 5915 .pvt = true, 5916 .multi_chip = true, 5917 .ptp_support = true, 5918 .ops = &mv88e6165_ops, 5919 }, 5920 5921 [MV88E6171] = { 5922 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5923 .family = MV88E6XXX_FAMILY_6351, 5924 .name = "Marvell 88E6171", 5925 .num_databases = 4096, 5926 .num_macs = 8192, 5927 .num_ports = 7, 5928 .num_internal_phys = 5, 5929 .max_vid = 4095, 5930 .max_sid = 63, 5931 .port_base_addr = 0x10, 5932 .phy_base_addr = 0x0, 5933 .global1_addr = 0x1b, 5934 .global2_addr = 0x1c, 5935 .age_time_coeff = 15000, 5936 .g1_irqs = 9, 5937 .g2_irqs = 10, 5938 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 5939 .atu_move_port_mask = 0xf, 5940 .pvt = true, 5941 .multi_chip = true, 5942 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5943 .ops = &mv88e6171_ops, 5944 }, 5945 5946 [MV88E6172] = { 5947 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5948 .family = MV88E6XXX_FAMILY_6352, 5949 .name = "Marvell 88E6172", 5950 .num_databases = 4096, 5951 .num_macs = 8192, 5952 .num_ports = 7, 5953 .num_internal_phys = 5, 5954 .num_gpio = 15, 5955 .max_vid = 4095, 5956 .max_sid = 63, 5957 .port_base_addr = 0x10, 5958 .phy_base_addr = 0x0, 5959 .global1_addr = 0x1b, 5960 .global2_addr = 0x1c, 5961 .age_time_coeff = 15000, 5962 .g1_irqs = 9, 5963 .g2_irqs = 10, 5964 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5965 .atu_move_port_mask = 0xf, 5966 .pvt = true, 5967 .multi_chip = true, 5968 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5969 .ops = &mv88e6172_ops, 5970 }, 5971 5972 [MV88E6175] = { 5973 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5974 .family = MV88E6XXX_FAMILY_6351, 5975 .name = "Marvell 88E6175", 5976 .num_databases = 4096, 5977 .num_macs = 8192, 5978 .num_ports = 7, 5979 .num_internal_phys = 5, 5980 .max_vid = 4095, 5981 .max_sid = 63, 5982 .port_base_addr = 0x10, 5983 .phy_base_addr = 0x0, 5984 .global1_addr = 0x1b, 5985 .global2_addr = 0x1c, 5986 .age_time_coeff = 15000, 5987 .g1_irqs = 9, 5988 .g2_irqs = 10, 5989 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5990 .atu_move_port_mask = 0xf, 5991 .pvt = true, 5992 .multi_chip = true, 5993 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5994 .ops = &mv88e6175_ops, 5995 }, 5996 5997 [MV88E6176] = { 5998 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5999 .family = MV88E6XXX_FAMILY_6352, 6000 .name = "Marvell 88E6176", 6001 .num_databases = 4096, 6002 .num_macs = 8192, 6003 .num_ports = 7, 6004 .num_internal_phys = 5, 6005 .num_gpio = 15, 6006 .max_vid = 4095, 6007 .max_sid = 63, 6008 .port_base_addr = 0x10, 6009 .phy_base_addr = 0x0, 6010 .global1_addr = 0x1b, 6011 .global2_addr = 0x1c, 6012 .age_time_coeff = 15000, 6013 .g1_irqs = 9, 6014 .g2_irqs = 10, 6015 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6016 .atu_move_port_mask = 0xf, 6017 .pvt = true, 6018 .multi_chip = true, 6019 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6020 .ops = &mv88e6176_ops, 6021 }, 6022 6023 [MV88E6185] = { 6024 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 6025 .family = MV88E6XXX_FAMILY_6185, 6026 .name = "Marvell 88E6185", 6027 .num_databases = 256, 6028 .num_macs = 8192, 6029 .num_ports = 10, 6030 .num_internal_phys = 0, 6031 .max_vid = 4095, 6032 .port_base_addr = 0x10, 6033 .phy_base_addr = 0x0, 6034 .global1_addr = 0x1b, 6035 .global2_addr = 0x1c, 6036 .age_time_coeff = 15000, 6037 .g1_irqs = 8, 6038 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6039 .atu_move_port_mask = 0xf, 6040 .multi_chip = true, 6041 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6042 .ops = &mv88e6185_ops, 6043 }, 6044 6045 [MV88E6190] = { 6046 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 6047 .family = MV88E6XXX_FAMILY_6390, 6048 .name = "Marvell 88E6190", 6049 .num_databases = 4096, 6050 .num_macs = 16384, 6051 .num_ports = 11, /* 10 + Z80 */ 6052 .num_internal_phys = 9, 6053 .num_gpio = 16, 6054 .max_vid = 8191, 6055 .max_sid = 63, 6056 .port_base_addr = 0x0, 6057 .phy_base_addr = 0x0, 6058 .global1_addr = 0x1b, 6059 .global2_addr = 0x1c, 6060 .age_time_coeff = 3750, 6061 .g1_irqs = 9, 6062 .g2_irqs = 14, 6063 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6064 .pvt = true, 6065 .multi_chip = true, 6066 .atu_move_port_mask = 0x1f, 6067 .ops = &mv88e6190_ops, 6068 }, 6069 6070 [MV88E6190X] = { 6071 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 6072 .family = MV88E6XXX_FAMILY_6390, 6073 .name = "Marvell 88E6190X", 6074 .num_databases = 4096, 6075 .num_macs = 16384, 6076 .num_ports = 11, /* 10 + Z80 */ 6077 .num_internal_phys = 9, 6078 .num_gpio = 16, 6079 .max_vid = 8191, 6080 .max_sid = 63, 6081 .port_base_addr = 0x0, 6082 .phy_base_addr = 0x0, 6083 .global1_addr = 0x1b, 6084 .global2_addr = 0x1c, 6085 .age_time_coeff = 3750, 6086 .g1_irqs = 9, 6087 .g2_irqs = 14, 6088 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6089 .atu_move_port_mask = 0x1f, 6090 .pvt = true, 6091 .multi_chip = true, 6092 .ops = &mv88e6190x_ops, 6093 }, 6094 6095 [MV88E6191] = { 6096 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 6097 .family = MV88E6XXX_FAMILY_6390, 6098 .name = "Marvell 88E6191", 6099 .num_databases = 4096, 6100 .num_macs = 16384, 6101 .num_ports = 11, /* 10 + Z80 */ 6102 .num_internal_phys = 9, 6103 .max_vid = 8191, 6104 .max_sid = 63, 6105 .port_base_addr = 0x0, 6106 .phy_base_addr = 0x0, 6107 .global1_addr = 0x1b, 6108 .global2_addr = 0x1c, 6109 .age_time_coeff = 3750, 6110 .g1_irqs = 9, 6111 .g2_irqs = 14, 6112 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6113 .atu_move_port_mask = 0x1f, 6114 .pvt = true, 6115 .multi_chip = true, 6116 .ptp_support = true, 6117 .ops = &mv88e6191_ops, 6118 }, 6119 6120 [MV88E6191X] = { 6121 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 6122 .family = MV88E6XXX_FAMILY_6393, 6123 .name = "Marvell 88E6191X", 6124 .num_databases = 4096, 6125 .num_ports = 11, /* 10 + Z80 */ 6126 .num_internal_phys = 8, 6127 .internal_phys_offset = 1, 6128 .max_vid = 8191, 6129 .max_sid = 63, 6130 .port_base_addr = 0x0, 6131 .phy_base_addr = 0x0, 6132 .global1_addr = 0x1b, 6133 .global2_addr = 0x1c, 6134 .age_time_coeff = 3750, 6135 .g1_irqs = 10, 6136 .g2_irqs = 14, 6137 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6138 .atu_move_port_mask = 0x1f, 6139 .pvt = true, 6140 .multi_chip = true, 6141 .ptp_support = true, 6142 .ops = &mv88e6393x_ops, 6143 }, 6144 6145 [MV88E6193X] = { 6146 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 6147 .family = MV88E6XXX_FAMILY_6393, 6148 .name = "Marvell 88E6193X", 6149 .num_databases = 4096, 6150 .num_ports = 11, /* 10 + Z80 */ 6151 .num_internal_phys = 8, 6152 .num_tcam_entries = 256, 6153 .internal_phys_offset = 1, 6154 .max_vid = 8191, 6155 .max_sid = 63, 6156 .port_base_addr = 0x0, 6157 .phy_base_addr = 0x0, 6158 .global1_addr = 0x1b, 6159 .global2_addr = 0x1c, 6160 .tcam_addr = 0x1f, 6161 .age_time_coeff = 3750, 6162 .g1_irqs = 10, 6163 .g2_irqs = 14, 6164 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6165 .atu_move_port_mask = 0x1f, 6166 .pvt = true, 6167 .multi_chip = true, 6168 .ptp_support = true, 6169 .ops = &mv88e6393x_ops, 6170 }, 6171 6172 [MV88E6220] = { 6173 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 6174 .family = MV88E6XXX_FAMILY_6250, 6175 .name = "Marvell 88E6220", 6176 .num_databases = 64, 6177 6178 /* Ports 2-4 are not routed to pins 6179 * => usable ports 0, 1, 5, 6 6180 */ 6181 .num_ports = 7, 6182 .num_internal_phys = 2, 6183 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 6184 .max_vid = 4095, 6185 .port_base_addr = 0x08, 6186 .phy_base_addr = 0x00, 6187 .global1_addr = 0x0f, 6188 .global2_addr = 0x07, 6189 .age_time_coeff = 15000, 6190 .g1_irqs = 9, 6191 .g2_irqs = 10, 6192 .stats_type = STATS_TYPE_BANK0, 6193 .atu_move_port_mask = 0xf, 6194 .dual_chip = true, 6195 .ptp_support = true, 6196 .ops = &mv88e6250_ops, 6197 }, 6198 6199 [MV88E6240] = { 6200 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 6201 .family = MV88E6XXX_FAMILY_6352, 6202 .name = "Marvell 88E6240", 6203 .num_databases = 4096, 6204 .num_macs = 8192, 6205 .num_ports = 7, 6206 .num_internal_phys = 5, 6207 .num_gpio = 15, 6208 .max_vid = 4095, 6209 .max_sid = 63, 6210 .port_base_addr = 0x10, 6211 .phy_base_addr = 0x0, 6212 .global1_addr = 0x1b, 6213 .global2_addr = 0x1c, 6214 .age_time_coeff = 15000, 6215 .g1_irqs = 9, 6216 .g2_irqs = 10, 6217 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6218 .atu_move_port_mask = 0xf, 6219 .pvt = true, 6220 .multi_chip = true, 6221 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6222 .ptp_support = true, 6223 .ops = &mv88e6240_ops, 6224 }, 6225 6226 [MV88E6250] = { 6227 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 6228 .family = MV88E6XXX_FAMILY_6250, 6229 .name = "Marvell 88E6250", 6230 .num_databases = 64, 6231 .num_ports = 7, 6232 .num_internal_phys = 5, 6233 .max_vid = 4095, 6234 .port_base_addr = 0x08, 6235 .phy_base_addr = 0x00, 6236 .global1_addr = 0x0f, 6237 .global2_addr = 0x07, 6238 .age_time_coeff = 15000, 6239 .g1_irqs = 9, 6240 .g2_irqs = 10, 6241 .stats_type = STATS_TYPE_BANK0, 6242 .atu_move_port_mask = 0xf, 6243 .dual_chip = true, 6244 .ptp_support = true, 6245 .ops = &mv88e6250_ops, 6246 }, 6247 6248 [MV88E6290] = { 6249 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 6250 .family = MV88E6XXX_FAMILY_6390, 6251 .name = "Marvell 88E6290", 6252 .num_databases = 4096, 6253 .num_ports = 11, /* 10 + Z80 */ 6254 .num_internal_phys = 9, 6255 .num_gpio = 16, 6256 .num_tcam_entries = 256, 6257 .max_vid = 8191, 6258 .max_sid = 63, 6259 .port_base_addr = 0x0, 6260 .phy_base_addr = 0x0, 6261 .global1_addr = 0x1b, 6262 .global2_addr = 0x1c, 6263 .tcam_addr = 0x1f, 6264 .age_time_coeff = 3750, 6265 .g1_irqs = 9, 6266 .g2_irqs = 14, 6267 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6268 .atu_move_port_mask = 0x1f, 6269 .pvt = true, 6270 .multi_chip = true, 6271 .ptp_support = true, 6272 .ops = &mv88e6290_ops, 6273 }, 6274 6275 [MV88E6320] = { 6276 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 6277 .family = MV88E6XXX_FAMILY_6320, 6278 .name = "Marvell 88E6320", 6279 .num_databases = 4096, 6280 .num_macs = 8192, 6281 .num_ports = 7, 6282 .num_internal_phys = 2, 6283 .internal_phys_offset = 3, 6284 .num_gpio = 15, 6285 .max_vid = 4095, 6286 .max_sid = 63, 6287 .port_base_addr = 0x10, 6288 .phy_base_addr = 0x0, 6289 .global1_addr = 0x1b, 6290 .global2_addr = 0x1c, 6291 .age_time_coeff = 15000, 6292 .g1_irqs = 8, 6293 .g2_irqs = 10, 6294 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6295 .atu_move_port_mask = 0xf, 6296 .pvt = true, 6297 .multi_chip = true, 6298 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6299 .ptp_support = true, 6300 .ops = &mv88e6320_ops, 6301 }, 6302 6303 [MV88E6321] = { 6304 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 6305 .family = MV88E6XXX_FAMILY_6320, 6306 .name = "Marvell 88E6321", 6307 .num_databases = 4096, 6308 .num_macs = 8192, 6309 .num_ports = 7, 6310 .num_internal_phys = 2, 6311 .internal_phys_offset = 3, 6312 .num_gpio = 15, 6313 .max_vid = 4095, 6314 .max_sid = 63, 6315 .port_base_addr = 0x10, 6316 .phy_base_addr = 0x0, 6317 .global1_addr = 0x1b, 6318 .global2_addr = 0x1c, 6319 .age_time_coeff = 15000, 6320 .g1_irqs = 8, 6321 .g2_irqs = 10, 6322 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6323 .atu_move_port_mask = 0xf, 6324 .pvt = true, 6325 .multi_chip = true, 6326 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6327 .ptp_support = true, 6328 .ops = &mv88e6321_ops, 6329 }, 6330 6331 [MV88E6341] = { 6332 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 6333 .family = MV88E6XXX_FAMILY_6341, 6334 .name = "Marvell 88E6341", 6335 .num_databases = 256, 6336 .num_macs = 2048, 6337 .num_internal_phys = 5, 6338 .num_ports = 6, 6339 .num_gpio = 11, 6340 .max_vid = 4095, 6341 .max_sid = 63, 6342 .port_base_addr = 0x10, 6343 .phy_base_addr = 0x10, 6344 .global1_addr = 0x1b, 6345 .global2_addr = 0x1c, 6346 .age_time_coeff = 3750, 6347 .atu_move_port_mask = 0xf, 6348 .g1_irqs = 9, 6349 .g2_irqs = 10, 6350 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6351 .pvt = true, 6352 .multi_chip = true, 6353 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6354 .ptp_support = true, 6355 .ops = &mv88e6341_ops, 6356 }, 6357 6358 [MV88E6350] = { 6359 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 6360 .family = MV88E6XXX_FAMILY_6351, 6361 .name = "Marvell 88E6350", 6362 .num_databases = 4096, 6363 .num_macs = 8192, 6364 .num_ports = 7, 6365 .num_internal_phys = 5, 6366 .max_vid = 4095, 6367 .max_sid = 63, 6368 .port_base_addr = 0x10, 6369 .phy_base_addr = 0x0, 6370 .global1_addr = 0x1b, 6371 .global2_addr = 0x1c, 6372 .age_time_coeff = 15000, 6373 .g1_irqs = 9, 6374 .g2_irqs = 10, 6375 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6376 .atu_move_port_mask = 0xf, 6377 .pvt = true, 6378 .multi_chip = true, 6379 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6380 .ops = &mv88e6350_ops, 6381 }, 6382 6383 [MV88E6351] = { 6384 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 6385 .family = MV88E6XXX_FAMILY_6351, 6386 .name = "Marvell 88E6351", 6387 .num_databases = 4096, 6388 .num_macs = 8192, 6389 .num_ports = 7, 6390 .num_internal_phys = 5, 6391 .max_vid = 4095, 6392 .max_sid = 63, 6393 .port_base_addr = 0x10, 6394 .phy_base_addr = 0x0, 6395 .global1_addr = 0x1b, 6396 .global2_addr = 0x1c, 6397 .age_time_coeff = 15000, 6398 .g1_irqs = 9, 6399 .g2_irqs = 10, 6400 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6401 .atu_move_port_mask = 0xf, 6402 .pvt = true, 6403 .multi_chip = true, 6404 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6405 .ops = &mv88e6351_ops, 6406 }, 6407 6408 [MV88E6352] = { 6409 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 6410 .family = MV88E6XXX_FAMILY_6352, 6411 .name = "Marvell 88E6352", 6412 .num_databases = 4096, 6413 .num_macs = 8192, 6414 .num_ports = 7, 6415 .num_internal_phys = 5, 6416 .num_gpio = 15, 6417 .max_vid = 4095, 6418 .max_sid = 63, 6419 .port_base_addr = 0x10, 6420 .phy_base_addr = 0x0, 6421 .global1_addr = 0x1b, 6422 .global2_addr = 0x1c, 6423 .age_time_coeff = 15000, 6424 .g1_irqs = 9, 6425 .g2_irqs = 10, 6426 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6427 .atu_move_port_mask = 0xf, 6428 .pvt = true, 6429 .multi_chip = true, 6430 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6431 .ptp_support = true, 6432 .ops = &mv88e6352_ops, 6433 }, 6434 [MV88E6361] = { 6435 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361, 6436 .family = MV88E6XXX_FAMILY_6393, 6437 .name = "Marvell 88E6361", 6438 .num_databases = 4096, 6439 .num_macs = 16384, 6440 .num_ports = 11, 6441 /* Ports 1, 2 and 8 are not routed */ 6442 .invalid_port_mask = BIT(1) | BIT(2) | BIT(8), 6443 .num_internal_phys = 5, 6444 .internal_phys_offset = 3, 6445 .max_vid = 8191, 6446 .max_sid = 63, 6447 .port_base_addr = 0x0, 6448 .phy_base_addr = 0x0, 6449 .global1_addr = 0x1b, 6450 .global2_addr = 0x1c, 6451 .age_time_coeff = 3750, 6452 .g1_irqs = 10, 6453 .g2_irqs = 14, 6454 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6455 .atu_move_port_mask = 0x1f, 6456 .pvt = true, 6457 .multi_chip = true, 6458 .ptp_support = true, 6459 .ops = &mv88e6393x_ops, 6460 }, 6461 [MV88E6390] = { 6462 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 6463 .family = MV88E6XXX_FAMILY_6390, 6464 .name = "Marvell 88E6390", 6465 .num_databases = 4096, 6466 .num_macs = 16384, 6467 .num_ports = 11, /* 10 + Z80 */ 6468 .num_internal_phys = 9, 6469 .num_gpio = 16, 6470 .num_tcam_entries = 256, 6471 .max_vid = 8191, 6472 .max_sid = 63, 6473 .port_base_addr = 0x0, 6474 .phy_base_addr = 0x0, 6475 .global1_addr = 0x1b, 6476 .global2_addr = 0x1c, 6477 .tcam_addr = 0x1f, 6478 .age_time_coeff = 3750, 6479 .g1_irqs = 9, 6480 .g2_irqs = 14, 6481 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6482 .atu_move_port_mask = 0x1f, 6483 .pvt = true, 6484 .multi_chip = true, 6485 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6486 .ptp_support = true, 6487 .ops = &mv88e6390_ops, 6488 }, 6489 [MV88E6390X] = { 6490 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 6491 .family = MV88E6XXX_FAMILY_6390, 6492 .name = "Marvell 88E6390X", 6493 .num_databases = 4096, 6494 .num_macs = 16384, 6495 .num_ports = 11, /* 10 + Z80 */ 6496 .num_internal_phys = 9, 6497 .num_gpio = 16, 6498 .max_vid = 8191, 6499 .max_sid = 63, 6500 .port_base_addr = 0x0, 6501 .phy_base_addr = 0x0, 6502 .global1_addr = 0x1b, 6503 .global2_addr = 0x1c, 6504 .age_time_coeff = 3750, 6505 .g1_irqs = 9, 6506 .g2_irqs = 14, 6507 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6508 .atu_move_port_mask = 0x1f, 6509 .pvt = true, 6510 .multi_chip = true, 6511 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6512 .ptp_support = true, 6513 .ops = &mv88e6390x_ops, 6514 }, 6515 6516 [MV88E6393X] = { 6517 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 6518 .family = MV88E6XXX_FAMILY_6393, 6519 .name = "Marvell 88E6393X", 6520 .num_databases = 4096, 6521 .num_ports = 11, /* 10 + Z80 */ 6522 .num_internal_phys = 8, 6523 .num_tcam_entries = 256, 6524 .internal_phys_offset = 1, 6525 .max_vid = 8191, 6526 .max_sid = 63, 6527 .port_base_addr = 0x0, 6528 .phy_base_addr = 0x0, 6529 .global1_addr = 0x1b, 6530 .global2_addr = 0x1c, 6531 .tcam_addr = 0x1f, 6532 .age_time_coeff = 3750, 6533 .g1_irqs = 10, 6534 .g2_irqs = 14, 6535 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6536 .atu_move_port_mask = 0x1f, 6537 .pvt = true, 6538 .multi_chip = true, 6539 .ptp_support = true, 6540 .ops = &mv88e6393x_ops, 6541 }, 6542 }; 6543 6544 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 6545 { 6546 int i; 6547 6548 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 6549 if (mv88e6xxx_table[i].prod_num == prod_num) 6550 return &mv88e6xxx_table[i]; 6551 6552 return NULL; 6553 } 6554 6555 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 6556 { 6557 const struct mv88e6xxx_info *info; 6558 unsigned int prod_num, rev; 6559 u16 id; 6560 int err; 6561 6562 mv88e6xxx_reg_lock(chip); 6563 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 6564 mv88e6xxx_reg_unlock(chip); 6565 if (err) 6566 return err; 6567 6568 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 6569 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 6570 6571 info = mv88e6xxx_lookup_info(prod_num); 6572 if (!info) 6573 return -ENODEV; 6574 6575 /* Update the compatible info with the probed one */ 6576 chip->info = info; 6577 6578 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 6579 chip->info->prod_num, chip->info->name, rev); 6580 6581 return 0; 6582 } 6583 6584 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip, 6585 struct mdio_device *mdiodev) 6586 { 6587 int err; 6588 6589 /* dual_chip takes precedence over single/multi-chip modes */ 6590 if (chip->info->dual_chip) 6591 return -EINVAL; 6592 6593 /* If the mdio addr is 16 indicating the first port address of a switch 6594 * (e.g. mv88e6*41) in single chip addressing mode the device may be 6595 * configured in single chip addressing mode. Setup the smi access as 6596 * single chip addressing mode and attempt to detect the model of the 6597 * switch, if this fails the device is not configured in single chip 6598 * addressing mode. 6599 */ 6600 if (mdiodev->addr != 16) 6601 return -EINVAL; 6602 6603 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0); 6604 if (err) 6605 return err; 6606 6607 return mv88e6xxx_detect(chip); 6608 } 6609 6610 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 6611 { 6612 struct mv88e6xxx_chip *chip; 6613 6614 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 6615 if (!chip) 6616 return NULL; 6617 6618 chip->dev = dev; 6619 6620 mutex_init(&chip->reg_lock); 6621 INIT_LIST_HEAD(&chip->mdios); 6622 idr_init(&chip->policies); 6623 INIT_LIST_HEAD(&chip->msts); 6624 INIT_LIST_HEAD(&chip->tcam.entries); 6625 6626 return chip; 6627 } 6628 6629 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 6630 int port, 6631 enum dsa_tag_protocol m) 6632 { 6633 struct mv88e6xxx_chip *chip = ds->priv; 6634 6635 return chip->tag_protocol; 6636 } 6637 6638 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, 6639 enum dsa_tag_protocol proto) 6640 { 6641 struct mv88e6xxx_chip *chip = ds->priv; 6642 enum dsa_tag_protocol old_protocol; 6643 struct dsa_port *cpu_dp; 6644 int err; 6645 6646 switch (proto) { 6647 case DSA_TAG_PROTO_EDSA: 6648 switch (chip->info->edsa_support) { 6649 case MV88E6XXX_EDSA_UNSUPPORTED: 6650 return -EPROTONOSUPPORT; 6651 case MV88E6XXX_EDSA_UNDOCUMENTED: 6652 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 6653 fallthrough; 6654 case MV88E6XXX_EDSA_SUPPORTED: 6655 break; 6656 } 6657 break; 6658 case DSA_TAG_PROTO_DSA: 6659 break; 6660 default: 6661 return -EPROTONOSUPPORT; 6662 } 6663 6664 old_protocol = chip->tag_protocol; 6665 chip->tag_protocol = proto; 6666 6667 mv88e6xxx_reg_lock(chip); 6668 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 6669 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6670 if (err) { 6671 mv88e6xxx_reg_unlock(chip); 6672 goto unwind; 6673 } 6674 } 6675 mv88e6xxx_reg_unlock(chip); 6676 6677 return 0; 6678 6679 unwind: 6680 chip->tag_protocol = old_protocol; 6681 6682 mv88e6xxx_reg_lock(chip); 6683 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds) 6684 mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6685 mv88e6xxx_reg_unlock(chip); 6686 6687 return err; 6688 } 6689 6690 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 6691 const struct switchdev_obj_port_mdb *mdb, 6692 struct dsa_db db) 6693 { 6694 struct mv88e6xxx_chip *chip = ds->priv; 6695 int err; 6696 6697 mv88e6xxx_reg_lock(chip); 6698 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 6699 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 6700 if (err) 6701 goto out; 6702 6703 if (!mv88e6xxx_port_db_find(chip, mdb->addr, mdb->vid)) 6704 err = -ENOSPC; 6705 6706 out: 6707 mv88e6xxx_reg_unlock(chip); 6708 6709 return err; 6710 } 6711 6712 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 6713 const struct switchdev_obj_port_mdb *mdb, 6714 struct dsa_db db) 6715 { 6716 struct mv88e6xxx_chip *chip = ds->priv; 6717 int err; 6718 6719 mv88e6xxx_reg_lock(chip); 6720 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 6721 mv88e6xxx_reg_unlock(chip); 6722 6723 return err; 6724 } 6725 6726 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 6727 struct dsa_mall_mirror_tc_entry *mirror, 6728 bool ingress, 6729 struct netlink_ext_ack *extack) 6730 { 6731 enum mv88e6xxx_egress_direction direction = ingress ? 6732 MV88E6XXX_EGRESS_DIR_INGRESS : 6733 MV88E6XXX_EGRESS_DIR_EGRESS; 6734 struct mv88e6xxx_chip *chip = ds->priv; 6735 bool other_mirrors = false; 6736 int i; 6737 int err; 6738 6739 mutex_lock(&chip->reg_lock); 6740 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 6741 mirror->to_local_port) { 6742 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6743 other_mirrors |= ingress ? 6744 chip->ports[i].mirror_ingress : 6745 chip->ports[i].mirror_egress; 6746 6747 /* Can't change egress port when other mirror is active */ 6748 if (other_mirrors) { 6749 err = -EBUSY; 6750 goto out; 6751 } 6752 6753 err = mv88e6xxx_set_egress_port(chip, direction, 6754 mirror->to_local_port); 6755 if (err) 6756 goto out; 6757 } 6758 6759 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 6760 out: 6761 mutex_unlock(&chip->reg_lock); 6762 6763 return err; 6764 } 6765 6766 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 6767 struct dsa_mall_mirror_tc_entry *mirror) 6768 { 6769 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 6770 MV88E6XXX_EGRESS_DIR_INGRESS : 6771 MV88E6XXX_EGRESS_DIR_EGRESS; 6772 struct mv88e6xxx_chip *chip = ds->priv; 6773 bool other_mirrors = false; 6774 int i; 6775 6776 mutex_lock(&chip->reg_lock); 6777 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 6778 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 6779 6780 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6781 other_mirrors |= mirror->ingress ? 6782 chip->ports[i].mirror_ingress : 6783 chip->ports[i].mirror_egress; 6784 6785 /* Reset egress port when no other mirror is active */ 6786 if (!other_mirrors) { 6787 if (mv88e6xxx_set_egress_port(chip, direction, 6788 dsa_upstream_port(ds, port))) 6789 dev_err(ds->dev, "failed to set egress port\n"); 6790 } 6791 6792 mutex_unlock(&chip->reg_lock); 6793 } 6794 6795 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 6796 struct switchdev_brport_flags flags, 6797 struct netlink_ext_ack *extack) 6798 { 6799 struct mv88e6xxx_chip *chip = ds->priv; 6800 const struct mv88e6xxx_ops *ops; 6801 6802 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 6803 BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB)) 6804 return -EINVAL; 6805 6806 ops = chip->info->ops; 6807 6808 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 6809 return -EINVAL; 6810 6811 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 6812 return -EINVAL; 6813 6814 return 0; 6815 } 6816 6817 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 6818 struct switchdev_brport_flags flags, 6819 struct netlink_ext_ack *extack) 6820 { 6821 struct mv88e6xxx_chip *chip = ds->priv; 6822 int err = 0; 6823 6824 mv88e6xxx_reg_lock(chip); 6825 6826 if (flags.mask & BR_LEARNING) { 6827 bool learning = !!(flags.val & BR_LEARNING); 6828 u16 pav = learning ? (1 << port) : 0; 6829 6830 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 6831 if (err) 6832 goto out; 6833 } 6834 6835 if (flags.mask & BR_FLOOD) { 6836 bool unicast = !!(flags.val & BR_FLOOD); 6837 6838 err = chip->info->ops->port_set_ucast_flood(chip, port, 6839 unicast); 6840 if (err) 6841 goto out; 6842 } 6843 6844 if (flags.mask & BR_MCAST_FLOOD) { 6845 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 6846 6847 err = chip->info->ops->port_set_mcast_flood(chip, port, 6848 multicast); 6849 if (err) 6850 goto out; 6851 } 6852 6853 if (flags.mask & BR_BCAST_FLOOD) { 6854 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 6855 6856 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 6857 if (err) 6858 goto out; 6859 } 6860 6861 if (flags.mask & BR_PORT_MAB) { 6862 bool mab = !!(flags.val & BR_PORT_MAB); 6863 6864 mv88e6xxx_port_set_mab(chip, port, mab); 6865 } 6866 6867 if (flags.mask & BR_PORT_LOCKED) { 6868 bool locked = !!(flags.val & BR_PORT_LOCKED); 6869 6870 err = mv88e6xxx_port_set_lock(chip, port, locked); 6871 if (err) 6872 goto out; 6873 } 6874 out: 6875 mv88e6xxx_reg_unlock(chip); 6876 6877 return err; 6878 } 6879 6880 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 6881 struct dsa_lag lag, 6882 struct netdev_lag_upper_info *info, 6883 struct netlink_ext_ack *extack) 6884 { 6885 struct mv88e6xxx_chip *chip = ds->priv; 6886 struct dsa_port *dp; 6887 int members = 0; 6888 6889 if (!mv88e6xxx_has_lag(chip)) { 6890 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload"); 6891 return false; 6892 } 6893 6894 if (!lag.id) 6895 return false; 6896 6897 dsa_lag_foreach_port(dp, ds->dst, &lag) 6898 /* Includes the port joining the LAG */ 6899 members++; 6900 6901 if (members > 8) { 6902 NL_SET_ERR_MSG_MOD(extack, 6903 "Cannot offload more than 8 LAG ports"); 6904 return false; 6905 } 6906 6907 /* We could potentially relax this to include active 6908 * backup in the future. 6909 */ 6910 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 6911 NL_SET_ERR_MSG_MOD(extack, 6912 "Can only offload LAG using hash TX type"); 6913 return false; 6914 } 6915 6916 /* Ideally we would also validate that the hash type matches 6917 * the hardware. Alas, this is always set to unknown on team 6918 * interfaces. 6919 */ 6920 return true; 6921 } 6922 6923 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag) 6924 { 6925 struct mv88e6xxx_chip *chip = ds->priv; 6926 struct dsa_port *dp; 6927 u16 map = 0; 6928 int id; 6929 6930 /* DSA LAG IDs are one-based, hardware is zero-based */ 6931 id = lag.id - 1; 6932 6933 /* Build the map of all ports to distribute flows destined for 6934 * this LAG. This can be either a local user port, or a DSA 6935 * port if the LAG port is on a remote chip. 6936 */ 6937 dsa_lag_foreach_port(dp, ds->dst, &lag) 6938 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 6939 6940 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6941 } 6942 6943 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6944 /* Row number corresponds to the number of active members in a 6945 * LAG. Each column states which of the eight hash buckets are 6946 * mapped to the column:th port in the LAG. 6947 * 6948 * Example: In a LAG with three active ports, the second port 6949 * ([2][1]) would be selected for traffic mapped to buckets 6950 * 3,4,5 (0x38). 6951 */ 6952 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6953 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6954 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6955 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6956 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6957 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6958 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6959 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6960 }; 6961 6962 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6963 int num_tx, int nth) 6964 { 6965 u8 active = 0; 6966 int i; 6967 6968 num_tx = num_tx <= 8 ? num_tx : 8; 6969 if (nth < num_tx) 6970 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6971 6972 for (i = 0; i < 8; i++) { 6973 if (BIT(i) & active) 6974 mask[i] |= BIT(port); 6975 } 6976 } 6977 6978 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6979 { 6980 struct mv88e6xxx_chip *chip = ds->priv; 6981 unsigned int id, num_tx; 6982 struct dsa_port *dp; 6983 struct dsa_lag *lag; 6984 int i, err, nth; 6985 u16 mask[8]; 6986 u16 ivec; 6987 6988 /* Assume no port is a member of any LAG. */ 6989 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6990 6991 /* Disable all masks for ports that _are_ members of a LAG. */ 6992 dsa_switch_for_each_port(dp, ds) { 6993 if (!dp->lag) 6994 continue; 6995 6996 ivec &= ~BIT(dp->index); 6997 } 6998 6999 for (i = 0; i < 8; i++) 7000 mask[i] = ivec; 7001 7002 /* Enable the correct subset of masks for all LAG ports that 7003 * are in the Tx set. 7004 */ 7005 dsa_lags_foreach_id(id, ds->dst) { 7006 lag = dsa_lag_by_id(ds->dst, id); 7007 if (!lag) 7008 continue; 7009 7010 num_tx = 0; 7011 dsa_lag_foreach_port(dp, ds->dst, lag) { 7012 if (dp->lag_tx_enabled) 7013 num_tx++; 7014 } 7015 7016 if (!num_tx) 7017 continue; 7018 7019 nth = 0; 7020 dsa_lag_foreach_port(dp, ds->dst, lag) { 7021 if (!dp->lag_tx_enabled) 7022 continue; 7023 7024 if (dp->ds == ds) 7025 mv88e6xxx_lag_set_port_mask(mask, dp->index, 7026 num_tx, nth); 7027 7028 nth++; 7029 } 7030 } 7031 7032 for (i = 0; i < 8; i++) { 7033 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 7034 if (err) 7035 return err; 7036 } 7037 7038 return 0; 7039 } 7040 7041 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 7042 struct dsa_lag lag) 7043 { 7044 int err; 7045 7046 err = mv88e6xxx_lag_sync_masks(ds); 7047 7048 if (!err) 7049 err = mv88e6xxx_lag_sync_map(ds, lag); 7050 7051 return err; 7052 } 7053 7054 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 7055 { 7056 struct mv88e6xxx_chip *chip = ds->priv; 7057 int err; 7058 7059 mv88e6xxx_reg_lock(chip); 7060 err = mv88e6xxx_lag_sync_masks(ds); 7061 mv88e6xxx_reg_unlock(chip); 7062 return err; 7063 } 7064 7065 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 7066 struct dsa_lag lag, 7067 struct netdev_lag_upper_info *info, 7068 struct netlink_ext_ack *extack) 7069 { 7070 struct mv88e6xxx_chip *chip = ds->priv; 7071 int err, id; 7072 7073 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 7074 return -EOPNOTSUPP; 7075 7076 /* DSA LAG IDs are one-based */ 7077 id = lag.id - 1; 7078 7079 mv88e6xxx_reg_lock(chip); 7080 7081 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 7082 if (err) 7083 goto err_unlock; 7084 7085 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 7086 if (err) 7087 goto err_clear_trunk; 7088 7089 mv88e6xxx_reg_unlock(chip); 7090 return 0; 7091 7092 err_clear_trunk: 7093 mv88e6xxx_port_set_trunk(chip, port, false, 0); 7094 err_unlock: 7095 mv88e6xxx_reg_unlock(chip); 7096 return err; 7097 } 7098 7099 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 7100 struct dsa_lag lag) 7101 { 7102 struct mv88e6xxx_chip *chip = ds->priv; 7103 int err_sync, err_trunk; 7104 7105 mv88e6xxx_reg_lock(chip); 7106 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 7107 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 7108 mv88e6xxx_reg_unlock(chip); 7109 return err_sync ? : err_trunk; 7110 } 7111 7112 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 7113 int port) 7114 { 7115 struct mv88e6xxx_chip *chip = ds->priv; 7116 int err; 7117 7118 mv88e6xxx_reg_lock(chip); 7119 err = mv88e6xxx_lag_sync_masks(ds); 7120 mv88e6xxx_reg_unlock(chip); 7121 return err; 7122 } 7123 7124 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 7125 int port, struct dsa_lag lag, 7126 struct netdev_lag_upper_info *info, 7127 struct netlink_ext_ack *extack) 7128 { 7129 struct mv88e6xxx_chip *chip = ds->priv; 7130 int err; 7131 7132 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 7133 return -EOPNOTSUPP; 7134 7135 mv88e6xxx_reg_lock(chip); 7136 7137 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 7138 if (err) 7139 goto unlock; 7140 7141 err = mv88e6xxx_pvt_map(chip, sw_index, port); 7142 7143 unlock: 7144 mv88e6xxx_reg_unlock(chip); 7145 return err; 7146 } 7147 7148 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 7149 int port, struct dsa_lag lag) 7150 { 7151 struct mv88e6xxx_chip *chip = ds->priv; 7152 int err_sync, err_pvt; 7153 7154 mv88e6xxx_reg_lock(chip); 7155 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 7156 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 7157 mv88e6xxx_reg_unlock(chip); 7158 return err_sync ? : err_pvt; 7159 } 7160 7161 static const struct phylink_mac_ops mv88e6xxx_phylink_mac_ops = { 7162 .mac_select_pcs = mv88e6xxx_mac_select_pcs, 7163 .mac_prepare = mv88e6xxx_mac_prepare, 7164 .mac_config = mv88e6xxx_mac_config, 7165 .mac_finish = mv88e6xxx_mac_finish, 7166 .mac_link_down = mv88e6xxx_mac_link_down, 7167 .mac_link_up = mv88e6xxx_mac_link_up, 7168 }; 7169 7170 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 7171 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 7172 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 7173 .setup = mv88e6xxx_setup, 7174 .teardown = mv88e6xxx_teardown, 7175 .port_setup = mv88e6xxx_port_setup, 7176 .port_teardown = mv88e6xxx_port_teardown, 7177 .phylink_get_caps = mv88e6xxx_get_caps, 7178 .get_strings = mv88e6xxx_get_strings, 7179 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 7180 .get_eth_mac_stats = mv88e6xxx_get_eth_mac_stats, 7181 .get_rmon_stats = mv88e6xxx_get_rmon_stats, 7182 .get_sset_count = mv88e6xxx_get_sset_count, 7183 .port_max_mtu = mv88e6xxx_get_max_mtu, 7184 .port_change_mtu = mv88e6xxx_change_mtu, 7185 .support_eee = dsa_supports_eee, 7186 .set_mac_eee = mv88e6xxx_set_mac_eee, 7187 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 7188 .get_eeprom = mv88e6xxx_get_eeprom, 7189 .set_eeprom = mv88e6xxx_set_eeprom, 7190 .get_regs_len = mv88e6xxx_get_regs_len, 7191 .get_regs = mv88e6xxx_get_regs, 7192 .get_rxnfc = mv88e6xxx_get_rxnfc, 7193 .set_rxnfc = mv88e6xxx_set_rxnfc, 7194 .set_ageing_time = mv88e6xxx_set_ageing_time, 7195 .port_bridge_join = mv88e6xxx_port_bridge_join, 7196 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 7197 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 7198 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 7199 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 7200 .port_mst_state_set = mv88e6xxx_port_mst_state_set, 7201 .port_fast_age = mv88e6xxx_port_fast_age, 7202 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age, 7203 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 7204 .port_vlan_add = mv88e6xxx_port_vlan_add, 7205 .port_vlan_del = mv88e6xxx_port_vlan_del, 7206 .vlan_msti_set = mv88e6xxx_vlan_msti_set, 7207 .port_fdb_add = mv88e6xxx_port_fdb_add, 7208 .port_fdb_del = mv88e6xxx_port_fdb_del, 7209 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 7210 .port_mdb_add = mv88e6xxx_port_mdb_add, 7211 .port_mdb_del = mv88e6xxx_port_mdb_del, 7212 .port_mirror_add = mv88e6xxx_port_mirror_add, 7213 .port_mirror_del = mv88e6xxx_port_mirror_del, 7214 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 7215 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 7216 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 7217 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 7218 .port_txtstamp = mv88e6xxx_port_txtstamp, 7219 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 7220 .cls_flower_add = mv88e6xxx_cls_flower_add, 7221 .cls_flower_del = mv88e6xxx_cls_flower_del, 7222 .get_ts_info = mv88e6xxx_get_ts_info, 7223 .devlink_param_get = mv88e6xxx_devlink_param_get, 7224 .devlink_param_set = mv88e6xxx_devlink_param_set, 7225 .devlink_info_get = mv88e6xxx_devlink_info_get, 7226 .port_lag_change = mv88e6xxx_port_lag_change, 7227 .port_lag_join = mv88e6xxx_port_lag_join, 7228 .port_lag_leave = mv88e6xxx_port_lag_leave, 7229 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 7230 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 7231 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 7232 }; 7233 7234 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 7235 { 7236 struct device *dev = chip->dev; 7237 struct dsa_switch *ds; 7238 7239 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 7240 if (!ds) 7241 return -ENOMEM; 7242 7243 ds->dev = dev; 7244 ds->num_ports = mv88e6xxx_num_ports(chip); 7245 ds->priv = chip; 7246 ds->dev = dev; 7247 ds->ops = &mv88e6xxx_switch_ops; 7248 ds->phylink_mac_ops = &mv88e6xxx_phylink_mac_ops; 7249 ds->ageing_time_min = chip->info->age_time_coeff; 7250 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 7251 7252 /* Some chips support up to 32, but that requires enabling the 7253 * 5-bit port mode, which we do not support. 640k^W16 ought to 7254 * be enough for anyone. 7255 */ 7256 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 7257 7258 dev_set_drvdata(dev, ds); 7259 7260 return dsa_register_switch(ds); 7261 } 7262 7263 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 7264 { 7265 dsa_unregister_switch(chip->ds); 7266 } 7267 7268 static const void *pdata_device_get_match_data(struct device *dev) 7269 { 7270 const struct of_device_id *matches = dev->driver->of_match_table; 7271 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 7272 7273 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 7274 matches++) { 7275 if (!strcmp(pdata->compatible, matches->compatible)) 7276 return matches->data; 7277 } 7278 return NULL; 7279 } 7280 7281 /* There is no suspend to RAM support at DSA level yet, the switch configuration 7282 * would be lost after a power cycle so prevent it to be suspended. 7283 */ 7284 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 7285 { 7286 return -EOPNOTSUPP; 7287 } 7288 7289 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 7290 { 7291 return 0; 7292 } 7293 7294 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 7295 7296 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 7297 { 7298 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 7299 const struct mv88e6xxx_info *compat_info = NULL; 7300 struct device *dev = &mdiodev->dev; 7301 struct device_node *np = dev->of_node; 7302 struct mv88e6xxx_chip *chip; 7303 int port; 7304 int err; 7305 7306 if (!np && !pdata) 7307 return -EINVAL; 7308 7309 if (np) 7310 compat_info = of_device_get_match_data(dev); 7311 7312 if (pdata) { 7313 compat_info = pdata_device_get_match_data(dev); 7314 7315 if (!pdata->netdev) 7316 return -EINVAL; 7317 7318 for (port = 0; port < DSA_MAX_PORTS; port++) { 7319 if (!(pdata->enabled_ports & (1 << port))) 7320 continue; 7321 if (strcmp(pdata->cd.port_names[port], "cpu")) 7322 continue; 7323 pdata->cd.netdev[port] = &pdata->netdev->dev; 7324 break; 7325 } 7326 } 7327 7328 if (!compat_info) 7329 return -EINVAL; 7330 7331 chip = mv88e6xxx_alloc_chip(dev); 7332 if (!chip) { 7333 err = -ENOMEM; 7334 goto out; 7335 } 7336 7337 chip->info = compat_info; 7338 7339 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 7340 if (IS_ERR(chip->reset)) { 7341 err = PTR_ERR(chip->reset); 7342 goto out; 7343 } 7344 if (chip->reset) 7345 usleep_range(10000, 20000); 7346 7347 /* Detect if the device is configured in single chip addressing mode, 7348 * otherwise continue with address specific smi init/detection. 7349 */ 7350 err = mv88e6xxx_single_chip_detect(chip, mdiodev); 7351 if (err) { 7352 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 7353 if (err) 7354 goto out; 7355 7356 err = mv88e6xxx_detect(chip); 7357 if (err) 7358 goto out; 7359 } 7360 7361 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 7362 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 7363 else 7364 chip->tag_protocol = DSA_TAG_PROTO_DSA; 7365 7366 mv88e6xxx_phy_init(chip); 7367 7368 if (chip->info->ops->get_eeprom) { 7369 if (np) 7370 of_property_read_u32(np, "eeprom-length", 7371 &chip->eeprom_len); 7372 else 7373 chip->eeprom_len = pdata->eeprom_len; 7374 } 7375 7376 mv88e6xxx_reg_lock(chip); 7377 err = mv88e6xxx_switch_reset(chip); 7378 mv88e6xxx_reg_unlock(chip); 7379 if (err) 7380 goto out_phy; 7381 7382 if (np) { 7383 chip->irq = of_irq_get(np, 0); 7384 if (chip->irq == -EPROBE_DEFER) { 7385 err = chip->irq; 7386 goto out_phy; 7387 } 7388 } 7389 7390 if (pdata) 7391 chip->irq = pdata->irq; 7392 7393 /* Has to be performed before the MDIO bus is created, because 7394 * the PHYs will link their interrupts to these interrupt 7395 * controllers 7396 */ 7397 mv88e6xxx_reg_lock(chip); 7398 if (chip->irq > 0) 7399 err = mv88e6xxx_g1_irq_setup(chip); 7400 else 7401 err = mv88e6xxx_irq_poll_setup(chip); 7402 mv88e6xxx_reg_unlock(chip); 7403 7404 if (err) 7405 goto out_phy; 7406 7407 if (chip->info->g2_irqs > 0) { 7408 err = mv88e6xxx_g2_irq_setup(chip); 7409 if (err) 7410 goto out_g1_irq; 7411 } 7412 7413 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 7414 if (err) 7415 goto out_g2_irq; 7416 7417 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 7418 if (err) 7419 goto out_g1_atu_prob_irq; 7420 7421 err = mv88e6xxx_register_switch(chip); 7422 if (err) 7423 goto out_g1_vtu_prob_irq; 7424 7425 return 0; 7426 7427 out_g1_vtu_prob_irq: 7428 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7429 out_g1_atu_prob_irq: 7430 mv88e6xxx_g1_atu_prob_irq_free(chip); 7431 out_g2_irq: 7432 if (chip->info->g2_irqs > 0) 7433 mv88e6xxx_g2_irq_free(chip); 7434 out_g1_irq: 7435 if (chip->irq > 0) 7436 mv88e6xxx_g1_irq_free(chip); 7437 else 7438 mv88e6xxx_irq_poll_free(chip); 7439 out_phy: 7440 mv88e6xxx_phy_destroy(chip); 7441 out: 7442 if (pdata) 7443 dev_put(pdata->netdev); 7444 7445 return err; 7446 } 7447 7448 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 7449 { 7450 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7451 struct mv88e6xxx_chip *chip; 7452 7453 if (!ds) 7454 return; 7455 7456 chip = ds->priv; 7457 7458 mv88e6xxx_unregister_switch(chip); 7459 7460 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7461 mv88e6xxx_g1_atu_prob_irq_free(chip); 7462 7463 if (chip->info->g2_irqs > 0) 7464 mv88e6xxx_g2_irq_free(chip); 7465 7466 if (chip->irq > 0) 7467 mv88e6xxx_g1_irq_free(chip); 7468 else 7469 mv88e6xxx_irq_poll_free(chip); 7470 7471 mv88e6xxx_phy_destroy(chip); 7472 } 7473 7474 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 7475 { 7476 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7477 7478 if (!ds) 7479 return; 7480 7481 dsa_switch_shutdown(ds); 7482 7483 dev_set_drvdata(&mdiodev->dev, NULL); 7484 } 7485 7486 static const struct of_device_id mv88e6xxx_of_match[] = { 7487 { 7488 .compatible = "marvell,mv88e6085", 7489 .data = &mv88e6xxx_table[MV88E6085], 7490 }, 7491 { 7492 .compatible = "marvell,mv88e6190", 7493 .data = &mv88e6xxx_table[MV88E6190], 7494 }, 7495 { 7496 .compatible = "marvell,mv88e6250", 7497 .data = &mv88e6xxx_table[MV88E6250], 7498 }, 7499 { /* sentinel */ }, 7500 }; 7501 7502 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 7503 7504 static struct mdio_driver mv88e6xxx_driver = { 7505 .probe = mv88e6xxx_probe, 7506 .remove = mv88e6xxx_remove, 7507 .shutdown = mv88e6xxx_shutdown, 7508 .mdiodrv.driver = { 7509 .name = "mv88e6085", 7510 .of_match_table = mv88e6xxx_of_match, 7511 .pm = &mv88e6xxx_pm_ops, 7512 }, 7513 }; 7514 7515 mdio_module_driver(mv88e6xxx_driver); 7516 7517 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 7518 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 7519 MODULE_LICENSE("GPL"); 7520