1 /*
2 * Driver for the MDIO interface of Marvell network interfaces.
3 *
4 * Since the MDIO interface of Marvell network interfaces is shared
5 * between all network interfaces, having a single driver allows to
6 * handle concurrent accesses properly (you may have four Ethernet
7 * ports, but they in fact share the same SMI interface to access
8 * the MDIO bus). This driver is currently used by the mvneta and
9 * mv643xx_eth drivers.
10 *
11 * Copyright (C) 2012 Marvell
12 *
13 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
14 *
15 * This file is licensed under the terms of the GNU General Public
16 * License version 2. This program is licensed "as is" without any
17 * warranty of any kind, whether express or implied.
18 */
19
20 #include <linux/acpi.h>
21 #include <linux/acpi_mdio.h>
22 #include <linux/clk.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/io.h>
26 #include <linux/iopoll.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/of_mdio.h>
30 #include <linux/phy.h>
31 #include <linux/platform_device.h>
32 #include <linux/sched.h>
33 #include <linux/wait.h>
34
35 #define MVMDIO_SMI_DATA_SHIFT 0
36 #define MVMDIO_SMI_PHY_ADDR_SHIFT 16
37 #define MVMDIO_SMI_PHY_REG_SHIFT 21
38 #define MVMDIO_SMI_READ_OPERATION BIT(26)
39 #define MVMDIO_SMI_WRITE_OPERATION 0
40 #define MVMDIO_SMI_READ_VALID BIT(27)
41 #define MVMDIO_SMI_BUSY BIT(28)
42 #define MVMDIO_ERR_INT_CAUSE 0x007C
43 #define MVMDIO_ERR_INT_SMI_DONE 0x00000010
44 #define MVMDIO_ERR_INT_MASK 0x0080
45
46 #define MVMDIO_XSMI_MGNT_REG 0x0
47 #define MVMDIO_XSMI_PHYADDR_SHIFT 16
48 #define MVMDIO_XSMI_DEVADDR_SHIFT 21
49 #define MVMDIO_XSMI_WRITE_OPERATION (0x5 << 26)
50 #define MVMDIO_XSMI_READ_OPERATION (0x7 << 26)
51 #define MVMDIO_XSMI_READ_VALID BIT(29)
52 #define MVMDIO_XSMI_BUSY BIT(30)
53 #define MVMDIO_XSMI_ADDR_REG 0x8
54
55 #define MVMDIO_XSMI_CFG_REG 0xc
56 #define MVMDIO_XSMI_CLKDIV_MASK 0x3
57 #define MVMDIO_XSMI_CLKDIV_256 0x0
58 #define MVMDIO_XSMI_CLKDIV_64 0x1
59 #define MVMDIO_XSMI_CLKDIV_32 0x2
60 #define MVMDIO_XSMI_CLKDIV_8 0x3
61
62 /*
63 * SMI Timeout measurements:
64 * - Kirkwood 88F6281 (Globalscale Dreamplug): 45us to 95us (Interrupt)
65 * - Armada 370 (Globalscale Mirabox): 41us to 43us (Polled)
66 */
67 #define MVMDIO_SMI_TIMEOUT 1000 /* 1000us = 1ms */
68
69 struct orion_mdio_dev {
70 void __iomem *regs;
71 struct clk *clk[4];
72 /*
73 * If we have access to the error interrupt pin (which is
74 * somewhat misnamed as it not only reflects internal errors
75 * but also reflects SMI completion), use that to wait for
76 * SMI access completion instead of polling the SMI busy bit.
77 */
78 int err_interrupt;
79 wait_queue_head_t smi_busy_wait;
80 };
81
82 enum orion_mdio_bus_type {
83 BUS_TYPE_SMI,
84 BUS_TYPE_XSMI
85 };
86
87 struct orion_mdio_ops {
88 int (*is_done)(struct orion_mdio_dev *);
89 };
90
91 /* Wait for the SMI unit to be ready for another operation
92 */
orion_mdio_wait_ready(const struct orion_mdio_ops * ops,struct mii_bus * bus)93 static int orion_mdio_wait_ready(const struct orion_mdio_ops *ops,
94 struct mii_bus *bus)
95 {
96 struct orion_mdio_dev *dev = bus->priv;
97 unsigned long timeout;
98 int done;
99
100 if (dev->err_interrupt <= 0) {
101 if (!read_poll_timeout_atomic(ops->is_done, done, done, 2,
102 MVMDIO_SMI_TIMEOUT, false, dev))
103 return 0;
104 } else {
105 /* wait_event_timeout does not guarantee a delay of at
106 * least one whole jiffy, so timeout must be no less
107 * than two.
108 */
109 timeout = max(usecs_to_jiffies(MVMDIO_SMI_TIMEOUT), 2);
110
111 if (wait_event_timeout(dev->smi_busy_wait,
112 ops->is_done(dev), timeout))
113 return 0;
114 }
115
116 dev_err(bus->parent, "Timeout: SMI busy for too long\n");
117 return -ETIMEDOUT;
118 }
119
orion_mdio_smi_is_done(struct orion_mdio_dev * dev)120 static int orion_mdio_smi_is_done(struct orion_mdio_dev *dev)
121 {
122 return !(readl(dev->regs) & MVMDIO_SMI_BUSY);
123 }
124
125 static const struct orion_mdio_ops orion_mdio_smi_ops = {
126 .is_done = orion_mdio_smi_is_done,
127 };
128
orion_mdio_smi_read(struct mii_bus * bus,int mii_id,int regnum)129 static int orion_mdio_smi_read(struct mii_bus *bus, int mii_id,
130 int regnum)
131 {
132 struct orion_mdio_dev *dev = bus->priv;
133 u32 val;
134 int ret;
135
136 ret = orion_mdio_wait_ready(&orion_mdio_smi_ops, bus);
137 if (ret < 0)
138 return ret;
139
140 writel(((mii_id << MVMDIO_SMI_PHY_ADDR_SHIFT) |
141 (regnum << MVMDIO_SMI_PHY_REG_SHIFT) |
142 MVMDIO_SMI_READ_OPERATION),
143 dev->regs);
144
145 ret = orion_mdio_wait_ready(&orion_mdio_smi_ops, bus);
146 if (ret < 0)
147 return ret;
148
149 val = readl(dev->regs);
150 if (!(val & MVMDIO_SMI_READ_VALID)) {
151 dev_err(bus->parent, "SMI bus read not valid\n");
152 return -ENODEV;
153 }
154
155 return val & GENMASK(15, 0);
156 }
157
orion_mdio_smi_write(struct mii_bus * bus,int mii_id,int regnum,u16 value)158 static int orion_mdio_smi_write(struct mii_bus *bus, int mii_id,
159 int regnum, u16 value)
160 {
161 struct orion_mdio_dev *dev = bus->priv;
162 int ret;
163
164 ret = orion_mdio_wait_ready(&orion_mdio_smi_ops, bus);
165 if (ret < 0)
166 return ret;
167
168 writel(((mii_id << MVMDIO_SMI_PHY_ADDR_SHIFT) |
169 (regnum << MVMDIO_SMI_PHY_REG_SHIFT) |
170 MVMDIO_SMI_WRITE_OPERATION |
171 (value << MVMDIO_SMI_DATA_SHIFT)),
172 dev->regs);
173
174 return 0;
175 }
176
orion_mdio_xsmi_is_done(struct orion_mdio_dev * dev)177 static int orion_mdio_xsmi_is_done(struct orion_mdio_dev *dev)
178 {
179 return !(readl(dev->regs + MVMDIO_XSMI_MGNT_REG) & MVMDIO_XSMI_BUSY);
180 }
181
182 static const struct orion_mdio_ops orion_mdio_xsmi_ops = {
183 .is_done = orion_mdio_xsmi_is_done,
184 };
185
orion_mdio_xsmi_read_c45(struct mii_bus * bus,int mii_id,int dev_addr,int regnum)186 static int orion_mdio_xsmi_read_c45(struct mii_bus *bus, int mii_id,
187 int dev_addr, int regnum)
188 {
189 struct orion_mdio_dev *dev = bus->priv;
190 int ret;
191
192 ret = orion_mdio_wait_ready(&orion_mdio_xsmi_ops, bus);
193 if (ret < 0)
194 return ret;
195
196 writel(regnum, dev->regs + MVMDIO_XSMI_ADDR_REG);
197 writel((mii_id << MVMDIO_XSMI_PHYADDR_SHIFT) |
198 (dev_addr << MVMDIO_XSMI_DEVADDR_SHIFT) |
199 MVMDIO_XSMI_READ_OPERATION,
200 dev->regs + MVMDIO_XSMI_MGNT_REG);
201
202 ret = orion_mdio_wait_ready(&orion_mdio_xsmi_ops, bus);
203 if (ret < 0)
204 return ret;
205
206 if (!(readl(dev->regs + MVMDIO_XSMI_MGNT_REG) &
207 MVMDIO_XSMI_READ_VALID)) {
208 dev_err(bus->parent, "XSMI bus read not valid\n");
209 return -ENODEV;
210 }
211
212 return readl(dev->regs + MVMDIO_XSMI_MGNT_REG) & GENMASK(15, 0);
213 }
214
orion_mdio_xsmi_write_c45(struct mii_bus * bus,int mii_id,int dev_addr,int regnum,u16 value)215 static int orion_mdio_xsmi_write_c45(struct mii_bus *bus, int mii_id,
216 int dev_addr, int regnum, u16 value)
217 {
218 struct orion_mdio_dev *dev = bus->priv;
219 int ret;
220
221 ret = orion_mdio_wait_ready(&orion_mdio_xsmi_ops, bus);
222 if (ret < 0)
223 return ret;
224
225 writel(regnum, dev->regs + MVMDIO_XSMI_ADDR_REG);
226 writel((mii_id << MVMDIO_XSMI_PHYADDR_SHIFT) |
227 (dev_addr << MVMDIO_XSMI_DEVADDR_SHIFT) |
228 MVMDIO_XSMI_WRITE_OPERATION | value,
229 dev->regs + MVMDIO_XSMI_MGNT_REG);
230
231 return 0;
232 }
233
orion_mdio_xsmi_set_mdc_freq(struct mii_bus * bus)234 static void orion_mdio_xsmi_set_mdc_freq(struct mii_bus *bus)
235 {
236 struct orion_mdio_dev *dev = bus->priv;
237 struct clk *mg_core;
238 u32 div, freq, cfg;
239
240 if (device_property_read_u32(bus->parent, "clock-frequency", &freq))
241 return;
242
243 mg_core = of_clk_get_by_name(bus->parent->of_node, "mg_core_clk");
244 if (IS_ERR(mg_core)) {
245 dev_err(bus->parent,
246 "MG core clock unknown, not changing MDC frequency");
247 return;
248 }
249
250 div = clk_get_rate(mg_core) / (freq + 1) + 1;
251 clk_put(mg_core);
252
253 if (div <= 8)
254 div = MVMDIO_XSMI_CLKDIV_8;
255 else if (div <= 32)
256 div = MVMDIO_XSMI_CLKDIV_32;
257 else if (div <= 64)
258 div = MVMDIO_XSMI_CLKDIV_64;
259 else
260 div = MVMDIO_XSMI_CLKDIV_256;
261
262 cfg = readl(dev->regs + MVMDIO_XSMI_CFG_REG);
263 cfg &= ~MVMDIO_XSMI_CLKDIV_MASK;
264 cfg |= div;
265 writel(cfg, dev->regs + MVMDIO_XSMI_CFG_REG);
266 }
267
orion_mdio_err_irq(int irq,void * dev_id)268 static irqreturn_t orion_mdio_err_irq(int irq, void *dev_id)
269 {
270 struct orion_mdio_dev *dev = dev_id;
271
272 if (readl(dev->regs + MVMDIO_ERR_INT_CAUSE) &
273 MVMDIO_ERR_INT_SMI_DONE) {
274 writel(~MVMDIO_ERR_INT_SMI_DONE,
275 dev->regs + MVMDIO_ERR_INT_CAUSE);
276 wake_up(&dev->smi_busy_wait);
277 return IRQ_HANDLED;
278 }
279
280 return IRQ_NONE;
281 }
282
orion_mdio_probe(struct platform_device * pdev)283 static int orion_mdio_probe(struct platform_device *pdev)
284 {
285 enum orion_mdio_bus_type type;
286 struct resource *r;
287 struct mii_bus *bus;
288 struct orion_mdio_dev *dev;
289 int i, ret;
290
291 type = (uintptr_t)device_get_match_data(&pdev->dev);
292
293 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
294 if (!r) {
295 dev_err(&pdev->dev, "No SMI register address given\n");
296 return -ENODEV;
297 }
298
299 bus = devm_mdiobus_alloc_size(&pdev->dev,
300 sizeof(struct orion_mdio_dev));
301 if (!bus)
302 return -ENOMEM;
303
304 switch (type) {
305 case BUS_TYPE_SMI:
306 bus->read = orion_mdio_smi_read;
307 bus->write = orion_mdio_smi_write;
308 break;
309 case BUS_TYPE_XSMI:
310 bus->read_c45 = orion_mdio_xsmi_read_c45;
311 bus->write_c45 = orion_mdio_xsmi_write_c45;
312 break;
313 }
314
315 bus->name = "orion_mdio_bus";
316 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii",
317 dev_name(&pdev->dev));
318 bus->parent = &pdev->dev;
319
320 dev = bus->priv;
321 dev->regs = devm_ioremap(&pdev->dev, r->start, resource_size(r));
322 if (!dev->regs) {
323 dev_err(&pdev->dev, "Unable to remap SMI register\n");
324 return -ENODEV;
325 }
326
327 init_waitqueue_head(&dev->smi_busy_wait);
328
329 if (pdev->dev.of_node) {
330 for (i = 0; i < ARRAY_SIZE(dev->clk); i++) {
331 dev->clk[i] = of_clk_get(pdev->dev.of_node, i);
332 if (PTR_ERR(dev->clk[i]) == -EPROBE_DEFER) {
333 ret = -EPROBE_DEFER;
334 goto out_clk;
335 }
336 if (IS_ERR(dev->clk[i]))
337 break;
338 clk_prepare_enable(dev->clk[i]);
339 }
340
341 if (!IS_ERR(of_clk_get(pdev->dev.of_node,
342 ARRAY_SIZE(dev->clk))))
343 dev_warn(&pdev->dev,
344 "unsupported number of clocks, limiting to the first "
345 __stringify(ARRAY_SIZE(dev->clk)) "\n");
346
347 if (type == BUS_TYPE_XSMI)
348 orion_mdio_xsmi_set_mdc_freq(bus);
349 } else {
350 dev->clk[0] = clk_get_optional(&pdev->dev, NULL);
351 if (IS_ERR(dev->clk[0])) {
352 ret = PTR_ERR(dev->clk[0]);
353 goto out_clk;
354 }
355 clk_prepare_enable(dev->clk[0]);
356 }
357
358
359 dev->err_interrupt = platform_get_irq_optional(pdev, 0);
360 if (dev->err_interrupt > 0 &&
361 resource_size(r) < MVMDIO_ERR_INT_MASK + 4) {
362 dev_err(&pdev->dev,
363 "disabling interrupt, resource size is too small\n");
364 dev->err_interrupt = 0;
365 }
366 if (dev->err_interrupt > 0) {
367 ret = devm_request_irq(&pdev->dev, dev->err_interrupt,
368 orion_mdio_err_irq,
369 IRQF_SHARED, pdev->name, dev);
370 if (ret)
371 goto out_mdio;
372
373 writel(MVMDIO_ERR_INT_SMI_DONE,
374 dev->regs + MVMDIO_ERR_INT_MASK);
375
376 } else if (dev->err_interrupt == -EPROBE_DEFER) {
377 ret = -EPROBE_DEFER;
378 goto out_mdio;
379 }
380
381 /* For the platforms not supporting DT/ACPI fall-back
382 * to mdiobus_register via of_mdiobus_register.
383 */
384 if (is_acpi_node(pdev->dev.fwnode))
385 ret = acpi_mdiobus_register(bus, pdev->dev.fwnode);
386 else
387 ret = of_mdiobus_register(bus, pdev->dev.of_node);
388 if (ret < 0) {
389 dev_err(&pdev->dev, "Cannot register MDIO bus (%d)\n", ret);
390 goto out_mdio;
391 }
392
393 platform_set_drvdata(pdev, bus);
394
395 return 0;
396
397 out_mdio:
398 if (dev->err_interrupt > 0)
399 writel(0, dev->regs + MVMDIO_ERR_INT_MASK);
400
401 out_clk:
402 for (i = 0; i < ARRAY_SIZE(dev->clk); i++) {
403 if (IS_ERR(dev->clk[i]))
404 break;
405 clk_disable_unprepare(dev->clk[i]);
406 clk_put(dev->clk[i]);
407 }
408
409 return ret;
410 }
411
orion_mdio_remove(struct platform_device * pdev)412 static void orion_mdio_remove(struct platform_device *pdev)
413 {
414 struct mii_bus *bus = platform_get_drvdata(pdev);
415 struct orion_mdio_dev *dev = bus->priv;
416 int i;
417
418 if (dev->err_interrupt > 0)
419 writel(0, dev->regs + MVMDIO_ERR_INT_MASK);
420 mdiobus_unregister(bus);
421
422 for (i = 0; i < ARRAY_SIZE(dev->clk); i++) {
423 clk_disable_unprepare(dev->clk[i]);
424 clk_put(dev->clk[i]);
425 }
426 }
427
428 static const struct of_device_id orion_mdio_match[] = {
429 { .compatible = "marvell,orion-mdio", .data = (void *)BUS_TYPE_SMI },
430 { .compatible = "marvell,xmdio", .data = (void *)BUS_TYPE_XSMI },
431 { }
432 };
433 MODULE_DEVICE_TABLE(of, orion_mdio_match);
434
435 #ifdef CONFIG_ACPI
436 static const struct acpi_device_id orion_mdio_acpi_match[] = {
437 { "MRVL0100", BUS_TYPE_SMI },
438 { "MRVL0101", BUS_TYPE_XSMI },
439 { },
440 };
441 MODULE_DEVICE_TABLE(acpi, orion_mdio_acpi_match);
442 #endif
443
444 static struct platform_driver orion_mdio_driver = {
445 .probe = orion_mdio_probe,
446 .remove = orion_mdio_remove,
447 .driver = {
448 .name = "orion-mdio",
449 .of_match_table = orion_mdio_match,
450 .acpi_match_table = ACPI_PTR(orion_mdio_acpi_match),
451 },
452 };
453
454 module_platform_driver(orion_mdio_driver);
455
456 MODULE_DESCRIPTION("Marvell MDIO interface driver");
457 MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
458 MODULE_LICENSE("GPL");
459 MODULE_ALIAS("platform:orion-mdio");
460