1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Synopsys DesignWare PCIe controller debugfs driver
4 *
5 * Copyright (C) 2025 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 *
8 * Author: Shradha Todi <shradha.t@samsung.com>
9 */
10
11 #include <linux/debugfs.h>
12
13 #include "pcie-designware.h"
14
15 #define SD_STATUS_L1LANE_REG 0xb0
16 #define PIPE_RXVALID BIT(18)
17 #define PIPE_DETECT_LANE BIT(17)
18 #define LANE_SELECT GENMASK(3, 0)
19
20 #define ERR_INJ0_OFF 0x34
21 #define EINJ_VAL_DIFF GENMASK(28, 16)
22 #define EINJ_VC_NUM GENMASK(14, 12)
23 #define EINJ_TYPE_SHIFT 8
24 #define EINJ0_TYPE GENMASK(11, 8)
25 #define EINJ1_TYPE BIT(8)
26 #define EINJ2_TYPE GENMASK(9, 8)
27 #define EINJ3_TYPE GENMASK(10, 8)
28 #define EINJ4_TYPE GENMASK(10, 8)
29 #define EINJ5_TYPE BIT(8)
30 #define EINJ_COUNT GENMASK(7, 0)
31
32 #define ERR_INJ_ENABLE_REG 0x30
33
34 #define RAS_DES_EVENT_COUNTER_DATA_REG 0xc
35
36 #define RAS_DES_EVENT_COUNTER_CTRL_REG 0x8
37 #define EVENT_COUNTER_GROUP_SELECT GENMASK(27, 24)
38 #define EVENT_COUNTER_EVENT_SELECT GENMASK(23, 16)
39 #define EVENT_COUNTER_LANE_SELECT GENMASK(11, 8)
40 #define EVENT_COUNTER_STATUS BIT(7)
41 #define EVENT_COUNTER_ENABLE GENMASK(4, 2)
42 #define PER_EVENT_ON 0x3
43 #define PER_EVENT_OFF 0x1
44
45 #define DWC_DEBUGFS_BUF_MAX 128
46
47 /**
48 * struct dwc_pcie_rasdes_info - Stores controller common information
49 * @ras_cap_offset: RAS DES vendor specific extended capability offset
50 * @reg_event_lock: Mutex used for RAS DES shadow event registers
51 *
52 * Any parameter constant to all files of the debugfs hierarchy for a single
53 * controller will be stored in this struct. It is allocated and assigned to
54 * controller specific struct dw_pcie during initialization.
55 */
56 struct dwc_pcie_rasdes_info {
57 u32 ras_cap_offset;
58 struct mutex reg_event_lock;
59 };
60
61 /**
62 * struct dwc_pcie_rasdes_priv - Stores file specific private data information
63 * @pci: Reference to the dw_pcie structure
64 * @idx: Index of specific file related information in array of structs
65 *
66 * All debugfs files will have this struct as its private data.
67 */
68 struct dwc_pcie_rasdes_priv {
69 struct dw_pcie *pci;
70 int idx;
71 };
72
73 /**
74 * struct dwc_pcie_err_inj - Store details about each error injection
75 * supported by DWC RAS DES
76 * @name: Name of the error that can be injected
77 * @err_inj_group: Group number to which the error belongs. The value
78 * can range from 0 to 5
79 * @err_inj_type: Each group can have multiple types of error
80 */
81 struct dwc_pcie_err_inj {
82 const char *name;
83 u32 err_inj_group;
84 u32 err_inj_type;
85 };
86
87 static const struct dwc_pcie_err_inj err_inj_list[] = {
88 {"tx_lcrc", 0x0, 0x0},
89 {"b16_crc_dllp", 0x0, 0x1},
90 {"b16_crc_upd_fc", 0x0, 0x2},
91 {"tx_ecrc", 0x0, 0x3},
92 {"fcrc_tlp", 0x0, 0x4},
93 {"parity_tsos", 0x0, 0x5},
94 {"parity_skpos", 0x0, 0x6},
95 {"rx_lcrc", 0x0, 0x8},
96 {"rx_ecrc", 0x0, 0xb},
97 {"tlp_err_seq", 0x1, 0x0},
98 {"ack_nak_dllp_seq", 0x1, 0x1},
99 {"ack_nak_dllp", 0x2, 0x0},
100 {"upd_fc_dllp", 0x2, 0x1},
101 {"nak_dllp", 0x2, 0x2},
102 {"inv_sync_hdr_sym", 0x3, 0x0},
103 {"com_pad_ts1", 0x3, 0x1},
104 {"com_pad_ts2", 0x3, 0x2},
105 {"com_fts", 0x3, 0x3},
106 {"com_idl", 0x3, 0x4},
107 {"end_edb", 0x3, 0x5},
108 {"stp_sdp", 0x3, 0x6},
109 {"com_skp", 0x3, 0x7},
110 {"posted_tlp_hdr", 0x4, 0x0},
111 {"non_post_tlp_hdr", 0x4, 0x1},
112 {"cmpl_tlp_hdr", 0x4, 0x2},
113 {"posted_tlp_data", 0x4, 0x4},
114 {"non_post_tlp_data", 0x4, 0x5},
115 {"cmpl_tlp_data", 0x4, 0x6},
116 {"duplicate_tlp", 0x5, 0x0},
117 {"nullified_tlp", 0x5, 0x1},
118 };
119
120 static const u32 err_inj_type_mask[] = {
121 EINJ0_TYPE,
122 EINJ1_TYPE,
123 EINJ2_TYPE,
124 EINJ3_TYPE,
125 EINJ4_TYPE,
126 EINJ5_TYPE,
127 };
128
129 /**
130 * struct dwc_pcie_event_counter - Store details about each event counter
131 * supported in DWC RAS DES
132 * @name: Name of the error counter
133 * @group_no: Group number that the event belongs to. The value can range
134 * from 0 to 7
135 * @event_no: Event number of the particular event. The value ranges are:
136 * Group 0: 0 - 10
137 * Group 1: 5 - 13
138 * Group 2: 0 - 7
139 * Group 3: 0 - 5
140 * Group 4: 0 - 1
141 * Group 5: 0 - 13
142 * Group 6: 0 - 6
143 * Group 7: 0 - 25
144 */
145 struct dwc_pcie_event_counter {
146 const char *name;
147 u32 group_no;
148 u32 event_no;
149 };
150
151 static const struct dwc_pcie_event_counter event_list[] = {
152 {"ebuf_overflow", 0x0, 0x0},
153 {"ebuf_underrun", 0x0, 0x1},
154 {"decode_err", 0x0, 0x2},
155 {"running_disparity_err", 0x0, 0x3},
156 {"skp_os_parity_err", 0x0, 0x4},
157 {"sync_header_err", 0x0, 0x5},
158 {"rx_valid_deassertion", 0x0, 0x6},
159 {"ctl_skp_os_parity_err", 0x0, 0x7},
160 {"retimer_parity_err_1st", 0x0, 0x8},
161 {"retimer_parity_err_2nd", 0x0, 0x9},
162 {"margin_crc_parity_err", 0x0, 0xA},
163 {"detect_ei_infer", 0x1, 0x5},
164 {"receiver_err", 0x1, 0x6},
165 {"rx_recovery_req", 0x1, 0x7},
166 {"n_fts_timeout", 0x1, 0x8},
167 {"framing_err", 0x1, 0x9},
168 {"deskew_err", 0x1, 0xa},
169 {"framing_err_in_l0", 0x1, 0xc},
170 {"deskew_uncompleted_err", 0x1, 0xd},
171 {"bad_tlp", 0x2, 0x0},
172 {"lcrc_err", 0x2, 0x1},
173 {"bad_dllp", 0x2, 0x2},
174 {"replay_num_rollover", 0x2, 0x3},
175 {"replay_timeout", 0x2, 0x4},
176 {"rx_nak_dllp", 0x2, 0x5},
177 {"tx_nak_dllp", 0x2, 0x6},
178 {"retry_tlp", 0x2, 0x7},
179 {"fc_timeout", 0x3, 0x0},
180 {"poisoned_tlp", 0x3, 0x1},
181 {"ecrc_error", 0x3, 0x2},
182 {"unsupported_request", 0x3, 0x3},
183 {"completer_abort", 0x3, 0x4},
184 {"completion_timeout", 0x3, 0x5},
185 {"ebuf_skp_add", 0x4, 0x0},
186 {"ebuf_skp_del", 0x4, 0x1},
187 {"l0_to_recovery_entry", 0x5, 0x0},
188 {"l1_to_recovery_entry", 0x5, 0x1},
189 {"tx_l0s_entry", 0x5, 0x2},
190 {"rx_l0s_entry", 0x5, 0x3},
191 {"aspm_l1_reject", 0x5, 0x4},
192 {"l1_entry", 0x5, 0x5},
193 {"l1_cpm", 0x5, 0x6},
194 {"l1.1_entry", 0x5, 0x7},
195 {"l1.2_entry", 0x5, 0x8},
196 {"l1_short_duration", 0x5, 0x9},
197 {"l1.2_abort", 0x5, 0xa},
198 {"l2_entry", 0x5, 0xb},
199 {"speed_change", 0x5, 0xc},
200 {"link_width_change", 0x5, 0xd},
201 {"tx_ack_dllp", 0x6, 0x0},
202 {"tx_update_fc_dllp", 0x6, 0x1},
203 {"rx_ack_dllp", 0x6, 0x2},
204 {"rx_update_fc_dllp", 0x6, 0x3},
205 {"rx_nullified_tlp", 0x6, 0x4},
206 {"tx_nullified_tlp", 0x6, 0x5},
207 {"rx_duplicate_tlp", 0x6, 0x6},
208 {"tx_memory_write", 0x7, 0x0},
209 {"tx_memory_read", 0x7, 0x1},
210 {"tx_configuration_write", 0x7, 0x2},
211 {"tx_configuration_read", 0x7, 0x3},
212 {"tx_io_write", 0x7, 0x4},
213 {"tx_io_read", 0x7, 0x5},
214 {"tx_completion_without_data", 0x7, 0x6},
215 {"tx_completion_w_data", 0x7, 0x7},
216 {"tx_message_tlp_pcie_vc_only", 0x7, 0x8},
217 {"tx_atomic", 0x7, 0x9},
218 {"tx_tlp_with_prefix", 0x7, 0xa},
219 {"rx_memory_write", 0x7, 0xb},
220 {"rx_memory_read", 0x7, 0xc},
221 {"rx_configuration_write", 0x7, 0xd},
222 {"rx_configuration_read", 0x7, 0xe},
223 {"rx_io_write", 0x7, 0xf},
224 {"rx_io_read", 0x7, 0x10},
225 {"rx_completion_without_data", 0x7, 0x11},
226 {"rx_completion_w_data", 0x7, 0x12},
227 {"rx_message_tlp_pcie_vc_only", 0x7, 0x13},
228 {"rx_atomic", 0x7, 0x14},
229 {"rx_tlp_with_prefix", 0x7, 0x15},
230 {"tx_ccix_tlp", 0x7, 0x16},
231 {"rx_ccix_tlp", 0x7, 0x17},
232 {"tx_deferrable_memory_write_tlp", 0x7, 0x18},
233 {"rx_deferrable_memory_write_tlp", 0x7, 0x19},
234 };
235
lane_detect_read(struct file * file,char __user * buf,size_t count,loff_t * ppos)236 static ssize_t lane_detect_read(struct file *file, char __user *buf,
237 size_t count, loff_t *ppos)
238 {
239 struct dw_pcie *pci = file->private_data;
240 struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
241 char debugfs_buf[DWC_DEBUGFS_BUF_MAX];
242 ssize_t pos;
243 u32 val;
244
245 val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_REG);
246 val = FIELD_GET(PIPE_DETECT_LANE, val);
247 if (val)
248 pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Lane Detected\n");
249 else
250 pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Lane Undetected\n");
251
252 return simple_read_from_buffer(buf, count, ppos, debugfs_buf, pos);
253 }
254
lane_detect_write(struct file * file,const char __user * buf,size_t count,loff_t * ppos)255 static ssize_t lane_detect_write(struct file *file, const char __user *buf,
256 size_t count, loff_t *ppos)
257 {
258 struct dw_pcie *pci = file->private_data;
259 struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
260 u32 lane, val;
261 int ret;
262
263 ret = kstrtou32_from_user(buf, count, 0, &lane);
264 if (ret)
265 return ret;
266
267 val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_REG);
268 FIELD_MODIFY(LANE_SELECT, &val, lane);
269 dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_REG, val);
270
271 return count;
272 }
273
rx_valid_read(struct file * file,char __user * buf,size_t count,loff_t * ppos)274 static ssize_t rx_valid_read(struct file *file, char __user *buf,
275 size_t count, loff_t *ppos)
276 {
277 struct dw_pcie *pci = file->private_data;
278 struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
279 char debugfs_buf[DWC_DEBUGFS_BUF_MAX];
280 ssize_t pos;
281 u32 val;
282
283 val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_REG);
284 val = FIELD_GET(PIPE_RXVALID, val);
285 if (val)
286 pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "RX Valid\n");
287 else
288 pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "RX Invalid\n");
289
290 return simple_read_from_buffer(buf, count, ppos, debugfs_buf, pos);
291 }
292
rx_valid_write(struct file * file,const char __user * buf,size_t count,loff_t * ppos)293 static ssize_t rx_valid_write(struct file *file, const char __user *buf,
294 size_t count, loff_t *ppos)
295 {
296 return lane_detect_write(file, buf, count, ppos);
297 }
298
err_inj_write(struct file * file,const char __user * buf,size_t count,loff_t * ppos)299 static ssize_t err_inj_write(struct file *file, const char __user *buf,
300 size_t count, loff_t *ppos)
301 {
302 struct dwc_pcie_rasdes_priv *pdata = file->private_data;
303 struct dw_pcie *pci = pdata->pci;
304 struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
305 u32 val, counter, vc_num, err_group, type_mask;
306 int val_diff = 0;
307 char *kern_buf;
308 int ret;
309
310 err_group = err_inj_list[pdata->idx].err_inj_group;
311 type_mask = err_inj_type_mask[err_group];
312
313 kern_buf = memdup_user_nul(buf, count);
314 if (IS_ERR(kern_buf))
315 return PTR_ERR(kern_buf);
316
317 if (err_group == 4) {
318 val = sscanf(kern_buf, "%u %d %u", &counter, &val_diff, &vc_num);
319 if ((val != 3) || (val_diff < -4095 || val_diff > 4095)) {
320 kfree(kern_buf);
321 return -EINVAL;
322 }
323 } else if (err_group == 1) {
324 val = sscanf(kern_buf, "%u %d", &counter, &val_diff);
325 if ((val != 2) || (val_diff < -4095 || val_diff > 4095)) {
326 kfree(kern_buf);
327 return -EINVAL;
328 }
329 } else {
330 ret = kstrtou32(kern_buf, 0, &counter);
331 if (ret) {
332 kfree(kern_buf);
333 return ret;
334 }
335 }
336
337 val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + ERR_INJ0_OFF + (0x4 * err_group));
338 val &= ~(type_mask | EINJ_COUNT);
339 val |= ((err_inj_list[pdata->idx].err_inj_type << EINJ_TYPE_SHIFT) & type_mask);
340 val |= FIELD_PREP(EINJ_COUNT, counter);
341
342 if (err_group == 1 || err_group == 4)
343 FIELD_MODIFY(EINJ_VAL_DIFF, &val, val_diff);
344 if (err_group == 4)
345 FIELD_MODIFY(EINJ_VC_NUM, &val, vc_num);
346
347 dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + ERR_INJ0_OFF + (0x4 * err_group), val);
348 dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + ERR_INJ_ENABLE_REG, (0x1 << err_group));
349
350 kfree(kern_buf);
351 return count;
352 }
353
set_event_number(struct dwc_pcie_rasdes_priv * pdata,struct dw_pcie * pci,struct dwc_pcie_rasdes_info * rinfo)354 static void set_event_number(struct dwc_pcie_rasdes_priv *pdata,
355 struct dw_pcie *pci, struct dwc_pcie_rasdes_info *rinfo)
356 {
357 u32 val;
358
359 val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG);
360 val &= ~EVENT_COUNTER_ENABLE;
361 FIELD_MODIFY(EVENT_COUNTER_GROUP_SELECT, &val, event_list[pdata->idx].group_no);
362 FIELD_MODIFY(EVENT_COUNTER_EVENT_SELECT, &val, event_list[pdata->idx].event_no);
363 dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG, val);
364 }
365
counter_enable_read(struct file * file,char __user * buf,size_t count,loff_t * ppos)366 static ssize_t counter_enable_read(struct file *file, char __user *buf,
367 size_t count, loff_t *ppos)
368 {
369 struct dwc_pcie_rasdes_priv *pdata = file->private_data;
370 struct dw_pcie *pci = pdata->pci;
371 struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
372 char debugfs_buf[DWC_DEBUGFS_BUF_MAX];
373 ssize_t pos;
374 u32 val;
375
376 mutex_lock(&rinfo->reg_event_lock);
377 set_event_number(pdata, pci, rinfo);
378 val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG);
379 mutex_unlock(&rinfo->reg_event_lock);
380 val = FIELD_GET(EVENT_COUNTER_STATUS, val);
381 if (val)
382 pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Counter Enabled\n");
383 else
384 pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Counter Disabled\n");
385
386 return simple_read_from_buffer(buf, count, ppos, debugfs_buf, pos);
387 }
388
counter_enable_write(struct file * file,const char __user * buf,size_t count,loff_t * ppos)389 static ssize_t counter_enable_write(struct file *file, const char __user *buf,
390 size_t count, loff_t *ppos)
391 {
392 struct dwc_pcie_rasdes_priv *pdata = file->private_data;
393 struct dw_pcie *pci = pdata->pci;
394 struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
395 u32 val, enable;
396 int ret;
397
398 ret = kstrtou32_from_user(buf, count, 0, &enable);
399 if (ret)
400 return ret;
401
402 mutex_lock(&rinfo->reg_event_lock);
403 set_event_number(pdata, pci, rinfo);
404 val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG);
405 if (enable)
406 val |= FIELD_PREP(EVENT_COUNTER_ENABLE, PER_EVENT_ON);
407 else
408 val |= FIELD_PREP(EVENT_COUNTER_ENABLE, PER_EVENT_OFF);
409
410 dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG, val);
411
412 /*
413 * While enabling the counter, always read the status back to check if
414 * it is enabled or not. Return error if it is not enabled to let the
415 * users know that the counter is not supported on the platform.
416 */
417 if (enable) {
418 val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset +
419 RAS_DES_EVENT_COUNTER_CTRL_REG);
420 if (!FIELD_GET(EVENT_COUNTER_STATUS, val)) {
421 mutex_unlock(&rinfo->reg_event_lock);
422 return -EOPNOTSUPP;
423 }
424 }
425
426 mutex_unlock(&rinfo->reg_event_lock);
427
428 return count;
429 }
430
counter_lane_read(struct file * file,char __user * buf,size_t count,loff_t * ppos)431 static ssize_t counter_lane_read(struct file *file, char __user *buf,
432 size_t count, loff_t *ppos)
433 {
434 struct dwc_pcie_rasdes_priv *pdata = file->private_data;
435 struct dw_pcie *pci = pdata->pci;
436 struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
437 char debugfs_buf[DWC_DEBUGFS_BUF_MAX];
438 ssize_t pos;
439 u32 val;
440
441 mutex_lock(&rinfo->reg_event_lock);
442 set_event_number(pdata, pci, rinfo);
443 val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG);
444 mutex_unlock(&rinfo->reg_event_lock);
445 val = FIELD_GET(EVENT_COUNTER_LANE_SELECT, val);
446 pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Lane: %d\n", val);
447
448 return simple_read_from_buffer(buf, count, ppos, debugfs_buf, pos);
449 }
450
counter_lane_write(struct file * file,const char __user * buf,size_t count,loff_t * ppos)451 static ssize_t counter_lane_write(struct file *file, const char __user *buf,
452 size_t count, loff_t *ppos)
453 {
454 struct dwc_pcie_rasdes_priv *pdata = file->private_data;
455 struct dw_pcie *pci = pdata->pci;
456 struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
457 u32 val, lane;
458 int ret;
459
460 ret = kstrtou32_from_user(buf, count, 0, &lane);
461 if (ret)
462 return ret;
463
464 mutex_lock(&rinfo->reg_event_lock);
465 set_event_number(pdata, pci, rinfo);
466 val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG);
467 FIELD_MODIFY(EVENT_COUNTER_LANE_SELECT, &val, lane);
468 dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG, val);
469 mutex_unlock(&rinfo->reg_event_lock);
470
471 return count;
472 }
473
counter_value_read(struct file * file,char __user * buf,size_t count,loff_t * ppos)474 static ssize_t counter_value_read(struct file *file, char __user *buf,
475 size_t count, loff_t *ppos)
476 {
477 struct dwc_pcie_rasdes_priv *pdata = file->private_data;
478 struct dw_pcie *pci = pdata->pci;
479 struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
480 char debugfs_buf[DWC_DEBUGFS_BUF_MAX];
481 ssize_t pos;
482 u32 val;
483
484 mutex_lock(&rinfo->reg_event_lock);
485 set_event_number(pdata, pci, rinfo);
486 val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_DATA_REG);
487 mutex_unlock(&rinfo->reg_event_lock);
488 pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Counter value: %d\n", val);
489
490 return simple_read_from_buffer(buf, count, ppos, debugfs_buf, pos);
491 }
492
ltssm_status_show(struct seq_file * s,void * v)493 static int ltssm_status_show(struct seq_file *s, void *v)
494 {
495 struct dw_pcie *pci = s->private;
496 enum dw_pcie_ltssm val;
497
498 val = dw_pcie_get_ltssm(pci);
499 seq_printf(s, "%s (0x%02x)\n", dw_pcie_ltssm_status_string(val), val);
500
501 return 0;
502 }
503
504 #define dwc_debugfs_create(name) \
505 debugfs_create_file(#name, 0644, rasdes_debug, pci, \
506 &dbg_ ## name ## _fops)
507
508 #define DWC_DEBUGFS_FOPS(name) \
509 static const struct file_operations dbg_ ## name ## _fops = { \
510 .open = simple_open, \
511 .read = name ## _read, \
512 .write = name ## _write \
513 }
514
515 DWC_DEBUGFS_FOPS(lane_detect);
516 DWC_DEBUGFS_FOPS(rx_valid);
517
518 static const struct file_operations dwc_pcie_err_inj_ops = {
519 .open = simple_open,
520 .write = err_inj_write,
521 };
522
523 static const struct file_operations dwc_pcie_counter_enable_ops = {
524 .open = simple_open,
525 .read = counter_enable_read,
526 .write = counter_enable_write,
527 };
528
529 static const struct file_operations dwc_pcie_counter_lane_ops = {
530 .open = simple_open,
531 .read = counter_lane_read,
532 .write = counter_lane_write,
533 };
534
535 static const struct file_operations dwc_pcie_counter_value_ops = {
536 .open = simple_open,
537 .read = counter_value_read,
538 };
539
540 DEFINE_SHOW_ATTRIBUTE(ltssm_status);
541
dwc_pcie_rasdes_debugfs_deinit(struct dw_pcie * pci)542 static void dwc_pcie_rasdes_debugfs_deinit(struct dw_pcie *pci)
543 {
544 struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
545
546 if (!rinfo)
547 return;
548
549 mutex_destroy(&rinfo->reg_event_lock);
550 }
551
dwc_pcie_rasdes_debugfs_init(struct dw_pcie * pci,struct dentry * dir)552 static int dwc_pcie_rasdes_debugfs_init(struct dw_pcie *pci, struct dentry *dir)
553 {
554 struct dentry *rasdes_debug, *rasdes_err_inj;
555 struct dentry *rasdes_event_counter, *rasdes_events;
556 struct dwc_pcie_rasdes_info *rasdes_info;
557 struct dwc_pcie_rasdes_priv *priv_tmp;
558 struct device *dev = pci->dev;
559 int ras_cap, i, ret;
560
561 /*
562 * If a given SoC has no RAS DES capability, the following call is
563 * bound to return an error, breaking some existing platforms. So,
564 * return 0 here, as this is not necessarily an error.
565 */
566 ras_cap = dw_pcie_find_rasdes_capability(pci);
567 if (!ras_cap) {
568 dev_dbg(dev, "no RAS DES capability available\n");
569 return 0;
570 }
571
572 rasdes_info = devm_kzalloc(dev, sizeof(*rasdes_info), GFP_KERNEL);
573 if (!rasdes_info)
574 return -ENOMEM;
575
576 /* Create subdirectories for Debug, Error Injection, Statistics. */
577 rasdes_debug = debugfs_create_dir("rasdes_debug", dir);
578 rasdes_err_inj = debugfs_create_dir("rasdes_err_inj", dir);
579 rasdes_event_counter = debugfs_create_dir("rasdes_event_counter", dir);
580
581 mutex_init(&rasdes_info->reg_event_lock);
582 rasdes_info->ras_cap_offset = ras_cap;
583 pci->debugfs->rasdes_info = rasdes_info;
584
585 /* Create debugfs files for Debug subdirectory. */
586 dwc_debugfs_create(lane_detect);
587 dwc_debugfs_create(rx_valid);
588
589 /* Create debugfs files for Error Injection subdirectory. */
590 for (i = 0; i < ARRAY_SIZE(err_inj_list); i++) {
591 priv_tmp = devm_kzalloc(dev, sizeof(*priv_tmp), GFP_KERNEL);
592 if (!priv_tmp) {
593 ret = -ENOMEM;
594 goto err_deinit;
595 }
596
597 priv_tmp->idx = i;
598 priv_tmp->pci = pci;
599 debugfs_create_file(err_inj_list[i].name, 0200, rasdes_err_inj, priv_tmp,
600 &dwc_pcie_err_inj_ops);
601 }
602
603 /* Create debugfs files for Statistical Counter subdirectory. */
604 for (i = 0; i < ARRAY_SIZE(event_list); i++) {
605 priv_tmp = devm_kzalloc(dev, sizeof(*priv_tmp), GFP_KERNEL);
606 if (!priv_tmp) {
607 ret = -ENOMEM;
608 goto err_deinit;
609 }
610
611 priv_tmp->idx = i;
612 priv_tmp->pci = pci;
613 rasdes_events = debugfs_create_dir(event_list[i].name, rasdes_event_counter);
614 if (event_list[i].group_no == 0 || event_list[i].group_no == 4) {
615 debugfs_create_file("lane_select", 0644, rasdes_events,
616 priv_tmp, &dwc_pcie_counter_lane_ops);
617 }
618 debugfs_create_file("counter_value", 0444, rasdes_events, priv_tmp,
619 &dwc_pcie_counter_value_ops);
620 debugfs_create_file("counter_enable", 0644, rasdes_events, priv_tmp,
621 &dwc_pcie_counter_enable_ops);
622 }
623
624 return 0;
625
626 err_deinit:
627 dwc_pcie_rasdes_debugfs_deinit(pci);
628 return ret;
629 }
630
dwc_pcie_ltssm_debugfs_init(struct dw_pcie * pci,struct dentry * dir)631 static void dwc_pcie_ltssm_debugfs_init(struct dw_pcie *pci, struct dentry *dir)
632 {
633 debugfs_create_file("ltssm_status", 0444, dir, pci,
634 <ssm_status_fops);
635 }
636
dw_pcie_ptm_check_capability(void * drvdata)637 static int dw_pcie_ptm_check_capability(void *drvdata)
638 {
639 struct dw_pcie *pci = drvdata;
640
641 pci->ptm_vsec_offset = dw_pcie_find_ptm_capability(pci);
642
643 return pci->ptm_vsec_offset;
644 }
645
dw_pcie_ptm_context_update_write(void * drvdata,u8 mode)646 static int dw_pcie_ptm_context_update_write(void *drvdata, u8 mode)
647 {
648 struct dw_pcie *pci = drvdata;
649 u32 val;
650
651 if (mode == PCIE_PTM_CONTEXT_UPDATE_AUTO) {
652 val = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL);
653 val |= PTM_REQ_AUTO_UPDATE_ENABLED;
654 dw_pcie_writel_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, val);
655 } else if (mode == PCIE_PTM_CONTEXT_UPDATE_MANUAL) {
656 val = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL);
657 val &= ~PTM_REQ_AUTO_UPDATE_ENABLED;
658 val |= PTM_REQ_START_UPDATE;
659 dw_pcie_writel_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, val);
660 } else {
661 return -EINVAL;
662 }
663
664 return 0;
665 }
666
dw_pcie_ptm_context_update_read(void * drvdata,u8 * mode)667 static int dw_pcie_ptm_context_update_read(void *drvdata, u8 *mode)
668 {
669 struct dw_pcie *pci = drvdata;
670 u32 val;
671
672 val = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL);
673 if (FIELD_GET(PTM_REQ_AUTO_UPDATE_ENABLED, val))
674 *mode = PCIE_PTM_CONTEXT_UPDATE_AUTO;
675 else
676 /*
677 * PTM_REQ_START_UPDATE is a self clearing register bit. So if
678 * PTM_REQ_AUTO_UPDATE_ENABLED is not set, then it implies that
679 * manual update is used.
680 */
681 *mode = PCIE_PTM_CONTEXT_UPDATE_MANUAL;
682
683 return 0;
684 }
685
dw_pcie_ptm_context_valid_write(void * drvdata,bool valid)686 static int dw_pcie_ptm_context_valid_write(void *drvdata, bool valid)
687 {
688 struct dw_pcie *pci = drvdata;
689 u32 val;
690
691 if (valid) {
692 val = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL);
693 val |= PTM_RES_CCONTEXT_VALID;
694 dw_pcie_writel_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, val);
695 } else {
696 val = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL);
697 val &= ~PTM_RES_CCONTEXT_VALID;
698 dw_pcie_writel_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, val);
699 }
700
701 return 0;
702 }
703
dw_pcie_ptm_context_valid_read(void * drvdata,bool * valid)704 static int dw_pcie_ptm_context_valid_read(void *drvdata, bool *valid)
705 {
706 struct dw_pcie *pci = drvdata;
707 u32 val;
708
709 val = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL);
710 *valid = !!FIELD_GET(PTM_RES_CCONTEXT_VALID, val);
711
712 return 0;
713 }
714
dw_pcie_ptm_local_clock_read(void * drvdata,u64 * clock)715 static int dw_pcie_ptm_local_clock_read(void *drvdata, u64 *clock)
716 {
717 struct dw_pcie *pci = drvdata;
718 u32 msb, lsb;
719
720 do {
721 msb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_LOCAL_MSB);
722 lsb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_LOCAL_LSB);
723 } while (msb != dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_LOCAL_MSB));
724
725 *clock = ((u64) msb) << 32 | lsb;
726
727 return 0;
728 }
729
dw_pcie_ptm_master_clock_read(void * drvdata,u64 * clock)730 static int dw_pcie_ptm_master_clock_read(void *drvdata, u64 *clock)
731 {
732 struct dw_pcie *pci = drvdata;
733 u32 msb, lsb;
734
735 do {
736 msb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_MASTER_MSB);
737 lsb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_MASTER_LSB);
738 } while (msb != dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_MASTER_MSB));
739
740 *clock = ((u64) msb) << 32 | lsb;
741
742 return 0;
743 }
744
dw_pcie_ptm_t1_read(void * drvdata,u64 * clock)745 static int dw_pcie_ptm_t1_read(void *drvdata, u64 *clock)
746 {
747 struct dw_pcie *pci = drvdata;
748 u32 msb, lsb;
749
750 do {
751 msb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T1_T2_MSB);
752 lsb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T1_T2_LSB);
753 } while (msb != dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T1_T2_MSB));
754
755 *clock = ((u64) msb) << 32 | lsb;
756
757 return 0;
758 }
759
dw_pcie_ptm_t2_read(void * drvdata,u64 * clock)760 static int dw_pcie_ptm_t2_read(void *drvdata, u64 *clock)
761 {
762 struct dw_pcie *pci = drvdata;
763 u32 msb, lsb;
764
765 do {
766 msb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T1_T2_MSB);
767 lsb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T1_T2_LSB);
768 } while (msb != dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T1_T2_MSB));
769
770 *clock = ((u64) msb) << 32 | lsb;
771
772 return 0;
773 }
774
dw_pcie_ptm_t3_read(void * drvdata,u64 * clock)775 static int dw_pcie_ptm_t3_read(void *drvdata, u64 *clock)
776 {
777 struct dw_pcie *pci = drvdata;
778 u32 msb, lsb;
779
780 do {
781 msb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T3_T4_MSB);
782 lsb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T3_T4_LSB);
783 } while (msb != dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T3_T4_MSB));
784
785 *clock = ((u64) msb) << 32 | lsb;
786
787 return 0;
788 }
789
dw_pcie_ptm_t4_read(void * drvdata,u64 * clock)790 static int dw_pcie_ptm_t4_read(void *drvdata, u64 *clock)
791 {
792 struct dw_pcie *pci = drvdata;
793 u32 msb, lsb;
794
795 do {
796 msb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T3_T4_MSB);
797 lsb = dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T3_T4_LSB);
798 } while (msb != dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_T3_T4_MSB));
799
800 *clock = ((u64) msb) << 32 | lsb;
801
802 return 0;
803 }
804
dw_pcie_ptm_context_update_visible(void * drvdata)805 static bool dw_pcie_ptm_context_update_visible(void *drvdata)
806 {
807 struct dw_pcie *pci = drvdata;
808
809 return pci->mode == DW_PCIE_EP_TYPE;
810 }
811
dw_pcie_ptm_context_valid_visible(void * drvdata)812 static bool dw_pcie_ptm_context_valid_visible(void *drvdata)
813 {
814 struct dw_pcie *pci = drvdata;
815
816 return pci->mode == DW_PCIE_RC_TYPE;
817 }
818
dw_pcie_ptm_local_clock_visible(void * drvdata)819 static bool dw_pcie_ptm_local_clock_visible(void *drvdata)
820 {
821 /* PTM local clock is always visible */
822 return true;
823 }
824
dw_pcie_ptm_master_clock_visible(void * drvdata)825 static bool dw_pcie_ptm_master_clock_visible(void *drvdata)
826 {
827 struct dw_pcie *pci = drvdata;
828
829 return pci->mode == DW_PCIE_EP_TYPE;
830 }
831
dw_pcie_ptm_t1_visible(void * drvdata)832 static bool dw_pcie_ptm_t1_visible(void *drvdata)
833 {
834 struct dw_pcie *pci = drvdata;
835
836 return pci->mode == DW_PCIE_EP_TYPE;
837 }
838
dw_pcie_ptm_t2_visible(void * drvdata)839 static bool dw_pcie_ptm_t2_visible(void *drvdata)
840 {
841 struct dw_pcie *pci = drvdata;
842
843 return pci->mode == DW_PCIE_RC_TYPE;
844 }
845
dw_pcie_ptm_t3_visible(void * drvdata)846 static bool dw_pcie_ptm_t3_visible(void *drvdata)
847 {
848 struct dw_pcie *pci = drvdata;
849
850 return pci->mode == DW_PCIE_RC_TYPE;
851 }
852
dw_pcie_ptm_t4_visible(void * drvdata)853 static bool dw_pcie_ptm_t4_visible(void *drvdata)
854 {
855 struct dw_pcie *pci = drvdata;
856
857 return pci->mode == DW_PCIE_EP_TYPE;
858 }
859
860 static const struct pcie_ptm_ops dw_pcie_ptm_ops = {
861 .check_capability = dw_pcie_ptm_check_capability,
862 .context_update_write = dw_pcie_ptm_context_update_write,
863 .context_update_read = dw_pcie_ptm_context_update_read,
864 .context_valid_write = dw_pcie_ptm_context_valid_write,
865 .context_valid_read = dw_pcie_ptm_context_valid_read,
866 .local_clock_read = dw_pcie_ptm_local_clock_read,
867 .master_clock_read = dw_pcie_ptm_master_clock_read,
868 .t1_read = dw_pcie_ptm_t1_read,
869 .t2_read = dw_pcie_ptm_t2_read,
870 .t3_read = dw_pcie_ptm_t3_read,
871 .t4_read = dw_pcie_ptm_t4_read,
872 .context_update_visible = dw_pcie_ptm_context_update_visible,
873 .context_valid_visible = dw_pcie_ptm_context_valid_visible,
874 .local_clock_visible = dw_pcie_ptm_local_clock_visible,
875 .master_clock_visible = dw_pcie_ptm_master_clock_visible,
876 .t1_visible = dw_pcie_ptm_t1_visible,
877 .t2_visible = dw_pcie_ptm_t2_visible,
878 .t3_visible = dw_pcie_ptm_t3_visible,
879 .t4_visible = dw_pcie_ptm_t4_visible,
880 };
881
dwc_pcie_debugfs_deinit(struct dw_pcie * pci)882 void dwc_pcie_debugfs_deinit(struct dw_pcie *pci)
883 {
884 if (!pci->debugfs)
885 return;
886
887 pcie_ptm_destroy_debugfs(pci->ptm_debugfs);
888 dwc_pcie_rasdes_debugfs_deinit(pci);
889 debugfs_remove_recursive(pci->debugfs->debug_dir);
890 }
891
dwc_pcie_debugfs_init(struct dw_pcie * pci,enum dw_pcie_device_mode mode)892 void dwc_pcie_debugfs_init(struct dw_pcie *pci, enum dw_pcie_device_mode mode)
893 {
894 char dirname[DWC_DEBUGFS_BUF_MAX];
895 struct device *dev = pci->dev;
896 struct debugfs_info *debugfs;
897 struct dentry *dir;
898 int err;
899
900 /* Create main directory for each platform driver. */
901 snprintf(dirname, DWC_DEBUGFS_BUF_MAX, "dwc_pcie_%s", dev_name(dev));
902 dir = debugfs_create_dir(dirname, NULL);
903 debugfs = devm_kzalloc(dev, sizeof(*debugfs), GFP_KERNEL);
904 if (!debugfs)
905 return;
906
907 debugfs->debug_dir = dir;
908 pci->debugfs = debugfs;
909 err = dwc_pcie_rasdes_debugfs_init(pci, dir);
910 if (err)
911 dev_err(dev, "failed to initialize RAS DES debugfs, err=%d\n",
912 err);
913
914 dwc_pcie_ltssm_debugfs_init(pci, dir);
915
916 pci->mode = mode;
917 pci->ptm_debugfs = pcie_ptm_create_debugfs(pci->dev, pci,
918 &dw_pcie_ptm_ops);
919 }
920