1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * max98095.c -- MAX98095 ALSA SoC Audio driver
4 *
5 * Copyright 2011 Maxim Integrated Products
6 */
7
8 #include <linux/cleanup.h>
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/delay.h>
14 #include <linux/pm.h>
15 #include <linux/i2c.h>
16 #include <linux/clk.h>
17 #include <linux/mutex.h>
18 #include <sound/core.h>
19 #include <sound/pcm.h>
20 #include <sound/pcm_params.h>
21 #include <sound/soc.h>
22 #include <sound/initval.h>
23 #include <sound/tlv.h>
24 #include <linux/slab.h>
25 #include <asm/div64.h>
26 #include <sound/max98095.h>
27 #include <sound/jack.h>
28 #include "max98095.h"
29
30 enum max98095_type {
31 MAX98095,
32 };
33
34 struct max98095_cdata {
35 unsigned int rate;
36 unsigned int fmt;
37 int eq_sel;
38 int bq_sel;
39 };
40
41 struct max98095_priv {
42 struct regmap *regmap;
43 enum max98095_type devtype;
44 struct max98095_pdata *pdata;
45 struct clk *mclk;
46 unsigned int sysclk;
47 struct max98095_cdata dai[3];
48 const char **eq_texts;
49 const char **bq_texts;
50 struct soc_enum eq_enum;
51 struct soc_enum bq_enum;
52 int eq_textcnt;
53 int bq_textcnt;
54 u8 lin_state;
55 unsigned int mic1pre;
56 unsigned int mic2pre;
57 struct snd_soc_jack *headphone_jack;
58 struct snd_soc_jack *mic_jack;
59 struct mutex lock;
60 };
61
62 static const struct reg_default max98095_reg_def[] = {
63 { 0xf, 0x00 }, /* 0F */
64 { 0x10, 0x00 }, /* 10 */
65 { 0x11, 0x00 }, /* 11 */
66 { 0x12, 0x00 }, /* 12 */
67 { 0x13, 0x00 }, /* 13 */
68 { 0x14, 0x00 }, /* 14 */
69 { 0x15, 0x00 }, /* 15 */
70 { 0x16, 0x00 }, /* 16 */
71 { 0x17, 0x00 }, /* 17 */
72 { 0x18, 0x00 }, /* 18 */
73 { 0x19, 0x00 }, /* 19 */
74 { 0x1a, 0x00 }, /* 1A */
75 { 0x1b, 0x00 }, /* 1B */
76 { 0x1c, 0x00 }, /* 1C */
77 { 0x1d, 0x00 }, /* 1D */
78 { 0x1e, 0x00 }, /* 1E */
79 { 0x1f, 0x00 }, /* 1F */
80 { 0x20, 0x00 }, /* 20 */
81 { 0x21, 0x00 }, /* 21 */
82 { 0x22, 0x00 }, /* 22 */
83 { 0x23, 0x00 }, /* 23 */
84 { 0x24, 0x00 }, /* 24 */
85 { 0x25, 0x00 }, /* 25 */
86 { 0x26, 0x00 }, /* 26 */
87 { 0x27, 0x00 }, /* 27 */
88 { 0x28, 0x00 }, /* 28 */
89 { 0x29, 0x00 }, /* 29 */
90 { 0x2a, 0x00 }, /* 2A */
91 { 0x2b, 0x00 }, /* 2B */
92 { 0x2c, 0x00 }, /* 2C */
93 { 0x2d, 0x00 }, /* 2D */
94 { 0x2e, 0x00 }, /* 2E */
95 { 0x2f, 0x00 }, /* 2F */
96 { 0x30, 0x00 }, /* 30 */
97 { 0x31, 0x00 }, /* 31 */
98 { 0x32, 0x00 }, /* 32 */
99 { 0x33, 0x00 }, /* 33 */
100 { 0x34, 0x00 }, /* 34 */
101 { 0x35, 0x00 }, /* 35 */
102 { 0x36, 0x00 }, /* 36 */
103 { 0x37, 0x00 }, /* 37 */
104 { 0x38, 0x00 }, /* 38 */
105 { 0x39, 0x00 }, /* 39 */
106 { 0x3a, 0x00 }, /* 3A */
107 { 0x3b, 0x00 }, /* 3B */
108 { 0x3c, 0x00 }, /* 3C */
109 { 0x3d, 0x00 }, /* 3D */
110 { 0x3e, 0x00 }, /* 3E */
111 { 0x3f, 0x00 }, /* 3F */
112 { 0x40, 0x00 }, /* 40 */
113 { 0x41, 0x00 }, /* 41 */
114 { 0x42, 0x00 }, /* 42 */
115 { 0x43, 0x00 }, /* 43 */
116 { 0x44, 0x00 }, /* 44 */
117 { 0x45, 0x00 }, /* 45 */
118 { 0x46, 0x00 }, /* 46 */
119 { 0x47, 0x00 }, /* 47 */
120 { 0x48, 0x00 }, /* 48 */
121 { 0x49, 0x00 }, /* 49 */
122 { 0x4a, 0x00 }, /* 4A */
123 { 0x4b, 0x00 }, /* 4B */
124 { 0x4c, 0x00 }, /* 4C */
125 { 0x4d, 0x00 }, /* 4D */
126 { 0x4e, 0x00 }, /* 4E */
127 { 0x4f, 0x00 }, /* 4F */
128 { 0x50, 0x00 }, /* 50 */
129 { 0x51, 0x00 }, /* 51 */
130 { 0x52, 0x00 }, /* 52 */
131 { 0x53, 0x00 }, /* 53 */
132 { 0x54, 0x00 }, /* 54 */
133 { 0x55, 0x00 }, /* 55 */
134 { 0x56, 0x00 }, /* 56 */
135 { 0x57, 0x00 }, /* 57 */
136 { 0x58, 0x00 }, /* 58 */
137 { 0x59, 0x00 }, /* 59 */
138 { 0x5a, 0x00 }, /* 5A */
139 { 0x5b, 0x00 }, /* 5B */
140 { 0x5c, 0x00 }, /* 5C */
141 { 0x5d, 0x00 }, /* 5D */
142 { 0x5e, 0x00 }, /* 5E */
143 { 0x5f, 0x00 }, /* 5F */
144 { 0x60, 0x00 }, /* 60 */
145 { 0x61, 0x00 }, /* 61 */
146 { 0x62, 0x00 }, /* 62 */
147 { 0x63, 0x00 }, /* 63 */
148 { 0x64, 0x00 }, /* 64 */
149 { 0x65, 0x00 }, /* 65 */
150 { 0x66, 0x00 }, /* 66 */
151 { 0x67, 0x00 }, /* 67 */
152 { 0x68, 0x00 }, /* 68 */
153 { 0x69, 0x00 }, /* 69 */
154 { 0x6a, 0x00 }, /* 6A */
155 { 0x6b, 0x00 }, /* 6B */
156 { 0x6c, 0x00 }, /* 6C */
157 { 0x6d, 0x00 }, /* 6D */
158 { 0x6e, 0x00 }, /* 6E */
159 { 0x6f, 0x00 }, /* 6F */
160 { 0x70, 0x00 }, /* 70 */
161 { 0x71, 0x00 }, /* 71 */
162 { 0x72, 0x00 }, /* 72 */
163 { 0x73, 0x00 }, /* 73 */
164 { 0x74, 0x00 }, /* 74 */
165 { 0x75, 0x00 }, /* 75 */
166 { 0x76, 0x00 }, /* 76 */
167 { 0x77, 0x00 }, /* 77 */
168 { 0x78, 0x00 }, /* 78 */
169 { 0x79, 0x00 }, /* 79 */
170 { 0x7a, 0x00 }, /* 7A */
171 { 0x7b, 0x00 }, /* 7B */
172 { 0x7c, 0x00 }, /* 7C */
173 { 0x7d, 0x00 }, /* 7D */
174 { 0x7e, 0x00 }, /* 7E */
175 { 0x7f, 0x00 }, /* 7F */
176 { 0x80, 0x00 }, /* 80 */
177 { 0x81, 0x00 }, /* 81 */
178 { 0x82, 0x00 }, /* 82 */
179 { 0x83, 0x00 }, /* 83 */
180 { 0x84, 0x00 }, /* 84 */
181 { 0x85, 0x00 }, /* 85 */
182 { 0x86, 0x00 }, /* 86 */
183 { 0x87, 0x00 }, /* 87 */
184 { 0x88, 0x00 }, /* 88 */
185 { 0x89, 0x00 }, /* 89 */
186 { 0x8a, 0x00 }, /* 8A */
187 { 0x8b, 0x00 }, /* 8B */
188 { 0x8c, 0x00 }, /* 8C */
189 { 0x8d, 0x00 }, /* 8D */
190 { 0x8e, 0x00 }, /* 8E */
191 { 0x8f, 0x00 }, /* 8F */
192 { 0x90, 0x00 }, /* 90 */
193 { 0x91, 0x00 }, /* 91 */
194 { 0x92, 0x30 }, /* 92 */
195 { 0x93, 0xF0 }, /* 93 */
196 { 0x94, 0x00 }, /* 94 */
197 { 0x95, 0x00 }, /* 95 */
198 { 0x96, 0x3F }, /* 96 */
199 { 0x97, 0x00 }, /* 97 */
200 { 0xff, 0x00 }, /* FF */
201 };
202
max98095_readable(struct device * dev,unsigned int reg)203 static bool max98095_readable(struct device *dev, unsigned int reg)
204 {
205 switch (reg) {
206 case M98095_001_HOST_INT_STS ... M98095_097_PWR_SYS:
207 case M98095_0FF_REV_ID:
208 return true;
209 default:
210 return false;
211 }
212 }
213
max98095_writeable(struct device * dev,unsigned int reg)214 static bool max98095_writeable(struct device *dev, unsigned int reg)
215 {
216 switch (reg) {
217 case M98095_00F_HOST_CFG ... M98095_097_PWR_SYS:
218 return true;
219 default:
220 return false;
221 }
222 }
223
max98095_volatile(struct device * dev,unsigned int reg)224 static bool max98095_volatile(struct device *dev, unsigned int reg)
225 {
226 switch (reg) {
227 case M98095_000_HOST_DATA ... M98095_00E_TEMP_SENSOR_STS:
228 case M98095_REG_MAX_CACHED + 1 ... M98095_0FF_REV_ID:
229 return true;
230 default:
231 return false;
232 }
233 }
234
235 static const struct regmap_config max98095_regmap = {
236 .reg_bits = 8,
237 .val_bits = 8,
238
239 .reg_defaults = max98095_reg_def,
240 .num_reg_defaults = ARRAY_SIZE(max98095_reg_def),
241 .max_register = M98095_0FF_REV_ID,
242 .cache_type = REGCACHE_RBTREE,
243
244 .readable_reg = max98095_readable,
245 .writeable_reg = max98095_writeable,
246 .volatile_reg = max98095_volatile,
247 };
248
249 /*
250 * Load equalizer DSP coefficient configurations registers
251 */
m98095_eq_band(struct snd_soc_component * component,unsigned int dai,unsigned int band,u16 * coefs)252 static void m98095_eq_band(struct snd_soc_component *component, unsigned int dai,
253 unsigned int band, u16 *coefs)
254 {
255 unsigned int eq_reg;
256 unsigned int i;
257
258 if (WARN_ON(band > 4) ||
259 WARN_ON(dai > 1))
260 return;
261
262 /* Load the base register address */
263 eq_reg = dai ? M98095_142_DAI2_EQ_BASE : M98095_110_DAI1_EQ_BASE;
264
265 /* Add the band address offset, note adjustment for word address */
266 eq_reg += band * (M98095_COEFS_PER_BAND << 1);
267
268 /* Step through the registers and coefs */
269 for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
270 snd_soc_component_write(component, eq_reg++, M98095_BYTE1(coefs[i]));
271 snd_soc_component_write(component, eq_reg++, M98095_BYTE0(coefs[i]));
272 }
273 }
274
275 /*
276 * Load biquad filter coefficient configurations registers
277 */
m98095_biquad_band(struct snd_soc_component * component,unsigned int dai,unsigned int band,u16 * coefs)278 static void m98095_biquad_band(struct snd_soc_component *component, unsigned int dai,
279 unsigned int band, u16 *coefs)
280 {
281 unsigned int bq_reg;
282 unsigned int i;
283
284 if (WARN_ON(band > 1) ||
285 WARN_ON(dai > 1))
286 return;
287
288 /* Load the base register address */
289 bq_reg = dai ? M98095_17E_DAI2_BQ_BASE : M98095_174_DAI1_BQ_BASE;
290
291 /* Add the band address offset, note adjustment for word address */
292 bq_reg += band * (M98095_COEFS_PER_BAND << 1);
293
294 /* Step through the registers and coefs */
295 for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
296 snd_soc_component_write(component, bq_reg++, M98095_BYTE1(coefs[i]));
297 snd_soc_component_write(component, bq_reg++, M98095_BYTE0(coefs[i]));
298 }
299 }
300
301 static const char * const max98095_fltr_mode[] = { "Voice", "Music" };
302 static SOC_ENUM_SINGLE_DECL(max98095_dai1_filter_mode_enum,
303 M98095_02E_DAI1_FILTERS, 7,
304 max98095_fltr_mode);
305 static SOC_ENUM_SINGLE_DECL(max98095_dai2_filter_mode_enum,
306 M98095_038_DAI2_FILTERS, 7,
307 max98095_fltr_mode);
308
309 static const char * const max98095_extmic_text[] = { "None", "MIC1", "MIC2" };
310
311 static SOC_ENUM_SINGLE_DECL(max98095_extmic_enum,
312 M98095_087_CFG_MIC, 0,
313 max98095_extmic_text);
314
315 static const struct snd_kcontrol_new max98095_extmic_mux =
316 SOC_DAPM_ENUM("External MIC Mux", max98095_extmic_enum);
317
318 static const char * const max98095_linein_text[] = { "INA", "INB" };
319
320 static SOC_ENUM_SINGLE_DECL(max98095_linein_enum,
321 M98095_086_CFG_LINE, 6,
322 max98095_linein_text);
323
324 static const struct snd_kcontrol_new max98095_linein_mux =
325 SOC_DAPM_ENUM("Linein Input Mux", max98095_linein_enum);
326
327 static const char * const max98095_line_mode_text[] = {
328 "Stereo", "Differential"};
329
330 static SOC_ENUM_SINGLE_DECL(max98095_linein_mode_enum,
331 M98095_086_CFG_LINE, 7,
332 max98095_line_mode_text);
333
334 static SOC_ENUM_SINGLE_DECL(max98095_lineout_mode_enum,
335 M98095_086_CFG_LINE, 4,
336 max98095_line_mode_text);
337
338 static const char * const max98095_dai_fltr[] = {
339 "Off", "Elliptical-HPF-16k", "Butterworth-HPF-16k",
340 "Elliptical-HPF-8k", "Butterworth-HPF-8k", "Butterworth-HPF-Fs/240"};
341 static SOC_ENUM_SINGLE_DECL(max98095_dai1_dac_filter_enum,
342 M98095_02E_DAI1_FILTERS, 0,
343 max98095_dai_fltr);
344 static SOC_ENUM_SINGLE_DECL(max98095_dai2_dac_filter_enum,
345 M98095_038_DAI2_FILTERS, 0,
346 max98095_dai_fltr);
347 static SOC_ENUM_SINGLE_DECL(max98095_dai3_dac_filter_enum,
348 M98095_042_DAI3_FILTERS, 0,
349 max98095_dai_fltr);
350
max98095_mic1pre_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)351 static int max98095_mic1pre_set(struct snd_kcontrol *kcontrol,
352 struct snd_ctl_elem_value *ucontrol)
353 {
354 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
355 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
356 unsigned int sel = ucontrol->value.integer.value[0];
357
358 max98095->mic1pre = sel;
359 snd_soc_component_update_bits(component, M98095_05F_LVL_MIC1, M98095_MICPRE_MASK,
360 (1+sel)<<M98095_MICPRE_SHIFT);
361
362 return 0;
363 }
364
max98095_mic1pre_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)365 static int max98095_mic1pre_get(struct snd_kcontrol *kcontrol,
366 struct snd_ctl_elem_value *ucontrol)
367 {
368 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
369 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
370
371 ucontrol->value.integer.value[0] = max98095->mic1pre;
372 return 0;
373 }
374
max98095_mic2pre_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)375 static int max98095_mic2pre_set(struct snd_kcontrol *kcontrol,
376 struct snd_ctl_elem_value *ucontrol)
377 {
378 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
379 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
380 unsigned int sel = ucontrol->value.integer.value[0];
381
382 max98095->mic2pre = sel;
383 snd_soc_component_update_bits(component, M98095_060_LVL_MIC2, M98095_MICPRE_MASK,
384 (1+sel)<<M98095_MICPRE_SHIFT);
385
386 return 0;
387 }
388
max98095_mic2pre_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)389 static int max98095_mic2pre_get(struct snd_kcontrol *kcontrol,
390 struct snd_ctl_elem_value *ucontrol)
391 {
392 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
393 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
394
395 ucontrol->value.integer.value[0] = max98095->mic2pre;
396 return 0;
397 }
398
399 static const DECLARE_TLV_DB_RANGE(max98095_micboost_tlv,
400 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
401 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0)
402 );
403
404 static const DECLARE_TLV_DB_SCALE(max98095_mic_tlv, 0, 100, 0);
405 static const DECLARE_TLV_DB_SCALE(max98095_adc_tlv, -1200, 100, 0);
406 static const DECLARE_TLV_DB_SCALE(max98095_adcboost_tlv, 0, 600, 0);
407
408 static const DECLARE_TLV_DB_RANGE(max98095_hp_tlv,
409 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
410 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
411 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
412 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
413 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0)
414 );
415
416 static const DECLARE_TLV_DB_RANGE(max98095_spk_tlv,
417 0, 10, TLV_DB_SCALE_ITEM(-5900, 400, 0),
418 11, 18, TLV_DB_SCALE_ITEM(-1700, 200, 0),
419 19, 27, TLV_DB_SCALE_ITEM(-200, 100, 0),
420 28, 39, TLV_DB_SCALE_ITEM(650, 50, 0)
421 );
422
423 static const DECLARE_TLV_DB_RANGE(max98095_rcv_lout_tlv,
424 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
425 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
426 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
427 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
428 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0)
429 );
430
431 static const DECLARE_TLV_DB_RANGE(max98095_lin_tlv,
432 0, 2, TLV_DB_SCALE_ITEM(-600, 300, 0),
433 3, 3, TLV_DB_SCALE_ITEM(300, 1100, 0),
434 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0)
435 );
436
437 static const struct snd_kcontrol_new max98095_snd_controls[] = {
438
439 SOC_DOUBLE_R_TLV("Headphone Volume", M98095_064_LVL_HP_L,
440 M98095_065_LVL_HP_R, 0, 31, 0, max98095_hp_tlv),
441
442 SOC_DOUBLE_R_TLV("Speaker Volume", M98095_067_LVL_SPK_L,
443 M98095_068_LVL_SPK_R, 0, 39, 0, max98095_spk_tlv),
444
445 SOC_SINGLE_TLV("Receiver Volume", M98095_066_LVL_RCV,
446 0, 31, 0, max98095_rcv_lout_tlv),
447
448 SOC_DOUBLE_R_TLV("Lineout Volume", M98095_062_LVL_LINEOUT1,
449 M98095_063_LVL_LINEOUT2, 0, 31, 0, max98095_rcv_lout_tlv),
450
451 SOC_DOUBLE_R("Headphone Switch", M98095_064_LVL_HP_L,
452 M98095_065_LVL_HP_R, 7, 1, 1),
453
454 SOC_DOUBLE_R("Speaker Switch", M98095_067_LVL_SPK_L,
455 M98095_068_LVL_SPK_R, 7, 1, 1),
456
457 SOC_SINGLE("Receiver Switch", M98095_066_LVL_RCV, 7, 1, 1),
458
459 SOC_DOUBLE_R("Lineout Switch", M98095_062_LVL_LINEOUT1,
460 M98095_063_LVL_LINEOUT2, 7, 1, 1),
461
462 SOC_SINGLE_TLV("MIC1 Volume", M98095_05F_LVL_MIC1, 0, 20, 1,
463 max98095_mic_tlv),
464
465 SOC_SINGLE_TLV("MIC2 Volume", M98095_060_LVL_MIC2, 0, 20, 1,
466 max98095_mic_tlv),
467
468 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
469 M98095_05F_LVL_MIC1, 5, 2, 0,
470 max98095_mic1pre_get, max98095_mic1pre_set,
471 max98095_micboost_tlv),
472 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
473 M98095_060_LVL_MIC2, 5, 2, 0,
474 max98095_mic2pre_get, max98095_mic2pre_set,
475 max98095_micboost_tlv),
476
477 SOC_SINGLE_TLV("Linein Volume", M98095_061_LVL_LINEIN, 0, 5, 1,
478 max98095_lin_tlv),
479
480 SOC_SINGLE_TLV("ADCL Volume", M98095_05D_LVL_ADC_L, 0, 15, 1,
481 max98095_adc_tlv),
482 SOC_SINGLE_TLV("ADCR Volume", M98095_05E_LVL_ADC_R, 0, 15, 1,
483 max98095_adc_tlv),
484
485 SOC_SINGLE_TLV("ADCL Boost Volume", M98095_05D_LVL_ADC_L, 4, 3, 0,
486 max98095_adcboost_tlv),
487 SOC_SINGLE_TLV("ADCR Boost Volume", M98095_05E_LVL_ADC_R, 4, 3, 0,
488 max98095_adcboost_tlv),
489
490 SOC_SINGLE("EQ1 Switch", M98095_088_CFG_LEVEL, 0, 1, 0),
491 SOC_SINGLE("EQ2 Switch", M98095_088_CFG_LEVEL, 1, 1, 0),
492
493 SOC_SINGLE("Biquad1 Switch", M98095_088_CFG_LEVEL, 2, 1, 0),
494 SOC_SINGLE("Biquad2 Switch", M98095_088_CFG_LEVEL, 3, 1, 0),
495
496 SOC_ENUM("DAI1 Filter Mode", max98095_dai1_filter_mode_enum),
497 SOC_ENUM("DAI2 Filter Mode", max98095_dai2_filter_mode_enum),
498 SOC_ENUM("DAI1 DAC Filter", max98095_dai1_dac_filter_enum),
499 SOC_ENUM("DAI2 DAC Filter", max98095_dai2_dac_filter_enum),
500 SOC_ENUM("DAI3 DAC Filter", max98095_dai3_dac_filter_enum),
501
502 SOC_ENUM("Linein Mode", max98095_linein_mode_enum),
503 SOC_ENUM("Lineout Mode", max98095_lineout_mode_enum),
504 };
505
506 /* Left speaker mixer switch */
507 static const struct snd_kcontrol_new max98095_left_speaker_mixer_controls[] = {
508 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_050_MIX_SPK_LEFT, 0, 1, 0),
509 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_050_MIX_SPK_LEFT, 6, 1, 0),
510 SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0),
511 SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0),
512 SOC_DAPM_SINGLE("MIC1 Switch", M98095_050_MIX_SPK_LEFT, 4, 1, 0),
513 SOC_DAPM_SINGLE("MIC2 Switch", M98095_050_MIX_SPK_LEFT, 5, 1, 0),
514 SOC_DAPM_SINGLE("IN1 Switch", M98095_050_MIX_SPK_LEFT, 1, 1, 0),
515 SOC_DAPM_SINGLE("IN2 Switch", M98095_050_MIX_SPK_LEFT, 2, 1, 0),
516 };
517
518 /* Right speaker mixer switch */
519 static const struct snd_kcontrol_new max98095_right_speaker_mixer_controls[] = {
520 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 6, 1, 0),
521 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 0, 1, 0),
522 SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0),
523 SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0),
524 SOC_DAPM_SINGLE("MIC1 Switch", M98095_051_MIX_SPK_RIGHT, 5, 1, 0),
525 SOC_DAPM_SINGLE("MIC2 Switch", M98095_051_MIX_SPK_RIGHT, 4, 1, 0),
526 SOC_DAPM_SINGLE("IN1 Switch", M98095_051_MIX_SPK_RIGHT, 1, 1, 0),
527 SOC_DAPM_SINGLE("IN2 Switch", M98095_051_MIX_SPK_RIGHT, 2, 1, 0),
528 };
529
530 /* Left headphone mixer switch */
531 static const struct snd_kcontrol_new max98095_left_hp_mixer_controls[] = {
532 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04C_MIX_HP_LEFT, 0, 1, 0),
533 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04C_MIX_HP_LEFT, 5, 1, 0),
534 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04C_MIX_HP_LEFT, 3, 1, 0),
535 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04C_MIX_HP_LEFT, 4, 1, 0),
536 SOC_DAPM_SINGLE("IN1 Switch", M98095_04C_MIX_HP_LEFT, 1, 1, 0),
537 SOC_DAPM_SINGLE("IN2 Switch", M98095_04C_MIX_HP_LEFT, 2, 1, 0),
538 };
539
540 /* Right headphone mixer switch */
541 static const struct snd_kcontrol_new max98095_right_hp_mixer_controls[] = {
542 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 5, 1, 0),
543 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 0, 1, 0),
544 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04D_MIX_HP_RIGHT, 3, 1, 0),
545 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04D_MIX_HP_RIGHT, 4, 1, 0),
546 SOC_DAPM_SINGLE("IN1 Switch", M98095_04D_MIX_HP_RIGHT, 1, 1, 0),
547 SOC_DAPM_SINGLE("IN2 Switch", M98095_04D_MIX_HP_RIGHT, 2, 1, 0),
548 };
549
550 /* Receiver earpiece mixer switch */
551 static const struct snd_kcontrol_new max98095_mono_rcv_mixer_controls[] = {
552 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04F_MIX_RCV, 0, 1, 0),
553 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04F_MIX_RCV, 5, 1, 0),
554 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04F_MIX_RCV, 3, 1, 0),
555 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04F_MIX_RCV, 4, 1, 0),
556 SOC_DAPM_SINGLE("IN1 Switch", M98095_04F_MIX_RCV, 1, 1, 0),
557 SOC_DAPM_SINGLE("IN2 Switch", M98095_04F_MIX_RCV, 2, 1, 0),
558 };
559
560 /* Left lineout mixer switch */
561 static const struct snd_kcontrol_new max98095_left_lineout_mixer_controls[] = {
562 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_053_MIX_LINEOUT1, 5, 1, 0),
563 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_053_MIX_LINEOUT1, 0, 1, 0),
564 SOC_DAPM_SINGLE("MIC1 Switch", M98095_053_MIX_LINEOUT1, 3, 1, 0),
565 SOC_DAPM_SINGLE("MIC2 Switch", M98095_053_MIX_LINEOUT1, 4, 1, 0),
566 SOC_DAPM_SINGLE("IN1 Switch", M98095_053_MIX_LINEOUT1, 1, 1, 0),
567 SOC_DAPM_SINGLE("IN2 Switch", M98095_053_MIX_LINEOUT1, 2, 1, 0),
568 };
569
570 /* Right lineout mixer switch */
571 static const struct snd_kcontrol_new max98095_right_lineout_mixer_controls[] = {
572 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_054_MIX_LINEOUT2, 0, 1, 0),
573 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_054_MIX_LINEOUT2, 5, 1, 0),
574 SOC_DAPM_SINGLE("MIC1 Switch", M98095_054_MIX_LINEOUT2, 3, 1, 0),
575 SOC_DAPM_SINGLE("MIC2 Switch", M98095_054_MIX_LINEOUT2, 4, 1, 0),
576 SOC_DAPM_SINGLE("IN1 Switch", M98095_054_MIX_LINEOUT2, 1, 1, 0),
577 SOC_DAPM_SINGLE("IN2 Switch", M98095_054_MIX_LINEOUT2, 2, 1, 0),
578 };
579
580 /* Left ADC mixer switch */
581 static const struct snd_kcontrol_new max98095_left_ADC_mixer_controls[] = {
582 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04A_MIX_ADC_LEFT, 7, 1, 0),
583 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04A_MIX_ADC_LEFT, 6, 1, 0),
584 SOC_DAPM_SINGLE("IN1 Switch", M98095_04A_MIX_ADC_LEFT, 3, 1, 0),
585 SOC_DAPM_SINGLE("IN2 Switch", M98095_04A_MIX_ADC_LEFT, 2, 1, 0),
586 };
587
588 /* Right ADC mixer switch */
589 static const struct snd_kcontrol_new max98095_right_ADC_mixer_controls[] = {
590 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04B_MIX_ADC_RIGHT, 7, 1, 0),
591 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04B_MIX_ADC_RIGHT, 6, 1, 0),
592 SOC_DAPM_SINGLE("IN1 Switch", M98095_04B_MIX_ADC_RIGHT, 3, 1, 0),
593 SOC_DAPM_SINGLE("IN2 Switch", M98095_04B_MIX_ADC_RIGHT, 2, 1, 0),
594 };
595
max98095_mic_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)596 static int max98095_mic_event(struct snd_soc_dapm_widget *w,
597 struct snd_kcontrol *kcontrol, int event)
598 {
599 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
600 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
601
602 switch (event) {
603 case SND_SOC_DAPM_POST_PMU:
604 if (w->reg == M98095_05F_LVL_MIC1) {
605 snd_soc_component_update_bits(component, w->reg, M98095_MICPRE_MASK,
606 (1+max98095->mic1pre)<<M98095_MICPRE_SHIFT);
607 } else {
608 snd_soc_component_update_bits(component, w->reg, M98095_MICPRE_MASK,
609 (1+max98095->mic2pre)<<M98095_MICPRE_SHIFT);
610 }
611 break;
612 case SND_SOC_DAPM_POST_PMD:
613 snd_soc_component_update_bits(component, w->reg, M98095_MICPRE_MASK, 0);
614 break;
615 default:
616 return -EINVAL;
617 }
618
619 return 0;
620 }
621
622 /*
623 * The line inputs are stereo inputs with the left and right
624 * channels sharing a common PGA power control signal.
625 */
max98095_line_pga(struct snd_soc_dapm_widget * w,int event,u8 channel)626 static int max98095_line_pga(struct snd_soc_dapm_widget *w,
627 int event, u8 channel)
628 {
629 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
630 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
631 u8 *state;
632
633 if (WARN_ON(!(channel == 1 || channel == 2)))
634 return -EINVAL;
635
636 state = &max98095->lin_state;
637
638 switch (event) {
639 case SND_SOC_DAPM_POST_PMU:
640 *state |= channel;
641 snd_soc_component_update_bits(component, w->reg,
642 (1 << w->shift), (1 << w->shift));
643 break;
644 case SND_SOC_DAPM_POST_PMD:
645 *state &= ~channel;
646 if (*state == 0) {
647 snd_soc_component_update_bits(component, w->reg,
648 (1 << w->shift), 0);
649 }
650 break;
651 default:
652 return -EINVAL;
653 }
654
655 return 0;
656 }
657
max98095_pga_in1_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * k,int event)658 static int max98095_pga_in1_event(struct snd_soc_dapm_widget *w,
659 struct snd_kcontrol *k, int event)
660 {
661 return max98095_line_pga(w, event, 1);
662 }
663
max98095_pga_in2_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * k,int event)664 static int max98095_pga_in2_event(struct snd_soc_dapm_widget *w,
665 struct snd_kcontrol *k, int event)
666 {
667 return max98095_line_pga(w, event, 2);
668 }
669
670 /*
671 * The stereo line out mixer outputs to two stereo line outs.
672 * The 2nd pair has a separate set of enables.
673 */
max98095_lineout_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)674 static int max98095_lineout_event(struct snd_soc_dapm_widget *w,
675 struct snd_kcontrol *kcontrol, int event)
676 {
677 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
678
679 switch (event) {
680 case SND_SOC_DAPM_POST_PMU:
681 snd_soc_component_update_bits(component, w->reg,
682 (1 << (w->shift+2)), (1 << (w->shift+2)));
683 break;
684 case SND_SOC_DAPM_POST_PMD:
685 snd_soc_component_update_bits(component, w->reg,
686 (1 << (w->shift+2)), 0);
687 break;
688 default:
689 return -EINVAL;
690 }
691
692 return 0;
693 }
694
695 static const struct snd_soc_dapm_widget max98095_dapm_widgets[] = {
696
697 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98095_090_PWR_EN_IN, 0, 0),
698 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98095_090_PWR_EN_IN, 1, 0),
699
700 SND_SOC_DAPM_DAC("DACL1", "HiFi Playback",
701 M98095_091_PWR_EN_OUT, 0, 0),
702 SND_SOC_DAPM_DAC("DACR1", "HiFi Playback",
703 M98095_091_PWR_EN_OUT, 1, 0),
704 SND_SOC_DAPM_DAC("DACM2", "Aux Playback",
705 M98095_091_PWR_EN_OUT, 2, 0),
706 SND_SOC_DAPM_DAC("DACM3", "Voice Playback",
707 M98095_091_PWR_EN_OUT, 2, 0),
708
709 SND_SOC_DAPM_PGA("HP Left Out", M98095_091_PWR_EN_OUT,
710 6, 0, NULL, 0),
711 SND_SOC_DAPM_PGA("HP Right Out", M98095_091_PWR_EN_OUT,
712 7, 0, NULL, 0),
713
714 SND_SOC_DAPM_PGA("SPK Left Out", M98095_091_PWR_EN_OUT,
715 4, 0, NULL, 0),
716 SND_SOC_DAPM_PGA("SPK Right Out", M98095_091_PWR_EN_OUT,
717 5, 0, NULL, 0),
718
719 SND_SOC_DAPM_PGA("RCV Mono Out", M98095_091_PWR_EN_OUT,
720 3, 0, NULL, 0),
721
722 SND_SOC_DAPM_PGA_E("LINE Left Out", M98095_092_PWR_EN_OUT,
723 0, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD),
724 SND_SOC_DAPM_PGA_E("LINE Right Out", M98095_092_PWR_EN_OUT,
725 1, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD),
726
727 SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0,
728 &max98095_extmic_mux),
729
730 SND_SOC_DAPM_MUX("Linein Mux", SND_SOC_NOPM, 0, 0,
731 &max98095_linein_mux),
732
733 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
734 &max98095_left_hp_mixer_controls[0],
735 ARRAY_SIZE(max98095_left_hp_mixer_controls)),
736
737 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
738 &max98095_right_hp_mixer_controls[0],
739 ARRAY_SIZE(max98095_right_hp_mixer_controls)),
740
741 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
742 &max98095_left_speaker_mixer_controls[0],
743 ARRAY_SIZE(max98095_left_speaker_mixer_controls)),
744
745 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
746 &max98095_right_speaker_mixer_controls[0],
747 ARRAY_SIZE(max98095_right_speaker_mixer_controls)),
748
749 SND_SOC_DAPM_MIXER("Receiver Mixer", SND_SOC_NOPM, 0, 0,
750 &max98095_mono_rcv_mixer_controls[0],
751 ARRAY_SIZE(max98095_mono_rcv_mixer_controls)),
752
753 SND_SOC_DAPM_MIXER("Left Lineout Mixer", SND_SOC_NOPM, 0, 0,
754 &max98095_left_lineout_mixer_controls[0],
755 ARRAY_SIZE(max98095_left_lineout_mixer_controls)),
756
757 SND_SOC_DAPM_MIXER("Right Lineout Mixer", SND_SOC_NOPM, 0, 0,
758 &max98095_right_lineout_mixer_controls[0],
759 ARRAY_SIZE(max98095_right_lineout_mixer_controls)),
760
761 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
762 &max98095_left_ADC_mixer_controls[0],
763 ARRAY_SIZE(max98095_left_ADC_mixer_controls)),
764
765 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
766 &max98095_right_ADC_mixer_controls[0],
767 ARRAY_SIZE(max98095_right_ADC_mixer_controls)),
768
769 SND_SOC_DAPM_PGA_E("MIC1 Input", M98095_05F_LVL_MIC1,
770 5, 0, NULL, 0, max98095_mic_event,
771 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
772
773 SND_SOC_DAPM_PGA_E("MIC2 Input", M98095_060_LVL_MIC2,
774 5, 0, NULL, 0, max98095_mic_event,
775 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
776
777 SND_SOC_DAPM_PGA_E("IN1 Input", M98095_090_PWR_EN_IN,
778 7, 0, NULL, 0, max98095_pga_in1_event,
779 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
780
781 SND_SOC_DAPM_PGA_E("IN2 Input", M98095_090_PWR_EN_IN,
782 7, 0, NULL, 0, max98095_pga_in2_event,
783 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
784
785 SND_SOC_DAPM_MICBIAS("MICBIAS1", M98095_090_PWR_EN_IN, 2, 0),
786 SND_SOC_DAPM_MICBIAS("MICBIAS2", M98095_090_PWR_EN_IN, 3, 0),
787
788 SND_SOC_DAPM_OUTPUT("HPL"),
789 SND_SOC_DAPM_OUTPUT("HPR"),
790 SND_SOC_DAPM_OUTPUT("SPKL"),
791 SND_SOC_DAPM_OUTPUT("SPKR"),
792 SND_SOC_DAPM_OUTPUT("RCV"),
793 SND_SOC_DAPM_OUTPUT("OUT1"),
794 SND_SOC_DAPM_OUTPUT("OUT2"),
795 SND_SOC_DAPM_OUTPUT("OUT3"),
796 SND_SOC_DAPM_OUTPUT("OUT4"),
797
798 SND_SOC_DAPM_INPUT("MIC1"),
799 SND_SOC_DAPM_INPUT("MIC2"),
800 SND_SOC_DAPM_INPUT("INA1"),
801 SND_SOC_DAPM_INPUT("INA2"),
802 SND_SOC_DAPM_INPUT("INB1"),
803 SND_SOC_DAPM_INPUT("INB2"),
804 };
805
806 static const struct snd_soc_dapm_route max98095_audio_map[] = {
807 /* Left headphone output mixer */
808 {"Left Headphone Mixer", "Left DAC1 Switch", "DACL1"},
809 {"Left Headphone Mixer", "Right DAC1 Switch", "DACR1"},
810 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
811 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
812 {"Left Headphone Mixer", "IN1 Switch", "IN1 Input"},
813 {"Left Headphone Mixer", "IN2 Switch", "IN2 Input"},
814
815 /* Right headphone output mixer */
816 {"Right Headphone Mixer", "Left DAC1 Switch", "DACL1"},
817 {"Right Headphone Mixer", "Right DAC1 Switch", "DACR1"},
818 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
819 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
820 {"Right Headphone Mixer", "IN1 Switch", "IN1 Input"},
821 {"Right Headphone Mixer", "IN2 Switch", "IN2 Input"},
822
823 /* Left speaker output mixer */
824 {"Left Speaker Mixer", "Left DAC1 Switch", "DACL1"},
825 {"Left Speaker Mixer", "Right DAC1 Switch", "DACR1"},
826 {"Left Speaker Mixer", "Mono DAC2 Switch", "DACM2"},
827 {"Left Speaker Mixer", "Mono DAC3 Switch", "DACM3"},
828 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
829 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
830 {"Left Speaker Mixer", "IN1 Switch", "IN1 Input"},
831 {"Left Speaker Mixer", "IN2 Switch", "IN2 Input"},
832
833 /* Right speaker output mixer */
834 {"Right Speaker Mixer", "Left DAC1 Switch", "DACL1"},
835 {"Right Speaker Mixer", "Right DAC1 Switch", "DACR1"},
836 {"Right Speaker Mixer", "Mono DAC2 Switch", "DACM2"},
837 {"Right Speaker Mixer", "Mono DAC3 Switch", "DACM3"},
838 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
839 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
840 {"Right Speaker Mixer", "IN1 Switch", "IN1 Input"},
841 {"Right Speaker Mixer", "IN2 Switch", "IN2 Input"},
842
843 /* Earpiece/Receiver output mixer */
844 {"Receiver Mixer", "Left DAC1 Switch", "DACL1"},
845 {"Receiver Mixer", "Right DAC1 Switch", "DACR1"},
846 {"Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
847 {"Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
848 {"Receiver Mixer", "IN1 Switch", "IN1 Input"},
849 {"Receiver Mixer", "IN2 Switch", "IN2 Input"},
850
851 /* Left Lineout output mixer */
852 {"Left Lineout Mixer", "Left DAC1 Switch", "DACL1"},
853 {"Left Lineout Mixer", "Right DAC1 Switch", "DACR1"},
854 {"Left Lineout Mixer", "MIC1 Switch", "MIC1 Input"},
855 {"Left Lineout Mixer", "MIC2 Switch", "MIC2 Input"},
856 {"Left Lineout Mixer", "IN1 Switch", "IN1 Input"},
857 {"Left Lineout Mixer", "IN2 Switch", "IN2 Input"},
858
859 /* Right lineout output mixer */
860 {"Right Lineout Mixer", "Left DAC1 Switch", "DACL1"},
861 {"Right Lineout Mixer", "Right DAC1 Switch", "DACR1"},
862 {"Right Lineout Mixer", "MIC1 Switch", "MIC1 Input"},
863 {"Right Lineout Mixer", "MIC2 Switch", "MIC2 Input"},
864 {"Right Lineout Mixer", "IN1 Switch", "IN1 Input"},
865 {"Right Lineout Mixer", "IN2 Switch", "IN2 Input"},
866
867 {"HP Left Out", NULL, "Left Headphone Mixer"},
868 {"HP Right Out", NULL, "Right Headphone Mixer"},
869 {"SPK Left Out", NULL, "Left Speaker Mixer"},
870 {"SPK Right Out", NULL, "Right Speaker Mixer"},
871 {"RCV Mono Out", NULL, "Receiver Mixer"},
872 {"LINE Left Out", NULL, "Left Lineout Mixer"},
873 {"LINE Right Out", NULL, "Right Lineout Mixer"},
874
875 {"HPL", NULL, "HP Left Out"},
876 {"HPR", NULL, "HP Right Out"},
877 {"SPKL", NULL, "SPK Left Out"},
878 {"SPKR", NULL, "SPK Right Out"},
879 {"RCV", NULL, "RCV Mono Out"},
880 {"OUT1", NULL, "LINE Left Out"},
881 {"OUT2", NULL, "LINE Right Out"},
882 {"OUT3", NULL, "LINE Left Out"},
883 {"OUT4", NULL, "LINE Right Out"},
884
885 /* Left ADC input mixer */
886 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
887 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
888 {"Left ADC Mixer", "IN1 Switch", "IN1 Input"},
889 {"Left ADC Mixer", "IN2 Switch", "IN2 Input"},
890
891 /* Right ADC input mixer */
892 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
893 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
894 {"Right ADC Mixer", "IN1 Switch", "IN1 Input"},
895 {"Right ADC Mixer", "IN2 Switch", "IN2 Input"},
896
897 /* Inputs */
898 {"ADCL", NULL, "Left ADC Mixer"},
899 {"ADCR", NULL, "Right ADC Mixer"},
900
901 {"IN1 Input", NULL, "INA1"},
902 {"IN2 Input", NULL, "INA2"},
903
904 {"MIC1 Input", NULL, "MIC1"},
905 {"MIC2 Input", NULL, "MIC2"},
906 };
907
908 /* codec mclk clock divider coefficients */
909 static const struct {
910 u32 rate;
911 u8 sr;
912 } rate_table[] = {
913 {8000, 0x01},
914 {11025, 0x02},
915 {16000, 0x03},
916 {22050, 0x04},
917 {24000, 0x05},
918 {32000, 0x06},
919 {44100, 0x07},
920 {48000, 0x08},
921 {88200, 0x09},
922 {96000, 0x0A},
923 };
924
rate_value(int rate,u8 * value)925 static int rate_value(int rate, u8 *value)
926 {
927 int i;
928
929 for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
930 if (rate_table[i].rate >= rate) {
931 *value = rate_table[i].sr;
932 return 0;
933 }
934 }
935 *value = rate_table[0].sr;
936 return -EINVAL;
937 }
938
max98095_dai1_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)939 static int max98095_dai1_hw_params(struct snd_pcm_substream *substream,
940 struct snd_pcm_hw_params *params,
941 struct snd_soc_dai *dai)
942 {
943 struct snd_soc_component *component = dai->component;
944 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
945 struct max98095_cdata *cdata;
946 unsigned long long ni;
947 unsigned int rate;
948 u8 regval;
949
950 cdata = &max98095->dai[0];
951
952 rate = params_rate(params);
953
954 switch (params_width(params)) {
955 case 16:
956 snd_soc_component_update_bits(component, M98095_02A_DAI1_FORMAT,
957 M98095_DAI_WS, 0);
958 break;
959 case 24:
960 snd_soc_component_update_bits(component, M98095_02A_DAI1_FORMAT,
961 M98095_DAI_WS, M98095_DAI_WS);
962 break;
963 default:
964 return -EINVAL;
965 }
966
967 if (rate_value(rate, ®val))
968 return -EINVAL;
969
970 snd_soc_component_update_bits(component, M98095_027_DAI1_CLKMODE,
971 M98095_CLKMODE_MASK, regval);
972 cdata->rate = rate;
973
974 /* Configure NI when operating as master */
975 if (snd_soc_component_read(component, M98095_02A_DAI1_FORMAT) & M98095_DAI_MAS) {
976 if (max98095->sysclk == 0) {
977 dev_err(component->dev, "Invalid system clock frequency\n");
978 return -EINVAL;
979 }
980 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
981 * (unsigned long long int)rate;
982 do_div(ni, (unsigned long long int)max98095->sysclk);
983 snd_soc_component_write(component, M98095_028_DAI1_CLKCFG_HI,
984 (ni >> 8) & 0x7F);
985 snd_soc_component_write(component, M98095_029_DAI1_CLKCFG_LO,
986 ni & 0xFF);
987 }
988
989 /* Update sample rate mode */
990 if (rate < 50000)
991 snd_soc_component_update_bits(component, M98095_02E_DAI1_FILTERS,
992 M98095_DAI_DHF, 0);
993 else
994 snd_soc_component_update_bits(component, M98095_02E_DAI1_FILTERS,
995 M98095_DAI_DHF, M98095_DAI_DHF);
996
997 return 0;
998 }
999
max98095_dai2_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1000 static int max98095_dai2_hw_params(struct snd_pcm_substream *substream,
1001 struct snd_pcm_hw_params *params,
1002 struct snd_soc_dai *dai)
1003 {
1004 struct snd_soc_component *component = dai->component;
1005 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1006 struct max98095_cdata *cdata;
1007 unsigned long long ni;
1008 unsigned int rate;
1009 u8 regval;
1010
1011 cdata = &max98095->dai[1];
1012
1013 rate = params_rate(params);
1014
1015 switch (params_width(params)) {
1016 case 16:
1017 snd_soc_component_update_bits(component, M98095_034_DAI2_FORMAT,
1018 M98095_DAI_WS, 0);
1019 break;
1020 case 24:
1021 snd_soc_component_update_bits(component, M98095_034_DAI2_FORMAT,
1022 M98095_DAI_WS, M98095_DAI_WS);
1023 break;
1024 default:
1025 return -EINVAL;
1026 }
1027
1028 if (rate_value(rate, ®val))
1029 return -EINVAL;
1030
1031 snd_soc_component_update_bits(component, M98095_031_DAI2_CLKMODE,
1032 M98095_CLKMODE_MASK, regval);
1033 cdata->rate = rate;
1034
1035 /* Configure NI when operating as master */
1036 if (snd_soc_component_read(component, M98095_034_DAI2_FORMAT) & M98095_DAI_MAS) {
1037 if (max98095->sysclk == 0) {
1038 dev_err(component->dev, "Invalid system clock frequency\n");
1039 return -EINVAL;
1040 }
1041 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1042 * (unsigned long long int)rate;
1043 do_div(ni, (unsigned long long int)max98095->sysclk);
1044 snd_soc_component_write(component, M98095_032_DAI2_CLKCFG_HI,
1045 (ni >> 8) & 0x7F);
1046 snd_soc_component_write(component, M98095_033_DAI2_CLKCFG_LO,
1047 ni & 0xFF);
1048 }
1049
1050 /* Update sample rate mode */
1051 if (rate < 50000)
1052 snd_soc_component_update_bits(component, M98095_038_DAI2_FILTERS,
1053 M98095_DAI_DHF, 0);
1054 else
1055 snd_soc_component_update_bits(component, M98095_038_DAI2_FILTERS,
1056 M98095_DAI_DHF, M98095_DAI_DHF);
1057
1058 return 0;
1059 }
1060
max98095_dai3_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1061 static int max98095_dai3_hw_params(struct snd_pcm_substream *substream,
1062 struct snd_pcm_hw_params *params,
1063 struct snd_soc_dai *dai)
1064 {
1065 struct snd_soc_component *component = dai->component;
1066 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1067 struct max98095_cdata *cdata;
1068 unsigned long long ni;
1069 unsigned int rate;
1070 u8 regval;
1071
1072 cdata = &max98095->dai[2];
1073
1074 rate = params_rate(params);
1075
1076 switch (params_width(params)) {
1077 case 16:
1078 snd_soc_component_update_bits(component, M98095_03E_DAI3_FORMAT,
1079 M98095_DAI_WS, 0);
1080 break;
1081 case 24:
1082 snd_soc_component_update_bits(component, M98095_03E_DAI3_FORMAT,
1083 M98095_DAI_WS, M98095_DAI_WS);
1084 break;
1085 default:
1086 return -EINVAL;
1087 }
1088
1089 if (rate_value(rate, ®val))
1090 return -EINVAL;
1091
1092 snd_soc_component_update_bits(component, M98095_03B_DAI3_CLKMODE,
1093 M98095_CLKMODE_MASK, regval);
1094 cdata->rate = rate;
1095
1096 /* Configure NI when operating as master */
1097 if (snd_soc_component_read(component, M98095_03E_DAI3_FORMAT) & M98095_DAI_MAS) {
1098 if (max98095->sysclk == 0) {
1099 dev_err(component->dev, "Invalid system clock frequency\n");
1100 return -EINVAL;
1101 }
1102 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1103 * (unsigned long long int)rate;
1104 do_div(ni, (unsigned long long int)max98095->sysclk);
1105 snd_soc_component_write(component, M98095_03C_DAI3_CLKCFG_HI,
1106 (ni >> 8) & 0x7F);
1107 snd_soc_component_write(component, M98095_03D_DAI3_CLKCFG_LO,
1108 ni & 0xFF);
1109 }
1110
1111 /* Update sample rate mode */
1112 if (rate < 50000)
1113 snd_soc_component_update_bits(component, M98095_042_DAI3_FILTERS,
1114 M98095_DAI_DHF, 0);
1115 else
1116 snd_soc_component_update_bits(component, M98095_042_DAI3_FILTERS,
1117 M98095_DAI_DHF, M98095_DAI_DHF);
1118
1119 return 0;
1120 }
1121
max98095_dai_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)1122 static int max98095_dai_set_sysclk(struct snd_soc_dai *dai,
1123 int clk_id, unsigned int freq, int dir)
1124 {
1125 struct snd_soc_component *component = dai->component;
1126 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1127
1128 /* Requested clock frequency is already setup */
1129 if (freq == max98095->sysclk)
1130 return 0;
1131
1132 if (!IS_ERR(max98095->mclk)) {
1133 freq = clk_round_rate(max98095->mclk, freq);
1134 clk_set_rate(max98095->mclk, freq);
1135 }
1136
1137 /* Setup clocks for slave mode, and using the PLL
1138 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1139 * 0x02 (when master clk is 20MHz to 40MHz)..
1140 * 0x03 (when master clk is 40MHz to 60MHz)..
1141 */
1142 if ((freq >= 10000000) && (freq < 20000000)) {
1143 snd_soc_component_write(component, M98095_026_SYS_CLK, 0x10);
1144 } else if ((freq >= 20000000) && (freq < 40000000)) {
1145 snd_soc_component_write(component, M98095_026_SYS_CLK, 0x20);
1146 } else if ((freq >= 40000000) && (freq < 60000000)) {
1147 snd_soc_component_write(component, M98095_026_SYS_CLK, 0x30);
1148 } else {
1149 dev_err(component->dev, "Invalid master clock frequency\n");
1150 return -EINVAL;
1151 }
1152
1153 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1154
1155 max98095->sysclk = freq;
1156 return 0;
1157 }
1158
max98095_dai1_set_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)1159 static int max98095_dai1_set_fmt(struct snd_soc_dai *codec_dai,
1160 unsigned int fmt)
1161 {
1162 struct snd_soc_component *component = codec_dai->component;
1163 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1164 struct max98095_cdata *cdata;
1165 u8 regval = 0;
1166
1167 cdata = &max98095->dai[0];
1168
1169 if (fmt != cdata->fmt) {
1170 cdata->fmt = fmt;
1171
1172 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1173 case SND_SOC_DAIFMT_CBC_CFC:
1174 /* Consumer mode PLL */
1175 snd_soc_component_write(component, M98095_028_DAI1_CLKCFG_HI,
1176 0x80);
1177 snd_soc_component_write(component, M98095_029_DAI1_CLKCFG_LO,
1178 0x00);
1179 break;
1180 case SND_SOC_DAIFMT_CBP_CFP:
1181 /* Set to provider mode */
1182 regval |= M98095_DAI_MAS;
1183 break;
1184 default:
1185 dev_err(component->dev, "Clock mode unsupported");
1186 return -EINVAL;
1187 }
1188
1189 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1190 case SND_SOC_DAIFMT_I2S:
1191 regval |= M98095_DAI_DLY;
1192 break;
1193 case SND_SOC_DAIFMT_LEFT_J:
1194 break;
1195 default:
1196 return -EINVAL;
1197 }
1198
1199 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1200 case SND_SOC_DAIFMT_NB_NF:
1201 break;
1202 case SND_SOC_DAIFMT_NB_IF:
1203 regval |= M98095_DAI_WCI;
1204 break;
1205 case SND_SOC_DAIFMT_IB_NF:
1206 regval |= M98095_DAI_BCI;
1207 break;
1208 case SND_SOC_DAIFMT_IB_IF:
1209 regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1210 break;
1211 default:
1212 return -EINVAL;
1213 }
1214
1215 snd_soc_component_update_bits(component, M98095_02A_DAI1_FORMAT,
1216 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1217 M98095_DAI_WCI, regval);
1218
1219 snd_soc_component_write(component, M98095_02B_DAI1_CLOCK, M98095_DAI_BSEL64);
1220 }
1221
1222 return 0;
1223 }
1224
max98095_dai2_set_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)1225 static int max98095_dai2_set_fmt(struct snd_soc_dai *codec_dai,
1226 unsigned int fmt)
1227 {
1228 struct snd_soc_component *component = codec_dai->component;
1229 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1230 struct max98095_cdata *cdata;
1231 u8 regval = 0;
1232
1233 cdata = &max98095->dai[1];
1234
1235 if (fmt != cdata->fmt) {
1236 cdata->fmt = fmt;
1237
1238 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1239 case SND_SOC_DAIFMT_CBC_CFC:
1240 /* Consumer mode PLL */
1241 snd_soc_component_write(component, M98095_032_DAI2_CLKCFG_HI,
1242 0x80);
1243 snd_soc_component_write(component, M98095_033_DAI2_CLKCFG_LO,
1244 0x00);
1245 break;
1246 case SND_SOC_DAIFMT_CBP_CFP:
1247 /* Set to provider mode */
1248 regval |= M98095_DAI_MAS;
1249 break;
1250 default:
1251 dev_err(component->dev, "Clock mode unsupported");
1252 return -EINVAL;
1253 }
1254
1255 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1256 case SND_SOC_DAIFMT_I2S:
1257 regval |= M98095_DAI_DLY;
1258 break;
1259 case SND_SOC_DAIFMT_LEFT_J:
1260 break;
1261 default:
1262 return -EINVAL;
1263 }
1264
1265 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1266 case SND_SOC_DAIFMT_NB_NF:
1267 break;
1268 case SND_SOC_DAIFMT_NB_IF:
1269 regval |= M98095_DAI_WCI;
1270 break;
1271 case SND_SOC_DAIFMT_IB_NF:
1272 regval |= M98095_DAI_BCI;
1273 break;
1274 case SND_SOC_DAIFMT_IB_IF:
1275 regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1276 break;
1277 default:
1278 return -EINVAL;
1279 }
1280
1281 snd_soc_component_update_bits(component, M98095_034_DAI2_FORMAT,
1282 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1283 M98095_DAI_WCI, regval);
1284
1285 snd_soc_component_write(component, M98095_035_DAI2_CLOCK,
1286 M98095_DAI_BSEL64);
1287 }
1288
1289 return 0;
1290 }
1291
max98095_dai3_set_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)1292 static int max98095_dai3_set_fmt(struct snd_soc_dai *codec_dai,
1293 unsigned int fmt)
1294 {
1295 struct snd_soc_component *component = codec_dai->component;
1296 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1297 struct max98095_cdata *cdata;
1298 u8 regval = 0;
1299
1300 cdata = &max98095->dai[2];
1301
1302 if (fmt != cdata->fmt) {
1303 cdata->fmt = fmt;
1304
1305 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1306 case SND_SOC_DAIFMT_CBC_CFC:
1307 /* Consumer mode PLL */
1308 snd_soc_component_write(component, M98095_03C_DAI3_CLKCFG_HI,
1309 0x80);
1310 snd_soc_component_write(component, M98095_03D_DAI3_CLKCFG_LO,
1311 0x00);
1312 break;
1313 case SND_SOC_DAIFMT_CBP_CFP:
1314 /* Set to provider mode */
1315 regval |= M98095_DAI_MAS;
1316 break;
1317 default:
1318 dev_err(component->dev, "Clock mode unsupported");
1319 return -EINVAL;
1320 }
1321
1322 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1323 case SND_SOC_DAIFMT_I2S:
1324 regval |= M98095_DAI_DLY;
1325 break;
1326 case SND_SOC_DAIFMT_LEFT_J:
1327 break;
1328 default:
1329 return -EINVAL;
1330 }
1331
1332 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1333 case SND_SOC_DAIFMT_NB_NF:
1334 break;
1335 case SND_SOC_DAIFMT_NB_IF:
1336 regval |= M98095_DAI_WCI;
1337 break;
1338 case SND_SOC_DAIFMT_IB_NF:
1339 regval |= M98095_DAI_BCI;
1340 break;
1341 case SND_SOC_DAIFMT_IB_IF:
1342 regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1343 break;
1344 default:
1345 return -EINVAL;
1346 }
1347
1348 snd_soc_component_update_bits(component, M98095_03E_DAI3_FORMAT,
1349 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1350 M98095_DAI_WCI, regval);
1351
1352 snd_soc_component_write(component, M98095_03F_DAI3_CLOCK,
1353 M98095_DAI_BSEL64);
1354 }
1355
1356 return 0;
1357 }
1358
max98095_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)1359 static int max98095_set_bias_level(struct snd_soc_component *component,
1360 enum snd_soc_bias_level level)
1361 {
1362 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1363 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
1364 int ret;
1365
1366 switch (level) {
1367 case SND_SOC_BIAS_ON:
1368 break;
1369
1370 case SND_SOC_BIAS_PREPARE:
1371 /*
1372 * SND_SOC_BIAS_PREPARE is called while preparing for a
1373 * transition to ON or away from ON. If current bias_level
1374 * is SND_SOC_BIAS_ON, then it is preparing for a transition
1375 * away from ON. Disable the clock in that case, otherwise
1376 * enable it.
1377 */
1378 if (IS_ERR(max98095->mclk))
1379 break;
1380
1381 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_ON) {
1382 clk_disable_unprepare(max98095->mclk);
1383 } else {
1384 ret = clk_prepare_enable(max98095->mclk);
1385 if (ret)
1386 return ret;
1387 }
1388 break;
1389
1390 case SND_SOC_BIAS_STANDBY:
1391 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) {
1392 ret = regcache_sync(max98095->regmap);
1393
1394 if (ret != 0) {
1395 dev_err(component->dev, "Failed to sync cache: %d\n", ret);
1396 return ret;
1397 }
1398 }
1399
1400 snd_soc_component_update_bits(component, M98095_090_PWR_EN_IN,
1401 M98095_MBEN, M98095_MBEN);
1402 break;
1403
1404 case SND_SOC_BIAS_OFF:
1405 snd_soc_component_update_bits(component, M98095_090_PWR_EN_IN,
1406 M98095_MBEN, 0);
1407 regcache_mark_dirty(max98095->regmap);
1408 break;
1409 }
1410 return 0;
1411 }
1412
1413 #define MAX98095_RATES SNDRV_PCM_RATE_8000_96000
1414 #define MAX98095_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
1415
1416 static const struct snd_soc_dai_ops max98095_dai1_ops = {
1417 .set_sysclk = max98095_dai_set_sysclk,
1418 .set_fmt = max98095_dai1_set_fmt,
1419 .hw_params = max98095_dai1_hw_params,
1420 };
1421
1422 static const struct snd_soc_dai_ops max98095_dai2_ops = {
1423 .set_sysclk = max98095_dai_set_sysclk,
1424 .set_fmt = max98095_dai2_set_fmt,
1425 .hw_params = max98095_dai2_hw_params,
1426 };
1427
1428 static const struct snd_soc_dai_ops max98095_dai3_ops = {
1429 .set_sysclk = max98095_dai_set_sysclk,
1430 .set_fmt = max98095_dai3_set_fmt,
1431 .hw_params = max98095_dai3_hw_params,
1432 };
1433
1434 static struct snd_soc_dai_driver max98095_dai[] = {
1435 {
1436 .name = "HiFi",
1437 .playback = {
1438 .stream_name = "HiFi Playback",
1439 .channels_min = 1,
1440 .channels_max = 2,
1441 .rates = MAX98095_RATES,
1442 .formats = MAX98095_FORMATS,
1443 },
1444 .capture = {
1445 .stream_name = "HiFi Capture",
1446 .channels_min = 1,
1447 .channels_max = 2,
1448 .rates = MAX98095_RATES,
1449 .formats = MAX98095_FORMATS,
1450 },
1451 .ops = &max98095_dai1_ops,
1452 },
1453 {
1454 .name = "Aux",
1455 .playback = {
1456 .stream_name = "Aux Playback",
1457 .channels_min = 1,
1458 .channels_max = 1,
1459 .rates = MAX98095_RATES,
1460 .formats = MAX98095_FORMATS,
1461 },
1462 .ops = &max98095_dai2_ops,
1463 },
1464 {
1465 .name = "Voice",
1466 .playback = {
1467 .stream_name = "Voice Playback",
1468 .channels_min = 1,
1469 .channels_max = 1,
1470 .rates = MAX98095_RATES,
1471 .formats = MAX98095_FORMATS,
1472 },
1473 .ops = &max98095_dai3_ops,
1474 }
1475
1476 };
1477
max98095_get_eq_channel(const char * name)1478 static int max98095_get_eq_channel(const char *name)
1479 {
1480 if (strcmp(name, "EQ1 Mode") == 0)
1481 return 0;
1482 if (strcmp(name, "EQ2 Mode") == 0)
1483 return 1;
1484 return -EINVAL;
1485 }
1486
max98095_put_eq_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1487 static int max98095_put_eq_enum(struct snd_kcontrol *kcontrol,
1488 struct snd_ctl_elem_value *ucontrol)
1489 {
1490 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1491 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1492 struct max98095_pdata *pdata = max98095->pdata;
1493 int channel = max98095_get_eq_channel(kcontrol->id.name);
1494 struct max98095_cdata *cdata;
1495 unsigned int sel = ucontrol->value.enumerated.item[0];
1496 struct max98095_eq_cfg *coef_set;
1497 int fs, best, best_val, i;
1498 int regmask, regsave;
1499
1500 if (WARN_ON(channel > 1))
1501 return -EINVAL;
1502
1503 if (!pdata || !max98095->eq_textcnt)
1504 return 0;
1505
1506 if (sel >= pdata->eq_cfgcnt)
1507 return -EINVAL;
1508
1509 cdata = &max98095->dai[channel];
1510 cdata->eq_sel = sel;
1511 fs = cdata->rate;
1512
1513 /* Find the selected configuration with nearest sample rate */
1514 best = 0;
1515 best_val = INT_MAX;
1516 for (i = 0; i < pdata->eq_cfgcnt; i++) {
1517 if (strcmp(pdata->eq_cfg[i].name, max98095->eq_texts[sel]) == 0 &&
1518 abs(pdata->eq_cfg[i].rate - fs) < best_val) {
1519 best = i;
1520 best_val = abs(pdata->eq_cfg[i].rate - fs);
1521 }
1522 }
1523
1524 dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n",
1525 pdata->eq_cfg[best].name,
1526 pdata->eq_cfg[best].rate, fs);
1527
1528 coef_set = &pdata->eq_cfg[best];
1529
1530 regmask = (channel == 0) ? M98095_EQ1EN : M98095_EQ2EN;
1531
1532 /* Disable filter while configuring, and save current on/off state */
1533 regsave = snd_soc_component_read(component, M98095_088_CFG_LEVEL);
1534 snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, 0);
1535
1536 scoped_guard(mutex, &max98095->lock) {
1537 snd_soc_component_update_bits(component, M98095_00F_HOST_CFG,
1538 M98095_SEG, M98095_SEG);
1539 m98095_eq_band(component, channel, 0, coef_set->band1);
1540 m98095_eq_band(component, channel, 1, coef_set->band2);
1541 m98095_eq_band(component, channel, 2, coef_set->band3);
1542 m98095_eq_band(component, channel, 3, coef_set->band4);
1543 m98095_eq_band(component, channel, 4, coef_set->band5);
1544 snd_soc_component_update_bits(component, M98095_00F_HOST_CFG,
1545 M98095_SEG, 0);
1546 }
1547
1548 /* Restore the original on/off state */
1549 snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, regsave);
1550 return 0;
1551 }
1552
max98095_get_eq_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1553 static int max98095_get_eq_enum(struct snd_kcontrol *kcontrol,
1554 struct snd_ctl_elem_value *ucontrol)
1555 {
1556 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1557 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1558 int channel = max98095_get_eq_channel(kcontrol->id.name);
1559 struct max98095_cdata *cdata;
1560
1561 cdata = &max98095->dai[channel];
1562 ucontrol->value.enumerated.item[0] = cdata->eq_sel;
1563
1564 return 0;
1565 }
1566
max98095_handle_eq_pdata(struct snd_soc_component * component)1567 static void max98095_handle_eq_pdata(struct snd_soc_component *component)
1568 {
1569 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1570 struct max98095_pdata *pdata = max98095->pdata;
1571 struct max98095_eq_cfg *cfg;
1572 unsigned int cfgcnt;
1573 int i, j;
1574 const char **t;
1575 int ret;
1576
1577 struct snd_kcontrol_new controls[] = {
1578 SOC_ENUM_EXT("EQ1 Mode",
1579 max98095->eq_enum,
1580 max98095_get_eq_enum,
1581 max98095_put_eq_enum),
1582 SOC_ENUM_EXT("EQ2 Mode",
1583 max98095->eq_enum,
1584 max98095_get_eq_enum,
1585 max98095_put_eq_enum),
1586 };
1587
1588 cfg = pdata->eq_cfg;
1589 cfgcnt = pdata->eq_cfgcnt;
1590
1591 /* Setup an array of texts for the equalizer enum.
1592 * This is based on Mark Brown's equalizer driver code.
1593 */
1594 max98095->eq_textcnt = 0;
1595 max98095->eq_texts = NULL;
1596 for (i = 0; i < cfgcnt; i++) {
1597 for (j = 0; j < max98095->eq_textcnt; j++) {
1598 if (strcmp(cfg[i].name, max98095->eq_texts[j]) == 0)
1599 break;
1600 }
1601
1602 if (j != max98095->eq_textcnt)
1603 continue;
1604
1605 /* Expand the array */
1606 t = krealloc(max98095->eq_texts,
1607 sizeof(char *) * (max98095->eq_textcnt + 1),
1608 GFP_KERNEL);
1609 if (t == NULL)
1610 continue;
1611
1612 /* Store the new entry */
1613 t[max98095->eq_textcnt] = cfg[i].name;
1614 max98095->eq_textcnt++;
1615 max98095->eq_texts = t;
1616 }
1617
1618 /* Now point the soc_enum to .texts array items */
1619 max98095->eq_enum.texts = max98095->eq_texts;
1620 max98095->eq_enum.items = max98095->eq_textcnt;
1621
1622 ret = snd_soc_add_component_controls(component, controls, ARRAY_SIZE(controls));
1623 if (ret != 0)
1624 dev_err(component->dev, "Failed to add EQ control: %d\n", ret);
1625 }
1626
1627 static const char *bq_mode_name[] = {"Biquad1 Mode", "Biquad2 Mode"};
1628
max98095_get_bq_channel(struct snd_soc_component * component,const char * name)1629 static int max98095_get_bq_channel(struct snd_soc_component *component,
1630 const char *name)
1631 {
1632 int ret;
1633
1634 ret = match_string(bq_mode_name, ARRAY_SIZE(bq_mode_name), name);
1635 if (ret < 0)
1636 dev_err(component->dev, "Bad biquad channel name '%s'\n", name);
1637 return ret;
1638 }
1639
max98095_put_bq_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1640 static int max98095_put_bq_enum(struct snd_kcontrol *kcontrol,
1641 struct snd_ctl_elem_value *ucontrol)
1642 {
1643 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1644 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1645 struct max98095_pdata *pdata = max98095->pdata;
1646 int channel = max98095_get_bq_channel(component, kcontrol->id.name);
1647 struct max98095_cdata *cdata;
1648 unsigned int sel = ucontrol->value.enumerated.item[0];
1649 struct max98095_biquad_cfg *coef_set;
1650 int fs, best, best_val, i;
1651 int regmask, regsave;
1652
1653 if (channel < 0)
1654 return channel;
1655
1656 if (!pdata || !max98095->bq_textcnt)
1657 return 0;
1658
1659 if (sel >= pdata->bq_cfgcnt)
1660 return -EINVAL;
1661
1662 cdata = &max98095->dai[channel];
1663 cdata->bq_sel = sel;
1664 fs = cdata->rate;
1665
1666 /* Find the selected configuration with nearest sample rate */
1667 best = 0;
1668 best_val = INT_MAX;
1669 for (i = 0; i < pdata->bq_cfgcnt; i++) {
1670 if (strcmp(pdata->bq_cfg[i].name, max98095->bq_texts[sel]) == 0 &&
1671 abs(pdata->bq_cfg[i].rate - fs) < best_val) {
1672 best = i;
1673 best_val = abs(pdata->bq_cfg[i].rate - fs);
1674 }
1675 }
1676
1677 dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n",
1678 pdata->bq_cfg[best].name,
1679 pdata->bq_cfg[best].rate, fs);
1680
1681 coef_set = &pdata->bq_cfg[best];
1682
1683 regmask = (channel == 0) ? M98095_BQ1EN : M98095_BQ2EN;
1684
1685 /* Disable filter while configuring, and save current on/off state */
1686 regsave = snd_soc_component_read(component, M98095_088_CFG_LEVEL);
1687 snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, 0);
1688
1689 scoped_guard(mutex, &max98095->lock) {
1690 snd_soc_component_update_bits(component, M98095_00F_HOST_CFG,
1691 M98095_SEG, M98095_SEG);
1692 m98095_biquad_band(component, channel, 0, coef_set->band1);
1693 m98095_biquad_band(component, channel, 1, coef_set->band2);
1694 snd_soc_component_update_bits(component, M98095_00F_HOST_CFG,
1695 M98095_SEG, 0);
1696 }
1697
1698 /* Restore the original on/off state */
1699 snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, regsave);
1700 return 0;
1701 }
1702
max98095_get_bq_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1703 static int max98095_get_bq_enum(struct snd_kcontrol *kcontrol,
1704 struct snd_ctl_elem_value *ucontrol)
1705 {
1706 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1707 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1708 int channel = max98095_get_bq_channel(component, kcontrol->id.name);
1709 struct max98095_cdata *cdata;
1710
1711 if (channel < 0)
1712 return channel;
1713
1714 cdata = &max98095->dai[channel];
1715 ucontrol->value.enumerated.item[0] = cdata->bq_sel;
1716
1717 return 0;
1718 }
1719
max98095_handle_bq_pdata(struct snd_soc_component * component)1720 static void max98095_handle_bq_pdata(struct snd_soc_component *component)
1721 {
1722 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1723 struct max98095_pdata *pdata = max98095->pdata;
1724 struct max98095_biquad_cfg *cfg;
1725 unsigned int cfgcnt;
1726 int i, j;
1727 const char **t;
1728 int ret;
1729
1730 struct snd_kcontrol_new controls[] = {
1731 SOC_ENUM_EXT((char *)bq_mode_name[0],
1732 max98095->bq_enum,
1733 max98095_get_bq_enum,
1734 max98095_put_bq_enum),
1735 SOC_ENUM_EXT((char *)bq_mode_name[1],
1736 max98095->bq_enum,
1737 max98095_get_bq_enum,
1738 max98095_put_bq_enum),
1739 };
1740 BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(bq_mode_name));
1741
1742 cfg = pdata->bq_cfg;
1743 cfgcnt = pdata->bq_cfgcnt;
1744
1745 /* Setup an array of texts for the biquad enum.
1746 * This is based on Mark Brown's equalizer driver code.
1747 */
1748 max98095->bq_textcnt = 0;
1749 max98095->bq_texts = NULL;
1750 for (i = 0; i < cfgcnt; i++) {
1751 for (j = 0; j < max98095->bq_textcnt; j++) {
1752 if (strcmp(cfg[i].name, max98095->bq_texts[j]) == 0)
1753 break;
1754 }
1755
1756 if (j != max98095->bq_textcnt)
1757 continue;
1758
1759 /* Expand the array */
1760 t = krealloc(max98095->bq_texts,
1761 sizeof(char *) * (max98095->bq_textcnt + 1),
1762 GFP_KERNEL);
1763 if (t == NULL)
1764 continue;
1765
1766 /* Store the new entry */
1767 t[max98095->bq_textcnt] = cfg[i].name;
1768 max98095->bq_textcnt++;
1769 max98095->bq_texts = t;
1770 }
1771
1772 /* Now point the soc_enum to .texts array items */
1773 max98095->bq_enum.texts = max98095->bq_texts;
1774 max98095->bq_enum.items = max98095->bq_textcnt;
1775
1776 ret = snd_soc_add_component_controls(component, controls, ARRAY_SIZE(controls));
1777 if (ret != 0)
1778 dev_err(component->dev, "Failed to add Biquad control: %d\n", ret);
1779 }
1780
max98095_handle_pdata(struct snd_soc_component * component)1781 static void max98095_handle_pdata(struct snd_soc_component *component)
1782 {
1783 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1784 struct max98095_pdata *pdata = max98095->pdata;
1785 u8 regval = 0;
1786
1787 if (!pdata) {
1788 dev_dbg(component->dev, "No platform data\n");
1789 return;
1790 }
1791
1792 /* Configure mic for analog/digital mic mode */
1793 if (pdata->digmic_left_mode)
1794 regval |= M98095_DIGMIC_L;
1795
1796 if (pdata->digmic_right_mode)
1797 regval |= M98095_DIGMIC_R;
1798
1799 snd_soc_component_write(component, M98095_087_CFG_MIC, regval);
1800
1801 /* Configure equalizers */
1802 if (pdata->eq_cfgcnt)
1803 max98095_handle_eq_pdata(component);
1804
1805 /* Configure bi-quad filters */
1806 if (pdata->bq_cfgcnt)
1807 max98095_handle_bq_pdata(component);
1808 }
1809
max98095_report_jack(int irq,void * data)1810 static irqreturn_t max98095_report_jack(int irq, void *data)
1811 {
1812 struct snd_soc_component *component = data;
1813 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1814 unsigned int value;
1815 int hp_report = 0;
1816 int mic_report = 0;
1817
1818 /* Read the Jack Status Register */
1819 value = snd_soc_component_read(component, M98095_007_JACK_AUTO_STS);
1820
1821 /* If ddone is not set, then detection isn't finished yet */
1822 if ((value & M98095_DDONE) == 0)
1823 return IRQ_NONE;
1824
1825 /* if hp, check its bit, and if set, clear it */
1826 if ((value & M98095_HP_IN || value & M98095_LO_IN) &&
1827 max98095->headphone_jack)
1828 hp_report |= SND_JACK_HEADPHONE;
1829
1830 /* if mic, check its bit, and if set, clear it */
1831 if ((value & M98095_MIC_IN) && max98095->mic_jack)
1832 mic_report |= SND_JACK_MICROPHONE;
1833
1834 if (max98095->headphone_jack == max98095->mic_jack) {
1835 snd_soc_jack_report(max98095->headphone_jack,
1836 hp_report | mic_report,
1837 SND_JACK_HEADSET);
1838 } else {
1839 if (max98095->headphone_jack)
1840 snd_soc_jack_report(max98095->headphone_jack,
1841 hp_report, SND_JACK_HEADPHONE);
1842 if (max98095->mic_jack)
1843 snd_soc_jack_report(max98095->mic_jack,
1844 mic_report, SND_JACK_MICROPHONE);
1845 }
1846
1847 return IRQ_HANDLED;
1848 }
1849
max98095_jack_detect_enable(struct snd_soc_component * component)1850 static int max98095_jack_detect_enable(struct snd_soc_component *component)
1851 {
1852 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1853 int ret = 0;
1854 int detect_enable = M98095_JDEN;
1855 unsigned int slew = M98095_DEFAULT_SLEW_DELAY;
1856
1857 if (max98095->pdata->jack_detect_pin5en)
1858 detect_enable |= M98095_PIN5EN;
1859
1860 if (max98095->pdata->jack_detect_delay)
1861 slew = max98095->pdata->jack_detect_delay;
1862
1863 ret = snd_soc_component_write(component, M98095_08E_JACK_DC_SLEW, slew);
1864 if (ret < 0) {
1865 dev_err(component->dev, "Failed to cfg auto detect %d\n", ret);
1866 return ret;
1867 }
1868
1869 /* configure auto detection to be enabled */
1870 ret = snd_soc_component_write(component, M98095_089_JACK_DET_AUTO, detect_enable);
1871 if (ret < 0) {
1872 dev_err(component->dev, "Failed to cfg auto detect %d\n", ret);
1873 return ret;
1874 }
1875
1876 return ret;
1877 }
1878
max98095_jack_detect_disable(struct snd_soc_component * component)1879 static int max98095_jack_detect_disable(struct snd_soc_component *component)
1880 {
1881 int ret = 0;
1882
1883 /* configure auto detection to be disabled */
1884 ret = snd_soc_component_write(component, M98095_089_JACK_DET_AUTO, 0x0);
1885 if (ret < 0) {
1886 dev_err(component->dev, "Failed to cfg auto detect %d\n", ret);
1887 return ret;
1888 }
1889
1890 return ret;
1891 }
1892
max98095_jack_detect(struct snd_soc_component * component,struct snd_soc_jack * hp_jack,struct snd_soc_jack * mic_jack)1893 int max98095_jack_detect(struct snd_soc_component *component,
1894 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack)
1895 {
1896 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1897 struct i2c_client *client = to_i2c_client(component->dev);
1898 int ret = 0;
1899
1900 max98095->headphone_jack = hp_jack;
1901 max98095->mic_jack = mic_jack;
1902
1903 /* only progress if we have at least 1 jack pointer */
1904 if (!hp_jack && !mic_jack)
1905 return -EINVAL;
1906
1907 max98095_jack_detect_enable(component);
1908
1909 /* enable interrupts for headphone jack detection */
1910 ret = snd_soc_component_update_bits(component, M98095_013_JACK_INT_EN,
1911 M98095_IDDONE, M98095_IDDONE);
1912 if (ret < 0) {
1913 dev_err(component->dev, "Failed to cfg jack irqs %d\n", ret);
1914 return ret;
1915 }
1916
1917 max98095_report_jack(client->irq, component);
1918 return 0;
1919 }
1920 EXPORT_SYMBOL_GPL(max98095_jack_detect);
1921
1922 #ifdef CONFIG_PM
max98095_suspend(struct snd_soc_component * component)1923 static int max98095_suspend(struct snd_soc_component *component)
1924 {
1925 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1926 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
1927
1928 if (max98095->headphone_jack || max98095->mic_jack)
1929 max98095_jack_detect_disable(component);
1930
1931 snd_soc_dapm_force_bias_level(dapm, SND_SOC_BIAS_OFF);
1932
1933 return 0;
1934 }
1935
max98095_resume(struct snd_soc_component * component)1936 static int max98095_resume(struct snd_soc_component *component)
1937 {
1938 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1939 struct i2c_client *client = to_i2c_client(component->dev);
1940 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
1941
1942 snd_soc_dapm_force_bias_level(dapm, SND_SOC_BIAS_STANDBY);
1943
1944 if (max98095->headphone_jack || max98095->mic_jack) {
1945 max98095_jack_detect_enable(component);
1946 max98095_report_jack(client->irq, component);
1947 }
1948
1949 return 0;
1950 }
1951 #else
1952 #define max98095_suspend NULL
1953 #define max98095_resume NULL
1954 #endif
1955
max98095_reset(struct snd_soc_component * component)1956 static int max98095_reset(struct snd_soc_component *component)
1957 {
1958 int i, ret;
1959
1960 /* Gracefully reset the DSP core and the codec hardware
1961 * in a proper sequence */
1962 ret = snd_soc_component_write(component, M98095_00F_HOST_CFG, 0);
1963 if (ret < 0) {
1964 dev_err(component->dev, "Failed to reset DSP: %d\n", ret);
1965 return ret;
1966 }
1967
1968 ret = snd_soc_component_write(component, M98095_097_PWR_SYS, 0);
1969 if (ret < 0) {
1970 dev_err(component->dev, "Failed to reset component: %d\n", ret);
1971 return ret;
1972 }
1973
1974 /* Reset to hardware default for registers, as there is not
1975 * a soft reset hardware control register */
1976 for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) {
1977 ret = snd_soc_component_write(component, i, snd_soc_component_read(component, i));
1978 if (ret < 0) {
1979 dev_err(component->dev, "Failed to reset: %d\n", ret);
1980 return ret;
1981 }
1982 }
1983
1984 return ret;
1985 }
1986
max98095_probe(struct snd_soc_component * component)1987 static int max98095_probe(struct snd_soc_component *component)
1988 {
1989 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1990 struct max98095_cdata *cdata;
1991 struct i2c_client *client;
1992 int ret = 0;
1993
1994 max98095->mclk = devm_clk_get(component->dev, "mclk");
1995 if (IS_ERR(max98095->mclk))
1996 if (PTR_ERR(max98095->mclk) == -EPROBE_DEFER)
1997 return -EPROBE_DEFER;
1998
1999 /* reset the codec, the DSP core, and disable all interrupts */
2000 max98095_reset(component);
2001
2002 client = to_i2c_client(component->dev);
2003
2004 /* initialize private data */
2005
2006 max98095->sysclk = (unsigned)-1;
2007 max98095->eq_textcnt = 0;
2008 max98095->bq_textcnt = 0;
2009
2010 cdata = &max98095->dai[0];
2011 cdata->rate = (unsigned)-1;
2012 cdata->fmt = (unsigned)-1;
2013 cdata->eq_sel = 0;
2014 cdata->bq_sel = 0;
2015
2016 cdata = &max98095->dai[1];
2017 cdata->rate = (unsigned)-1;
2018 cdata->fmt = (unsigned)-1;
2019 cdata->eq_sel = 0;
2020 cdata->bq_sel = 0;
2021
2022 cdata = &max98095->dai[2];
2023 cdata->rate = (unsigned)-1;
2024 cdata->fmt = (unsigned)-1;
2025 cdata->eq_sel = 0;
2026 cdata->bq_sel = 0;
2027
2028 max98095->lin_state = 0;
2029 max98095->mic1pre = 0;
2030 max98095->mic2pre = 0;
2031
2032 if (client->irq) {
2033 /* register an audio interrupt */
2034 ret = request_threaded_irq(client->irq, NULL,
2035 max98095_report_jack,
2036 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING |
2037 IRQF_ONESHOT, "max98095", component);
2038 if (ret) {
2039 dev_err(component->dev, "Failed to request IRQ: %d\n", ret);
2040 goto err_access;
2041 }
2042 }
2043
2044 ret = snd_soc_component_read(component, M98095_0FF_REV_ID);
2045 if (ret < 0) {
2046 dev_err(component->dev, "Failure reading hardware revision: %d\n",
2047 ret);
2048 goto err_irq;
2049 }
2050 dev_info(component->dev, "Hardware revision: %c\n", ret - 0x40 + 'A');
2051
2052 snd_soc_component_write(component, M98095_097_PWR_SYS, M98095_PWRSV);
2053
2054 snd_soc_component_write(component, M98095_048_MIX_DAC_LR,
2055 M98095_DAI1L_TO_DACL|M98095_DAI1R_TO_DACR);
2056
2057 snd_soc_component_write(component, M98095_049_MIX_DAC_M,
2058 M98095_DAI2M_TO_DACM|M98095_DAI3M_TO_DACM);
2059
2060 snd_soc_component_write(component, M98095_092_PWR_EN_OUT, M98095_SPK_SPREADSPECTRUM);
2061 snd_soc_component_write(component, M98095_045_CFG_DSP, M98095_DSPNORMAL);
2062 snd_soc_component_write(component, M98095_04E_CFG_HP, M98095_HPNORMAL);
2063
2064 snd_soc_component_write(component, M98095_02C_DAI1_IOCFG,
2065 M98095_S1NORMAL|M98095_SDATA);
2066
2067 snd_soc_component_write(component, M98095_036_DAI2_IOCFG,
2068 M98095_S2NORMAL|M98095_SDATA);
2069
2070 snd_soc_component_write(component, M98095_040_DAI3_IOCFG,
2071 M98095_S3NORMAL|M98095_SDATA);
2072
2073 max98095_handle_pdata(component);
2074
2075 /* take the codec out of the shut down */
2076 snd_soc_component_update_bits(component, M98095_097_PWR_SYS, M98095_SHDNRUN,
2077 M98095_SHDNRUN);
2078
2079 return 0;
2080
2081 err_irq:
2082 if (client->irq)
2083 free_irq(client->irq, component);
2084 err_access:
2085 return ret;
2086 }
2087
max98095_remove(struct snd_soc_component * component)2088 static void max98095_remove(struct snd_soc_component *component)
2089 {
2090 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
2091 struct i2c_client *client = to_i2c_client(component->dev);
2092
2093 if (max98095->headphone_jack || max98095->mic_jack)
2094 max98095_jack_detect_disable(component);
2095
2096 if (client->irq)
2097 free_irq(client->irq, component);
2098 }
2099
2100 static const struct snd_soc_component_driver soc_component_dev_max98095 = {
2101 .probe = max98095_probe,
2102 .remove = max98095_remove,
2103 .suspend = max98095_suspend,
2104 .resume = max98095_resume,
2105 .set_bias_level = max98095_set_bias_level,
2106 .controls = max98095_snd_controls,
2107 .num_controls = ARRAY_SIZE(max98095_snd_controls),
2108 .dapm_widgets = max98095_dapm_widgets,
2109 .num_dapm_widgets = ARRAY_SIZE(max98095_dapm_widgets),
2110 .dapm_routes = max98095_audio_map,
2111 .num_dapm_routes = ARRAY_SIZE(max98095_audio_map),
2112 .idle_bias_on = 1,
2113 .use_pmdown_time = 1,
2114 .endianness = 1,
2115 };
2116
2117 static const struct i2c_device_id max98095_i2c_id[] = {
2118 { .name = "max98095", .driver_data = MAX98095 },
2119 { }
2120 };
2121 MODULE_DEVICE_TABLE(i2c, max98095_i2c_id);
2122
max98095_i2c_probe(struct i2c_client * i2c)2123 static int max98095_i2c_probe(struct i2c_client *i2c)
2124 {
2125 struct max98095_priv *max98095;
2126 int ret;
2127
2128 max98095 = devm_kzalloc(&i2c->dev, sizeof(struct max98095_priv),
2129 GFP_KERNEL);
2130 if (max98095 == NULL)
2131 return -ENOMEM;
2132
2133 mutex_init(&max98095->lock);
2134
2135 max98095->regmap = devm_regmap_init_i2c(i2c, &max98095_regmap);
2136 if (IS_ERR(max98095->regmap)) {
2137 ret = PTR_ERR(max98095->regmap);
2138 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
2139 return ret;
2140 }
2141
2142 max98095->devtype = (uintptr_t)i2c_get_match_data(i2c);
2143 i2c_set_clientdata(i2c, max98095);
2144 max98095->pdata = i2c->dev.platform_data;
2145
2146 ret = devm_snd_soc_register_component(&i2c->dev,
2147 &soc_component_dev_max98095,
2148 max98095_dai, ARRAY_SIZE(max98095_dai));
2149 return ret;
2150 }
2151
2152 #ifdef CONFIG_OF
2153 static const struct of_device_id max98095_of_match[] = {
2154 { .compatible = "maxim,max98095", },
2155 { }
2156 };
2157 MODULE_DEVICE_TABLE(of, max98095_of_match);
2158 #endif
2159
2160 static struct i2c_driver max98095_i2c_driver = {
2161 .driver = {
2162 .name = "max98095",
2163 .of_match_table = of_match_ptr(max98095_of_match),
2164 },
2165 .probe = max98095_i2c_probe,
2166 .id_table = max98095_i2c_id,
2167 };
2168
2169 module_i2c_driver(max98095_i2c_driver);
2170
2171 MODULE_DESCRIPTION("ALSA SoC MAX98095 driver");
2172 MODULE_AUTHOR("Peter Hsiang");
2173 MODULE_LICENSE("GPL");
2174