1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_wa.h" 7 8 #include <drm/drm_managed.h> 9 #include <kunit/visibility.h> 10 #include <linux/compiler_types.h> 11 #include <linux/fault-inject.h> 12 13 #include <generated/xe_device_wa_oob.h> 14 #include <generated/xe_wa_oob.h> 15 16 #include "regs/xe_engine_regs.h" 17 #include "regs/xe_gt_regs.h" 18 #include "regs/xe_guc_regs.h" 19 #include "regs/xe_regs.h" 20 #include "xe_device_types.h" 21 #include "xe_force_wake.h" 22 #include "xe_gt_types.h" 23 #include "xe_hw_engine_types.h" 24 #include "xe_mmio.h" 25 #include "xe_platform_types.h" 26 #include "xe_rtp.h" 27 #include "xe_sriov.h" 28 #include "xe_step.h" 29 30 /** 31 * DOC: Hardware workarounds 32 * 33 * Hardware workarounds are register programming documented to be executed in 34 * the driver that fall outside of the normal programming sequences for a 35 * platform. There are some basic categories of workarounds, depending on 36 * how/when they are applied: 37 * 38 * - LRC workarounds: workarounds that touch registers that are 39 * saved/restored to/from the HW context image. The list is emitted (via Load 40 * Register Immediate commands) once when initializing the device and saved in 41 * the default context. That default context is then used on every context 42 * creation to have a "primed golden context", i.e. a context image that 43 * already contains the changes needed to all the registers. See 44 * drivers/gpu/drm/xe/xe_lrc.c for default context handling. 45 * 46 * - Engine workarounds: the list of these WAs is applied whenever the specific 47 * engine is reset. It's also possible that a set of engine classes share a 48 * common power domain and they are reset together. This happens on some 49 * platforms with render and compute engines. In this case (at least) one of 50 * them need to keeep the workaround programming: the approach taken in the 51 * driver is to tie those workarounds to the first compute/render engine that 52 * is registered. When executing with GuC submission, engine resets are 53 * outside of kernel driver control, hence the list of registers involved is 54 * written once, on engine initialization, and then passed to GuC, that 55 * saves/restores their values before/after the reset takes place. See 56 * drivers/gpu/drm/xe/xe_guc_ads.c for reference. 57 * 58 * - GT workarounds: the list of these WAs is applied whenever these registers 59 * revert to their default values: on GPU reset, suspend/resume [1]_, etc. 60 * 61 * - Register whitelist: some workarounds need to be implemented in userspace, 62 * but need to touch privileged registers. The whitelist in the kernel 63 * instructs the hardware to allow the access to happen. From the kernel side, 64 * this is just a special case of a MMIO workaround (as we write the list of 65 * these to/be-whitelisted registers to some special HW registers). 66 * 67 * - Workaround batchbuffers: buffers that get executed automatically by the 68 * hardware on every HW context restore. These buffers are created and 69 * programmed in the default context so the hardware always go through those 70 * programming sequences when switching contexts. The support for workaround 71 * batchbuffers is enabled via these hardware mechanisms: 72 * 73 * #. INDIRECT_CTX (also known as **mid context restore bb**): A batchbuffer 74 * and an offset are provided in the default context, pointing the hardware 75 * to jump to that location when that offset is reached in the context 76 * restore. When a context is being restored, this is executed after the 77 * ring context, in the middle (or beginning) of the engine context image. 78 * 79 * #. BB_PER_CTX_PTR (also known as **post context restore bb**): A 80 * batchbuffer is provided in the default context, pointing the hardware to 81 * a buffer to continue executing after the engine registers are restored 82 * in a context restore sequence. 83 * 84 * Below is the timeline for a context restore sequence: 85 * 86 * .. code:: 87 * 88 * INDIRECT_CTX_OFFSET 89 * |----------->| 90 * .------------.------------.-------------.------------.--------------.-----------. 91 * |Ring | Engine | Mid-context | Engine | Post-context | Ring | 92 * |Restore | Restore (1)| BB Restore | Restore (2)| BB Restore | Execution | 93 * `------------'------------'-------------'------------'--------------'-----------' 94 * 95 * - Other/OOB: There are WAs that, due to their nature, cannot be applied from 96 * a central place. Those are peppered around the rest of the code, as needed. 97 * There's a central place to control which workarounds are enabled: 98 * drivers/gpu/drm/xe/xe_wa_oob.rules for GT workarounds and 99 * drivers/gpu/drm/xe/xe_device_wa_oob.rules for device/SoC workarounds. 100 * These files only record which workarounds are enabled: during early device 101 * initialization those rules are evaluated and recorded by the driver. Then 102 * later the driver checks with ``XE_GT_WA()`` and ``XE_DEVICE_WA()`` to 103 * implement them. 104 * 105 * .. [1] Technically, some registers are powercontext saved & restored, so they 106 * survive a suspend/resume. In practice, writing them again is not too 107 * costly and simplifies things, so it's the approach taken in the driver. 108 * 109 * .. note:: 110 * Hardware workarounds in xe work the same way as in i915, with the 111 * difference of how they are maintained in the code. In xe it uses the 112 * xe_rtp infrastructure so the workarounds can be kept in tables, following 113 * a more declarative approach rather than procedural. 114 */ 115 116 #undef XE_REG_MCR 117 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1) 118 119 __diag_push(); 120 __diag_ignore_all("-Woverride-init", "Allow field overrides in table"); 121 122 static const struct xe_rtp_entry_sr gt_was[] = { 123 { XE_RTP_NAME("14011060649"), 124 XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255), 125 ENGINE_CLASS(VIDEO_DECODE), 126 FUNC(xe_rtp_match_even_instance)), 127 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 128 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 129 }, 130 { XE_RTP_NAME("14011059788"), 131 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 132 XE_RTP_ACTIONS(SET(DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE)) 133 }, 134 { XE_RTP_NAME("14015795083"), 135 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260)), 136 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE)) 137 }, 138 139 /* DG1 */ 140 141 { XE_RTP_NAME("1409420604"), 142 XE_RTP_RULES(PLATFORM(DG1)), 143 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS)) 144 }, 145 { XE_RTP_NAME("1408615072"), 146 XE_RTP_RULES(PLATFORM(DG1)), 147 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE2_DIS)) 148 }, 149 150 /* DG2 */ 151 152 { XE_RTP_NAME("22010523718"), 153 XE_RTP_RULES(SUBPLATFORM(DG2, G10)), 154 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS)) 155 }, 156 { XE_RTP_NAME("14011006942"), 157 XE_RTP_RULES(SUBPLATFORM(DG2, G10)), 158 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS)) 159 }, 160 { XE_RTP_NAME("14014830051"), 161 XE_RTP_RULES(PLATFORM(DG2)), 162 XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN)) 163 }, 164 { XE_RTP_NAME("18018781329"), 165 XE_RTP_RULES(PLATFORM(DG2)), 166 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB), 167 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB), 168 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB), 169 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB)) 170 }, 171 { XE_RTP_NAME("1509235366"), 172 XE_RTP_RULES(PLATFORM(DG2)), 173 XE_RTP_ACTIONS(SET(XEHP_GAMCNTRL_CTRL, 174 INVALIDATION_BROADCAST_MODE_DIS | 175 GLOBAL_INVALIDATION_MODE)) 176 }, 177 178 /* PVC */ 179 180 { XE_RTP_NAME("18018781329"), 181 XE_RTP_RULES(PLATFORM(PVC)), 182 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB), 183 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB), 184 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB), 185 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB)) 186 }, 187 { XE_RTP_NAME("16016694945"), 188 XE_RTP_RULES(PLATFORM(PVC)), 189 XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC)) 190 }, 191 192 /* Xe_LPG */ 193 194 { XE_RTP_NAME("14015795083"), 195 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)), 196 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE)) 197 }, 198 { XE_RTP_NAME("14018575942"), 199 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 200 XE_RTP_ACTIONS(SET(COMP_MOD_CTRL, FORCE_MISS_FTLB)) 201 }, 202 { XE_RTP_NAME("22016670082"), 203 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 204 XE_RTP_ACTIONS(SET(SQCNT1, ENFORCE_RAR)) 205 }, 206 207 /* Xe_LPM+ */ 208 209 { XE_RTP_NAME("16021867713"), 210 XE_RTP_RULES(MEDIA_VERSION(1300), 211 ENGINE_CLASS(VIDEO_DECODE)), 212 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 213 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 214 }, 215 { XE_RTP_NAME("22016670082"), 216 XE_RTP_RULES(MEDIA_VERSION(1300)), 217 XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR)) 218 }, 219 220 /* Xe2_LPM */ 221 222 { XE_RTP_NAME("14017421178"), 223 XE_RTP_RULES(MEDIA_VERSION(2000), 224 ENGINE_CLASS(VIDEO_DECODE)), 225 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 226 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 227 }, 228 { XE_RTP_NAME("16021867713"), 229 XE_RTP_RULES(MEDIA_VERSION(2000), 230 ENGINE_CLASS(VIDEO_DECODE)), 231 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 232 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 233 }, 234 { XE_RTP_NAME("14019449301"), 235 XE_RTP_RULES(MEDIA_VERSION(2000), ENGINE_CLASS(VIDEO_DECODE)), 236 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)), 237 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 238 }, 239 240 /* Xe2_HPG */ 241 242 { XE_RTP_NAME("16025250150"), 243 XE_RTP_RULES(GRAPHICS_VERSION(2001)), 244 XE_RTP_ACTIONS(FIELD_SET(LSN_VC_REG2, 245 LSN_LNI_WGT_MASK | LSN_LNE_WGT_MASK | 246 LSN_DIM_X_WGT_MASK | LSN_DIM_Y_WGT_MASK | 247 LSN_DIM_Z_WGT_MASK, 248 LSN_LNI_WGT(1) | LSN_LNE_WGT(1) | 249 LSN_DIM_X_WGT(1) | LSN_DIM_Y_WGT(1) | 250 LSN_DIM_Z_WGT(1)), 251 SET(LSC_CHICKEN_BIT_0_UDW, L3_128B_256B_WRT_DIS)) 252 }, 253 254 /* Xe2_HPM */ 255 256 { XE_RTP_NAME("16021867713"), 257 XE_RTP_RULES(MEDIA_VERSION(1301), 258 ENGINE_CLASS(VIDEO_DECODE)), 259 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 260 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 261 }, 262 { XE_RTP_NAME("14019449301"), 263 XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)), 264 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)), 265 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 266 }, 267 268 /* Xe3_LPG */ 269 270 { XE_RTP_NAME("14021871409"), 271 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)), 272 XE_RTP_ACTIONS(SET(UNSLCGCTL9454, LSCFE_CLKGATE_DIS)) 273 }, 274 275 /* Xe3_LPM */ 276 277 { XE_RTP_NAME("16021867713"), 278 XE_RTP_RULES(MEDIA_VERSION(3000), 279 ENGINE_CLASS(VIDEO_DECODE)), 280 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 281 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 282 }, 283 { XE_RTP_NAME("16021865536"), 284 XE_RTP_RULES(MEDIA_VERSION(3000), 285 ENGINE_CLASS(VIDEO_DECODE)), 286 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 287 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 288 }, 289 { XE_RTP_NAME("16021865536"), 290 XE_RTP_RULES(MEDIA_VERSION(3002), 291 ENGINE_CLASS(VIDEO_DECODE)), 292 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 293 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 294 }, 295 { XE_RTP_NAME("16021867713"), 296 XE_RTP_RULES(MEDIA_VERSION(3002), 297 ENGINE_CLASS(VIDEO_DECODE)), 298 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 299 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 300 }, 301 { XE_RTP_NAME("14021486841"), 302 XE_RTP_RULES(MEDIA_VERSION(3000), MEDIA_STEP(A0, B0), 303 ENGINE_CLASS(VIDEO_DECODE)), 304 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), RAMDFTUNIT_CLKGATE_DIS)), 305 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 306 }, 307 { XE_RTP_NAME("16028005424"), 308 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005)), 309 XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES)) 310 }, 311 }; 312 313 static const struct xe_rtp_entry_sr engine_was[] = { 314 { XE_RTP_NAME("22010931296, 18011464164, 14010919138"), 315 XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)), 316 XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE), 317 FF_TESSELATION_DOP_GATE_DISABLE)) 318 }, 319 { XE_RTP_NAME("1409804808"), 320 XE_RTP_RULES(GRAPHICS_VERSION(1200), 321 ENGINE_CLASS(RENDER), 322 IS_INTEGRATED), 323 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS)) 324 }, 325 { XE_RTP_NAME("14010229206, 1409085225"), 326 XE_RTP_RULES(GRAPHICS_VERSION(1200), 327 ENGINE_CLASS(RENDER), 328 IS_INTEGRATED), 329 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 330 }, 331 { XE_RTP_NAME("1606931601"), 332 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 333 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ)) 334 }, 335 { XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"), 336 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)), 337 XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1(RENDER_RING_BASE), 338 FF_DOP_CLOCK_GATE_DISABLE)) 339 }, 340 { XE_RTP_NAME("1406941453"), 341 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 342 XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL)) 343 }, 344 { XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"), 345 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)), 346 XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1(RENDER_RING_BASE), 347 FFSC_PERCTX_PREEMPT_CTRL)) 348 }, 349 350 /* TGL */ 351 352 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 353 XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)), 354 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 355 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 356 RC_SEMA_IDLE_MSG_DISABLE)) 357 }, 358 359 /* RKL */ 360 361 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 362 XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)), 363 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 364 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 365 RC_SEMA_IDLE_MSG_DISABLE)) 366 }, 367 368 /* ADL-P */ 369 370 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 371 XE_RTP_RULES(PLATFORM(ALDERLAKE_P), ENGINE_CLASS(RENDER)), 372 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 373 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 374 RC_SEMA_IDLE_MSG_DISABLE)) 375 }, 376 377 /* DG2 */ 378 379 { XE_RTP_NAME("22013037850"), 380 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 381 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, 382 DISABLE_128B_EVICTION_COMMAND_UDW)) 383 }, 384 { XE_RTP_NAME("22014226127"), 385 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 386 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE)) 387 }, 388 { XE_RTP_NAME("18017747507"), 389 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 390 XE_RTP_ACTIONS(SET(VFG_PREEMPTION_CHICKEN, 391 POLYGON_TRIFAN_LINELOOP_DISABLE)) 392 }, 393 { XE_RTP_NAME("22012826095, 22013059131"), 394 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 395 FUNC(xe_rtp_match_first_render_or_compute)), 396 XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW, 397 MAXREQS_PER_BANK, 398 REG_FIELD_PREP(MAXREQS_PER_BANK, 2))) 399 }, 400 { XE_RTP_NAME("22013059131"), 401 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 402 FUNC(xe_rtp_match_first_render_or_compute)), 403 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT)) 404 }, 405 { XE_RTP_NAME("14015227452"), 406 XE_RTP_RULES(PLATFORM(DG2), 407 FUNC(xe_rtp_match_first_render_or_compute)), 408 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE)) 409 }, 410 { XE_RTP_NAME("18028616096"), 411 XE_RTP_RULES(PLATFORM(DG2), 412 FUNC(xe_rtp_match_first_render_or_compute)), 413 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3)) 414 }, 415 { XE_RTP_NAME("22015475538"), 416 XE_RTP_RULES(PLATFORM(DG2), 417 FUNC(xe_rtp_match_first_render_or_compute)), 418 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8)) 419 }, 420 { XE_RTP_NAME("22012654132"), 421 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 422 FUNC(xe_rtp_match_first_render_or_compute)), 423 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC, 424 /* 425 * Register can't be read back for verification on 426 * DG2 due to Wa_14012342262 427 */ 428 .read_mask = 0)) 429 }, 430 { XE_RTP_NAME("1509727124"), 431 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 432 XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB)) 433 }, 434 { XE_RTP_NAME("22012856258"), 435 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 436 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION)) 437 }, 438 { XE_RTP_NAME("22010960976, 14013347512"), 439 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 440 XE_RTP_ACTIONS(CLR(XEHP_HDC_CHICKEN0, 441 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK)) 442 }, 443 { XE_RTP_NAME("14015150844"), 444 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 445 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES, 446 XE_RTP_NOCHECK)) 447 }, 448 449 /* PVC */ 450 451 { XE_RTP_NAME("22014226127"), 452 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)), 453 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE)) 454 }, 455 { XE_RTP_NAME("14015227452"), 456 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)), 457 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE)) 458 }, 459 { XE_RTP_NAME("18020744125"), 460 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute), 461 ENGINE_CLASS(COMPUTE)), 462 XE_RTP_ACTIONS(SET(RING_HWSTAM(RENDER_RING_BASE), ~0)) 463 }, 464 { XE_RTP_NAME("14014999345"), 465 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COMPUTE), 466 GRAPHICS_STEP(B0, C0)), 467 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC)) 468 }, 469 470 /* Xe_LPG */ 471 472 { XE_RTP_NAME("14017856879"), 473 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), 474 FUNC(xe_rtp_match_first_render_or_compute)), 475 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_FIX_EOT1_FLUSH)) 476 }, 477 { XE_RTP_NAME("14015150844"), 478 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), 479 FUNC(xe_rtp_match_first_render_or_compute)), 480 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES, 481 XE_RTP_NOCHECK)) 482 }, 483 { XE_RTP_NAME("14020495402"), 484 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), 485 FUNC(xe_rtp_match_first_render_or_compute)), 486 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_TDL_SVHS_GATING)) 487 }, 488 489 /* Xe2_LPG */ 490 491 { XE_RTP_NAME("18032247524"), 492 XE_RTP_RULES(GRAPHICS_VERSION(2004), 493 FUNC(xe_rtp_match_first_render_or_compute)), 494 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE)) 495 }, 496 { XE_RTP_NAME("16018712365"), 497 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 498 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS)) 499 }, 500 { XE_RTP_NAME("14020338487"), 501 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 502 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS)) 503 }, 504 { XE_RTP_NAME("18034896535, 16021540221"), /* 16021540221: GRAPHICS_STEP(A0, B0) */ 505 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), 506 FUNC(xe_rtp_match_first_render_or_compute)), 507 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 508 }, 509 { XE_RTP_NAME("14018471104"), 510 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 511 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL)) 512 }, 513 /* 514 * These two workarounds are the same, just applying to different 515 * engines. Although Wa_18032095049 (for the RCS) isn't required on 516 * all steppings, disabling these reports has no impact for our 517 * driver or the GuC, so we go ahead and treat it the same as 518 * Wa_16021639441 which does apply to all steppings. 519 */ 520 { XE_RTP_NAME("18032095049, 16021639441"), 521 XE_RTP_RULES(GRAPHICS_VERSION(2004)), 522 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 523 GHWSP_CSB_REPORT_DIS | 524 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 525 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 526 }, 527 { XE_RTP_NAME("16018610683"), 528 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 529 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE)) 530 }, 531 { XE_RTP_NAME("14021402888"), 532 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 533 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 534 }, 535 { XE_RTP_NAME("13012615864"), 536 XE_RTP_RULES(GRAPHICS_VERSION(2004), 537 FUNC(xe_rtp_match_first_render_or_compute)), 538 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS)) 539 }, 540 541 /* Xe2_HPG */ 542 543 { XE_RTP_NAME("16018712365"), 544 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 545 FUNC(xe_rtp_match_first_render_or_compute)), 546 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS)) 547 }, 548 { XE_RTP_NAME("16018737384"), 549 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED), 550 FUNC(xe_rtp_match_first_render_or_compute)), 551 XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS)) 552 }, 553 { XE_RTP_NAME("14020338487"), 554 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 555 FUNC(xe_rtp_match_first_render_or_compute)), 556 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS)) 557 }, 558 { XE_RTP_NAME("18032247524"), 559 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 560 FUNC(xe_rtp_match_first_render_or_compute)), 561 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE)) 562 }, 563 { XE_RTP_NAME("14018471104"), 564 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 565 FUNC(xe_rtp_match_first_render_or_compute)), 566 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL)) 567 }, 568 /* 569 * Although this workaround isn't required for the RCS, disabling these 570 * reports has no impact for our driver or the GuC, so we go ahead and 571 * apply this to all engines for simplicity. 572 */ 573 { XE_RTP_NAME("16021639441"), 574 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002)), 575 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 576 GHWSP_CSB_REPORT_DIS | 577 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 578 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 579 }, 580 { XE_RTP_NAME("14019811474"), 581 XE_RTP_RULES(GRAPHICS_VERSION(2001), 582 FUNC(xe_rtp_match_first_render_or_compute)), 583 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS)) 584 }, 585 { XE_RTP_NAME("14021402888"), 586 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 587 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 588 }, 589 { XE_RTP_NAME("14021821874, 14022954250"), 590 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 591 FUNC(xe_rtp_match_first_render_or_compute)), 592 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, STK_ID_RESTRICT)) 593 }, 594 { XE_RTP_NAME("13012615864"), 595 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 596 FUNC(xe_rtp_match_first_render_or_compute)), 597 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS)) 598 }, 599 { XE_RTP_NAME("18041344222"), 600 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 601 FUNC(xe_rtp_match_first_render_or_compute), 602 FUNC(xe_rtp_match_not_sriov_vf), 603 FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)), 604 XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE)) 605 }, 606 607 /* Xe2_LPM */ 608 609 { XE_RTP_NAME("16021639441"), 610 XE_RTP_RULES(MEDIA_VERSION(2000)), 611 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 612 GHWSP_CSB_REPORT_DIS | 613 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 614 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 615 }, 616 617 /* Xe2_HPM */ 618 619 { XE_RTP_NAME("16021639441"), 620 XE_RTP_RULES(MEDIA_VERSION(1301)), 621 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 622 GHWSP_CSB_REPORT_DIS | 623 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 624 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 625 }, 626 627 /* Xe3_LPG */ 628 629 { XE_RTP_NAME("14021402888"), 630 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), 631 FUNC(xe_rtp_match_first_render_or_compute)), 632 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 633 }, 634 { XE_RTP_NAME("18034896535"), 635 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 636 FUNC(xe_rtp_match_first_render_or_compute)), 637 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 638 }, 639 { XE_RTP_NAME("16024792527"), 640 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 641 FUNC(xe_rtp_match_first_render_or_compute)), 642 XE_RTP_ACTIONS(FIELD_SET(SAMPLER_MODE, SMP_WAIT_FETCH_MERGING_COUNTER, 643 SMP_FORCE_128B_OVERFETCH)) 644 }, 645 { XE_RTP_NAME("14023061436"), 646 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), 647 FUNC(xe_rtp_match_first_render_or_compute), OR, 648 GRAPHICS_VERSION_RANGE(3003, 3005), 649 FUNC(xe_rtp_match_first_render_or_compute)), 650 XE_RTP_ACTIONS(SET(TDL_CHICKEN, QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE)) 651 }, 652 { XE_RTP_NAME("13012615864"), 653 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), OR, 654 GRAPHICS_VERSION_RANGE(3003, 3005), 655 FUNC(xe_rtp_match_first_render_or_compute)), 656 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS)) 657 }, 658 { XE_RTP_NAME("16023105232"), 659 XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 3000), OR, 660 GRAPHICS_VERSION_RANGE(2001, 3001)), 661 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(0), RC_SEMA_IDLE_MSG_DISABLE, 662 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 663 }, 664 { XE_RTP_NAME("14021402888"), 665 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3003, 3005), FUNC(xe_rtp_match_first_render_or_compute)), 666 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 667 }, 668 { XE_RTP_NAME("18041344222"), 669 XE_RTP_RULES(GRAPHICS_VERSION(3000), 670 FUNC(xe_rtp_match_first_render_or_compute), 671 FUNC(xe_rtp_match_not_sriov_vf), 672 FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)), 673 XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE)) 674 }, 675 }; 676 677 static const struct xe_rtp_entry_sr lrc_was[] = { 678 { XE_RTP_NAME("16011163337"), 679 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 680 /* read verification is ignored due to 1608008084. */ 681 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2, 682 FF_MODE2_GS_TIMER_MASK, 683 FF_MODE2_GS_TIMER_224)) 684 }, 685 { XE_RTP_NAME("1604555607"), 686 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 687 /* read verification is ignored due to 1608008084. */ 688 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2, 689 FF_MODE2_TDS_TIMER_MASK, 690 FF_MODE2_TDS_TIMER_128)) 691 }, 692 { XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"), 693 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 694 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN3, 695 DISABLE_CPS_AWARE_COLOR_PIPE)) 696 }, 697 { XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"), 698 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 699 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(RENDER_RING_BASE), 700 PREEMPT_GPGPU_LEVEL_MASK, 701 PREEMPT_GPGPU_THREAD_GROUP_LEVEL)) 702 }, 703 { XE_RTP_NAME("1806527549"), 704 XE_RTP_RULES(GRAPHICS_VERSION(1200)), 705 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE)) 706 }, 707 { XE_RTP_NAME("1606376872"), 708 XE_RTP_RULES(GRAPHICS_VERSION(1200)), 709 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC)) 710 }, 711 712 /* DG1 */ 713 714 { XE_RTP_NAME("1409044764"), 715 XE_RTP_RULES(PLATFORM(DG1)), 716 XE_RTP_ACTIONS(CLR(COMMON_SLICE_CHICKEN3, 717 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN)) 718 }, 719 { XE_RTP_NAME("22010493298"), 720 XE_RTP_RULES(PLATFORM(DG1)), 721 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, 722 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE)) 723 }, 724 725 /* DG2 */ 726 727 { XE_RTP_NAME("16013271637"), 728 XE_RTP_RULES(PLATFORM(DG2)), 729 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1, 730 MSC_MSAA_REODER_BUF_BYPASS_DISABLE)) 731 }, 732 { XE_RTP_NAME("14014947963"), 733 XE_RTP_RULES(PLATFORM(DG2)), 734 XE_RTP_ACTIONS(FIELD_SET(VF_PREEMPTION, 735 PREEMPTION_VERTEX_COUNT, 736 0x4000)) 737 }, 738 { XE_RTP_NAME("18018764978"), 739 XE_RTP_RULES(PLATFORM(DG2)), 740 XE_RTP_ACTIONS(SET(XEHP_PSS_MODE2, 741 SCOREBOARD_STALL_FLUSH_CONTROL)) 742 }, 743 { XE_RTP_NAME("18019271663"), 744 XE_RTP_RULES(PLATFORM(DG2)), 745 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE)) 746 }, 747 { XE_RTP_NAME("14019877138"), 748 XE_RTP_RULES(PLATFORM(DG2)), 749 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 750 }, 751 752 /* PVC */ 753 754 { XE_RTP_NAME("16017236439"), 755 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY), 756 FUNC(xe_rtp_match_even_instance)), 757 XE_RTP_ACTIONS(SET(BCS_SWCTRL(0), 758 BCS_SWCTRL_DISABLE_256B, 759 XE_RTP_ACTION_FLAG(ENGINE_BASE))), 760 }, 761 762 /* Xe_LPG */ 763 764 { XE_RTP_NAME("18019271663"), 765 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 766 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE)) 767 }, 768 { XE_RTP_NAME("14019877138"), 769 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), ENGINE_CLASS(RENDER)), 770 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 771 }, 772 773 /* Xe2_LPG */ 774 775 { XE_RTP_NAME("14019386621"), 776 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 777 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE)) 778 }, 779 { XE_RTP_NAME("14019877138"), 780 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 781 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 782 }, 783 { XE_RTP_NAME("14019988906"), 784 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 785 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD)) 786 }, 787 { XE_RTP_NAME("18033852989"), 788 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 789 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST)) 790 }, 791 { XE_RTP_NAME("14021567978"), 792 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED), 793 ENGINE_CLASS(RENDER)), 794 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP)) 795 }, 796 { XE_RTP_NAME("14020756599"), 797 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER), OR, 798 MEDIA_VERSION_ANY_GT(2000), ENGINE_CLASS(RENDER)), 799 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) 800 }, 801 { XE_RTP_NAME("14021490052"), 802 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 803 XE_RTP_ACTIONS(SET(FF_MODE, 804 DIS_MESH_PARTIAL_AUTOSTRIP | 805 DIS_MESH_AUTOSTRIP), 806 SET(VFLSKPD, 807 DIS_PARTIAL_AUTOSTRIP | 808 DIS_AUTOSTRIP)) 809 }, 810 { XE_RTP_NAME("15016589081"), 811 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 812 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX)) 813 }, 814 815 /* Xe2_HPG */ 816 { XE_RTP_NAME("15010599737"), 817 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 818 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN)) 819 }, 820 { XE_RTP_NAME("14019386621"), 821 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 822 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE)) 823 }, 824 { XE_RTP_NAME("14020756599"), 825 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 826 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) 827 }, 828 { XE_RTP_NAME("14019988906"), 829 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 830 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD)) 831 }, 832 { XE_RTP_NAME("14019877138"), 833 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 834 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 835 }, 836 { XE_RTP_NAME("14021490052"), 837 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 838 XE_RTP_ACTIONS(SET(FF_MODE, 839 DIS_MESH_PARTIAL_AUTOSTRIP | 840 DIS_MESH_AUTOSTRIP), 841 SET(VFLSKPD, 842 DIS_PARTIAL_AUTOSTRIP | 843 DIS_AUTOSTRIP)) 844 }, 845 { XE_RTP_NAME("15016589081"), 846 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 847 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX)) 848 }, 849 { XE_RTP_NAME("22021007897"), 850 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 851 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE)) 852 }, 853 { XE_RTP_NAME("18033852989"), 854 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 855 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST)) 856 }, 857 858 /* Xe3_LPG */ 859 { XE_RTP_NAME("14021490052"), 860 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 861 ENGINE_CLASS(RENDER)), 862 XE_RTP_ACTIONS(SET(FF_MODE, 863 DIS_MESH_PARTIAL_AUTOSTRIP | 864 DIS_MESH_AUTOSTRIP), 865 SET(VFLSKPD, 866 DIS_PARTIAL_AUTOSTRIP | 867 DIS_AUTOSTRIP)) 868 }, 869 { XE_RTP_NAME("22021007897"), 870 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), ENGINE_CLASS(RENDER)), 871 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE)) 872 }, 873 { XE_RTP_NAME("14024681466"), 874 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), ENGINE_CLASS(RENDER)), 875 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1, FAST_CLEAR_VALIGN_FIX)) 876 }, 877 { XE_RTP_NAME("15016589081"), 878 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 879 ENGINE_CLASS(RENDER)), 880 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX)) 881 }, 882 }; 883 884 static __maybe_unused const struct xe_rtp_entry oob_was[] = { 885 #include <generated/xe_wa_oob.c> 886 {} 887 }; 888 889 static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT); 890 891 static __maybe_unused const struct xe_rtp_entry device_oob_was[] = { 892 #include <generated/xe_device_wa_oob.c> 893 {} 894 }; 895 896 static_assert(ARRAY_SIZE(device_oob_was) - 1 == _XE_DEVICE_WA_OOB_COUNT); 897 898 __diag_pop(); 899 900 /** 901 * xe_wa_process_device_oob - process OOB workaround table 902 * @xe: device instance to process workarounds for 903 * 904 * process OOB workaround table for this device, marking in @xe the 905 * workarounds that are active. 906 */ 907 908 void xe_wa_process_device_oob(struct xe_device *xe) 909 { 910 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(xe); 911 912 xe_rtp_process_ctx_enable_active_tracking(&ctx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was)); 913 914 xe->wa_active.oob_initialized = true; 915 xe_rtp_process(&ctx, device_oob_was); 916 } 917 918 /** 919 * xe_wa_process_gt_oob - process GT OOB workaround table 920 * @gt: GT instance to process workarounds for 921 * 922 * Process OOB workaround table for this platform, marking in @gt the 923 * workarounds that are active. 924 */ 925 void xe_wa_process_gt_oob(struct xe_gt *gt) 926 { 927 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt); 928 929 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob, 930 ARRAY_SIZE(oob_was)); 931 gt->wa_active.oob_initialized = true; 932 xe_rtp_process(&ctx, oob_was); 933 } 934 935 /** 936 * xe_wa_process_gt - process GT workaround table 937 * @gt: GT instance to process workarounds for 938 * 939 * Process GT workaround table for this platform, saving in @gt all the 940 * workarounds that need to be applied at the GT level. 941 */ 942 void xe_wa_process_gt(struct xe_gt *gt) 943 { 944 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt); 945 946 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.gt, 947 ARRAY_SIZE(gt_was)); 948 xe_rtp_process_to_sr(&ctx, gt_was, ARRAY_SIZE(gt_was), >->reg_sr); 949 } 950 EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt); 951 952 /** 953 * xe_wa_process_engine - process engine workaround table 954 * @hwe: engine instance to process workarounds for 955 * 956 * Process engine workaround table for this platform, saving in @hwe all the 957 * workarounds that need to be applied at the engine level that match this 958 * engine. 959 */ 960 void xe_wa_process_engine(struct xe_hw_engine *hwe) 961 { 962 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 963 964 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.engine, 965 ARRAY_SIZE(engine_was)); 966 xe_rtp_process_to_sr(&ctx, engine_was, ARRAY_SIZE(engine_was), &hwe->reg_sr); 967 } 968 969 /** 970 * xe_wa_process_lrc - process context workaround table 971 * @hwe: engine instance to process workarounds for 972 * 973 * Process context workaround table for this platform, saving in @hwe all the 974 * workarounds that need to be applied on context restore. These are workarounds 975 * touching registers that are part of the HW context image. 976 */ 977 void xe_wa_process_lrc(struct xe_hw_engine *hwe) 978 { 979 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 980 981 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.lrc, 982 ARRAY_SIZE(lrc_was)); 983 xe_rtp_process_to_sr(&ctx, lrc_was, ARRAY_SIZE(lrc_was), &hwe->reg_lrc); 984 } 985 986 /** 987 * xe_wa_device_init - initialize device with workaround oob bookkeeping 988 * @xe: Xe device instance to initialize 989 * 990 * Returns 0 for success, negative with error code otherwise 991 */ 992 int xe_wa_device_init(struct xe_device *xe) 993 { 994 unsigned long *p; 995 996 p = drmm_kzalloc(&xe->drm, 997 sizeof(*p) * BITS_TO_LONGS(ARRAY_SIZE(device_oob_was)), 998 GFP_KERNEL); 999 1000 if (!p) 1001 return -ENOMEM; 1002 1003 xe->wa_active.oob = p; 1004 1005 return 0; 1006 } 1007 1008 /** 1009 * xe_wa_gt_init - initialize gt with workaround bookkeeping 1010 * @gt: GT instance to initialize 1011 * 1012 * Returns 0 for success, negative error code otherwise. 1013 */ 1014 int xe_wa_gt_init(struct xe_gt *gt) 1015 { 1016 struct xe_device *xe = gt_to_xe(gt); 1017 size_t n_oob, n_lrc, n_engine, n_gt, total; 1018 unsigned long *p; 1019 1020 n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was)); 1021 n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was)); 1022 n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was)); 1023 n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was)); 1024 total = n_gt + n_engine + n_lrc + n_oob; 1025 1026 p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL); 1027 if (!p) 1028 return -ENOMEM; 1029 1030 gt->wa_active.gt = p; 1031 p += n_gt; 1032 gt->wa_active.engine = p; 1033 p += n_engine; 1034 gt->wa_active.lrc = p; 1035 p += n_lrc; 1036 gt->wa_active.oob = p; 1037 1038 return 0; 1039 } 1040 ALLOW_ERROR_INJECTION(xe_wa_gt_init, ERRNO); /* See xe_pci_probe() */ 1041 1042 void xe_wa_device_dump(struct xe_device *xe, struct drm_printer *p) 1043 { 1044 size_t idx; 1045 1046 drm_printf(p, "Device OOB Workarounds\n"); 1047 for_each_set_bit(idx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was)) 1048 if (device_oob_was[idx].name) 1049 drm_printf_indent(p, 1, "%s\n", device_oob_was[idx].name); 1050 } 1051 1052 /** 1053 * xe_wa_gt_dump() - Dump GT workarounds into a drm printer. 1054 * @gt: the &xe_gt 1055 * @p: the &drm_printer 1056 * 1057 * Return: always 0. 1058 */ 1059 int xe_wa_gt_dump(struct xe_gt *gt, struct drm_printer *p) 1060 { 1061 size_t idx; 1062 1063 drm_printf(p, "GT Workarounds\n"); 1064 for_each_set_bit(idx, gt->wa_active.gt, ARRAY_SIZE(gt_was)) 1065 drm_printf_indent(p, 1, "%s\n", gt_was[idx].name); 1066 1067 drm_puts(p, "\n"); 1068 drm_printf(p, "Engine Workarounds\n"); 1069 for_each_set_bit(idx, gt->wa_active.engine, ARRAY_SIZE(engine_was)) 1070 drm_printf_indent(p, 1, "%s\n", engine_was[idx].name); 1071 1072 drm_puts(p, "\n"); 1073 drm_printf(p, "LRC Workarounds\n"); 1074 for_each_set_bit(idx, gt->wa_active.lrc, ARRAY_SIZE(lrc_was)) 1075 drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name); 1076 1077 drm_puts(p, "\n"); 1078 drm_printf(p, "OOB Workarounds\n"); 1079 for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was)) 1080 if (oob_was[idx].name) 1081 drm_printf_indent(p, 1, "%s\n", oob_was[idx].name); 1082 return 0; 1083 } 1084 1085 /* 1086 * Apply tile (non-GT, non-display) workarounds. Think very carefully before 1087 * adding anything to this function; most workarounds should be implemented 1088 * elsewhere. The programming here is primarily for sgunit/soc workarounds, 1089 * which are relatively rare. Since the registers these workarounds target are 1090 * outside the GT, they should only need to be applied once at device 1091 * probe/resume; they will not lose their values on any kind of GT or engine 1092 * reset. 1093 * 1094 * TODO: We may want to move this over to xe_rtp in the future once we have 1095 * enough workarounds to justify the work. 1096 */ 1097 void xe_wa_apply_tile_workarounds(struct xe_tile *tile) 1098 { 1099 struct xe_mmio *mmio = &tile->mmio; 1100 1101 if (IS_SRIOV_VF(tile->xe)) 1102 return; 1103 1104 if (XE_DEVICE_WA(tile->xe, 22010954014)) 1105 xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS); 1106 } 1107