1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /* Copyright 2017-2019 NXP */
3
4 #include <linux/unaligned.h>
5 #include <linux/module.h>
6 #include <linux/of.h>
7 #include <linux/of_platform.h>
8 #include <linux/of_net.h>
9 #include <linux/pcs-lynx.h>
10 #include "enetc_ierb.h"
11 #include "enetc_pf_common.h"
12
13 #define ENETC_DRV_NAME_STR "ENETC PF driver"
14
enetc_pf_get_primary_mac_addr(struct enetc_hw * hw,int si,u8 * addr)15 static void enetc_pf_get_primary_mac_addr(struct enetc_hw *hw, int si, u8 *addr)
16 {
17 u32 upper = __raw_readl(hw->port + ENETC_PSIPMAR0(si));
18 u16 lower = __raw_readw(hw->port + ENETC_PSIPMAR1(si));
19
20 put_unaligned_le32(upper, addr);
21 put_unaligned_le16(lower, addr + 4);
22 }
23
enetc_pf_set_primary_mac_addr(struct enetc_hw * hw,int si,const u8 * addr)24 static void enetc_pf_set_primary_mac_addr(struct enetc_hw *hw, int si,
25 const u8 *addr)
26 {
27 u32 upper = get_unaligned_le32(addr);
28 u16 lower = get_unaligned_le16(addr + 4);
29
30 __raw_writel(upper, hw->port + ENETC_PSIPMAR0(si));
31 __raw_writew(lower, hw->port + ENETC_PSIPMAR1(si));
32 }
33
enetc_pf_create_pcs(struct enetc_pf * pf,struct mii_bus * bus)34 static struct phylink_pcs *enetc_pf_create_pcs(struct enetc_pf *pf,
35 struct mii_bus *bus)
36 {
37 return lynx_pcs_create_mdiodev(bus, 0);
38 }
39
enetc_pf_destroy_pcs(struct phylink_pcs * pcs)40 static void enetc_pf_destroy_pcs(struct phylink_pcs *pcs)
41 {
42 lynx_pcs_destroy(pcs);
43 }
44
enetc_set_vlan_promisc(struct enetc_hw * hw,char si_map)45 static void enetc_set_vlan_promisc(struct enetc_hw *hw, char si_map)
46 {
47 u32 val = enetc_port_rd(hw, ENETC_PSIPVMR);
48
49 val &= ~ENETC_PSIPVMR_SET_VP(ENETC_VLAN_PROMISC_MAP_ALL);
50 enetc_port_wr(hw, ENETC_PSIPVMR, ENETC_PSIPVMR_SET_VP(si_map) | val);
51 }
52
enetc_enable_si_vlan_promisc(struct enetc_pf * pf,int si_idx)53 static void enetc_enable_si_vlan_promisc(struct enetc_pf *pf, int si_idx)
54 {
55 pf->vlan_promisc_simap |= BIT(si_idx);
56 enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap);
57 }
58
enetc_disable_si_vlan_promisc(struct enetc_pf * pf,int si_idx)59 static void enetc_disable_si_vlan_promisc(struct enetc_pf *pf, int si_idx)
60 {
61 pf->vlan_promisc_simap &= ~BIT(si_idx);
62 enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap);
63 }
64
enetc_set_isol_vlan(struct enetc_hw * hw,int si,u16 vlan,u8 qos)65 static void enetc_set_isol_vlan(struct enetc_hw *hw, int si, u16 vlan, u8 qos)
66 {
67 u32 val = 0;
68
69 if (vlan)
70 val = ENETC_PSIVLAN_EN | ENETC_PSIVLAN_SET_QOS(qos) | vlan;
71
72 enetc_port_wr(hw, ENETC_PSIVLANR(si), val);
73 }
74
enetc_add_mac_addr_em_filter(struct enetc_mac_filter * filter,const unsigned char * addr)75 static void enetc_add_mac_addr_em_filter(struct enetc_mac_filter *filter,
76 const unsigned char *addr)
77 {
78 /* add exact match addr */
79 ether_addr_copy(filter->mac_addr, addr);
80 filter->mac_addr_cnt++;
81 }
82
enetc_clear_mac_ht_flt(struct enetc_si * si,int si_idx,int type)83 static void enetc_clear_mac_ht_flt(struct enetc_si *si, int si_idx, int type)
84 {
85 bool err = si->errata & ENETC_ERR_UCMCSWP;
86
87 if (type == UC) {
88 enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err), 0);
89 enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx), 0);
90 } else { /* MC */
91 enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err), 0);
92 enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx), 0);
93 }
94 }
95
enetc_set_mac_ht_flt(struct enetc_si * si,int si_idx,int type,unsigned long hash)96 static void enetc_set_mac_ht_flt(struct enetc_si *si, int si_idx, int type,
97 unsigned long hash)
98 {
99 bool err = si->errata & ENETC_ERR_UCMCSWP;
100
101 if (type == UC) {
102 enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err),
103 lower_32_bits(hash));
104 enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx),
105 upper_32_bits(hash));
106 } else { /* MC */
107 enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err),
108 lower_32_bits(hash));
109 enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx),
110 upper_32_bits(hash));
111 }
112 }
113
enetc_sync_mac_filters(struct enetc_pf * pf)114 static void enetc_sync_mac_filters(struct enetc_pf *pf)
115 {
116 struct enetc_mac_filter *f = pf->mac_filter;
117 struct enetc_si *si = pf->si;
118 int i, pos;
119
120 pos = EMETC_MAC_ADDR_FILT_RES;
121
122 for (i = 0; i < MADDR_TYPE; i++, f++) {
123 bool em = (f->mac_addr_cnt == 1) && (i == UC);
124 bool clear = !f->mac_addr_cnt;
125
126 if (clear) {
127 if (i == UC)
128 enetc_clear_mac_flt_entry(si, pos);
129
130 enetc_clear_mac_ht_flt(si, 0, i);
131 continue;
132 }
133
134 /* exact match filter */
135 if (em) {
136 int err;
137
138 enetc_clear_mac_ht_flt(si, 0, UC);
139
140 err = enetc_set_mac_flt_entry(si, pos, f->mac_addr,
141 BIT(0));
142 if (!err)
143 continue;
144
145 /* fallback to HT filtering */
146 dev_warn(&si->pdev->dev, "fallback to HT filt (%d)\n",
147 err);
148 }
149
150 /* hash table filter, clear EM filter for UC entries */
151 if (i == UC)
152 enetc_clear_mac_flt_entry(si, pos);
153
154 enetc_set_mac_ht_flt(si, 0, i, *f->mac_hash_table);
155 }
156 }
157
enetc_pf_set_rx_mode(struct net_device * ndev)158 static void enetc_pf_set_rx_mode(struct net_device *ndev)
159 {
160 struct enetc_ndev_priv *priv = netdev_priv(ndev);
161 struct enetc_pf *pf = enetc_si_priv(priv->si);
162 struct enetc_hw *hw = &priv->si->hw;
163 bool uprom = false, mprom = false;
164 struct enetc_mac_filter *filter;
165 struct netdev_hw_addr *ha;
166 u32 psipmr = 0;
167 bool em;
168
169 if (ndev->flags & IFF_PROMISC) {
170 /* enable promisc mode for SI0 (PF) */
171 psipmr = ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0);
172 uprom = true;
173 mprom = true;
174 } else if (ndev->flags & IFF_ALLMULTI) {
175 /* enable multi cast promisc mode for SI0 (PF) */
176 psipmr = ENETC_PSIPMR_SET_MP(0);
177 mprom = true;
178 }
179
180 /* first 2 filter entries belong to PF */
181 if (!uprom) {
182 /* Update unicast filters */
183 filter = &pf->mac_filter[UC];
184 enetc_reset_mac_addr_filter(filter);
185
186 em = (netdev_uc_count(ndev) == 1);
187 netdev_for_each_uc_addr(ha, ndev) {
188 if (em) {
189 enetc_add_mac_addr_em_filter(filter, ha->addr);
190 break;
191 }
192
193 enetc_add_mac_addr_ht_filter(filter, ha->addr);
194 }
195 }
196
197 if (!mprom) {
198 /* Update multicast filters */
199 filter = &pf->mac_filter[MC];
200 enetc_reset_mac_addr_filter(filter);
201
202 netdev_for_each_mc_addr(ha, ndev) {
203 if (!is_multicast_ether_addr(ha->addr))
204 continue;
205
206 enetc_add_mac_addr_ht_filter(filter, ha->addr);
207 }
208 }
209
210 if (!uprom || !mprom)
211 /* update PF entries */
212 enetc_sync_mac_filters(pf);
213
214 psipmr |= enetc_port_rd(hw, ENETC_PSIPMR) &
215 ~(ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0));
216 enetc_port_wr(hw, ENETC_PSIPMR, psipmr);
217 }
218
enetc_set_loopback(struct net_device * ndev,bool en)219 static void enetc_set_loopback(struct net_device *ndev, bool en)
220 {
221 struct enetc_ndev_priv *priv = netdev_priv(ndev);
222 struct enetc_si *si = priv->si;
223 u32 reg;
224
225 reg = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE);
226 if (reg & ENETC_PM0_IFM_RG) {
227 /* RGMII mode */
228 reg = (reg & ~ENETC_PM0_IFM_RLP) |
229 (en ? ENETC_PM0_IFM_RLP : 0);
230 enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, reg);
231 } else {
232 /* assume SGMII mode */
233 reg = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG);
234 reg = (reg & ~ENETC_PM0_CMD_XGLP) |
235 (en ? ENETC_PM0_CMD_XGLP : 0);
236 reg = (reg & ~ENETC_PM0_CMD_PHY_TX_EN) |
237 (en ? ENETC_PM0_CMD_PHY_TX_EN : 0);
238 enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, reg);
239 }
240 }
241
enetc_pf_set_vf_mac(struct net_device * ndev,int vf,u8 * mac)242 static int enetc_pf_set_vf_mac(struct net_device *ndev, int vf, u8 *mac)
243 {
244 struct enetc_ndev_priv *priv = netdev_priv(ndev);
245 struct enetc_pf *pf = enetc_si_priv(priv->si);
246 struct enetc_vf_state *vf_state;
247
248 if (vf >= pf->total_vfs)
249 return -EINVAL;
250
251 if (!is_valid_ether_addr(mac))
252 return -EADDRNOTAVAIL;
253
254 vf_state = &pf->vf_state[vf];
255
256 mutex_lock(&vf_state->lock);
257 vf_state->flags |= ENETC_VF_FLAG_PF_SET_MAC;
258 enetc_pf_set_primary_mac_addr(&priv->si->hw, vf + 1, mac);
259 mutex_unlock(&vf_state->lock);
260
261 return 0;
262 }
263
enetc_pf_set_vf_vlan(struct net_device * ndev,int vf,u16 vlan,u8 qos,__be16 proto)264 static int enetc_pf_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan,
265 u8 qos, __be16 proto)
266 {
267 struct enetc_ndev_priv *priv = netdev_priv(ndev);
268 struct enetc_pf *pf = enetc_si_priv(priv->si);
269
270 if (priv->si->errata & ENETC_ERR_VLAN_ISOL)
271 return -EOPNOTSUPP;
272
273 if (vf >= pf->total_vfs)
274 return -EINVAL;
275
276 if (proto != htons(ETH_P_8021Q))
277 /* only C-tags supported for now */
278 return -EPROTONOSUPPORT;
279
280 enetc_set_isol_vlan(&priv->si->hw, vf + 1, vlan, qos);
281 return 0;
282 }
283
enetc_pf_set_vf_spoofchk(struct net_device * ndev,int vf,bool en)284 static int enetc_pf_set_vf_spoofchk(struct net_device *ndev, int vf, bool en)
285 {
286 struct enetc_ndev_priv *priv = netdev_priv(ndev);
287 struct enetc_pf *pf = enetc_si_priv(priv->si);
288 u32 cfgr;
289
290 if (vf >= pf->total_vfs)
291 return -EINVAL;
292
293 cfgr = enetc_port_rd(&priv->si->hw, ENETC_PSICFGR0(vf + 1));
294 cfgr = (cfgr & ~ENETC_PSICFGR0_ASE) | (en ? ENETC_PSICFGR0_ASE : 0);
295 enetc_port_wr(&priv->si->hw, ENETC_PSICFGR0(vf + 1), cfgr);
296
297 return 0;
298 }
299
enetc_port_assign_rfs_entries(struct enetc_si * si)300 static void enetc_port_assign_rfs_entries(struct enetc_si *si)
301 {
302 struct enetc_pf *pf = enetc_si_priv(si);
303 struct enetc_hw *hw = &si->hw;
304 int num_entries, vf_entries, i;
305 u32 val;
306
307 /* split RFS entries between functions */
308 val = enetc_port_rd(hw, ENETC_PRFSCAPR);
309 num_entries = ENETC_PRFSCAPR_GET_NUM_RFS(val);
310 vf_entries = num_entries / (pf->total_vfs + 1);
311
312 for (i = 0; i < pf->total_vfs; i++)
313 enetc_port_wr(hw, ENETC_PSIRFSCFGR(i + 1), vf_entries);
314 enetc_port_wr(hw, ENETC_PSIRFSCFGR(0),
315 num_entries - vf_entries * pf->total_vfs);
316
317 /* enable RFS on port */
318 enetc_port_wr(hw, ENETC_PRFSMR, ENETC_PRFSMR_RFSE);
319 }
320
enetc_port_get_caps(struct enetc_si * si)321 static void enetc_port_get_caps(struct enetc_si *si)
322 {
323 struct enetc_hw *hw = &si->hw;
324 u32 val;
325
326 val = enetc_port_rd(hw, ENETC_PCAPR0);
327
328 if (val & ENETC_PCAPR0_QBV)
329 si->hw_features |= ENETC_SI_F_QBV;
330
331 if (val & ENETC_PCAPR0_QBU)
332 si->hw_features |= ENETC_SI_F_QBU;
333
334 if (val & ENETC_PCAPR0_PSFP)
335 si->hw_features |= ENETC_SI_F_PSFP;
336 }
337
enetc_port_si_configure(struct enetc_si * si)338 static void enetc_port_si_configure(struct enetc_si *si)
339 {
340 struct enetc_pf *pf = enetc_si_priv(si);
341 struct enetc_hw *hw = &si->hw;
342 int num_rings, i;
343 u32 val;
344
345 enetc_port_get_caps(si);
346
347 val = enetc_port_rd(hw, ENETC_PCAPR0);
348 num_rings = min(ENETC_PCAPR0_RXBDR(val), ENETC_PCAPR0_TXBDR(val));
349
350 val = ENETC_PSICFGR0_SET_TXBDR(ENETC_PF_NUM_RINGS);
351 val |= ENETC_PSICFGR0_SET_RXBDR(ENETC_PF_NUM_RINGS);
352
353 if (unlikely(num_rings < ENETC_PF_NUM_RINGS)) {
354 val = ENETC_PSICFGR0_SET_TXBDR(num_rings);
355 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings);
356
357 dev_warn(&si->pdev->dev, "Found %d rings, expected %d!\n",
358 num_rings, ENETC_PF_NUM_RINGS);
359
360 num_rings = 0;
361 }
362
363 /* Add default one-time settings for SI0 (PF) */
364 val |= ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
365
366 enetc_port_wr(hw, ENETC_PSICFGR0(0), val);
367
368 if (num_rings)
369 num_rings -= ENETC_PF_NUM_RINGS;
370
371 /* Configure the SIs for each available VF */
372 val = ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
373 val |= ENETC_PSICFGR0_VTE | ENETC_PSICFGR0_SIVIE;
374
375 if (num_rings) {
376 num_rings /= pf->total_vfs;
377 val |= ENETC_PSICFGR0_SET_TXBDR(num_rings);
378 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings);
379 }
380
381 for (i = 0; i < pf->total_vfs; i++)
382 enetc_port_wr(hw, ENETC_PSICFGR0(i + 1), val);
383
384 /* Port level VLAN settings */
385 val = ENETC_PVCLCTR_OVTPIDL(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
386 enetc_port_wr(hw, ENETC_PVCLCTR, val);
387 /* use outer tag for VLAN filtering */
388 enetc_port_wr(hw, ENETC_PSIVLANFMR, ENETC_PSIVLANFMR_VS);
389 }
390
enetc_set_ptcmsdur(struct enetc_hw * hw,u32 * max_sdu)391 void enetc_set_ptcmsdur(struct enetc_hw *hw, u32 *max_sdu)
392 {
393 int tc;
394
395 for (tc = 0; tc < 8; tc++) {
396 u32 val = ENETC_MAC_MAXFRM_SIZE;
397
398 if (max_sdu[tc])
399 val = max_sdu[tc] + VLAN_ETH_HLEN;
400
401 enetc_port_wr(hw, ENETC_PTCMSDUR(tc), val);
402 }
403 }
404
enetc_reset_ptcmsdur(struct enetc_hw * hw)405 void enetc_reset_ptcmsdur(struct enetc_hw *hw)
406 {
407 int tc;
408
409 for (tc = 0; tc < 8; tc++)
410 enetc_port_wr(hw, ENETC_PTCMSDUR(tc), ENETC_MAC_MAXFRM_SIZE);
411 }
412
enetc_configure_port_mac(struct enetc_si * si)413 static void enetc_configure_port_mac(struct enetc_si *si)
414 {
415 struct enetc_hw *hw = &si->hw;
416
417 enetc_port_mac_wr(si, ENETC_PM0_MAXFRM,
418 ENETC_SET_MAXFRM(ENETC_RX_MAXFRM_SIZE));
419
420 enetc_reset_ptcmsdur(hw);
421
422 enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN |
423 ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC);
424
425 /* On LS1028A, the MAC RX FIFO defaults to 2, which is too high
426 * and may lead to RX lock-up under traffic. Set it to 1 instead,
427 * as recommended by the hardware team.
428 */
429 enetc_port_mac_wr(si, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL);
430 }
431
enetc_mac_config(struct enetc_si * si,phy_interface_t phy_mode)432 static void enetc_mac_config(struct enetc_si *si, phy_interface_t phy_mode)
433 {
434 u32 val;
435
436 if (phy_interface_mode_is_rgmii(phy_mode)) {
437 val = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE);
438 val &= ~(ENETC_PM0_IFM_EN_AUTO | ENETC_PM0_IFM_IFMODE_MASK);
439 val |= ENETC_PM0_IFM_IFMODE_GMII | ENETC_PM0_IFM_RG;
440 enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val);
441 }
442
443 if (phy_mode == PHY_INTERFACE_MODE_USXGMII) {
444 val = ENETC_PM0_IFM_FULL_DPX | ENETC_PM0_IFM_IFMODE_XGMII;
445 enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val);
446 }
447 }
448
enetc_mac_enable(struct enetc_si * si,bool en)449 static void enetc_mac_enable(struct enetc_si *si, bool en)
450 {
451 u32 val = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG);
452
453 val &= ~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN);
454 val |= en ? (ENETC_PM0_TX_EN | ENETC_PM0_RX_EN) : 0;
455
456 enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, val);
457 }
458
enetc_configure_port(struct enetc_pf * pf)459 static void enetc_configure_port(struct enetc_pf *pf)
460 {
461 struct enetc_hw *hw = &pf->si->hw;
462
463 enetc_configure_port_mac(pf->si);
464
465 enetc_port_si_configure(pf->si);
466
467 /* set up hash key */
468 enetc_set_default_rss_key(pf);
469
470 /* split up RFS entries */
471 enetc_port_assign_rfs_entries(pf->si);
472
473 /* enforce VLAN promisc mode for all SIs */
474 pf->vlan_promisc_simap = ENETC_VLAN_PROMISC_MAP_ALL;
475 enetc_set_vlan_promisc(hw, pf->vlan_promisc_simap);
476
477 enetc_port_wr(hw, ENETC_PSIPMR, 0);
478
479 /* enable port */
480 enetc_port_wr(hw, ENETC_PMR, ENETC_PMR_EN);
481 }
482
483 /* Messaging */
enetc_msg_pf_set_vf_primary_mac_addr(struct enetc_pf * pf,int vf_id,void * msg)484 static u16 enetc_msg_pf_set_vf_primary_mac_addr(struct enetc_pf *pf,
485 int vf_id, void *msg)
486 {
487 struct enetc_vf_state *vf_state = &pf->vf_state[vf_id];
488 struct enetc_msg_cmd_set_primary_mac *cmd = msg;
489 struct device *dev = &pf->si->pdev->dev;
490 u16 cmd_id = cmd->header.id;
491 char *addr;
492
493 if (cmd_id != ENETC_MSG_CMD_MNG_ADD)
494 return ENETC_MSG_CMD_STATUS_FAIL;
495
496 addr = cmd->mac.sa_data;
497 if (!is_valid_ether_addr(addr)) {
498 dev_err_ratelimited(dev, "VF%d attempted to set invalid MAC\n",
499 vf_id);
500 return ENETC_MSG_CMD_STATUS_FAIL;
501 }
502
503 mutex_lock(&vf_state->lock);
504 if (vf_state->flags & ENETC_VF_FLAG_PF_SET_MAC) {
505 mutex_unlock(&vf_state->lock);
506 dev_err_ratelimited(dev,
507 "VF%d attempted to override PF set MAC\n",
508 vf_id);
509 return ENETC_MSG_CMD_STATUS_FAIL;
510 }
511
512 enetc_pf_set_primary_mac_addr(&pf->si->hw, vf_id + 1, addr);
513 mutex_unlock(&vf_state->lock);
514
515 return ENETC_MSG_CMD_STATUS_OK;
516 }
517
enetc_msg_handle_rxmsg(struct enetc_pf * pf,int vf_id,u16 * status)518 void enetc_msg_handle_rxmsg(struct enetc_pf *pf, int vf_id, u16 *status)
519 {
520 struct enetc_msg_swbd *msg_swbd = &pf->rxmsg[vf_id];
521 struct device *dev = &pf->si->pdev->dev;
522 struct enetc_msg_cmd_header *cmd_hdr;
523 u16 cmd_type;
524 u8 *msg;
525
526 msg = kzalloc_objs(*msg, msg_swbd->size);
527 if (!msg) {
528 dev_err_ratelimited(dev,
529 "Failed to allocate message buffer\n");
530 *status = ENETC_MSG_CMD_STATUS_FAIL;
531 return;
532 }
533
534 /* Currently, only ENETC_MSG_CMD_MNG_MAC command is supported, so
535 * only sizeof(struct enetc_msg_cmd_set_primary_mac) bytes need to
536 * be copied. This data already includes the cmd_type field, so it
537 * can correctly return an error code.
538 */
539 memcpy(msg, msg_swbd->vaddr,
540 sizeof(struct enetc_msg_cmd_set_primary_mac));
541 cmd_hdr = (struct enetc_msg_cmd_header *)msg;
542 cmd_type = cmd_hdr->type;
543
544 switch (cmd_type) {
545 case ENETC_MSG_CMD_MNG_MAC:
546 *status = enetc_msg_pf_set_vf_primary_mac_addr(pf, vf_id, msg);
547 break;
548 default:
549 *status = ENETC_MSG_CMD_STATUS_FAIL;
550 dev_err_ratelimited(dev,
551 "command not supported (cmd_type: 0x%x)\n",
552 cmd_type);
553 }
554
555 kfree(msg);
556 }
557
558 #ifdef CONFIG_PCI_IOV
enetc_sriov_configure(struct pci_dev * pdev,int num_vfs)559 static int enetc_sriov_configure(struct pci_dev *pdev, int num_vfs)
560 {
561 struct enetc_si *si = pci_get_drvdata(pdev);
562 struct enetc_pf *pf = enetc_si_priv(si);
563 int err;
564
565 if (!num_vfs) {
566 pci_disable_sriov(pdev);
567 enetc_msg_psi_free(pf);
568 pf->num_vfs = 0;
569 } else {
570 pf->num_vfs = num_vfs;
571
572 err = enetc_msg_psi_init(pf);
573 if (err) {
574 dev_err(&pdev->dev, "enetc_msg_psi_init (%d)\n", err);
575 goto err_msg_psi;
576 }
577
578 err = pci_enable_sriov(pdev, num_vfs);
579 if (err) {
580 dev_err(&pdev->dev, "pci_enable_sriov err %d\n", err);
581 goto err_en_sriov;
582 }
583 }
584
585 return num_vfs;
586
587 err_en_sriov:
588 enetc_msg_psi_free(pf);
589 err_msg_psi:
590 pf->num_vfs = 0;
591
592 return err;
593 }
594 #else
595 #define enetc_sriov_configure(pdev, num_vfs) (void)0
596 #endif
597
enetc_pf_set_features(struct net_device * ndev,netdev_features_t features)598 static int enetc_pf_set_features(struct net_device *ndev,
599 netdev_features_t features)
600 {
601 netdev_features_t changed = ndev->features ^ features;
602 struct enetc_ndev_priv *priv = netdev_priv(ndev);
603 int err;
604
605 if (changed & NETIF_F_HW_TC) {
606 err = enetc_set_psfp(ndev, !!(features & NETIF_F_HW_TC));
607 if (err)
608 return err;
609 }
610
611 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {
612 struct enetc_pf *pf = enetc_si_priv(priv->si);
613
614 if (!!(features & NETIF_F_HW_VLAN_CTAG_FILTER))
615 enetc_disable_si_vlan_promisc(pf, 0);
616 else
617 enetc_enable_si_vlan_promisc(pf, 0);
618 }
619
620 if (changed & NETIF_F_LOOPBACK)
621 enetc_set_loopback(ndev, !!(features & NETIF_F_LOOPBACK));
622
623 enetc_set_features(ndev, features);
624
625 return 0;
626 }
627
enetc_pf_setup_tc(struct net_device * ndev,enum tc_setup_type type,void * type_data)628 static int enetc_pf_setup_tc(struct net_device *ndev, enum tc_setup_type type,
629 void *type_data)
630 {
631 switch (type) {
632 case TC_QUERY_CAPS:
633 return enetc_qos_query_caps(ndev, type_data);
634 case TC_SETUP_QDISC_MQPRIO:
635 return enetc_setup_tc_mqprio(ndev, type_data);
636 case TC_SETUP_QDISC_TAPRIO:
637 return enetc_setup_tc_taprio(ndev, type_data);
638 case TC_SETUP_QDISC_CBS:
639 return enetc_setup_tc_cbs(ndev, type_data);
640 case TC_SETUP_QDISC_ETF:
641 return enetc_setup_tc_txtime(ndev, type_data);
642 case TC_SETUP_BLOCK:
643 return enetc_setup_tc_psfp(ndev, type_data);
644 default:
645 return -EOPNOTSUPP;
646 }
647 }
648
649 static const struct net_device_ops enetc_ndev_ops = {
650 .ndo_open = enetc_open,
651 .ndo_stop = enetc_close,
652 .ndo_start_xmit = enetc_xmit,
653 .ndo_get_stats = enetc_get_stats,
654 .ndo_set_mac_address = enetc_pf_set_mac_addr,
655 .ndo_set_rx_mode = enetc_pf_set_rx_mode,
656 .ndo_vlan_rx_add_vid = enetc_vlan_rx_add_vid,
657 .ndo_vlan_rx_kill_vid = enetc_vlan_rx_del_vid,
658 .ndo_set_vf_mac = enetc_pf_set_vf_mac,
659 .ndo_set_vf_vlan = enetc_pf_set_vf_vlan,
660 .ndo_set_vf_spoofchk = enetc_pf_set_vf_spoofchk,
661 .ndo_set_features = enetc_pf_set_features,
662 .ndo_eth_ioctl = enetc_ioctl,
663 .ndo_setup_tc = enetc_pf_setup_tc,
664 .ndo_bpf = enetc_setup_bpf,
665 .ndo_xdp_xmit = enetc_xdp_xmit,
666 .ndo_hwtstamp_get = enetc_hwtstamp_get,
667 .ndo_hwtstamp_set = enetc_hwtstamp_set,
668 };
669
670 static struct phylink_pcs *
enetc_pl_mac_select_pcs(struct phylink_config * config,phy_interface_t iface)671 enetc_pl_mac_select_pcs(struct phylink_config *config, phy_interface_t iface)
672 {
673 struct enetc_pf *pf = phylink_to_enetc_pf(config);
674
675 return pf->pcs;
676 }
677
enetc_pl_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)678 static void enetc_pl_mac_config(struct phylink_config *config,
679 unsigned int mode,
680 const struct phylink_link_state *state)
681 {
682 struct enetc_pf *pf = phylink_to_enetc_pf(config);
683
684 enetc_mac_config(pf->si, state->interface);
685 }
686
enetc_force_rgmii_mac(struct enetc_si * si,int speed,int duplex)687 static void enetc_force_rgmii_mac(struct enetc_si *si, int speed, int duplex)
688 {
689 u32 old_val, val;
690
691 old_val = val = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE);
692
693 if (speed == SPEED_1000) {
694 val &= ~ENETC_PM0_IFM_SSP_MASK;
695 val |= ENETC_PM0_IFM_SSP_1000;
696 } else if (speed == SPEED_100) {
697 val &= ~ENETC_PM0_IFM_SSP_MASK;
698 val |= ENETC_PM0_IFM_SSP_100;
699 } else if (speed == SPEED_10) {
700 val &= ~ENETC_PM0_IFM_SSP_MASK;
701 val |= ENETC_PM0_IFM_SSP_10;
702 }
703
704 if (duplex == DUPLEX_FULL)
705 val |= ENETC_PM0_IFM_FULL_DPX;
706 else
707 val &= ~ENETC_PM0_IFM_FULL_DPX;
708
709 if (val == old_val)
710 return;
711
712 enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val);
713 }
714
enetc_pl_mac_link_up(struct phylink_config * config,struct phy_device * phy,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)715 static void enetc_pl_mac_link_up(struct phylink_config *config,
716 struct phy_device *phy, unsigned int mode,
717 phy_interface_t interface, int speed,
718 int duplex, bool tx_pause, bool rx_pause)
719 {
720 struct enetc_pf *pf = phylink_to_enetc_pf(config);
721 u32 pause_off_thresh = 0, pause_on_thresh = 0;
722 u32 init_quanta = 0, refresh_quanta = 0;
723 struct enetc_hw *hw = &pf->si->hw;
724 struct enetc_si *si = pf->si;
725 struct enetc_ndev_priv *priv;
726 u32 rbmr, cmd_cfg;
727 int idx;
728
729 priv = netdev_priv(pf->si->ndev);
730
731 if (pf->si->hw_features & ENETC_SI_F_QBV)
732 enetc_sched_speed_set(priv, speed);
733
734 if (!phylink_autoneg_inband(mode) &&
735 phy_interface_mode_is_rgmii(interface))
736 enetc_force_rgmii_mac(si, speed, duplex);
737
738 /* Flow control */
739 for (idx = 0; idx < priv->num_rx_rings; idx++) {
740 rbmr = enetc_rxbdr_rd(hw, idx, ENETC_RBMR);
741
742 if (tx_pause)
743 rbmr |= ENETC_RBMR_CM;
744 else
745 rbmr &= ~ENETC_RBMR_CM;
746
747 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, rbmr);
748 }
749
750 if (tx_pause) {
751 /* When the port first enters congestion, send a PAUSE request
752 * with the maximum number of quanta. When the port exits
753 * congestion, it will automatically send a PAUSE frame with
754 * zero quanta.
755 */
756 init_quanta = 0xffff;
757
758 /* Also, set up the refresh timer to send follow-up PAUSE
759 * frames at half the quanta value, in case the congestion
760 * condition persists.
761 */
762 refresh_quanta = 0xffff / 2;
763
764 /* Start emitting PAUSE frames when 3 large frames (or more
765 * smaller frames) have accumulated in the FIFO waiting to be
766 * DMAed to the RX ring.
767 */
768 pause_on_thresh = 3 * ENETC_MAC_MAXFRM_SIZE;
769 pause_off_thresh = 1 * ENETC_MAC_MAXFRM_SIZE;
770 }
771
772 enetc_port_mac_wr(si, ENETC_PM0_PAUSE_QUANTA, init_quanta);
773 enetc_port_mac_wr(si, ENETC_PM0_PAUSE_THRESH, refresh_quanta);
774 enetc_port_wr(hw, ENETC_PPAUONTR, pause_on_thresh);
775 enetc_port_wr(hw, ENETC_PPAUOFFTR, pause_off_thresh);
776
777 cmd_cfg = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG);
778
779 if (rx_pause)
780 cmd_cfg &= ~ENETC_PM0_PAUSE_IGN;
781 else
782 cmd_cfg |= ENETC_PM0_PAUSE_IGN;
783
784 enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, cmd_cfg);
785
786 enetc_mac_enable(si, true);
787
788 if (si->hw_features & ENETC_SI_F_QBU)
789 enetc_mm_link_state_update(priv, true);
790 }
791
enetc_pl_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)792 static void enetc_pl_mac_link_down(struct phylink_config *config,
793 unsigned int mode,
794 phy_interface_t interface)
795 {
796 struct enetc_pf *pf = phylink_to_enetc_pf(config);
797 struct enetc_si *si = pf->si;
798 struct enetc_ndev_priv *priv;
799
800 priv = netdev_priv(si->ndev);
801
802 if (si->hw_features & ENETC_SI_F_QBU)
803 enetc_mm_link_state_update(priv, false);
804
805 enetc_mac_enable(si, false);
806 }
807
808 static const struct phylink_mac_ops enetc_mac_phylink_ops = {
809 .mac_select_pcs = enetc_pl_mac_select_pcs,
810 .mac_config = enetc_pl_mac_config,
811 .mac_link_up = enetc_pl_mac_link_up,
812 .mac_link_down = enetc_pl_mac_link_down,
813 };
814
815 /* Initialize the entire shared memory for the flow steering entries
816 * of this port (PF + VFs)
817 */
enetc_init_port_rfs_memory(struct enetc_si * si)818 static int enetc_init_port_rfs_memory(struct enetc_si *si)
819 {
820 struct enetc_cmd_rfse rfse = {0};
821 struct enetc_hw *hw = &si->hw;
822 int num_rfs, i, err = 0;
823 u32 val;
824
825 val = enetc_port_rd(hw, ENETC_PRFSCAPR);
826 num_rfs = ENETC_PRFSCAPR_GET_NUM_RFS(val);
827
828 for (i = 0; i < num_rfs; i++) {
829 err = enetc_set_fs_entry(si, &rfse, i);
830 if (err)
831 break;
832 }
833
834 return err;
835 }
836
enetc_init_port_rss_memory(struct enetc_si * si)837 static int enetc_init_port_rss_memory(struct enetc_si *si)
838 {
839 struct enetc_hw *hw = &si->hw;
840 int num_rss, err;
841 int *rss_table;
842 u32 val;
843
844 val = enetc_port_rd(hw, ENETC_PRSSCAPR);
845 num_rss = ENETC_PRSSCAPR_GET_NUM_RSS(val);
846 if (!num_rss)
847 return 0;
848
849 rss_table = kzalloc_objs(*rss_table, num_rss);
850 if (!rss_table)
851 return -ENOMEM;
852
853 err = enetc_set_rss_table(si, rss_table, num_rss);
854
855 kfree(rss_table);
856
857 return err;
858 }
859
enetc_pf_register_with_ierb(struct pci_dev * pdev)860 static int enetc_pf_register_with_ierb(struct pci_dev *pdev)
861 {
862 struct platform_device *ierb_pdev;
863 struct device_node *ierb_node;
864 int ret;
865
866 ierb_node = of_find_compatible_node(NULL, NULL,
867 "fsl,ls1028a-enetc-ierb");
868 if (!ierb_node)
869 return -ENODEV;
870
871 if (!of_device_is_available(ierb_node)) {
872 of_node_put(ierb_node);
873 return -ENODEV;
874 }
875
876 ierb_pdev = of_find_device_by_node(ierb_node);
877 of_node_put(ierb_node);
878
879 if (!ierb_pdev)
880 return -EPROBE_DEFER;
881
882 ret = enetc_ierb_register_pf(ierb_pdev, pdev);
883
884 put_device(&ierb_pdev->dev);
885
886 return ret;
887 }
888
889 static const struct enetc_si_ops enetc_psi_ops = {
890 .get_rss_table = enetc_get_rss_table,
891 .set_rss_table = enetc_set_rss_table,
892 };
893
enetc_psi_create(struct pci_dev * pdev)894 static struct enetc_si *enetc_psi_create(struct pci_dev *pdev)
895 {
896 struct enetc_si *si;
897 int err;
898
899 err = enetc_pci_probe(pdev, KBUILD_MODNAME, sizeof(struct enetc_pf));
900 if (err) {
901 dev_err_probe(&pdev->dev, err, "PCI probing failed\n");
902 goto out;
903 }
904
905 si = pci_get_drvdata(pdev);
906 if (!si->hw.port || !si->hw.global) {
907 err = -ENODEV;
908 dev_err(&pdev->dev, "could not map PF space, probing a VF?\n");
909 goto out_pci_remove;
910 }
911
912 si->revision = enetc_get_ip_revision(&si->hw);
913 si->ops = &enetc_psi_ops;
914 err = enetc_get_driver_data(si);
915 if (err) {
916 dev_err(&pdev->dev, "Could not get PF driver data\n");
917 goto out_pci_remove;
918 }
919
920 err = enetc_setup_cbdr(&pdev->dev, &si->hw, ENETC_CBDR_DEFAULT_SIZE,
921 &si->cbd_ring);
922 if (err)
923 goto out_pci_remove;
924
925 err = enetc_init_port_rfs_memory(si);
926 if (err) {
927 dev_err(&pdev->dev, "Failed to initialize RFS memory\n");
928 goto out_teardown_cbdr;
929 }
930
931 err = enetc_init_port_rss_memory(si);
932 if (err) {
933 dev_err(&pdev->dev, "Failed to initialize RSS memory\n");
934 goto out_teardown_cbdr;
935 }
936
937 return si;
938
939 out_teardown_cbdr:
940 enetc_teardown_cbdr(&si->cbd_ring);
941 out_pci_remove:
942 enetc_pci_remove(pdev);
943 out:
944 return ERR_PTR(err);
945 }
946
enetc_psi_destroy(struct pci_dev * pdev)947 static void enetc_psi_destroy(struct pci_dev *pdev)
948 {
949 struct enetc_si *si = pci_get_drvdata(pdev);
950
951 enetc_teardown_cbdr(&si->cbd_ring);
952 enetc_pci_remove(pdev);
953 }
954
955 static const struct enetc_pf_ops enetc_pf_ops = {
956 .set_si_primary_mac = enetc_pf_set_primary_mac_addr,
957 .get_si_primary_mac = enetc_pf_get_primary_mac_addr,
958 .create_pcs = enetc_pf_create_pcs,
959 .destroy_pcs = enetc_pf_destroy_pcs,
960 .enable_psfp = enetc_psfp_enable,
961 };
962
enetc_pf_probe(struct pci_dev * pdev,const struct pci_device_id * ent)963 static int enetc_pf_probe(struct pci_dev *pdev,
964 const struct pci_device_id *ent)
965 {
966 struct device_node *node = pdev->dev.of_node;
967 struct enetc_ndev_priv *priv;
968 struct net_device *ndev;
969 struct enetc_si *si;
970 struct enetc_pf *pf;
971 int err;
972
973 err = enetc_pf_register_with_ierb(pdev);
974 if (err == -EPROBE_DEFER)
975 return err;
976 if (err)
977 dev_warn(&pdev->dev,
978 "Could not register with IERB driver: %pe, please update the device tree\n",
979 ERR_PTR(err));
980
981 si = enetc_psi_create(pdev);
982 if (IS_ERR(si)) {
983 err = PTR_ERR(si);
984 goto err_psi_create;
985 }
986
987 pf = enetc_si_priv(si);
988 pf->si = si;
989 pf->ops = &enetc_pf_ops;
990
991 pf->total_vfs = pci_sriov_get_totalvfs(pdev);
992 if (pf->total_vfs) {
993 pf->vf_state = kzalloc_objs(struct enetc_vf_state,
994 pf->total_vfs);
995 if (!pf->vf_state) {
996 err = -ENOMEM;
997 goto err_alloc_vf_state;
998 }
999
1000 for (int i = 0; i < pf->total_vfs; i++)
1001 mutex_init(&pf->vf_state[i].lock);
1002 }
1003
1004 err = enetc_setup_mac_addresses(node, pf);
1005 if (err)
1006 goto err_setup_mac_addresses;
1007
1008 enetc_configure_port(pf);
1009
1010 enetc_get_si_caps(si);
1011
1012 ndev = alloc_etherdev_mq(sizeof(*priv), ENETC_MAX_NUM_TXQS);
1013 if (!ndev) {
1014 err = -ENOMEM;
1015 dev_err(&pdev->dev, "netdev creation failed\n");
1016 goto err_alloc_netdev;
1017 }
1018
1019 enetc_pf_netdev_setup(si, ndev, &enetc_ndev_ops);
1020
1021 priv = netdev_priv(ndev);
1022
1023 mutex_init(&priv->mm_lock);
1024
1025 enetc_init_si_rings_params(priv);
1026
1027 err = enetc_alloc_si_resources(priv);
1028 if (err) {
1029 dev_err(&pdev->dev, "SI resource alloc failed\n");
1030 goto err_alloc_si_res;
1031 }
1032
1033 err = enetc_configure_si(priv);
1034 if (err) {
1035 dev_err(&pdev->dev, "Failed to configure SI\n");
1036 goto err_config_si;
1037 }
1038
1039 err = enetc_alloc_msix(priv);
1040 if (err) {
1041 dev_err(&pdev->dev, "MSIX alloc failed\n");
1042 goto err_alloc_msix;
1043 }
1044
1045 err = of_get_phy_mode(node, &pf->if_mode);
1046 if (err) {
1047 dev_err(&pdev->dev, "Failed to read PHY mode\n");
1048 goto err_phy_mode;
1049 }
1050
1051 err = enetc_mdiobus_create(pf, node);
1052 if (err)
1053 goto err_mdiobus_create;
1054
1055 err = enetc_phylink_create(priv, node, &enetc_mac_phylink_ops);
1056 if (err)
1057 goto err_phylink_create;
1058
1059 err = register_netdev(ndev);
1060 if (err)
1061 goto err_reg_netdev;
1062
1063 return 0;
1064
1065 err_reg_netdev:
1066 enetc_phylink_destroy(priv);
1067 err_phylink_create:
1068 enetc_mdiobus_destroy(pf);
1069 err_mdiobus_create:
1070 err_phy_mode:
1071 enetc_free_msix(priv);
1072 err_config_si:
1073 err_alloc_msix:
1074 enetc_free_si_resources(priv);
1075 err_alloc_si_res:
1076 si->ndev = NULL;
1077 free_netdev(ndev);
1078 err_alloc_netdev:
1079 err_setup_mac_addresses:
1080 kfree(pf->vf_state);
1081 err_alloc_vf_state:
1082 enetc_psi_destroy(pdev);
1083 err_psi_create:
1084 return err;
1085 }
1086
enetc_pf_remove(struct pci_dev * pdev)1087 static void enetc_pf_remove(struct pci_dev *pdev)
1088 {
1089 struct enetc_si *si = pci_get_drvdata(pdev);
1090 struct enetc_pf *pf = enetc_si_priv(si);
1091 struct enetc_ndev_priv *priv;
1092
1093 priv = netdev_priv(si->ndev);
1094
1095 if (pf->num_vfs)
1096 enetc_sriov_configure(pdev, 0);
1097
1098 unregister_netdev(si->ndev);
1099
1100 enetc_phylink_destroy(priv);
1101 enetc_mdiobus_destroy(pf);
1102
1103 enetc_free_msix(priv);
1104
1105 enetc_free_si_resources(priv);
1106
1107 free_netdev(si->ndev);
1108 kfree(pf->vf_state);
1109
1110 enetc_psi_destroy(pdev);
1111 }
1112
enetc_fixup_clear_rss_rfs(struct pci_dev * pdev)1113 static void enetc_fixup_clear_rss_rfs(struct pci_dev *pdev)
1114 {
1115 struct device_node *node = pdev->dev.of_node;
1116 struct enetc_si *si;
1117
1118 /* Only apply quirk for disabled functions. For the ones
1119 * that are enabled, enetc_pf_probe() will apply it.
1120 */
1121 if (node && of_device_is_available(node))
1122 return;
1123
1124 si = enetc_psi_create(pdev);
1125 if (!IS_ERR(si))
1126 enetc_psi_destroy(pdev);
1127 }
1128 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_PF,
1129 enetc_fixup_clear_rss_rfs);
1130
1131 static const struct pci_device_id enetc_pf_id_table[] = {
1132 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_PF) },
1133 { 0, } /* End of table. */
1134 };
1135 MODULE_DEVICE_TABLE(pci, enetc_pf_id_table);
1136
1137 static struct pci_driver enetc_pf_driver = {
1138 .name = KBUILD_MODNAME,
1139 .id_table = enetc_pf_id_table,
1140 .probe = enetc_pf_probe,
1141 .remove = enetc_pf_remove,
1142 #ifdef CONFIG_PCI_IOV
1143 .sriov_configure = enetc_sriov_configure,
1144 #endif
1145 };
1146 module_pci_driver(enetc_pf_driver);
1147
1148 MODULE_DESCRIPTION(ENETC_DRV_NAME_STR);
1149 MODULE_LICENSE("Dual BSD/GPL");
1150