1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
4 *
5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
6 *
7 */
8 #include <linux/clk.h>
9 #include <linux/iopoll.h>
10 #include <linux/of.h>
11 #include <linux/module.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/property.h>
14 #include <linux/regmap.h>
15 #include <linux/sys_soc.h>
16
17 #include "cqhci.h"
18 #include "sdhci-cqhci.h"
19 #include "sdhci-pltfm.h"
20
21 /* CTL_CFG Registers */
22 #define CTL_CFG_2 0x14
23 #define CTL_CFG_3 0x18
24
25 #define SLOTTYPE_MASK GENMASK(31, 30)
26 #define SLOTTYPE_EMBEDDED BIT(30)
27 #define TUNINGFORSDR50_MASK BIT(13)
28
29 /* PHY Registers */
30 #define PHY_CTRL1 0x100
31 #define PHY_CTRL2 0x104
32 #define PHY_CTRL3 0x108
33 #define PHY_CTRL4 0x10C
34 #define PHY_CTRL5 0x110
35 #define PHY_CTRL6 0x114
36 #define PHY_STAT1 0x130
37 #define PHY_STAT2 0x134
38
39 #define IOMUX_ENABLE_SHIFT 31
40 #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT)
41 #define OTAPDLYENA_SHIFT 20
42 #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT)
43 #define OTAPDLYSEL_SHIFT 12
44 #define OTAPDLYSEL_MASK GENMASK(15, 12)
45 #define STRBSEL_SHIFT 24
46 #define STRBSEL_4BIT_MASK GENMASK(27, 24)
47 #define STRBSEL_8BIT_MASK GENMASK(31, 24)
48 #define SEL50_SHIFT 8
49 #define SEL50_MASK BIT(SEL50_SHIFT)
50 #define SEL100_SHIFT 9
51 #define SEL100_MASK BIT(SEL100_SHIFT)
52 #define FREQSEL_SHIFT 8
53 #define FREQSEL_MASK GENMASK(10, 8)
54 #define CLKBUFSEL_SHIFT 0
55 #define CLKBUFSEL_MASK GENMASK(2, 0)
56 #define DLL_TRIM_ICP_SHIFT 4
57 #define DLL_TRIM_ICP_MASK GENMASK(7, 4)
58 #define DR_TY_SHIFT 20
59 #define DR_TY_MASK GENMASK(22, 20)
60 #define ENDLL_SHIFT 1
61 #define ENDLL_MASK BIT(ENDLL_SHIFT)
62 #define DLLRDY_SHIFT 0
63 #define DLLRDY_MASK BIT(DLLRDY_SHIFT)
64 #define PDB_SHIFT 0
65 #define PDB_MASK BIT(PDB_SHIFT)
66 #define CALDONE_SHIFT 1
67 #define CALDONE_MASK BIT(CALDONE_SHIFT)
68 #define RETRIM_SHIFT 17
69 #define RETRIM_MASK BIT(RETRIM_SHIFT)
70 #define SELDLYTXCLK_SHIFT 17
71 #define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT)
72 #define SELDLYRXCLK_SHIFT 16
73 #define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT)
74 #define ITAPDLYSEL_SHIFT 0
75 #define ITAPDLYSEL_MASK GENMASK(4, 0)
76 #define ITAPDLYENA_SHIFT 8
77 #define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT)
78 #define ITAPCHGWIN_SHIFT 9
79 #define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT)
80
81 #define DRIVER_STRENGTH_50_OHM 0x0
82 #define DRIVER_STRENGTH_33_OHM 0x1
83 #define DRIVER_STRENGTH_66_OHM 0x2
84 #define DRIVER_STRENGTH_100_OHM 0x3
85 #define DRIVER_STRENGTH_40_OHM 0x4
86
87 #define CLOCK_TOO_SLOW_HZ 50000000
88 #define SDHCI_AM654_AUTOSUSPEND_DELAY -1
89 #define RETRY_TUNING_MAX 10
90
91 /* Command Queue Host Controller Interface Base address */
92 #define SDHCI_AM654_CQE_BASE_ADDR 0x200
93
94 static const struct regmap_config sdhci_am654_regmap_config = {
95 .reg_bits = 32,
96 .val_bits = 32,
97 .reg_stride = 4,
98 .fast_io = true,
99 };
100
101 struct timing_data {
102 const char *otap_binding;
103 const char *itap_binding;
104 u32 capability;
105 };
106
107 static const struct timing_data td[] = {
108 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy",
109 "ti,itap-del-sel-legacy",
110 0},
111 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs",
112 "ti,itap-del-sel-mmc-hs",
113 MMC_CAP_MMC_HIGHSPEED},
114 [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs",
115 "ti,itap-del-sel-sd-hs",
116 MMC_CAP_SD_HIGHSPEED},
117 [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12",
118 "ti,itap-del-sel-sdr12",
119 MMC_CAP_UHS_SDR12},
120 [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25",
121 "ti,itap-del-sel-sdr25",
122 MMC_CAP_UHS_SDR25},
123 [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50",
124 NULL,
125 MMC_CAP_UHS_SDR50},
126 [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104",
127 NULL,
128 MMC_CAP_UHS_SDR104},
129 [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50",
130 NULL,
131 MMC_CAP_UHS_DDR50},
132 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52",
133 "ti,itap-del-sel-ddr52",
134 MMC_CAP_DDR},
135 [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200",
136 NULL,
137 MMC_CAP2_HS200},
138 [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400",
139 NULL,
140 MMC_CAP2_HS400},
141 };
142
143 struct sdhci_am654_data {
144 struct regmap *base;
145 u32 otap_del_sel[ARRAY_SIZE(td)];
146 u32 itap_del_sel[ARRAY_SIZE(td)];
147 u32 itap_del_ena[ARRAY_SIZE(td)];
148 int clkbuf_sel;
149 int trm_icp;
150 int drv_strength;
151 int strb_sel;
152 u32 flags;
153 u32 quirks;
154 bool dll_enable;
155 u32 tuning_loop;
156
157 #define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0)
158 #define SDHCI_AM654_QUIRK_SUPPRESS_V1P8_ENA BIT(1)
159 #define SDHCI_AM654_QUIRK_DISABLE_HS400 BIT(2)
160 };
161
162 struct window {
163 u8 start;
164 u8 end;
165 u8 length;
166 };
167
168 struct sdhci_am654_driver_data {
169 const struct sdhci_pltfm_data *pdata;
170 u32 flags;
171 u32 quirks;
172 #define IOMUX_PRESENT (1 << 0)
173 #define FREQSEL_2_BIT (1 << 1)
174 #define STRBSEL_4_BIT (1 << 2)
175 #define DLL_PRESENT (1 << 3)
176 #define DLL_CALIB (1 << 4)
177 };
178
sdhci_am654_setup_dll(struct sdhci_host * host,unsigned int clock)179 static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock)
180 {
181 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
182 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
183 int sel50, sel100, freqsel;
184 u32 mask, val;
185 int ret;
186
187 /* Disable delay chain mode */
188 regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
189 SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0);
190
191 if (sdhci_am654->flags & FREQSEL_2_BIT) {
192 switch (clock) {
193 case 200000000:
194 sel50 = 0;
195 sel100 = 0;
196 break;
197 case 100000000:
198 sel50 = 0;
199 sel100 = 1;
200 break;
201 default:
202 sel50 = 1;
203 sel100 = 0;
204 }
205
206 /* Configure PHY DLL frequency */
207 mask = SEL50_MASK | SEL100_MASK;
208 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
209 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
210
211 } else {
212 switch (clock) {
213 case 200000000:
214 freqsel = 0x0;
215 break;
216 default:
217 freqsel = 0x4;
218 }
219
220 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK,
221 freqsel << FREQSEL_SHIFT);
222 }
223 /* Configure DLL TRIM */
224 mask = DLL_TRIM_ICP_MASK;
225 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT;
226
227 /* Configure DLL driver strength */
228 mask |= DR_TY_MASK;
229 val |= sdhci_am654->drv_strength << DR_TY_SHIFT;
230 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val);
231
232 /* Enable DLL */
233 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK,
234 0x1 << ENDLL_SHIFT);
235 /*
236 * Poll for DLL ready. Use a one second timeout.
237 * Works in all experiments done so far
238 */
239 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val,
240 val & DLLRDY_MASK, 1000, 1000000);
241 if (ret) {
242 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n");
243 return;
244 }
245 }
246
sdhci_am654_write_itapdly(struct sdhci_am654_data * sdhci_am654,u32 itapdly,u32 enable)247 static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654,
248 u32 itapdly, u32 enable)
249 {
250 /* Set ITAPCHGWIN before writing to ITAPDLY */
251 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK,
252 1 << ITAPCHGWIN_SHIFT);
253 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK,
254 enable << ITAPDLYENA_SHIFT);
255 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK,
256 itapdly << ITAPDLYSEL_SHIFT);
257 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
258 }
259
sdhci_am654_setup_delay_chain(struct sdhci_am654_data * sdhci_am654,unsigned char timing)260 static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654,
261 unsigned char timing)
262 {
263 u32 mask, val;
264
265 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
266
267 val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT;
268 mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK;
269 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
270
271 sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing],
272 sdhci_am654->itap_del_ena[timing]);
273 }
274
sdhci_am654_set_clock(struct sdhci_host * host,unsigned int clock)275 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)
276 {
277 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
278 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
279 unsigned char timing = host->mmc->ios.timing;
280 u32 otap_del_sel;
281 u32 mask, val;
282
283 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
284
285 sdhci_set_clock(host, clock);
286
287 /* Setup Output TAP delay */
288 otap_del_sel = sdhci_am654->otap_del_sel[timing];
289
290 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
291 val = (0x1 << OTAPDLYENA_SHIFT) |
292 (otap_del_sel << OTAPDLYSEL_SHIFT);
293
294 /* Write to STRBSEL for HS400 speed mode */
295 if (timing == MMC_TIMING_MMC_HS400) {
296 if (sdhci_am654->flags & STRBSEL_4_BIT)
297 mask |= STRBSEL_4BIT_MASK;
298 else
299 mask |= STRBSEL_8BIT_MASK;
300
301 val |= sdhci_am654->strb_sel << STRBSEL_SHIFT;
302 }
303
304 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
305
306 if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) {
307 sdhci_am654_setup_dll(host, clock);
308 sdhci_am654->dll_enable = true;
309
310 if (timing == MMC_TIMING_MMC_HS400) {
311 sdhci_am654->itap_del_ena[timing] = 0x1;
312 sdhci_am654->itap_del_sel[timing] = sdhci_am654->itap_del_sel[timing - 1];
313 }
314
315 sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing],
316 sdhci_am654->itap_del_ena[timing]);
317 } else {
318 sdhci_am654_setup_delay_chain(sdhci_am654, timing);
319 sdhci_am654->dll_enable = false;
320 }
321
322 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
323 sdhci_am654->clkbuf_sel);
324 }
325
sdhci_j721e_4bit_set_clock(struct sdhci_host * host,unsigned int clock)326 static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host,
327 unsigned int clock)
328 {
329 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
330 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
331 unsigned char timing = host->mmc->ios.timing;
332 u32 otap_del_sel;
333 u32 itap_del_ena;
334 u32 itap_del_sel;
335 u32 mask, val;
336
337 /* Setup Output TAP delay */
338 otap_del_sel = sdhci_am654->otap_del_sel[timing];
339
340 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
341 val = (0x1 << OTAPDLYENA_SHIFT) |
342 (otap_del_sel << OTAPDLYSEL_SHIFT);
343
344 /* Setup Input TAP delay */
345 itap_del_ena = sdhci_am654->itap_del_ena[timing];
346 itap_del_sel = sdhci_am654->itap_del_sel[timing];
347
348 mask |= ITAPDLYENA_MASK | ITAPDLYSEL_MASK;
349 val |= (itap_del_ena << ITAPDLYENA_SHIFT) |
350 (itap_del_sel << ITAPDLYSEL_SHIFT);
351
352 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK,
353 1 << ITAPCHGWIN_SHIFT);
354 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
355 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
356 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
357 sdhci_am654->clkbuf_sel);
358
359 sdhci_set_clock(host, clock);
360 }
361
sdhci_am654_start_signal_voltage_switch(struct mmc_host * mmc,struct mmc_ios * ios)362 static int sdhci_am654_start_signal_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
363 {
364 struct sdhci_host *host = mmc_priv(mmc);
365 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
366 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
367 int ret;
368
369 if ((sdhci_am654->quirks & SDHCI_AM654_QUIRK_SUPPRESS_V1P8_ENA) &&
370 ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
371 if (!IS_ERR(mmc->supply.vqmmc)) {
372 ret = mmc_regulator_set_vqmmc(mmc, ios);
373 if (ret < 0) {
374 pr_err("%s: Switching to 1.8V signalling voltage failed,\n",
375 mmc_hostname(mmc));
376 return -EIO;
377 }
378 }
379 return 0;
380 }
381
382 return sdhci_start_signal_voltage_switch(mmc, ios);
383 }
384
sdhci_am654_write_power_on(struct sdhci_host * host,u8 val,int reg)385 static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg)
386 {
387 writeb(val, host->ioaddr + reg);
388 usleep_range(1000, 10000);
389 return readb(host->ioaddr + reg);
390 }
391
392 #define MAX_POWER_ON_TIMEOUT 1500000 /* us */
sdhci_am654_write_b(struct sdhci_host * host,u8 val,int reg)393 static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg)
394 {
395 unsigned char timing = host->mmc->ios.timing;
396 u8 pwr;
397 int ret;
398
399 if (reg == SDHCI_HOST_CONTROL) {
400 switch (timing) {
401 /*
402 * According to the data manual, HISPD bit
403 * should not be set in these speed modes.
404 */
405 case MMC_TIMING_SD_HS:
406 case MMC_TIMING_MMC_HS:
407 val &= ~SDHCI_CTRL_HISPD;
408 }
409 }
410
411 writeb(val, host->ioaddr + reg);
412 if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) {
413 /*
414 * Power on will not happen until the card detect debounce
415 * timer expires. Wait at least 1.5 seconds for the power on
416 * bit to be set
417 */
418 ret = read_poll_timeout(sdhci_am654_write_power_on, pwr,
419 pwr & SDHCI_POWER_ON, 0,
420 MAX_POWER_ON_TIMEOUT, false, host, val,
421 reg);
422 if (ret)
423 dev_info(mmc_dev(host->mmc), "Power on failed\n");
424 }
425 }
426
sdhci_am654_reset(struct sdhci_host * host,u8 mask)427 static void sdhci_am654_reset(struct sdhci_host *host, u8 mask)
428 {
429 u8 ctrl;
430 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
431 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
432
433 sdhci_and_cqhci_reset(host, mask);
434
435 if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) {
436 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
437 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
438 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
439 }
440 }
441
sdhci_am654_execute_tuning(struct mmc_host * mmc,u32 opcode)442 static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode)
443 {
444 struct sdhci_host *host = mmc_priv(mmc);
445 int err = sdhci_execute_tuning(mmc, opcode);
446
447 if (err)
448 return err;
449 /*
450 * Tuning data remains in the buffer after tuning.
451 * Do a command and data reset to get rid of it
452 */
453 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
454
455 return 0;
456 }
457
sdhci_am654_cqhci_irq(struct sdhci_host * host,u32 intmask)458 static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask)
459 {
460 int cmd_error = 0;
461 int data_error = 0;
462
463 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
464 return intmask;
465
466 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
467
468 return 0;
469 }
470
471 #define ITAPDLY_LENGTH 32
472 #define ITAPDLY_LAST_INDEX (ITAPDLY_LENGTH - 1)
473
sdhci_am654_calculate_itap(struct sdhci_host * host,struct window * fail_window,u8 num_fails,bool circular_buffer)474 static int sdhci_am654_calculate_itap(struct sdhci_host *host, struct window
475 *fail_window, u8 num_fails, bool circular_buffer)
476 {
477 u8 itap = 0, start_fail = 0, end_fail = 0, pass_length = 0;
478 u8 first_fail_start = 0, last_fail_end = 0;
479 struct device *dev = mmc_dev(host->mmc);
480 struct window pass_window = {0, 0, 0};
481 int prev_fail_end = -1;
482 u8 i;
483
484 if (!num_fails) {
485 /* Retry tuning */
486 dev_dbg(dev, "No failing region found, retry tuning\n");
487 return -1;
488 }
489
490 if (fail_window->length == ITAPDLY_LENGTH) {
491 /* Retry tuning */
492 dev_dbg(dev, "No passing itapdly, retry tuning\n");
493 return -1;
494 }
495
496 first_fail_start = fail_window->start;
497 last_fail_end = fail_window[num_fails - 1].end;
498
499 for (i = 0; i < num_fails; i++) {
500 start_fail = fail_window[i].start;
501 end_fail = fail_window[i].end;
502 pass_length = start_fail - (prev_fail_end + 1);
503
504 if (pass_length > pass_window.length) {
505 pass_window.start = prev_fail_end + 1;
506 pass_window.length = pass_length;
507 }
508 prev_fail_end = end_fail;
509 }
510
511 if (!circular_buffer)
512 pass_length = ITAPDLY_LAST_INDEX - last_fail_end;
513 else
514 pass_length = ITAPDLY_LAST_INDEX - last_fail_end + first_fail_start;
515
516 if (pass_length > pass_window.length) {
517 pass_window.start = last_fail_end + 1;
518 pass_window.length = pass_length;
519 }
520
521 if (!circular_buffer)
522 itap = pass_window.start + (pass_window.length >> 1);
523 else
524 itap = (pass_window.start + (pass_window.length >> 1)) % ITAPDLY_LENGTH;
525
526 return (itap > ITAPDLY_LAST_INDEX) ? ITAPDLY_LAST_INDEX >> 1 : itap;
527 }
528
sdhci_am654_do_tuning(struct sdhci_host * host,u32 opcode)529 static int sdhci_am654_do_tuning(struct sdhci_host *host,
530 u32 opcode)
531 {
532 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
533 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
534 unsigned char timing = host->mmc->ios.timing;
535 struct window fail_window[ITAPDLY_LENGTH];
536 struct device *dev = mmc_dev(host->mmc);
537 u8 curr_pass, itap;
538 u8 fail_index = 0;
539 u8 prev_pass = 1;
540
541 memset(fail_window, 0, sizeof(fail_window));
542
543 /* Enable ITAPDLY */
544 sdhci_am654->itap_del_ena[timing] = 0x1;
545
546 for (itap = 0; itap < ITAPDLY_LENGTH; itap++) {
547 sdhci_am654_write_itapdly(sdhci_am654, itap, sdhci_am654->itap_del_ena[timing]);
548
549 curr_pass = !mmc_send_tuning(host->mmc, opcode, NULL);
550
551 if (!curr_pass && prev_pass)
552 fail_window[fail_index].start = itap;
553
554 if (!curr_pass) {
555 fail_window[fail_index].end = itap;
556 fail_window[fail_index].length++;
557 dev_dbg(dev, "Failed itapdly=%d\n", itap);
558 }
559
560 if (curr_pass && !prev_pass)
561 fail_index++;
562
563 prev_pass = curr_pass;
564 }
565
566 if (fail_window[fail_index].length != 0)
567 fail_index++;
568
569 return sdhci_am654_calculate_itap(host, fail_window, fail_index,
570 sdhci_am654->dll_enable);
571 }
572
sdhci_am654_platform_execute_tuning(struct sdhci_host * host,u32 opcode)573 static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host,
574 u32 opcode)
575 {
576 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
577 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
578 unsigned char timing = host->mmc->ios.timing;
579 struct device *dev = mmc_dev(host->mmc);
580 int itapdly;
581
582 do {
583 itapdly = sdhci_am654_do_tuning(host, opcode);
584 if (itapdly >= 0)
585 break;
586 } while (++sdhci_am654->tuning_loop < RETRY_TUNING_MAX);
587
588 if (itapdly < 0) {
589 dev_err(dev, "Failed to find itapdly, fail tuning\n");
590 return -1;
591 }
592
593 dev_dbg(dev, "Passed tuning, final itapdly=%d\n", itapdly);
594 sdhci_am654_write_itapdly(sdhci_am654, itapdly, sdhci_am654->itap_del_ena[timing]);
595 /* Save ITAPDLY */
596 sdhci_am654->itap_del_sel[timing] = itapdly;
597
598 return 0;
599 }
600
601 static const struct sdhci_ops sdhci_am654_ops = {
602 .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
603 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
604 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
605 .set_uhs_signaling = sdhci_set_uhs_signaling,
606 .set_bus_width = sdhci_set_bus_width,
607 .set_power = sdhci_set_power_and_bus_voltage,
608 .set_clock = sdhci_am654_set_clock,
609 .write_b = sdhci_am654_write_b,
610 .irq = sdhci_am654_cqhci_irq,
611 .reset = sdhci_and_cqhci_reset,
612 };
613
614 static const struct sdhci_pltfm_data sdhci_am654_pdata = {
615 .ops = &sdhci_am654_ops,
616 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
617 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
618 SDHCI_QUIRK2_DISABLE_HW_TIMEOUT,
619 };
620
621 static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = {
622 .pdata = &sdhci_am654_pdata,
623 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT |
624 DLL_CALIB,
625 };
626
627 static const struct sdhci_am654_driver_data sdhci_am654_drvdata = {
628 .pdata = &sdhci_am654_pdata,
629 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT,
630 };
631
632 static const struct sdhci_ops sdhci_j721e_8bit_ops = {
633 .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
634 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
635 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
636 .set_uhs_signaling = sdhci_set_uhs_signaling,
637 .set_bus_width = sdhci_set_bus_width,
638 .set_power = sdhci_set_power_and_bus_voltage,
639 .set_clock = sdhci_am654_set_clock,
640 .write_b = sdhci_am654_write_b,
641 .irq = sdhci_am654_cqhci_irq,
642 .reset = sdhci_and_cqhci_reset,
643 };
644
645 static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = {
646 .ops = &sdhci_j721e_8bit_ops,
647 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
648 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
649 SDHCI_QUIRK2_DISABLE_HW_TIMEOUT,
650 };
651
652 static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = {
653 .pdata = &sdhci_j721e_8bit_pdata,
654 .flags = DLL_PRESENT | DLL_CALIB,
655 };
656
657 static const struct sdhci_ops sdhci_j721e_4bit_ops = {
658 .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
659 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
660 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
661 .set_uhs_signaling = sdhci_set_uhs_signaling,
662 .set_bus_width = sdhci_set_bus_width,
663 .set_power = sdhci_set_power_and_bus_voltage,
664 .set_clock = sdhci_j721e_4bit_set_clock,
665 .write_b = sdhci_am654_write_b,
666 .irq = sdhci_am654_cqhci_irq,
667 .reset = sdhci_am654_reset,
668 };
669
670 static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = {
671 .ops = &sdhci_j721e_4bit_ops,
672 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
673 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
674 SDHCI_QUIRK2_DISABLE_HW_TIMEOUT,
675 };
676
677 static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = {
678 .pdata = &sdhci_j721e_4bit_pdata,
679 .flags = IOMUX_PRESENT,
680 };
681
682 static const struct sdhci_am654_driver_data sdhci_am62_4bit_drvdata = {
683 .pdata = &sdhci_j721e_4bit_pdata,
684 .flags = IOMUX_PRESENT,
685 .quirks = SDHCI_AM654_QUIRK_SUPPRESS_V1P8_ENA,
686 };
687
688 static const struct soc_device_attribute sdhci_am654_devices[] = {
689 { .family = "AM65X",
690 .revision = "SR1.0",
691 .data = &sdhci_am654_sr1_drvdata
692 },
693 {/* sentinel */}
694 };
695
sdhci_am654_dumpregs(struct mmc_host * mmc)696 static void sdhci_am654_dumpregs(struct mmc_host *mmc)
697 {
698 sdhci_dumpregs(mmc_priv(mmc));
699 }
700
701 static const struct cqhci_host_ops sdhci_am654_cqhci_ops = {
702 .enable = sdhci_cqe_enable,
703 .disable = sdhci_cqe_disable,
704 .dumpregs = sdhci_am654_dumpregs,
705 };
706
sdhci_am654_cqe_add_host(struct sdhci_host * host)707 static int sdhci_am654_cqe_add_host(struct sdhci_host *host)
708 {
709 struct cqhci_host *cq_host;
710
711 cq_host = devm_kzalloc(mmc_dev(host->mmc), sizeof(struct cqhci_host),
712 GFP_KERNEL);
713 if (!cq_host)
714 return -ENOMEM;
715
716 cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR;
717 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
718 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
719 cq_host->ops = &sdhci_am654_cqhci_ops;
720
721 host->mmc->caps2 |= MMC_CAP2_CQE;
722
723 return cqhci_init(cq_host, host->mmc, 1);
724 }
725
sdhci_am654_get_otap_delay(struct sdhci_host * host,struct sdhci_am654_data * sdhci_am654)726 static int sdhci_am654_get_otap_delay(struct sdhci_host *host,
727 struct sdhci_am654_data *sdhci_am654)
728 {
729 struct device *dev = mmc_dev(host->mmc);
730 int i;
731 int ret;
732
733 for (i = MMC_TIMING_LEGACY; i <= MMC_TIMING_MMC_HS400; i++) {
734
735 ret = device_property_read_u32(dev, td[i].otap_binding,
736 &sdhci_am654->otap_del_sel[i]);
737 if (ret) {
738 if (i == MMC_TIMING_LEGACY) {
739 dev_err(dev, "Couldn't find mandatory ti,otap-del-sel-legacy\n");
740 return ret;
741 }
742 dev_dbg(dev, "Couldn't find %s\n",
743 td[i].otap_binding);
744 /*
745 * Remove the corresponding capability
746 * if an otap-del-sel value is not found
747 */
748 if (i <= MMC_TIMING_MMC_DDR52)
749 host->mmc->caps &= ~td[i].capability;
750 else
751 host->mmc->caps2 &= ~td[i].capability;
752 }
753
754 if (td[i].itap_binding) {
755 ret = device_property_read_u32(dev, td[i].itap_binding,
756 &sdhci_am654->itap_del_sel[i]);
757 if (!ret)
758 sdhci_am654->itap_del_ena[i] = 0x1;
759 }
760 }
761
762 return 0;
763 }
764
sdhci_am654_init(struct sdhci_host * host)765 static int sdhci_am654_init(struct sdhci_host *host)
766 {
767 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
768 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
769 struct device *dev = mmc_dev(host->mmc);
770 u32 ctl_cfg_2 = 0;
771 u32 mask;
772 u32 val;
773 int ret;
774
775 /* Reset OTAP to default value */
776 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
777 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0);
778
779 if (sdhci_am654->flags & DLL_CALIB) {
780 regmap_read(sdhci_am654->base, PHY_STAT1, &val);
781 if (~val & CALDONE_MASK) {
782 /* Calibrate IO lines */
783 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
784 PDB_MASK, PDB_MASK);
785 ret = regmap_read_poll_timeout(sdhci_am654->base,
786 PHY_STAT1, val,
787 val & CALDONE_MASK,
788 1, 20);
789 if (ret)
790 return ret;
791 }
792 }
793
794 /* Enable pins by setting IO mux to 0 */
795 if (sdhci_am654->flags & IOMUX_PRESENT)
796 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
797 IOMUX_ENABLE_MASK, 0);
798
799 /* Set slot type based on SD or eMMC */
800 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
801 ctl_cfg_2 = SLOTTYPE_EMBEDDED;
802
803 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
804 ctl_cfg_2);
805
806 /* Enable tuning for SDR50 */
807 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK,
808 TUNINGFORSDR50_MASK);
809
810 /* Use to re-execute tuning */
811 sdhci_am654->tuning_loop = 0;
812
813 ret = sdhci_setup_host(host);
814 if (ret)
815 return ret;
816
817 ret = sdhci_am654_cqe_add_host(host);
818 if (ret)
819 goto err_cleanup_host;
820
821 ret = sdhci_am654_get_otap_delay(host, sdhci_am654);
822 if (ret)
823 goto err_cleanup_host;
824
825 if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_DISABLE_HS400 &&
826 host->mmc->caps2 & (MMC_CAP2_HS400 | MMC_CAP2_HS400_ES)) {
827 dev_info(dev, "HS400 mode not supported on this silicon revision, disabling it\n");
828 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
829 }
830
831 ret = __sdhci_add_host(host);
832 if (ret)
833 goto err_cleanup_host;
834
835 return 0;
836
837 err_cleanup_host:
838 sdhci_cleanup_host(host);
839 return ret;
840 }
841
sdhci_am654_get_of_property(struct platform_device * pdev,struct sdhci_am654_data * sdhci_am654)842 static int sdhci_am654_get_of_property(struct platform_device *pdev,
843 struct sdhci_am654_data *sdhci_am654)
844 {
845 struct device *dev = &pdev->dev;
846 int drv_strength;
847 int ret;
848
849 if (sdhci_am654->flags & DLL_PRESENT) {
850 ret = device_property_read_u32(dev, "ti,trm-icp",
851 &sdhci_am654->trm_icp);
852 if (ret)
853 return ret;
854
855 ret = device_property_read_u32(dev, "ti,driver-strength-ohm",
856 &drv_strength);
857 if (ret)
858 return ret;
859
860 switch (drv_strength) {
861 case 50:
862 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM;
863 break;
864 case 33:
865 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM;
866 break;
867 case 66:
868 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM;
869 break;
870 case 100:
871 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM;
872 break;
873 case 40:
874 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM;
875 break;
876 default:
877 dev_err(dev, "Invalid driver strength\n");
878 return -EINVAL;
879 }
880 }
881
882 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel);
883 device_property_read_u32(dev, "ti,clkbuf-sel",
884 &sdhci_am654->clkbuf_sel);
885
886 if (device_property_read_bool(dev, "ti,fails-without-test-cd"))
887 sdhci_am654->quirks |= SDHCI_AM654_QUIRK_FORCE_CDTEST;
888
889 sdhci_get_of_property(pdev);
890
891 return 0;
892 }
893
894 static const struct soc_device_attribute sdhci_am654_descope_hs400[] = {
895 { .family = "AM62PX", .revision = "SR1.0" },
896 { .family = "AM62PX", .revision = "SR1.1" },
897 { /* sentinel */ }
898 };
899
900 static const struct of_device_id sdhci_am654_of_match[] = {
901 {
902 .compatible = "ti,am654-sdhci-5.1",
903 .data = &sdhci_am654_drvdata,
904 },
905 {
906 .compatible = "ti,j721e-sdhci-8bit",
907 .data = &sdhci_j721e_8bit_drvdata,
908 },
909 {
910 .compatible = "ti,j721e-sdhci-4bit",
911 .data = &sdhci_j721e_4bit_drvdata,
912 },
913 {
914 .compatible = "ti,am64-sdhci-8bit",
915 .data = &sdhci_j721e_8bit_drvdata,
916 },
917 {
918 .compatible = "ti,am64-sdhci-4bit",
919 .data = &sdhci_j721e_4bit_drvdata,
920 },
921 {
922 .compatible = "ti,am62-sdhci",
923 .data = &sdhci_am62_4bit_drvdata,
924 },
925 { /* sentinel */ }
926 };
927 MODULE_DEVICE_TABLE(of, sdhci_am654_of_match);
928
sdhci_am654_probe(struct platform_device * pdev)929 static int sdhci_am654_probe(struct platform_device *pdev)
930 {
931 const struct sdhci_am654_driver_data *drvdata;
932 const struct soc_device_attribute *soc;
933 struct sdhci_pltfm_host *pltfm_host;
934 struct sdhci_am654_data *sdhci_am654;
935 const struct of_device_id *match;
936 struct sdhci_host *host;
937 struct clk *clk_xin;
938 struct device *dev = &pdev->dev;
939 void __iomem *base;
940 int ret;
941
942 match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node);
943 drvdata = match->data;
944
945 /* Update drvdata based on SoC revision */
946 soc = soc_device_match(sdhci_am654_devices);
947 if (soc && soc->data)
948 drvdata = soc->data;
949
950 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654));
951 if (IS_ERR(host))
952 return PTR_ERR(host);
953
954 pltfm_host = sdhci_priv(host);
955 sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
956 sdhci_am654->flags = drvdata->flags;
957 sdhci_am654->quirks = drvdata->quirks;
958
959 clk_xin = devm_clk_get(dev, "clk_xin");
960 if (IS_ERR(clk_xin)) {
961 dev_err(dev, "clk_xin clock not found.\n");
962 return PTR_ERR(clk_xin);
963 }
964
965 pltfm_host->clk = clk_xin;
966
967 base = devm_platform_ioremap_resource(pdev, 1);
968 if (IS_ERR(base)) {
969 return PTR_ERR(base);
970 }
971
972 sdhci_am654->base = devm_regmap_init_mmio(dev, base,
973 &sdhci_am654_regmap_config);
974 if (IS_ERR(sdhci_am654->base)) {
975 dev_err(dev, "Failed to initialize regmap\n");
976 return PTR_ERR(sdhci_am654->base);
977 }
978
979 ret = sdhci_am654_get_of_property(pdev, sdhci_am654);
980 if (ret)
981 return ret;
982
983 ret = mmc_of_parse(host->mmc);
984 if (ret)
985 return dev_err_probe(dev, ret, "parsing dt failed\n");
986
987 soc = soc_device_match(sdhci_am654_descope_hs400);
988 if (soc)
989 sdhci_am654->quirks |= SDHCI_AM654_QUIRK_DISABLE_HS400;
990
991 host->mmc_host_ops.start_signal_voltage_switch = sdhci_am654_start_signal_voltage_switch;
992 host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning;
993
994 pm_runtime_get_noresume(dev);
995 ret = pm_runtime_set_active(dev);
996 if (ret)
997 goto pm_put;
998 pm_runtime_enable(dev);
999 ret = clk_prepare_enable(pltfm_host->clk);
1000 if (ret)
1001 goto pm_disable;
1002
1003 ret = sdhci_am654_init(host);
1004 if (ret)
1005 goto clk_disable;
1006
1007 /* Setting up autosuspend */
1008 pm_runtime_set_autosuspend_delay(dev, SDHCI_AM654_AUTOSUSPEND_DELAY);
1009 pm_runtime_use_autosuspend(dev);
1010 pm_runtime_put_autosuspend(dev);
1011 return 0;
1012
1013 clk_disable:
1014 clk_disable_unprepare(pltfm_host->clk);
1015 pm_disable:
1016 pm_runtime_disable(dev);
1017 pm_put:
1018 pm_runtime_put_noidle(dev);
1019 return ret;
1020 }
1021
sdhci_am654_remove(struct platform_device * pdev)1022 static void sdhci_am654_remove(struct platform_device *pdev)
1023 {
1024 struct sdhci_host *host = platform_get_drvdata(pdev);
1025 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1026 struct device *dev = &pdev->dev;
1027 int ret;
1028
1029 ret = pm_runtime_get_sync(dev);
1030 if (ret < 0)
1031 dev_err(dev, "pm_runtime_get_sync() Failed\n");
1032
1033 sdhci_remove_host(host, true);
1034 clk_disable_unprepare(pltfm_host->clk);
1035 pm_runtime_disable(dev);
1036 pm_runtime_put_noidle(dev);
1037 }
1038
1039 #ifdef CONFIG_PM
sdhci_am654_restore(struct sdhci_host * host)1040 static int sdhci_am654_restore(struct sdhci_host *host)
1041 {
1042 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1043 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
1044 u32 ctl_cfg_2 = 0;
1045 u32 val;
1046 int ret;
1047
1048 if (sdhci_am654->flags & DLL_CALIB) {
1049 regmap_read(sdhci_am654->base, PHY_STAT1, &val);
1050 if (~val & CALDONE_MASK) {
1051 /* Calibrate IO lines */
1052 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
1053 PDB_MASK, PDB_MASK);
1054 ret = regmap_read_poll_timeout(sdhci_am654->base,
1055 PHY_STAT1, val,
1056 val & CALDONE_MASK,
1057 1, 20);
1058 if (ret)
1059 return ret;
1060 }
1061 }
1062
1063 /* Enable pins by setting IO mux to 0 */
1064 if (sdhci_am654->flags & IOMUX_PRESENT)
1065 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
1066 IOMUX_ENABLE_MASK, 0);
1067
1068 /* Set slot type based on SD or eMMC */
1069 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
1070 ctl_cfg_2 = SLOTTYPE_EMBEDDED;
1071
1072 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
1073 ctl_cfg_2);
1074
1075 regmap_read(sdhci_am654->base, CTL_CFG_3, &val);
1076 if (~val & TUNINGFORSDR50_MASK)
1077 /* Enable tuning for SDR50 */
1078 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK,
1079 TUNINGFORSDR50_MASK);
1080
1081 return 0;
1082 }
1083
sdhci_am654_runtime_suspend(struct device * dev)1084 static int sdhci_am654_runtime_suspend(struct device *dev)
1085 {
1086 struct sdhci_host *host = dev_get_drvdata(dev);
1087 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1088 int ret;
1089
1090 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1091 mmc_retune_needed(host->mmc);
1092
1093 ret = cqhci_suspend(host->mmc);
1094 if (ret)
1095 return ret;
1096
1097 sdhci_runtime_suspend_host(host);
1098
1099 /* disable the clock */
1100 clk_disable_unprepare(pltfm_host->clk);
1101 return 0;
1102 }
1103
sdhci_am654_runtime_resume(struct device * dev)1104 static int sdhci_am654_runtime_resume(struct device *dev)
1105 {
1106 struct sdhci_host *host = dev_get_drvdata(dev);
1107 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1108 int ret;
1109
1110 /* Enable the clock */
1111 ret = clk_prepare_enable(pltfm_host->clk);
1112 if (ret)
1113 return ret;
1114
1115 ret = sdhci_am654_restore(host);
1116 if (ret)
1117 return ret;
1118
1119 sdhci_runtime_resume_host(host, 0);
1120
1121 ret = cqhci_resume(host->mmc);
1122 if (ret)
1123 return ret;
1124
1125 return 0;
1126 }
1127 #endif
1128
1129 static const struct dev_pm_ops sdhci_am654_dev_pm_ops = {
1130 SET_RUNTIME_PM_OPS(sdhci_am654_runtime_suspend,
1131 sdhci_am654_runtime_resume, NULL)
1132 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1133 pm_runtime_force_resume)
1134 };
1135
1136 static struct platform_driver sdhci_am654_driver = {
1137 .driver = {
1138 .name = "sdhci-am654",
1139 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1140 .pm = &sdhci_am654_dev_pm_ops,
1141 .of_match_table = sdhci_am654_of_match,
1142 },
1143 .probe = sdhci_am654_probe,
1144 .remove = sdhci_am654_remove,
1145 };
1146
1147 module_platform_driver(sdhci_am654_driver);
1148
1149 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices");
1150 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>");
1151 MODULE_LICENSE("GPL");
1152