1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Xia Jiang <xia.jiang@mediatek.com>
5 *
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/bits.h>
10 #include <linux/clk.h>
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/io.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/slab.h>
19 #include <media/media-device.h>
20 #include <media/videobuf2-core.h>
21 #include <media/videobuf2-dma-contig.h>
22 #include <media/videobuf2-v4l2.h>
23 #include <media/v4l2-mem2mem.h>
24 #include <media/v4l2-dev.h>
25 #include <media/v4l2-device.h>
26 #include <media/v4l2-fh.h>
27 #include <media/v4l2-event.h>
28
29 #include "mtk_jpeg_core.h"
30 #include "mtk_jpeg_enc_hw.h"
31
32 static const struct mtk_jpeg_enc_qlt mtk_jpeg_enc_quality[] = {
33 {.quality_param = 34, .hardware_value = JPEG_ENC_QUALITY_Q34},
34 {.quality_param = 39, .hardware_value = JPEG_ENC_QUALITY_Q39},
35 {.quality_param = 48, .hardware_value = JPEG_ENC_QUALITY_Q48},
36 {.quality_param = 60, .hardware_value = JPEG_ENC_QUALITY_Q60},
37 {.quality_param = 64, .hardware_value = JPEG_ENC_QUALITY_Q64},
38 {.quality_param = 68, .hardware_value = JPEG_ENC_QUALITY_Q68},
39 {.quality_param = 74, .hardware_value = JPEG_ENC_QUALITY_Q74},
40 {.quality_param = 80, .hardware_value = JPEG_ENC_QUALITY_Q80},
41 {.quality_param = 82, .hardware_value = JPEG_ENC_QUALITY_Q82},
42 {.quality_param = 84, .hardware_value = JPEG_ENC_QUALITY_Q84},
43 {.quality_param = 87, .hardware_value = JPEG_ENC_QUALITY_Q87},
44 {.quality_param = 90, .hardware_value = JPEG_ENC_QUALITY_Q90},
45 {.quality_param = 92, .hardware_value = JPEG_ENC_QUALITY_Q92},
46 {.quality_param = 95, .hardware_value = JPEG_ENC_QUALITY_Q95},
47 {.quality_param = 97, .hardware_value = JPEG_ENC_QUALITY_Q97},
48 };
49
50 static const struct of_device_id mtk_jpegenc_drv_ids[] = {
51 {
52 .compatible = "mediatek,mt8195-jpgenc-hw",
53 },
54 {},
55 };
56 MODULE_DEVICE_TABLE(of, mtk_jpegenc_drv_ids);
57
mtk_jpeg_enc_reset(void __iomem * base)58 void mtk_jpeg_enc_reset(void __iomem *base)
59 {
60 writel(0, base + JPEG_ENC_RSTB);
61 writel(JPEG_ENC_RESET_BIT, base + JPEG_ENC_RSTB);
62 writel(0, base + JPEG_ENC_CODEC_SEL);
63 }
64 EXPORT_SYMBOL_GPL(mtk_jpeg_enc_reset);
65
mtk_jpeg_enc_get_file_size(void __iomem * base,bool support_34bit)66 u32 mtk_jpeg_enc_get_file_size(void __iomem *base, bool support_34bit)
67 {
68 return (readl(base + JPEG_ENC_DMA_ADDR0) << ((support_34bit) ? 2 : 0)) -
69 readl(base + JPEG_ENC_DST_ADDR0);
70 }
71 EXPORT_SYMBOL_GPL(mtk_jpeg_enc_get_file_size);
72
mtk_jpeg_enc_start(void __iomem * base)73 void mtk_jpeg_enc_start(void __iomem *base)
74 {
75 u32 value;
76
77 value = readl(base + JPEG_ENC_CTRL);
78 value |= JPEG_ENC_CTRL_INT_EN_BIT | JPEG_ENC_CTRL_ENABLE_BIT;
79 writel(value, base + JPEG_ENC_CTRL);
80 }
81 EXPORT_SYMBOL_GPL(mtk_jpeg_enc_start);
82
mtk_jpeg_set_enc_src(struct mtk_jpeg_ctx * ctx,void __iomem * base,struct vb2_buffer * src_buf)83 void mtk_jpeg_set_enc_src(struct mtk_jpeg_ctx *ctx, void __iomem *base,
84 struct vb2_buffer *src_buf)
85 {
86 int i;
87 dma_addr_t dma_addr;
88 u32 addr_ext;
89 bool support_34bit = ctx->jpeg->variant->support_34bit;
90
91 for (i = 0; i < src_buf->num_planes; i++) {
92 dma_addr = vb2_dma_contig_plane_dma_addr(src_buf, i) +
93 src_buf->planes[i].data_offset;
94 if (i == 0)
95 writel(lower_32_bits(dma_addr), base + JPEG_ENC_SRC_LUMA_ADDR);
96 else
97 writel(lower_32_bits(dma_addr), base + JPEG_ENC_SRC_CHROMA_ADDR);
98
99 if (support_34bit) {
100 addr_ext = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(dma_addr));
101 if (i == 0)
102 writel(addr_ext, base + JPEG_ENC_SRC_LUMA_ADDR_EXT);
103 else
104 writel(addr_ext, base + JPEG_ENC_SRC_CHRO_ADDR_EXT);
105 }
106 }
107 }
108 EXPORT_SYMBOL_GPL(mtk_jpeg_set_enc_src);
109
mtk_jpeg_set_enc_dst(struct mtk_jpeg_ctx * ctx,void __iomem * base,struct vb2_buffer * dst_buf)110 void mtk_jpeg_set_enc_dst(struct mtk_jpeg_ctx *ctx, void __iomem *base,
111 struct vb2_buffer *dst_buf)
112 {
113 dma_addr_t dma_addr;
114 size_t size;
115 u32 dma_addr_offset;
116 u32 dma_addr_offsetmask;
117 u32 addr_ext;
118 bool support_34bit = ctx->jpeg->variant->support_34bit;
119
120 dma_addr = vb2_dma_contig_plane_dma_addr(dst_buf, 0);
121 dma_addr_offset = ctx->enable_exif ? MTK_JPEG_MAX_EXIF_SIZE : 0;
122 dma_addr_offsetmask = dma_addr & JPEG_ENC_DST_ADDR_OFFSET_MASK;
123 size = vb2_plane_size(dst_buf, 0);
124
125 writel(dma_addr_offset & ~0xf, base + JPEG_ENC_OFFSET_ADDR);
126 writel(dma_addr_offsetmask & 0xf, base + JPEG_ENC_BYTE_OFFSET_MASK);
127 writel(dma_addr & ~0xf, base + JPEG_ENC_DST_ADDR0);
128 writel((dma_addr + size) & ~0xf, base + JPEG_ENC_STALL_ADDR0);
129
130 if (support_34bit) {
131 addr_ext = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(dma_addr));
132 writel(addr_ext, base + JPEG_ENC_DEST_ADDR0_EXT);
133 writel(addr_ext + size, base + JPEG_ENC_STALL_ADDR0_EXT);
134 }
135 }
136 EXPORT_SYMBOL_GPL(mtk_jpeg_set_enc_dst);
137
mtk_jpeg_set_enc_params(struct mtk_jpeg_ctx * ctx,void __iomem * base)138 void mtk_jpeg_set_enc_params(struct mtk_jpeg_ctx *ctx, void __iomem *base)
139 {
140 u32 value;
141 u32 width = ctx->out_q.enc_crop_rect.width;
142 u32 height = ctx->out_q.enc_crop_rect.height;
143 u32 enc_format = ctx->out_q.fmt->fourcc;
144 u32 bytesperline = ctx->out_q.pix_mp.plane_fmt[0].bytesperline;
145 u32 blk_num;
146 u32 img_stride;
147 u32 mem_stride;
148 u32 i, enc_quality;
149 u32 nr_enc_quality = ARRAY_SIZE(mtk_jpeg_enc_quality);
150
151 value = width << 16 | height;
152 writel(value, base + JPEG_ENC_IMG_SIZE);
153
154 if (enc_format == V4L2_PIX_FMT_NV12M ||
155 enc_format == V4L2_PIX_FMT_NV21M)
156 /*
157 * Total 8 x 8 block number of luma and chroma.
158 * The number of blocks is counted from 0.
159 */
160 blk_num = DIV_ROUND_UP(width, 16) *
161 DIV_ROUND_UP(height, 16) * 6 - 1;
162 else
163 blk_num = DIV_ROUND_UP(width, 16) *
164 DIV_ROUND_UP(height, 8) * 4 - 1;
165 writel(blk_num, base + JPEG_ENC_BLK_NUM);
166
167 if (enc_format == V4L2_PIX_FMT_NV12M ||
168 enc_format == V4L2_PIX_FMT_NV21M) {
169 /* 4:2:0 */
170 img_stride = round_up(width, 16);
171 mem_stride = bytesperline;
172 } else {
173 /* 4:2:2 */
174 img_stride = round_up(width * 2, 32);
175 mem_stride = img_stride;
176 }
177 writel(img_stride, base + JPEG_ENC_IMG_STRIDE);
178 writel(mem_stride, base + JPEG_ENC_STRIDE);
179
180 enc_quality = mtk_jpeg_enc_quality[nr_enc_quality - 1].hardware_value;
181 for (i = 0; i < nr_enc_quality; i++) {
182 if (ctx->enc_quality <= mtk_jpeg_enc_quality[i].quality_param) {
183 enc_quality = mtk_jpeg_enc_quality[i].hardware_value;
184 break;
185 }
186 }
187 writel(enc_quality, base + JPEG_ENC_QUALITY);
188
189 value = readl(base + JPEG_ENC_CTRL);
190 value &= ~JPEG_ENC_CTRL_YUV_FORMAT_MASK;
191 value |= (ctx->out_q.fmt->hw_format & 3) << 3;
192 if (ctx->enable_exif)
193 value |= JPEG_ENC_CTRL_FILE_FORMAT_BIT;
194 else
195 value &= ~JPEG_ENC_CTRL_FILE_FORMAT_BIT;
196 if (ctx->restart_interval)
197 value |= JPEG_ENC_CTRL_RESTART_EN_BIT;
198 else
199 value &= ~JPEG_ENC_CTRL_RESTART_EN_BIT;
200 writel(value, base + JPEG_ENC_CTRL);
201
202 writel(ctx->restart_interval, base + JPEG_ENC_RST_MCU_NUM);
203 }
204 EXPORT_SYMBOL_GPL(mtk_jpeg_set_enc_params);
205
mtk_jpegenc_put_buf(struct mtk_jpegenc_comp_dev * jpeg)206 static void mtk_jpegenc_put_buf(struct mtk_jpegenc_comp_dev *jpeg)
207 {
208 struct mtk_jpeg_ctx *ctx;
209 struct vb2_v4l2_buffer *dst_buffer;
210 struct list_head *temp_entry;
211 struct list_head *pos = NULL;
212 struct mtk_jpeg_src_buf *dst_done_buf, *tmp_dst_done_buf;
213 unsigned long flags;
214
215 ctx = jpeg->hw_param.curr_ctx;
216 if (!ctx) {
217 dev_err(jpeg->dev, "comp_jpeg ctx fail !!!\n");
218 return;
219 }
220
221 dst_buffer = jpeg->hw_param.dst_buffer;
222 if (!dst_buffer) {
223 dev_err(jpeg->dev, "comp_jpeg dst_buffer fail !!!\n");
224 return;
225 }
226
227 dst_done_buf = container_of(dst_buffer,
228 struct mtk_jpeg_src_buf, b);
229
230 spin_lock_irqsave(&ctx->done_queue_lock, flags);
231 list_add_tail(&dst_done_buf->list, &ctx->dst_done_queue);
232 while (!list_empty(&ctx->dst_done_queue) &&
233 (pos != &ctx->dst_done_queue)) {
234 list_for_each_prev_safe(pos, temp_entry, &ctx->dst_done_queue) {
235 tmp_dst_done_buf = list_entry(pos,
236 struct mtk_jpeg_src_buf,
237 list);
238 if (tmp_dst_done_buf->frame_num ==
239 ctx->last_done_frame_num) {
240 list_del(&tmp_dst_done_buf->list);
241 v4l2_m2m_buf_done(&tmp_dst_done_buf->b,
242 VB2_BUF_STATE_DONE);
243 ctx->last_done_frame_num++;
244 }
245 }
246 }
247 spin_unlock_irqrestore(&ctx->done_queue_lock, flags);
248 }
249
mtk_jpegenc_timeout_work(struct work_struct * work)250 static void mtk_jpegenc_timeout_work(struct work_struct *work)
251 {
252 struct delayed_work *dly_work = to_delayed_work(work);
253 struct mtk_jpegenc_comp_dev *cjpeg =
254 container_of(dly_work,
255 struct mtk_jpegenc_comp_dev,
256 job_timeout_work);
257 struct mtk_jpeg_dev *master_jpeg = cjpeg->master_dev;
258 enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR;
259 struct vb2_v4l2_buffer *src_buf, *dst_buf;
260
261 src_buf = cjpeg->hw_param.src_buffer;
262 dst_buf = cjpeg->hw_param.dst_buffer;
263 v4l2_m2m_buf_copy_metadata(src_buf, dst_buf);
264
265 mtk_jpeg_enc_reset(cjpeg->reg_base);
266 clk_disable_unprepare(cjpeg->venc_clk.clks->clk);
267 pm_runtime_put(cjpeg->dev);
268 cjpeg->hw_state = MTK_JPEG_HW_IDLE;
269 atomic_inc(&master_jpeg->hw_rdy);
270 wake_up(&master_jpeg->hw_wq);
271 v4l2_m2m_buf_done(src_buf, buf_state);
272 mtk_jpegenc_put_buf(cjpeg);
273 }
274
mtk_jpegenc_hw_irq_handler(int irq,void * priv)275 static irqreturn_t mtk_jpegenc_hw_irq_handler(int irq, void *priv)
276 {
277 struct vb2_v4l2_buffer *src_buf, *dst_buf;
278 enum vb2_buffer_state buf_state;
279 struct mtk_jpeg_ctx *ctx;
280 u32 result_size;
281 u32 irq_status;
282
283 struct mtk_jpegenc_comp_dev *jpeg = priv;
284 struct mtk_jpeg_dev *master_jpeg = jpeg->master_dev;
285
286 cancel_delayed_work(&jpeg->job_timeout_work);
287
288 ctx = jpeg->hw_param.curr_ctx;
289 src_buf = jpeg->hw_param.src_buffer;
290 dst_buf = jpeg->hw_param.dst_buffer;
291 v4l2_m2m_buf_copy_metadata(src_buf, dst_buf);
292
293 irq_status = readl(jpeg->reg_base + JPEG_ENC_INT_STS) &
294 JPEG_ENC_INT_STATUS_MASK_ALLIRQ;
295 if (irq_status)
296 writel(0, jpeg->reg_base + JPEG_ENC_INT_STS);
297 if (!(irq_status & JPEG_ENC_INT_STATUS_DONE))
298 dev_warn(jpeg->dev, "Jpg Enc occurs unknown Err.");
299
300 result_size = mtk_jpeg_enc_get_file_size(jpeg->reg_base,
301 ctx->jpeg->variant->support_34bit);
302 vb2_set_plane_payload(&dst_buf->vb2_buf, 0, result_size);
303 buf_state = VB2_BUF_STATE_DONE;
304 v4l2_m2m_buf_done(src_buf, buf_state);
305 mtk_jpegenc_put_buf(jpeg);
306 pm_runtime_put(ctx->jpeg->dev);
307 clk_disable_unprepare(jpeg->venc_clk.clks->clk);
308
309 jpeg->hw_state = MTK_JPEG_HW_IDLE;
310 wake_up(&master_jpeg->hw_wq);
311 atomic_inc(&master_jpeg->hw_rdy);
312
313 return IRQ_HANDLED;
314 }
315
mtk_jpegenc_hw_init_irq(struct mtk_jpegenc_comp_dev * dev)316 static int mtk_jpegenc_hw_init_irq(struct mtk_jpegenc_comp_dev *dev)
317 {
318 struct platform_device *pdev = dev->plat_dev;
319 int ret;
320
321 dev->jpegenc_irq = platform_get_irq(pdev, 0);
322 if (dev->jpegenc_irq < 0)
323 return dev->jpegenc_irq;
324
325 ret = devm_request_irq(&pdev->dev,
326 dev->jpegenc_irq,
327 mtk_jpegenc_hw_irq_handler,
328 0,
329 pdev->name, dev);
330 if (ret) {
331 dev_err(&pdev->dev, "Failed to devm_request_irq %d (%d)",
332 dev->jpegenc_irq, ret);
333 return ret;
334 }
335
336 return 0;
337 }
338
mtk_jpegenc_hw_probe(struct platform_device * pdev)339 static int mtk_jpegenc_hw_probe(struct platform_device *pdev)
340 {
341 struct mtk_jpegenc_clk *jpegenc_clk;
342 struct mtk_jpeg_dev *master_dev;
343 struct mtk_jpegenc_comp_dev *dev;
344 int ret, i;
345
346 struct device *decs = &pdev->dev;
347
348 if (!decs->parent)
349 return -EPROBE_DEFER;
350
351 master_dev = dev_get_drvdata(decs->parent);
352 if (!master_dev)
353 return -EPROBE_DEFER;
354
355 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
356 if (!dev)
357 return -ENOMEM;
358
359 dev->plat_dev = pdev;
360 dev->dev = &pdev->dev;
361
362 spin_lock_init(&dev->hw_lock);
363 dev->hw_state = MTK_JPEG_HW_IDLE;
364
365 INIT_DELAYED_WORK(&dev->job_timeout_work,
366 mtk_jpegenc_timeout_work);
367
368 jpegenc_clk = &dev->venc_clk;
369
370 jpegenc_clk->clk_num = devm_clk_bulk_get_all(&pdev->dev,
371 &jpegenc_clk->clks);
372 if (jpegenc_clk->clk_num < 0)
373 return dev_err_probe(&pdev->dev, jpegenc_clk->clk_num,
374 "Failed to get jpegenc clock count\n");
375
376 dev->reg_base = devm_platform_ioremap_resource(pdev, 0);
377 if (IS_ERR(dev->reg_base))
378 return PTR_ERR(dev->reg_base);
379
380 ret = mtk_jpegenc_hw_init_irq(dev);
381 if (ret)
382 return ret;
383
384 i = atomic_add_return(1, &master_dev->hw_index) - 1;
385 master_dev->enc_hw_dev[i] = dev;
386 master_dev->reg_encbase[i] = dev->reg_base;
387 dev->master_dev = master_dev;
388
389 platform_set_drvdata(pdev, dev);
390 pm_runtime_enable(&pdev->dev);
391
392 return 0;
393 }
394
395 static struct platform_driver mtk_jpegenc_hw_driver = {
396 .probe = mtk_jpegenc_hw_probe,
397 .driver = {
398 .name = "mtk-jpegenc-hw",
399 .of_match_table = mtk_jpegenc_drv_ids,
400 },
401 };
402
403 module_platform_driver(mtk_jpegenc_hw_driver);
404
405 MODULE_DESCRIPTION("MediaTek JPEG encode HW driver");
406 MODULE_LICENSE("GPL");
407