1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* Copyright (C) 2019 ASPEED Technology Inc. */ 3 /* Copyright (C) 2019 IBM Corp. */ 4 5 #include <linux/clk.h> 6 #include <linux/delay.h> 7 #include <linux/device.h> 8 #include <linux/io.h> 9 #include <linux/math64.h> 10 #include <linux/mmc/host.h> 11 #include <linux/module.h> 12 #include <linux/of_address.h> 13 #include <linux/of.h> 14 #include <linux/of_platform.h> 15 #include <linux/platform_device.h> 16 #include <linux/reset.h> 17 #include <linux/spinlock.h> 18 19 #include "sdhci-pltfm.h" 20 21 #define ASPEED_SDC_INFO 0x00 22 #define ASPEED_SDC_S1_MMC8 BIT(25) 23 #define ASPEED_SDC_S0_MMC8 BIT(24) 24 #define ASPEED_SDC_PHASE 0xf4 25 #define ASPEED_SDC_S1_PHASE_IN GENMASK(25, 21) 26 #define ASPEED_SDC_S0_PHASE_IN GENMASK(20, 16) 27 #define ASPEED_SDC_S1_PHASE_OUT GENMASK(15, 11) 28 #define ASPEED_SDC_S1_PHASE_IN_EN BIT(10) 29 #define ASPEED_SDC_S1_PHASE_OUT_EN GENMASK(9, 8) 30 #define ASPEED_SDC_S0_PHASE_OUT GENMASK(7, 3) 31 #define ASPEED_SDC_S0_PHASE_IN_EN BIT(2) 32 #define ASPEED_SDC_S0_PHASE_OUT_EN GENMASK(1, 0) 33 #define ASPEED_SDC_PHASE_MAX 31 34 35 /* SDIO{10,20} */ 36 #define ASPEED_SDC_CAP1_1_8V (0 * 32 + 26) 37 /* SDIO{14,24} */ 38 #define ASPEED_SDC_CAP2_SDR104 (1 * 32 + 1) 39 40 struct aspeed_sdc { 41 struct clk *clk; 42 struct resource *res; 43 44 spinlock_t lock; 45 void __iomem *regs; 46 }; 47 48 struct aspeed_sdhci_tap_param { 49 bool valid; 50 51 #define ASPEED_SDHCI_TAP_PARAM_INVERT_CLK BIT(4) 52 u8 in; 53 u8 out; 54 }; 55 56 struct aspeed_sdhci_tap_desc { 57 u32 tap_mask; 58 u32 enable_mask; 59 u8 enable_value; 60 }; 61 62 struct aspeed_sdhci_phase_desc { 63 struct aspeed_sdhci_tap_desc in; 64 struct aspeed_sdhci_tap_desc out; 65 }; 66 67 struct aspeed_sdhci_pdata { 68 unsigned int clk_div_start; 69 const struct aspeed_sdhci_phase_desc *phase_desc; 70 size_t nr_phase_descs; 71 }; 72 73 struct aspeed_sdhci { 74 const struct aspeed_sdhci_pdata *pdata; 75 struct aspeed_sdc *parent; 76 u32 width_mask; 77 struct mmc_clk_phase_map phase_map; 78 const struct aspeed_sdhci_phase_desc *phase_desc; 79 }; 80 81 /* 82 * The function sets the mirror register for updating 83 * capbilities of the current slot. 84 * 85 * slot | capability | caps_reg | mirror_reg 86 * -----|-------------|----------|------------ 87 * 0 | CAP1_1_8V | SDIO140 | SDIO10 88 * 0 | CAP2_SDR104 | SDIO144 | SDIO14 89 * 1 | CAP1_1_8V | SDIO240 | SDIO20 90 * 1 | CAP2_SDR104 | SDIO244 | SDIO24 91 */ 92 static void aspeed_sdc_set_slot_capability(struct sdhci_host *host, struct aspeed_sdc *sdc, 93 int capability, bool enable, u8 slot) 94 { 95 u32 mirror_reg_offset; 96 u32 cap_val; 97 u8 cap_reg; 98 99 if (slot > 1) 100 return; 101 102 cap_reg = capability / 32; 103 cap_val = sdhci_readl(host, 0x40 + (cap_reg * 4)); 104 if (enable) 105 cap_val |= BIT(capability % 32); 106 else 107 cap_val &= ~BIT(capability % 32); 108 mirror_reg_offset = ((slot + 1) * 0x10) + (cap_reg * 4); 109 writel(cap_val, sdc->regs + mirror_reg_offset); 110 } 111 112 static void aspeed_sdc_configure_8bit_mode(struct aspeed_sdc *sdc, 113 struct aspeed_sdhci *sdhci, 114 bool bus8) 115 { 116 u32 info; 117 118 /* Set/clear 8 bit mode */ 119 spin_lock(&sdc->lock); 120 info = readl(sdc->regs + ASPEED_SDC_INFO); 121 if (bus8) 122 info |= sdhci->width_mask; 123 else 124 info &= ~sdhci->width_mask; 125 writel(info, sdc->regs + ASPEED_SDC_INFO); 126 spin_unlock(&sdc->lock); 127 } 128 129 static u32 130 aspeed_sdc_set_phase_tap(const struct aspeed_sdhci_tap_desc *desc, 131 u8 tap, bool enable, u32 reg) 132 { 133 reg &= ~(desc->enable_mask | desc->tap_mask); 134 if (enable) { 135 reg |= tap << __ffs(desc->tap_mask); 136 reg |= desc->enable_value << __ffs(desc->enable_mask); 137 } 138 139 return reg; 140 } 141 142 static void 143 aspeed_sdc_set_phase_taps(struct aspeed_sdc *sdc, 144 const struct aspeed_sdhci_phase_desc *desc, 145 const struct aspeed_sdhci_tap_param *taps) 146 { 147 u32 reg; 148 149 spin_lock(&sdc->lock); 150 reg = readl(sdc->regs + ASPEED_SDC_PHASE); 151 152 reg = aspeed_sdc_set_phase_tap(&desc->in, taps->in, taps->valid, reg); 153 reg = aspeed_sdc_set_phase_tap(&desc->out, taps->out, taps->valid, reg); 154 155 writel(reg, sdc->regs + ASPEED_SDC_PHASE); 156 spin_unlock(&sdc->lock); 157 } 158 159 #define PICOSECONDS_PER_SECOND 1000000000000ULL 160 #define ASPEED_SDHCI_NR_TAPS 15 161 /* Measured value with *handwave* environmentals and static loading */ 162 #define ASPEED_SDHCI_MAX_TAP_DELAY_PS 1253 163 static int aspeed_sdhci_phase_to_tap(struct device *dev, unsigned long rate_hz, 164 int phase_deg) 165 { 166 u64 phase_period_ps; 167 u64 prop_delay_ps; 168 u64 clk_period_ps; 169 unsigned int tap; 170 u8 inverted; 171 172 phase_deg %= 360; 173 174 if (phase_deg >= 180) { 175 inverted = ASPEED_SDHCI_TAP_PARAM_INVERT_CLK; 176 phase_deg -= 180; 177 dev_dbg(dev, 178 "Inverting clock to reduce phase correction from %d to %d degrees\n", 179 phase_deg + 180, phase_deg); 180 } else { 181 inverted = 0; 182 } 183 184 prop_delay_ps = ASPEED_SDHCI_MAX_TAP_DELAY_PS / ASPEED_SDHCI_NR_TAPS; 185 clk_period_ps = div_u64(PICOSECONDS_PER_SECOND, (u64)rate_hz); 186 phase_period_ps = div_u64((u64)phase_deg * clk_period_ps, 360ULL); 187 188 tap = div_u64(phase_period_ps, prop_delay_ps); 189 if (tap > ASPEED_SDHCI_NR_TAPS) { 190 dev_dbg(dev, 191 "Requested out of range phase tap %d for %d degrees of phase compensation at %luHz, clamping to tap %d\n", 192 tap, phase_deg, rate_hz, ASPEED_SDHCI_NR_TAPS); 193 tap = ASPEED_SDHCI_NR_TAPS; 194 } 195 196 return inverted | tap; 197 } 198 199 static void 200 aspeed_sdhci_phases_to_taps(struct device *dev, unsigned long rate, 201 const struct mmc_clk_phase *phases, 202 struct aspeed_sdhci_tap_param *taps) 203 { 204 taps->valid = phases->valid; 205 206 if (!phases->valid) 207 return; 208 209 taps->in = aspeed_sdhci_phase_to_tap(dev, rate, phases->in_deg); 210 taps->out = aspeed_sdhci_phase_to_tap(dev, rate, phases->out_deg); 211 } 212 213 static void 214 aspeed_sdhci_configure_phase(struct sdhci_host *host, unsigned long rate) 215 { 216 struct aspeed_sdhci_tap_param _taps = {0}, *taps = &_taps; 217 struct mmc_clk_phase *params; 218 struct aspeed_sdhci *sdhci; 219 struct device *dev; 220 221 dev = mmc_dev(host->mmc); 222 sdhci = sdhci_pltfm_priv(sdhci_priv(host)); 223 224 if (!sdhci->phase_desc) 225 return; 226 227 params = &sdhci->phase_map.phase[host->timing]; 228 aspeed_sdhci_phases_to_taps(dev, rate, params, taps); 229 aspeed_sdc_set_phase_taps(sdhci->parent, sdhci->phase_desc, taps); 230 dev_dbg(dev, 231 "Using taps [%d, %d] for [%d, %d] degrees of phase correction at %luHz (%d)\n", 232 taps->in & ASPEED_SDHCI_NR_TAPS, 233 taps->out & ASPEED_SDHCI_NR_TAPS, 234 params->in_deg, params->out_deg, rate, host->timing); 235 } 236 237 static void aspeed_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 238 { 239 struct sdhci_pltfm_host *pltfm_host; 240 unsigned long parent, bus; 241 struct aspeed_sdhci *sdhci; 242 int div; 243 u16 clk; 244 245 pltfm_host = sdhci_priv(host); 246 sdhci = sdhci_pltfm_priv(pltfm_host); 247 248 parent = clk_get_rate(pltfm_host->clk); 249 250 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 251 252 if (clock == 0) 253 return; 254 255 if (WARN_ON(clock > host->max_clk)) 256 clock = host->max_clk; 257 258 /* 259 * Regarding the AST2600: 260 * 261 * If (EMMC12C[7:6], EMMC12C[15:8] == 0) then 262 * period of SDCLK = period of SDMCLK. 263 * 264 * If (EMMC12C[7:6], EMMC12C[15:8] != 0) then 265 * period of SDCLK = period of SDMCLK * 2 * (EMMC12C[7:6], EMMC[15:8]) 266 * 267 * If you keep EMMC12C[7:6] = 0 and EMMC12C[15:8] as one-hot, 268 * 0x1/0x2/0x4/etc, you will find it is compatible to AST2400 or AST2500 269 * 270 * Keep the one-hot behaviour for backwards compatibility except for 271 * supporting the value 0 in (EMMC12C[7:6], EMMC12C[15:8]), and capture 272 * the 0-value capability in clk_div_start. 273 */ 274 for (div = sdhci->pdata->clk_div_start; div < 256; div *= 2) { 275 bus = parent / div; 276 if (bus <= clock) 277 break; 278 } 279 280 div >>= 1; 281 282 clk = div << SDHCI_DIVIDER_SHIFT; 283 284 aspeed_sdhci_configure_phase(host, bus); 285 286 sdhci_enable_clk(host, clk); 287 } 288 289 static unsigned int aspeed_sdhci_get_max_clock(struct sdhci_host *host) 290 { 291 if (host->mmc->f_max) 292 return host->mmc->f_max; 293 294 return sdhci_pltfm_clk_get_max_clock(host); 295 } 296 297 static void aspeed_sdhci_set_bus_width(struct sdhci_host *host, int width) 298 { 299 struct sdhci_pltfm_host *pltfm_priv; 300 struct aspeed_sdhci *aspeed_sdhci; 301 struct aspeed_sdc *aspeed_sdc; 302 u8 ctrl; 303 304 pltfm_priv = sdhci_priv(host); 305 aspeed_sdhci = sdhci_pltfm_priv(pltfm_priv); 306 aspeed_sdc = aspeed_sdhci->parent; 307 308 /* Set/clear 8-bit mode */ 309 aspeed_sdc_configure_8bit_mode(aspeed_sdc, aspeed_sdhci, 310 width == MMC_BUS_WIDTH_8); 311 312 /* Set/clear 1 or 4 bit mode */ 313 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 314 if (width == MMC_BUS_WIDTH_4) 315 ctrl |= SDHCI_CTRL_4BITBUS; 316 else 317 ctrl &= ~SDHCI_CTRL_4BITBUS; 318 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 319 } 320 321 static u32 aspeed_sdhci_readl(struct sdhci_host *host, int reg) 322 { 323 u32 val = readl(host->ioaddr + reg); 324 325 if (unlikely(reg == SDHCI_PRESENT_STATE) && 326 (host->mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH)) 327 val ^= SDHCI_CARD_PRESENT; 328 329 return val; 330 } 331 332 static const struct sdhci_ops aspeed_sdhci_ops = { 333 .read_l = aspeed_sdhci_readl, 334 .set_clock = aspeed_sdhci_set_clock, 335 .get_max_clock = aspeed_sdhci_get_max_clock, 336 .set_bus_width = aspeed_sdhci_set_bus_width, 337 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 338 .reset = sdhci_reset, 339 .set_uhs_signaling = sdhci_set_uhs_signaling, 340 }; 341 342 static const struct sdhci_pltfm_data aspeed_sdhci_pdata = { 343 .ops = &aspeed_sdhci_ops, 344 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 345 }; 346 347 static inline int aspeed_sdhci_calculate_slot(struct aspeed_sdhci *dev, 348 struct resource *res) 349 { 350 resource_size_t delta; 351 352 if (!res || resource_type(res) != IORESOURCE_MEM) 353 return -EINVAL; 354 355 if (res->start < dev->parent->res->start) 356 return -EINVAL; 357 358 delta = res->start - dev->parent->res->start; 359 if (delta & (0x100 - 1)) 360 return -EINVAL; 361 362 return (delta / 0x100) - 1; 363 } 364 365 static int aspeed_sdhci_probe(struct platform_device *pdev) 366 { 367 const struct aspeed_sdhci_pdata *aspeed_pdata; 368 struct device_node *np = pdev->dev.of_node; 369 struct sdhci_pltfm_host *pltfm_host; 370 struct aspeed_sdhci *dev; 371 struct sdhci_host *host; 372 struct resource *res; 373 int slot; 374 int ret; 375 376 aspeed_pdata = of_device_get_match_data(&pdev->dev); 377 if (!aspeed_pdata) { 378 dev_err(&pdev->dev, "Missing platform configuration data\n"); 379 return -EINVAL; 380 } 381 382 host = sdhci_pltfm_init(pdev, &aspeed_sdhci_pdata, sizeof(*dev)); 383 if (IS_ERR(host)) 384 return PTR_ERR(host); 385 386 pltfm_host = sdhci_priv(host); 387 dev = sdhci_pltfm_priv(pltfm_host); 388 dev->pdata = aspeed_pdata; 389 dev->parent = dev_get_drvdata(pdev->dev.parent); 390 391 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 392 slot = aspeed_sdhci_calculate_slot(dev, res); 393 394 if (slot < 0) 395 return slot; 396 else if (slot >= 2) 397 return -EINVAL; 398 399 if (slot < dev->pdata->nr_phase_descs) { 400 dev->phase_desc = &dev->pdata->phase_desc[slot]; 401 } else { 402 dev_info(&pdev->dev, 403 "Phase control not supported for slot %d\n", slot); 404 dev->phase_desc = NULL; 405 } 406 407 dev->width_mask = !slot ? ASPEED_SDC_S0_MMC8 : ASPEED_SDC_S1_MMC8; 408 409 dev_info(&pdev->dev, "Configured for slot %d\n", slot); 410 411 sdhci_get_of_property(pdev); 412 413 if (of_property_read_bool(np, "mmc-hs200-1_8v") || 414 of_property_read_bool(np, "sd-uhs-sdr104")) { 415 aspeed_sdc_set_slot_capability(host, dev->parent, ASPEED_SDC_CAP1_1_8V, 416 true, slot); 417 } 418 419 if (of_property_read_bool(np, "sd-uhs-sdr104")) { 420 aspeed_sdc_set_slot_capability(host, dev->parent, ASPEED_SDC_CAP2_SDR104, 421 true, slot); 422 } 423 424 pltfm_host->clk = devm_clk_get(&pdev->dev, NULL); 425 if (IS_ERR(pltfm_host->clk)) 426 return PTR_ERR(pltfm_host->clk); 427 428 ret = clk_prepare_enable(pltfm_host->clk); 429 if (ret) 430 return dev_err_probe(&pdev->dev, ret, "Unable to enable SDIO clock\n"); 431 432 ret = mmc_of_parse(host->mmc); 433 if (ret) 434 goto err_sdhci_add; 435 436 if (dev->phase_desc) 437 mmc_of_parse_clk_phase(&pdev->dev, &dev->phase_map); 438 439 ret = sdhci_add_host(host); 440 if (ret) 441 goto err_sdhci_add; 442 443 return 0; 444 445 err_sdhci_add: 446 clk_disable_unprepare(pltfm_host->clk); 447 return ret; 448 } 449 450 static void aspeed_sdhci_remove(struct platform_device *pdev) 451 { 452 struct sdhci_pltfm_host *pltfm_host; 453 struct sdhci_host *host; 454 455 host = platform_get_drvdata(pdev); 456 pltfm_host = sdhci_priv(host); 457 458 sdhci_remove_host(host, 0); 459 460 clk_disable_unprepare(pltfm_host->clk); 461 } 462 463 static const struct aspeed_sdhci_pdata ast2400_sdhci_pdata = { 464 .clk_div_start = 2, 465 }; 466 467 static const struct aspeed_sdhci_phase_desc ast2600_sdhci_phase[] = { 468 /* SDHCI/Slot 0 */ 469 [0] = { 470 .in = { 471 .tap_mask = ASPEED_SDC_S0_PHASE_IN, 472 .enable_mask = ASPEED_SDC_S0_PHASE_IN_EN, 473 .enable_value = 1, 474 }, 475 .out = { 476 .tap_mask = ASPEED_SDC_S0_PHASE_OUT, 477 .enable_mask = ASPEED_SDC_S0_PHASE_OUT_EN, 478 .enable_value = 3, 479 }, 480 }, 481 /* SDHCI/Slot 1 */ 482 [1] = { 483 .in = { 484 .tap_mask = ASPEED_SDC_S1_PHASE_IN, 485 .enable_mask = ASPEED_SDC_S1_PHASE_IN_EN, 486 .enable_value = 1, 487 }, 488 .out = { 489 .tap_mask = ASPEED_SDC_S1_PHASE_OUT, 490 .enable_mask = ASPEED_SDC_S1_PHASE_OUT_EN, 491 .enable_value = 3, 492 }, 493 }, 494 }; 495 496 static const struct aspeed_sdhci_pdata ast2600_sdhci_pdata = { 497 .clk_div_start = 1, 498 .phase_desc = ast2600_sdhci_phase, 499 .nr_phase_descs = ARRAY_SIZE(ast2600_sdhci_phase), 500 }; 501 502 static const struct of_device_id aspeed_sdhci_of_match[] = { 503 { .compatible = "aspeed,ast2400-sdhci", .data = &ast2400_sdhci_pdata, }, 504 { .compatible = "aspeed,ast2500-sdhci", .data = &ast2400_sdhci_pdata, }, 505 { .compatible = "aspeed,ast2600-sdhci", .data = &ast2600_sdhci_pdata, }, 506 { } 507 }; 508 MODULE_DEVICE_TABLE(of, aspeed_sdhci_of_match); 509 510 static struct platform_driver aspeed_sdhci_driver = { 511 .driver = { 512 .name = "sdhci-aspeed", 513 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 514 .of_match_table = aspeed_sdhci_of_match, 515 }, 516 .probe = aspeed_sdhci_probe, 517 .remove = aspeed_sdhci_remove, 518 }; 519 520 static int aspeed_sdc_probe(struct platform_device *pdev) 521 522 { 523 struct reset_control *reset; 524 struct device_node *parent; 525 struct aspeed_sdc *sdc; 526 int ret; 527 528 sdc = devm_kzalloc(&pdev->dev, sizeof(*sdc), GFP_KERNEL); 529 if (!sdc) 530 return -ENOMEM; 531 532 spin_lock_init(&sdc->lock); 533 534 reset = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev, NULL); 535 if (IS_ERR(reset)) 536 return dev_err_probe(&pdev->dev, PTR_ERR(reset), "unable to acquire reset\n"); 537 538 sdc->clk = devm_clk_get(&pdev->dev, NULL); 539 if (IS_ERR(sdc->clk)) 540 return PTR_ERR(sdc->clk); 541 542 ret = clk_prepare_enable(sdc->clk); 543 if (ret) { 544 dev_err(&pdev->dev, "Unable to enable SDCLK\n"); 545 return ret; 546 } 547 548 sdc->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &sdc->res); 549 if (IS_ERR(sdc->regs)) { 550 ret = PTR_ERR(sdc->regs); 551 goto err_clk; 552 } 553 554 dev_set_drvdata(&pdev->dev, sdc); 555 556 parent = pdev->dev.of_node; 557 for_each_available_child_of_node_scoped(parent, child) { 558 struct platform_device *cpdev; 559 560 cpdev = of_platform_device_create(child, NULL, &pdev->dev); 561 if (!cpdev) { 562 ret = -ENODEV; 563 goto err_clk; 564 } 565 } 566 567 return 0; 568 569 err_clk: 570 clk_disable_unprepare(sdc->clk); 571 return ret; 572 } 573 574 static void aspeed_sdc_remove(struct platform_device *pdev) 575 { 576 struct aspeed_sdc *sdc = dev_get_drvdata(&pdev->dev); 577 578 clk_disable_unprepare(sdc->clk); 579 } 580 581 static const struct of_device_id aspeed_sdc_of_match[] = { 582 { .compatible = "aspeed,ast2400-sd-controller", }, 583 { .compatible = "aspeed,ast2500-sd-controller", }, 584 { .compatible = "aspeed,ast2600-sd-controller", }, 585 { } 586 }; 587 588 MODULE_DEVICE_TABLE(of, aspeed_sdc_of_match); 589 590 static struct platform_driver aspeed_sdc_driver = { 591 .driver = { 592 .name = "sd-controller-aspeed", 593 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 594 .pm = &sdhci_pltfm_pmops, 595 .of_match_table = aspeed_sdc_of_match, 596 }, 597 .probe = aspeed_sdc_probe, 598 .remove = aspeed_sdc_remove, 599 }; 600 601 #if defined(CONFIG_MMC_SDHCI_OF_ASPEED_TEST) 602 #include "sdhci-of-aspeed-test.c" 603 #endif 604 605 static int __init aspeed_sdc_init(void) 606 { 607 int rc; 608 609 rc = platform_driver_register(&aspeed_sdhci_driver); 610 if (rc < 0) 611 return rc; 612 613 rc = platform_driver_register(&aspeed_sdc_driver); 614 if (rc < 0) 615 platform_driver_unregister(&aspeed_sdhci_driver); 616 617 return rc; 618 } 619 module_init(aspeed_sdc_init); 620 621 static void __exit aspeed_sdc_exit(void) 622 { 623 platform_driver_unregister(&aspeed_sdc_driver); 624 platform_driver_unregister(&aspeed_sdhci_driver); 625 } 626 module_exit(aspeed_sdc_exit); 627 628 MODULE_DESCRIPTION("Driver for the ASPEED SD/SDIO/SDHCI Controllers"); 629 MODULE_AUTHOR("Ryan Chen <ryan_chen@aspeedtech.com>"); 630 MODULE_AUTHOR("Andrew Jeffery <andrew@aj.id.au>"); 631 MODULE_LICENSE("GPL"); 632