1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2016 MediaTek Inc.
4 * Author: Zhiyong Tao <zhiyong.tao@mediatek.com>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/err.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/property.h>
14 #include <linux/iopoll.h>
15 #include <linux/io.h>
16 #include <linux/iio/iio.h>
17
18 /* Register definitions */
19 #define MT6577_AUXADC_CON0 0x00
20 #define MT6577_AUXADC_CON1 0x04
21 #define MT6577_AUXADC_CON2 0x10
22 #define MT6577_AUXADC_STA BIT(0)
23
24 #define MT6577_AUXADC_DAT0 0x14
25 #define MT6577_AUXADC_RDY0 BIT(12)
26
27 #define MT6577_AUXADC_MISC 0x94
28 #define MT6577_AUXADC_PDN_EN BIT(14)
29
30 #define MT6577_AUXADC_DAT_MASK 0xfff
31 #define MT6577_AUXADC_SLEEP_US 1000
32 #define MT6577_AUXADC_TIMEOUT_US 10000
33 #define MT6577_AUXADC_POWER_READY_MS 1
34 #define MT6577_AUXADC_SAMPLE_READY_US 25
35
36 struct mtk_auxadc_compatible {
37 bool sample_data_cali;
38 bool check_global_idle;
39 };
40
41 struct mt6577_auxadc_device {
42 void __iomem *reg_base;
43 struct clk *adc_clk;
44 struct mutex lock;
45 const struct mtk_auxadc_compatible *dev_comp;
46 };
47
48 static const struct mtk_auxadc_compatible mt8186_compat = {
49 .sample_data_cali = false,
50 .check_global_idle = false,
51 };
52
53 static const struct mtk_auxadc_compatible mt8173_compat = {
54 .sample_data_cali = false,
55 .check_global_idle = true,
56 };
57
58 static const struct mtk_auxadc_compatible mt6765_compat = {
59 .sample_data_cali = true,
60 .check_global_idle = false,
61 };
62
63 #define MT6577_AUXADC_CHANNEL(idx) { \
64 .type = IIO_VOLTAGE, \
65 .indexed = 1, \
66 .channel = (idx), \
67 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \
68 }
69
70 static const struct iio_chan_spec mt6577_auxadc_iio_channels[] = {
71 MT6577_AUXADC_CHANNEL(0),
72 MT6577_AUXADC_CHANNEL(1),
73 MT6577_AUXADC_CHANNEL(2),
74 MT6577_AUXADC_CHANNEL(3),
75 MT6577_AUXADC_CHANNEL(4),
76 MT6577_AUXADC_CHANNEL(5),
77 MT6577_AUXADC_CHANNEL(6),
78 MT6577_AUXADC_CHANNEL(7),
79 MT6577_AUXADC_CHANNEL(8),
80 MT6577_AUXADC_CHANNEL(9),
81 MT6577_AUXADC_CHANNEL(10),
82 MT6577_AUXADC_CHANNEL(11),
83 MT6577_AUXADC_CHANNEL(12),
84 MT6577_AUXADC_CHANNEL(13),
85 MT6577_AUXADC_CHANNEL(14),
86 MT6577_AUXADC_CHANNEL(15),
87 };
88
89 /* For Voltage calculation */
90 #define VOLTAGE_FULL_RANGE 1500 /* VA voltage */
91 #define AUXADC_PRECISE 4096 /* 12 bits */
92
mt_auxadc_get_cali_data(int rawdata,bool enable_cali)93 static int mt_auxadc_get_cali_data(int rawdata, bool enable_cali)
94 {
95 return rawdata;
96 }
97
mt6577_auxadc_mod_reg(void __iomem * reg,u32 or_mask,u32 and_mask)98 static inline void mt6577_auxadc_mod_reg(void __iomem *reg,
99 u32 or_mask, u32 and_mask)
100 {
101 u32 val;
102
103 val = readl(reg);
104 val |= or_mask;
105 val &= ~and_mask;
106 writel(val, reg);
107 }
108
mt6577_auxadc_read(struct iio_dev * indio_dev,struct iio_chan_spec const * chan)109 static int mt6577_auxadc_read(struct iio_dev *indio_dev,
110 struct iio_chan_spec const *chan)
111 {
112 u32 val;
113 void __iomem *reg_channel;
114 int ret;
115 struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev);
116
117 reg_channel = adc_dev->reg_base + MT6577_AUXADC_DAT0 +
118 chan->channel * 0x04;
119
120 mutex_lock(&adc_dev->lock);
121
122 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_CON1,
123 0, 1 << chan->channel);
124
125 /* read channel and make sure old ready bit == 0 */
126 ret = readl_poll_timeout(reg_channel, val,
127 ((val & MT6577_AUXADC_RDY0) == 0),
128 MT6577_AUXADC_SLEEP_US,
129 MT6577_AUXADC_TIMEOUT_US);
130 if (ret < 0) {
131 dev_err(indio_dev->dev.parent,
132 "wait for channel[%d] ready bit clear time out\n",
133 chan->channel);
134 goto err_timeout;
135 }
136
137 /* set bit to trigger sample */
138 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_CON1,
139 1 << chan->channel, 0);
140
141 /* we must delay here for hardware sample channel data */
142 udelay(MT6577_AUXADC_SAMPLE_READY_US);
143
144 if (adc_dev->dev_comp->check_global_idle) {
145 /* check MTK_AUXADC_CON2 if auxadc is idle */
146 ret = readl_poll_timeout(adc_dev->reg_base + MT6577_AUXADC_CON2,
147 val, ((val & MT6577_AUXADC_STA) == 0),
148 MT6577_AUXADC_SLEEP_US,
149 MT6577_AUXADC_TIMEOUT_US);
150 if (ret < 0) {
151 dev_err(indio_dev->dev.parent,
152 "wait for auxadc idle time out\n");
153 goto err_timeout;
154 }
155 }
156
157 /* read channel and make sure ready bit == 1 */
158 ret = readl_poll_timeout(reg_channel, val,
159 ((val & MT6577_AUXADC_RDY0) != 0),
160 MT6577_AUXADC_SLEEP_US,
161 MT6577_AUXADC_TIMEOUT_US);
162 if (ret < 0) {
163 dev_err(indio_dev->dev.parent,
164 "wait for channel[%d] data ready time out\n",
165 chan->channel);
166 goto err_timeout;
167 }
168
169 /* read data */
170 val = readl(reg_channel) & MT6577_AUXADC_DAT_MASK;
171
172 mutex_unlock(&adc_dev->lock);
173
174 return val;
175
176 err_timeout:
177
178 mutex_unlock(&adc_dev->lock);
179
180 return -ETIMEDOUT;
181 }
182
mt6577_auxadc_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)183 static int mt6577_auxadc_read_raw(struct iio_dev *indio_dev,
184 struct iio_chan_spec const *chan,
185 int *val,
186 int *val2,
187 long info)
188 {
189 struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev);
190
191 switch (info) {
192 case IIO_CHAN_INFO_PROCESSED:
193 *val = mt6577_auxadc_read(indio_dev, chan);
194 if (*val < 0) {
195 dev_err(indio_dev->dev.parent,
196 "failed to sample data on channel[%d]\n",
197 chan->channel);
198 return *val;
199 }
200 if (adc_dev->dev_comp->sample_data_cali)
201 *val = mt_auxadc_get_cali_data(*val, true);
202
203 /* Convert adc raw data to voltage: 0 - 1500 mV */
204 *val = *val * VOLTAGE_FULL_RANGE / AUXADC_PRECISE;
205
206 return IIO_VAL_INT;
207
208 default:
209 return -EINVAL;
210 }
211 }
212
213 static const struct iio_info mt6577_auxadc_info = {
214 .read_raw = &mt6577_auxadc_read_raw,
215 };
216
mt6577_auxadc_resume(struct device * dev)217 static int mt6577_auxadc_resume(struct device *dev)
218 {
219 struct iio_dev *indio_dev = dev_get_drvdata(dev);
220 struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev);
221 int ret;
222
223 ret = clk_prepare_enable(adc_dev->adc_clk);
224 if (ret) {
225 pr_err("failed to enable auxadc clock\n");
226 return ret;
227 }
228
229 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
230 MT6577_AUXADC_PDN_EN, 0);
231 mdelay(MT6577_AUXADC_POWER_READY_MS);
232
233 return 0;
234 }
235
mt6577_auxadc_suspend(struct device * dev)236 static int mt6577_auxadc_suspend(struct device *dev)
237 {
238 struct iio_dev *indio_dev = dev_get_drvdata(dev);
239 struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev);
240
241 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
242 0, MT6577_AUXADC_PDN_EN);
243 clk_disable_unprepare(adc_dev->adc_clk);
244
245 return 0;
246 }
247
mt6577_power_off(void * data)248 static void mt6577_power_off(void *data)
249 {
250 struct mt6577_auxadc_device *adc_dev = data;
251
252 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
253 0, MT6577_AUXADC_PDN_EN);
254 }
255
mt6577_auxadc_probe(struct platform_device * pdev)256 static int mt6577_auxadc_probe(struct platform_device *pdev)
257 {
258 struct mt6577_auxadc_device *adc_dev;
259 unsigned long adc_clk_rate;
260 struct iio_dev *indio_dev;
261 int ret;
262
263 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc_dev));
264 if (!indio_dev)
265 return -ENOMEM;
266
267 adc_dev = iio_priv(indio_dev);
268 indio_dev->name = dev_name(&pdev->dev);
269 indio_dev->info = &mt6577_auxadc_info;
270 indio_dev->modes = INDIO_DIRECT_MODE;
271 indio_dev->channels = mt6577_auxadc_iio_channels;
272 indio_dev->num_channels = ARRAY_SIZE(mt6577_auxadc_iio_channels);
273
274 adc_dev->reg_base = devm_platform_ioremap_resource(pdev, 0);
275 if (IS_ERR(adc_dev->reg_base))
276 return dev_err_probe(&pdev->dev, PTR_ERR(adc_dev->reg_base),
277 "failed to get auxadc base address\n");
278
279 adc_dev->adc_clk = devm_clk_get_enabled(&pdev->dev, "main");
280 if (IS_ERR(adc_dev->adc_clk))
281 return dev_err_probe(&pdev->dev, PTR_ERR(adc_dev->adc_clk),
282 "failed to enable auxadc clock\n");
283
284 adc_clk_rate = clk_get_rate(adc_dev->adc_clk);
285 if (!adc_clk_rate)
286 return dev_err_probe(&pdev->dev, -EINVAL, "null clock rate\n");
287
288 adc_dev->dev_comp = device_get_match_data(&pdev->dev);
289
290 mutex_init(&adc_dev->lock);
291
292 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
293 MT6577_AUXADC_PDN_EN, 0);
294 mdelay(MT6577_AUXADC_POWER_READY_MS);
295 platform_set_drvdata(pdev, indio_dev);
296
297 ret = devm_add_action_or_reset(&pdev->dev, mt6577_power_off, adc_dev);
298 if (ret)
299 return ret;
300
301 ret = devm_iio_device_register(&pdev->dev, indio_dev);
302 if (ret < 0)
303 return dev_err_probe(&pdev->dev, ret, "failed to register iio device\n");
304
305 return 0;
306 }
307
308 static DEFINE_SIMPLE_DEV_PM_OPS(mt6577_auxadc_pm_ops,
309 mt6577_auxadc_suspend,
310 mt6577_auxadc_resume);
311
312 static const struct of_device_id mt6577_auxadc_of_match[] = {
313 { .compatible = "mediatek,mt2701-auxadc", .data = &mt8173_compat },
314 { .compatible = "mediatek,mt2712-auxadc", .data = &mt8173_compat },
315 { .compatible = "mediatek,mt7622-auxadc", .data = &mt8173_compat },
316 { .compatible = "mediatek,mt8173-auxadc", .data = &mt8173_compat },
317 { .compatible = "mediatek,mt8186-auxadc", .data = &mt8186_compat },
318 { .compatible = "mediatek,mt6765-auxadc", .data = &mt6765_compat },
319 { }
320 };
321 MODULE_DEVICE_TABLE(of, mt6577_auxadc_of_match);
322
323 static struct platform_driver mt6577_auxadc_driver = {
324 .driver = {
325 .name = "mt6577-auxadc",
326 .of_match_table = mt6577_auxadc_of_match,
327 .pm = pm_sleep_ptr(&mt6577_auxadc_pm_ops),
328 },
329 .probe = mt6577_auxadc_probe,
330 };
331 module_platform_driver(mt6577_auxadc_driver);
332
333 MODULE_AUTHOR("Zhiyong Tao <zhiyong.tao@mediatek.com>");
334 MODULE_DESCRIPTION("MTK AUXADC Device Driver");
335 MODULE_LICENSE("GPL v2");
336