1 /* 2 * Copyright 2015-2026 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "core_types.h" 28 #include "timing_generator.h" 29 #include "hw_sequencer.h" 30 #include "hw_sequencer_private.h" 31 #include "basics/dc_common.h" 32 #include "resource.h" 33 #include "dc_dmub_srv.h" 34 #include "dc_state_priv.h" 35 #include "opp.h" 36 #include "dsc.h" 37 #include "dchubbub.h" 38 #include "dccg.h" 39 #include "abm.h" 40 #include "dcn10/dcn10_hubbub.h" 41 #include "dce/dmub_hw_lock_mgr.h" 42 #include "link_service.h" 43 44 #define MAX_NUM_MCACHE 8 45 46 /* used as index in array of black_color_format */ 47 enum black_color_format { 48 BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0, 49 BLACK_COLOR_FORMAT_RGB_LIMITED, 50 BLACK_COLOR_FORMAT_YUV_TV, 51 BLACK_COLOR_FORMAT_YUV_CV, 52 BLACK_COLOR_FORMAT_YUV_SUPER_AA, 53 BLACK_COLOR_FORMAT_DEBUG, 54 }; 55 56 enum dc_color_space_type { 57 COLOR_SPACE_RGB_TYPE, 58 COLOR_SPACE_RGB_LIMITED_TYPE, 59 COLOR_SPACE_YCBCR601_TYPE, 60 COLOR_SPACE_YCBCR709_TYPE, 61 COLOR_SPACE_YCBCR2020_TYPE, 62 COLOR_SPACE_YCBCR601_LIMITED_TYPE, 63 COLOR_SPACE_YCBCR709_LIMITED_TYPE, 64 COLOR_SPACE_YCBCR709_BLACK_TYPE, 65 }; 66 67 static const struct tg_color black_color_format[] = { 68 /* BlackColorFormat_RGB_FullRange */ 69 {0, 0, 0}, 70 /* BlackColorFormat_RGB_Limited */ 71 {0x40, 0x40, 0x40}, 72 /* BlackColorFormat_YUV_TV */ 73 {0x200, 0x40, 0x200}, 74 /* BlackColorFormat_YUV_CV */ 75 {0x1f4, 0x40, 0x1f4}, 76 /* BlackColorFormat_YUV_SuperAA */ 77 {0x1a2, 0x20, 0x1a2}, 78 /* visual confirm debug */ 79 {0xff, 0xff, 0}, 80 }; 81 82 struct out_csc_color_matrix_type { 83 enum dc_color_space_type color_space_type; 84 uint16_t regval[12]; 85 }; 86 87 static const struct out_csc_color_matrix_type output_csc_matrix[] = { 88 { COLOR_SPACE_RGB_TYPE, 89 { 0x2000, 0, 0, 0, 90 0, 0x2000, 0, 0, 91 0, 0, 0x2000, 0} }, 92 { COLOR_SPACE_RGB_LIMITED_TYPE, 93 { 0x1B67, 0, 0, 0x201, 94 0, 0x1B67, 0, 0x201, 95 0, 0, 0x1B67, 0x201} }, 96 { COLOR_SPACE_YCBCR601_TYPE, 97 { 0xE04, 0xF444, 0xFDB9, 0x1004, 98 0x831, 0x1016, 0x320, 0x201, 99 0xFB45, 0xF6B7, 0xE04, 0x1004} }, 100 { COLOR_SPACE_YCBCR709_TYPE, 101 { 0xE04, 0xF345, 0xFEB7, 0x1004, 102 0x5D3, 0x1399, 0x1FA, 0x201, 103 0xFCCA, 0xF533, 0xE04, 0x1004} }, 104 /* TODO: correct values below */ 105 { COLOR_SPACE_YCBCR601_LIMITED_TYPE, 106 { 0xE00, 0xF447, 0xFDB9, 0x1000, 107 0x991, 0x12C9, 0x3A6, 0x200, 108 0xFB47, 0xF6B9, 0xE00, 0x1000} }, 109 { COLOR_SPACE_YCBCR709_LIMITED_TYPE, 110 { 0xE00, 0xF349, 0xFEB7, 0x1000, 111 0x6CE, 0x16E3, 0x24F, 0x200, 112 0xFCCB, 0xF535, 0xE00, 0x1000} }, 113 { COLOR_SPACE_YCBCR2020_TYPE, 114 { 0x1000, 0xF149, 0xFEB7, 0x1004, 115 0x0868, 0x15B2, 0x01E6, 0x201, 116 0xFB88, 0xF478, 0x1000, 0x1004} }, 117 { COLOR_SPACE_YCBCR709_BLACK_TYPE, 118 { 0x0000, 0x0000, 0x0000, 0x1000, 119 0x0000, 0x0000, 0x0000, 0x0200, 120 0x0000, 0x0000, 0x0000, 0x1000} }, 121 }; 122 123 static bool is_rgb_type( 124 enum dc_color_space color_space) 125 { 126 bool ret = false; 127 128 if (color_space == COLOR_SPACE_SRGB || 129 color_space == COLOR_SPACE_XR_RGB || 130 color_space == COLOR_SPACE_MSREF_SCRGB || 131 color_space == COLOR_SPACE_2020_RGB_FULLRANGE || 132 color_space == COLOR_SPACE_ADOBERGB || 133 color_space == COLOR_SPACE_DCIP3 || 134 color_space == COLOR_SPACE_DOLBYVISION) 135 ret = true; 136 return ret; 137 } 138 139 static bool is_rgb_limited_type( 140 enum dc_color_space color_space) 141 { 142 bool ret = false; 143 144 if (color_space == COLOR_SPACE_SRGB_LIMITED || 145 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) 146 ret = true; 147 return ret; 148 } 149 150 static bool is_ycbcr601_type( 151 enum dc_color_space color_space) 152 { 153 bool ret = false; 154 155 if (color_space == COLOR_SPACE_YCBCR601 || 156 color_space == COLOR_SPACE_XV_YCC_601) 157 ret = true; 158 return ret; 159 } 160 161 static bool is_ycbcr601_limited_type( 162 enum dc_color_space color_space) 163 { 164 bool ret = false; 165 166 if (color_space == COLOR_SPACE_YCBCR601_LIMITED) 167 ret = true; 168 return ret; 169 } 170 171 static bool is_ycbcr709_type( 172 enum dc_color_space color_space) 173 { 174 bool ret = false; 175 176 if (color_space == COLOR_SPACE_YCBCR709 || 177 color_space == COLOR_SPACE_XV_YCC_709) 178 ret = true; 179 return ret; 180 } 181 182 static bool is_ycbcr2020_type( 183 enum dc_color_space color_space) 184 { 185 bool ret = false; 186 187 if (color_space == COLOR_SPACE_2020_YCBCR_LIMITED || color_space == COLOR_SPACE_2020_YCBCR_FULL) 188 ret = true; 189 return ret; 190 } 191 192 static bool is_ycbcr709_limited_type( 193 enum dc_color_space color_space) 194 { 195 bool ret = false; 196 197 if (color_space == COLOR_SPACE_YCBCR709_LIMITED) 198 ret = true; 199 return ret; 200 } 201 202 static enum dc_color_space_type get_color_space_type(enum dc_color_space color_space) 203 { 204 enum dc_color_space_type type = COLOR_SPACE_RGB_TYPE; 205 206 if (is_rgb_type(color_space)) 207 type = COLOR_SPACE_RGB_TYPE; 208 else if (is_rgb_limited_type(color_space)) 209 type = COLOR_SPACE_RGB_LIMITED_TYPE; 210 else if (is_ycbcr601_type(color_space)) 211 type = COLOR_SPACE_YCBCR601_TYPE; 212 else if (is_ycbcr709_type(color_space)) 213 type = COLOR_SPACE_YCBCR709_TYPE; 214 else if (is_ycbcr601_limited_type(color_space)) 215 type = COLOR_SPACE_YCBCR601_LIMITED_TYPE; 216 else if (is_ycbcr709_limited_type(color_space)) 217 type = COLOR_SPACE_YCBCR709_LIMITED_TYPE; 218 else if (is_ycbcr2020_type(color_space)) 219 type = COLOR_SPACE_YCBCR2020_TYPE; 220 else if (color_space == COLOR_SPACE_YCBCR709) 221 type = COLOR_SPACE_YCBCR709_BLACK_TYPE; 222 else if (color_space == COLOR_SPACE_YCBCR709_BLACK) 223 type = COLOR_SPACE_YCBCR709_BLACK_TYPE; 224 return type; 225 } 226 227 const uint16_t *find_color_matrix(enum dc_color_space color_space, 228 uint32_t *array_size) 229 { 230 int i; 231 enum dc_color_space_type type; 232 const uint16_t *val = NULL; 233 int arr_size = ARRAY_SIZE(output_csc_matrix); 234 235 type = get_color_space_type(color_space); 236 for (i = 0; i < arr_size; i++) 237 if (output_csc_matrix[i].color_space_type == type) { 238 val = output_csc_matrix[i].regval; 239 *array_size = 12; 240 break; 241 } 242 243 return val; 244 } 245 246 247 void color_space_to_black_color( 248 const struct dc *dc, 249 enum dc_color_space colorspace, 250 struct tg_color *black_color) 251 { 252 (void)dc; 253 switch (colorspace) { 254 case COLOR_SPACE_YCBCR601: 255 case COLOR_SPACE_YCBCR709: 256 case COLOR_SPACE_YCBCR709_BLACK: 257 case COLOR_SPACE_YCBCR601_LIMITED: 258 case COLOR_SPACE_YCBCR709_LIMITED: 259 case COLOR_SPACE_2020_YCBCR_LIMITED: 260 case COLOR_SPACE_2020_YCBCR_FULL: 261 *black_color = black_color_format[BLACK_COLOR_FORMAT_YUV_CV]; 262 break; 263 264 case COLOR_SPACE_SRGB_LIMITED: 265 *black_color = 266 black_color_format[BLACK_COLOR_FORMAT_RGB_LIMITED]; 267 break; 268 269 /* 270 * Remove default and add case for all color space 271 * so when we forget to add new color space 272 * compiler will give a warning 273 */ 274 case COLOR_SPACE_UNKNOWN: 275 case COLOR_SPACE_SRGB: 276 case COLOR_SPACE_XR_RGB: 277 case COLOR_SPACE_MSREF_SCRGB: 278 case COLOR_SPACE_XV_YCC_709: 279 case COLOR_SPACE_XV_YCC_601: 280 case COLOR_SPACE_2020_RGB_FULLRANGE: 281 case COLOR_SPACE_2020_RGB_LIMITEDRANGE: 282 case COLOR_SPACE_ADOBERGB: 283 case COLOR_SPACE_DCIP3: 284 case COLOR_SPACE_DISPLAYNATIVE: 285 case COLOR_SPACE_DOLBYVISION: 286 case COLOR_SPACE_APPCTRL: 287 case COLOR_SPACE_CUSTOMPOINTS: 288 /* fefault is sRGB black (full range). */ 289 *black_color = 290 black_color_format[BLACK_COLOR_FORMAT_RGB_FULLRANGE]; 291 /* default is sRGB black 0. */ 292 break; 293 } 294 } 295 296 bool hwss_wait_for_blank_complete( 297 struct timing_generator *tg) 298 { 299 int counter; 300 301 /* Not applicable if the pipe is not primary, save 300ms of boot time */ 302 if (!tg->funcs->is_blanked) 303 return true; 304 for (counter = 0; counter < 100; counter++) { 305 if (tg->funcs->is_blanked(tg)) 306 break; 307 308 msleep(1); 309 } 310 311 if (counter == 100) { 312 dm_error("DC: failed to blank crtc!\n"); 313 return false; 314 } 315 316 return true; 317 } 318 319 void get_mpctree_visual_confirm_color( 320 struct pipe_ctx *pipe_ctx, 321 struct tg_color *color) 322 { 323 const struct tg_color pipe_colors[6] = { 324 {MAX_TG_COLOR_VALUE, 0, 0}, /* red */ 325 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, /* yellow */ 326 {0, MAX_TG_COLOR_VALUE, 0}, /* green */ 327 {0, MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE}, /* cyan */ 328 {0, 0, MAX_TG_COLOR_VALUE}, /* blue */ 329 {MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, /* magenta */ 330 }; 331 332 struct pipe_ctx *top_pipe = pipe_ctx; 333 334 while (top_pipe->top_pipe) 335 top_pipe = top_pipe->top_pipe; 336 337 *color = pipe_colors[top_pipe->pipe_idx]; 338 } 339 340 void get_surface_visual_confirm_color( 341 const struct pipe_ctx *pipe_ctx, 342 struct tg_color *color) 343 { 344 uint32_t color_value = MAX_TG_COLOR_VALUE; 345 346 switch (pipe_ctx->plane_res.scl_data.format) { 347 case PIXEL_FORMAT_ARGB8888: 348 /* set border color to red */ 349 color->color_r_cr = (uint16_t)color_value; 350 if (pipe_ctx->plane_state->layer_index > 0) { 351 /* set border color to pink */ 352 color->color_b_cb = (uint16_t)color_value; 353 color->color_g_y = (uint16_t)(color_value / 2); 354 } 355 break; 356 357 case PIXEL_FORMAT_ARGB2101010: 358 /* set border color to blue */ 359 color->color_b_cb = (uint16_t)color_value; 360 if (pipe_ctx->plane_state->layer_index > 0) { 361 /* set border color to cyan */ 362 color->color_g_y = (uint16_t)color_value; 363 } 364 break; 365 case PIXEL_FORMAT_420BPP8: 366 /* set border color to green */ 367 color->color_g_y = (uint16_t)color_value; 368 break; 369 case PIXEL_FORMAT_420BPP10: 370 /* set border color to yellow */ 371 color->color_g_y = (uint16_t)color_value; 372 color->color_r_cr = (uint16_t)color_value; 373 break; 374 case PIXEL_FORMAT_FP16: 375 /* set border color to white */ 376 color->color_r_cr = (uint16_t)color_value; 377 color->color_b_cb = (uint16_t)color_value; 378 color->color_g_y = (uint16_t)color_value; 379 if (pipe_ctx->plane_state->layer_index > 0) { 380 /* set border color to orange */ 381 color->color_g_y = (uint16_t)((color_value * 22) / 100); 382 color->color_b_cb = 0; 383 } 384 break; 385 default: 386 break; 387 } 388 } 389 390 void get_hdr_visual_confirm_color( 391 struct pipe_ctx *pipe_ctx, 392 struct tg_color *color) 393 { 394 uint32_t color_value = MAX_TG_COLOR_VALUE; 395 bool is_sdr = false; 396 397 /* Determine the overscan color based on the top-most (desktop) plane's context */ 398 struct pipe_ctx *top_pipe_ctx = pipe_ctx; 399 400 while (top_pipe_ctx->top_pipe != NULL) 401 top_pipe_ctx = top_pipe_ctx->top_pipe; 402 403 switch (top_pipe_ctx->plane_res.scl_data.format) { 404 case PIXEL_FORMAT_ARGB2101010: 405 if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_PQ) { 406 /* HDR10, ARGB2101010 - set border color to red */ 407 color->color_r_cr = (uint16_t)color_value; 408 } else if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) { 409 /* FreeSync 2 ARGB2101010 - set border color to pink */ 410 color->color_r_cr = (uint16_t)color_value; 411 color->color_b_cb = (uint16_t)color_value; 412 } else 413 is_sdr = true; 414 break; 415 case PIXEL_FORMAT_FP16: 416 if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_PQ) { 417 /* HDR10, FP16 - set border color to blue */ 418 color->color_b_cb = (uint16_t)color_value; 419 } else if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) { 420 /* FreeSync 2 HDR - set border color to green */ 421 color->color_g_y = (uint16_t)color_value; 422 } else 423 is_sdr = true; 424 break; 425 default: 426 is_sdr = true; 427 break; 428 } 429 430 if (is_sdr) { 431 /* SDR - set border color to Gray */ 432 color->color_r_cr = (uint16_t)(color_value / 2); 433 color->color_b_cb = (uint16_t)(color_value / 2); 434 color->color_g_y = (uint16_t)(color_value / 2); 435 } 436 } 437 438 /* Visual Confirm color definition for Smart Mux */ 439 void get_smartmux_visual_confirm_color( 440 struct dc *dc, 441 struct tg_color *color) 442 { 443 uint32_t color_value = MAX_TG_COLOR_VALUE; 444 445 const struct tg_color sm_ver_colors[5] = { 446 {0, 0, 0}, /* SMUX_MUXCONTROL_UNSUPPORTED - Black */ 447 {0, MAX_TG_COLOR_VALUE, 0}, /* SMUX_MUXCONTROL_v10 - Green */ 448 {0, MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE}, /* SMUX_MUXCONTROL_v15 - Cyan */ 449 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, /* SMUX_MUXCONTROL_MDM - Yellow */ 450 {MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, /* SMUX_MUXCONTROL_vUNKNOWN - Magenta*/ 451 }; 452 453 if (dc->caps.is_apu) { 454 /* APU driving the eDP */ 455 *color = sm_ver_colors[dc->config.smart_mux_version]; 456 } else { 457 /* dGPU driving the eDP - red */ 458 color->color_r_cr = (uint16_t)color_value; 459 color->color_g_y = 0; 460 color->color_b_cb = 0; 461 } 462 } 463 464 /* Visual Confirm color definition for VABC */ 465 void get_vabc_visual_confirm_color( 466 struct pipe_ctx *pipe_ctx, 467 struct tg_color *color) 468 { 469 uint32_t color_value = MAX_TG_COLOR_VALUE; 470 struct dc_link *edp_link = NULL; 471 472 if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link) { 473 if (pipe_ctx->stream->link->connector_signal == SIGNAL_TYPE_EDP) 474 edp_link = pipe_ctx->stream->link; 475 } 476 477 if (edp_link) { 478 switch (edp_link->backlight_control_type) { 479 case BACKLIGHT_CONTROL_PWM: 480 color->color_r_cr = (uint16_t)color_value; 481 color->color_g_y = 0; 482 color->color_b_cb = 0; 483 break; 484 case BACKLIGHT_CONTROL_AMD_AUX: 485 color->color_r_cr = 0; 486 color->color_g_y = (uint16_t)color_value; 487 color->color_b_cb = 0; 488 break; 489 case BACKLIGHT_CONTROL_VESA_AUX: 490 color->color_r_cr = 0; 491 color->color_g_y = 0; 492 color->color_b_cb = (uint16_t)color_value; 493 break; 494 } 495 } else { 496 color->color_r_cr = 0; 497 color->color_g_y = 0; 498 color->color_b_cb = 0; 499 } 500 } 501 502 void get_subvp_visual_confirm_color( 503 struct pipe_ctx *pipe_ctx, 504 struct tg_color *color) 505 { 506 uint32_t color_value = MAX_TG_COLOR_VALUE; 507 if (pipe_ctx) { 508 switch (pipe_ctx->p_state_type) { 509 case P_STATE_SUB_VP: 510 color->color_r_cr = (uint16_t)color_value; 511 color->color_g_y = 0; 512 color->color_b_cb = 0; 513 break; 514 case P_STATE_DRR_SUB_VP: 515 color->color_r_cr = 0; 516 color->color_g_y = (uint16_t)color_value; 517 color->color_b_cb = 0; 518 break; 519 case P_STATE_V_BLANK_SUB_VP: 520 color->color_r_cr = 0; 521 color->color_g_y = 0; 522 color->color_b_cb = (uint16_t)color_value; 523 break; 524 default: 525 break; 526 } 527 } 528 } 529 530 void get_mclk_switch_visual_confirm_color( 531 struct pipe_ctx *pipe_ctx, 532 struct tg_color *color) 533 { 534 uint32_t color_value = MAX_TG_COLOR_VALUE; 535 536 if (pipe_ctx) { 537 switch (pipe_ctx->p_state_type) { 538 case P_STATE_V_BLANK: 539 color->color_r_cr = (uint16_t)color_value; 540 color->color_g_y = (uint16_t)color_value; 541 color->color_b_cb = 0; 542 break; 543 case P_STATE_FPO: 544 color->color_r_cr = 0; 545 color->color_g_y = (uint16_t)color_value; 546 color->color_b_cb = (uint16_t)color_value; 547 break; 548 case P_STATE_V_ACTIVE: 549 color->color_r_cr = (uint16_t)color_value; 550 color->color_g_y = 0; 551 color->color_b_cb = (uint16_t)color_value; 552 break; 553 case P_STATE_SUB_VP: 554 color->color_r_cr = (uint16_t)color_value; 555 color->color_g_y = 0; 556 color->color_b_cb = 0; 557 break; 558 case P_STATE_DRR_SUB_VP: 559 color->color_r_cr = 0; 560 color->color_g_y = (uint16_t)color_value; 561 color->color_b_cb = 0; 562 break; 563 case P_STATE_V_BLANK_SUB_VP: 564 color->color_r_cr = 0; 565 color->color_g_y = 0; 566 color->color_b_cb = (uint16_t)color_value; 567 break; 568 default: 569 break; 570 } 571 } 572 } 573 574 void get_cursor_visual_confirm_color( 575 struct pipe_ctx *pipe_ctx, 576 struct tg_color *color) 577 { 578 uint32_t color_value = MAX_TG_COLOR_VALUE; 579 580 if (pipe_ctx->stream && pipe_ctx->stream->cursor_position.enable) { 581 color->color_r_cr = (uint16_t)color_value; 582 color->color_g_y = 0; 583 color->color_b_cb = 0; 584 } else { 585 color->color_r_cr = 0; 586 color->color_g_y = 0; 587 color->color_b_cb = (uint16_t)color_value; 588 } 589 } 590 591 void get_dcc_visual_confirm_color( 592 struct dc *dc, 593 struct pipe_ctx *pipe_ctx, 594 struct tg_color *color) 595 { 596 const uint32_t MCACHE_ID_UNASSIGNED = 0xF; 597 598 if (!pipe_ctx->plane_state->dcc.enable) { 599 color->color_r_cr = 0; /* black - DCC disabled */ 600 color->color_g_y = 0; 601 color->color_b_cb = 0; 602 return; 603 } 604 605 if (dc->ctx->dce_version < DCN_VERSION_4_01) { 606 color->color_r_cr = MAX_TG_COLOR_VALUE; /* red - DCC enabled */ 607 color->color_g_y = 0; 608 color->color_b_cb = 0; 609 return; 610 } 611 612 uint32_t first_id = pipe_ctx->mcache_regs.main.p0.mcache_id_first; 613 uint32_t second_id = pipe_ctx->mcache_regs.main.p0.mcache_id_second; 614 615 if (first_id != MCACHE_ID_UNASSIGNED && second_id != MCACHE_ID_UNASSIGNED && first_id != second_id) { 616 color->color_r_cr = MAX_TG_COLOR_VALUE/2; /* grey - 2 mcache */ 617 color->color_g_y = MAX_TG_COLOR_VALUE/2; 618 color->color_b_cb = MAX_TG_COLOR_VALUE/2; 619 } 620 621 else if (first_id != MCACHE_ID_UNASSIGNED || second_id != MCACHE_ID_UNASSIGNED) { 622 const struct tg_color id_colors[MAX_NUM_MCACHE] = { 623 {0, MAX_TG_COLOR_VALUE, 0}, /* green */ 624 {0, 0, MAX_TG_COLOR_VALUE}, /* blue */ 625 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, /* yellow */ 626 {MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, /* magenta */ 627 {0, MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE}, /* cyan */ 628 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE}, /* white */ 629 {MAX_TG_COLOR_VALUE/2, 0, 0}, /* dark red */ 630 {0, MAX_TG_COLOR_VALUE/2, 0}, /* dark green */ 631 }; 632 633 uint32_t assigned_id = (first_id != MCACHE_ID_UNASSIGNED) ? first_id : second_id; 634 *color = id_colors[assigned_id]; 635 } 636 } 637 638 void set_p_state_switch_method( 639 struct dc *dc, 640 struct dc_state *context, 641 struct pipe_ctx *pipe_ctx) 642 { 643 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 644 bool enable_subvp; 645 646 if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !vba) 647 return; 648 649 pipe_ctx->p_state_type = P_STATE_UNKNOWN; 650 if (vba->DRAMClockChangeSupport[vba->VoltageLevel][vba->maxMpcComb] != 651 dm_dram_clock_change_unsupported) { 652 /* MCLK switching is supported */ 653 if (!pipe_ctx->has_vactive_margin) { 654 /* In Vblank - yellow */ 655 pipe_ctx->p_state_type = P_STATE_V_BLANK; 656 657 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { 658 /* FPO + Vblank - cyan */ 659 pipe_ctx->p_state_type = P_STATE_FPO; 660 } 661 } else { 662 /* In Vactive - pink */ 663 pipe_ctx->p_state_type = P_STATE_V_ACTIVE; 664 } 665 666 /* SubVP */ 667 enable_subvp = false; 668 669 for (unsigned int i = 0; i < dc->res_pool->pipe_count; i++) { 670 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 671 672 if (pipe->stream && dc_state_get_paired_subvp_stream(context, pipe->stream) && 673 dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) { 674 /* SubVP enable - red */ 675 pipe_ctx->p_state_type = P_STATE_SUB_VP; 676 enable_subvp = true; 677 678 if (pipe_ctx->stream == pipe->stream) 679 return; 680 break; 681 } 682 } 683 684 if (enable_subvp && dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_NONE) { 685 if (pipe_ctx->stream->allow_freesync == 1) { 686 /* SubVP enable and DRR on - green */ 687 pipe_ctx->p_state_type = P_STATE_DRR_SUB_VP; 688 } else { 689 /* SubVP enable and No DRR - blue */ 690 pipe_ctx->p_state_type = P_STATE_V_BLANK_SUB_VP; 691 } 692 } 693 } 694 } 695 696 void set_drr_and_clear_adjust_pending( 697 struct pipe_ctx *pipe_ctx, 698 struct dc_stream_state *stream, 699 struct drr_params *params) 700 { 701 /* params can be null.*/ 702 if (pipe_ctx && pipe_ctx->stream_res.tg && 703 pipe_ctx->stream_res.tg->funcs->set_drr) 704 pipe_ctx->stream_res.tg->funcs->set_drr( 705 pipe_ctx->stream_res.tg, params); 706 707 if (stream) 708 stream->adjust.timing_adjust_pending = false; 709 } 710 711 void get_fams2_visual_confirm_color( 712 struct dc *dc, 713 struct dc_state *context, 714 struct pipe_ctx *pipe_ctx, 715 struct tg_color *color) 716 { 717 uint32_t color_value = MAX_TG_COLOR_VALUE; 718 719 if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !context || !dc->debug.fams2_config.bits.enable) 720 return; 721 722 /* driver only handles visual confirm when FAMS2 is disabled */ 723 if (!dc_state_is_fams2_in_use(dc, context)) { 724 /* when FAMS2 is disabled, all pipes are grey */ 725 color->color_g_y = (uint16_t)(color_value / 2); 726 color->color_b_cb = (uint16_t)(color_value / 2); 727 color->color_r_cr = (uint16_t)(color_value / 2); 728 } 729 } 730 731 void hwss_build_fast_sequence(struct dc *dc, 732 struct dc_dmub_cmd *dc_dmub_cmd, 733 unsigned int dmub_cmd_count, 734 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE], 735 unsigned int *num_steps, 736 struct pipe_ctx *pipe_ctx, 737 struct dc_stream_status *stream_status, 738 struct dc_state *context) 739 { 740 struct dc_plane_state *plane = pipe_ctx->plane_state; 741 struct dc_stream_state *stream = pipe_ctx->stream; 742 struct dce_hwseq *hws = dc->hwseq; 743 struct pipe_ctx *current_pipe = NULL; 744 struct pipe_ctx *current_mpc_pipe = NULL; 745 bool is_dmub_lock_required = false; 746 unsigned int i = 0; 747 748 *num_steps = 0; // Initialize to 0 749 750 if (!plane || !stream) 751 return; 752 753 if (dc->hwss.wait_for_dcc_meta_propagation) { 754 block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.dc = dc; 755 block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.top_pipe_to_program = pipe_ctx; 756 block_sequence[*num_steps].func = HUBP_WAIT_FOR_DCC_META_PROP; 757 (*num_steps)++; 758 } 759 if (dc->hwss.subvp_pipe_control_lock_fast) { 760 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc; 761 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = true; 762 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.subvp_immediate_flip = 763 plane->flip_immediate && stream_status->mall_stream_config.type == SUBVP_MAIN; 764 block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST; 765 (*num_steps)++; 766 } 767 if (dc->hwss.dmub_hw_control_lock_fast) { 768 is_dmub_lock_required = dc_state_is_fams2_in_use(dc, context) || 769 dmub_hw_lock_mgr_does_link_require_lock(dc, stream->link); 770 771 block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.dc = dc; 772 block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.lock = true; 773 block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.is_required = is_dmub_lock_required; 774 block_sequence[*num_steps].func = DMUB_HW_CONTROL_LOCK_FAST; 775 (*num_steps)++; 776 } 777 if (dc->hwss.pipe_control_lock) { 778 block_sequence[*num_steps].params.pipe_control_lock_params.dc = dc; 779 block_sequence[*num_steps].params.pipe_control_lock_params.lock = true; 780 block_sequence[*num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx; 781 block_sequence[*num_steps].func = OPTC_PIPE_CONTROL_LOCK; 782 (*num_steps)++; 783 } 784 785 for (i = 0; i < dmub_cmd_count; i++) { 786 block_sequence[*num_steps].params.send_dmcub_cmd_params.ctx = dc->ctx; 787 block_sequence[*num_steps].params.send_dmcub_cmd_params.cmd = &(dc_dmub_cmd[i].dmub_cmd); 788 block_sequence[*num_steps].params.send_dmcub_cmd_params.wait_type = dc_dmub_cmd[i].wait_type; 789 block_sequence[*num_steps].func = DMUB_SEND_DMCUB_CMD; 790 (*num_steps)++; 791 } 792 793 if (dc->hwss.setup_periodic_interrupt && stream->update_flags.bits.periodic_interrupt) { 794 block_sequence[*num_steps].params.setup_periodic_interrupt_params.dc = dc; 795 block_sequence[*num_steps].params.setup_periodic_interrupt_params.pipe_ctx = pipe_ctx; 796 block_sequence[*num_steps].func = HWSS_SETUP_PERIODIC_INTERRUPT; 797 (*num_steps)++; 798 } 799 800 if (stream->update_flags.bits.info_frame) { 801 resource_build_info_frame(pipe_ctx); 802 block_sequence[*num_steps].params.update_info_frame_params.dc = dc; 803 block_sequence[*num_steps].params.update_info_frame_params.pipe_ctx = pipe_ctx; 804 block_sequence[*num_steps].func = HWSS_UPDATE_INFO_FRAME; 805 (*num_steps)++; 806 807 if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 808 block_sequence[*num_steps].params.dp_trace_source_sequence_params.link = pipe_ctx->stream->link; 809 block_sequence[*num_steps].params.dp_trace_source_sequence_params.source = DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME; 810 block_sequence[*num_steps].func = DP_TRACE_SOURCE_SEQUENCE; 811 (*num_steps)++; 812 } 813 } 814 815 if (dc->hwss.set_dmdata_attributes && stream->update_flags.bits.dmdata && 816 stream->use_dynamic_meta && pipe_ctx->stream->dmdata_address.quad_part != 0) { 817 struct dc_dmdata_attributes attr = { 0 }; 818 819 attr.dmdata_mode = DMDATA_HW_MODE; 820 attr.dmdata_size = dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36; 821 attr.address.quad_part = pipe_ctx->stream->dmdata_address.quad_part; 822 attr.dmdata_dl_delta = 0; 823 attr.dmdata_qos_mode = 0; 824 attr.dmdata_qos_level = 0; 825 attr.dmdata_repeat = 1; /* always repeat */ 826 attr.dmdata_updated = 1; 827 attr.dmdata_sw_data = NULL; 828 829 block_sequence[*num_steps].params.set_dmdata_attributes_params.hubp = pipe_ctx->plane_res.hubp; 830 block_sequence[*num_steps].params.set_dmdata_attributes_params.attr = attr; 831 block_sequence[*num_steps].func = HUBP_SET_DMDATA_ATTRIBUTES; 832 (*num_steps)++; 833 } 834 835 /* Track cursor lock state - separate locks for attribute and position updates */ 836 bool enable_cursor_offload = false; 837 838 if ((dc->hwss.set_cursor_attribute && stream->update_flags.bits.cursor_attr) || 839 (dc->hwss.set_cursor_position && stream->update_flags.bits.cursor_pos)) 840 enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc); 841 842 /* Cursor attribute updates - separate lock/iterate/unlock */ 843 if (dc->hwss.set_cursor_attribute && stream->update_flags.bits.cursor_attr) { 844 struct pipe_ctx *cursor_pipe_to_program = NULL; 845 846 for (i = 0; i < MAX_PIPES; i++) { 847 current_pipe = &context->res_ctx.pipe_ctx[i]; 848 849 if (current_pipe->stream != stream) 850 continue; 851 852 if (!cursor_pipe_to_program) { 853 cursor_pipe_to_program = current_pipe; 854 855 if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update) { 856 block_sequence[*num_steps].params.begin_cursor_offload_update_params.dc = dc; 857 block_sequence[*num_steps].params.begin_cursor_offload_update_params.pipe_ctx = 858 current_pipe; 859 block_sequence[*num_steps].func = HWSS_BEGIN_CURSOR_OFFLOAD_UPDATE; 860 (*num_steps)++; 861 } else { 862 block_sequence[*num_steps].params.cursor_lock_params.dc = dc; 863 block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = current_pipe; 864 block_sequence[*num_steps].params.cursor_lock_params.lock = true; 865 block_sequence[*num_steps].func = HWSS_CURSOR_LOCK; 866 (*num_steps)++; 867 868 if (current_pipe->next_odm_pipe) { 869 block_sequence[*num_steps].params.cursor_lock_params.dc = dc; 870 block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = 871 current_pipe->next_odm_pipe; 872 block_sequence[*num_steps].params.cursor_lock_params.lock = true; 873 block_sequence[*num_steps].func = HWSS_CURSOR_LOCK; 874 (*num_steps)++; 875 } 876 } 877 } 878 879 block_sequence[*num_steps].params.hubp_set_cursor_attributes_params.hubp = 880 current_pipe->plane_res.hubp; 881 block_sequence[*num_steps].params.hubp_set_cursor_attributes_params.attributes = 882 ¤t_pipe->stream->cursor_attributes; 883 block_sequence[*num_steps].func = HUBP_SET_CURSOR_ATTRIBUTES; 884 (*num_steps)++; 885 886 block_sequence[*num_steps].params.dpp_set_cursor_attributes_params.dpp = 887 current_pipe->plane_res.dpp; 888 block_sequence[*num_steps].params.dpp_set_cursor_attributes_params.attributes = 889 ¤t_pipe->stream->cursor_attributes; 890 block_sequence[*num_steps].func = DPP_SET_CURSOR_ATTRIBUTES; 891 (*num_steps)++; 892 893 if (dc->ctx->dmub_srv) { 894 block_sequence[*num_steps].params.send_cursor_info_to_dmu_params.pipe_ctx = 895 current_pipe; 896 block_sequence[*num_steps].params.send_cursor_info_to_dmu_params.pipe_idx = 897 current_pipe->pipe_idx; 898 block_sequence[*num_steps].func = DC_SEND_CURSOR_INFO_TO_DMU; 899 (*num_steps)++; 900 } 901 902 block_sequence[*num_steps].params.set_cursor_sdr_white_level_params.dc = dc; 903 block_sequence[*num_steps].params.set_cursor_sdr_white_level_params.pipe_ctx = 904 current_pipe; 905 block_sequence[*num_steps].func = SET_CURSOR_SDR_WHITE_LEVEL; 906 (*num_steps)++; 907 908 if (enable_cursor_offload && dc->hwss.update_cursor_offload_pipe) { 909 block_sequence[*num_steps].params.update_cursor_offload_pipe_params.dc = dc; 910 block_sequence[*num_steps].params.update_cursor_offload_pipe_params.pipe_ctx = 911 current_pipe; 912 block_sequence[*num_steps].func = HWSS_UPDATE_CURSOR_OFFLOAD_PIPE; 913 (*num_steps)++; 914 } 915 } 916 917 /* Unlock cursor attributes after all pipes have been programmed */ 918 if (cursor_pipe_to_program) { 919 if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update) { 920 block_sequence[*num_steps].params.commit_cursor_offload_update_params.dc = dc; 921 block_sequence[*num_steps].params.commit_cursor_offload_update_params.pipe_ctx = 922 cursor_pipe_to_program; 923 block_sequence[*num_steps].func = HWSS_COMMIT_CURSOR_OFFLOAD_UPDATE; 924 (*num_steps)++; 925 } else { 926 block_sequence[*num_steps].params.cursor_lock_params.dc = dc; 927 block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = cursor_pipe_to_program; 928 block_sequence[*num_steps].params.cursor_lock_params.lock = false; 929 block_sequence[*num_steps].func = HWSS_CURSOR_LOCK; 930 (*num_steps)++; 931 932 if (cursor_pipe_to_program->next_odm_pipe) { 933 block_sequence[*num_steps].params.cursor_lock_params.dc = dc; 934 block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = 935 cursor_pipe_to_program->next_odm_pipe; 936 block_sequence[*num_steps].params.cursor_lock_params.lock = false; 937 block_sequence[*num_steps].func = HWSS_CURSOR_LOCK; 938 (*num_steps)++; 939 } 940 } 941 } 942 } 943 944 /* Cursor position updates */ 945 if (dc->hwss.set_cursor_position && stream->update_flags.bits.cursor_pos) { 946 struct pipe_ctx *cursor_pipe_to_program = NULL; 947 948 for (i = 0; i < MAX_PIPES; i++) { 949 current_pipe = &context->res_ctx.pipe_ctx[i]; 950 951 if (current_pipe->stream != stream || 952 (!current_pipe->plane_res.mi && !current_pipe->plane_res.hubp) || 953 !current_pipe->plane_state || 954 (!current_pipe->plane_res.xfm && !current_pipe->plane_res.dpp) || 955 (!current_pipe->plane_res.ipp && !current_pipe->plane_res.dpp)) 956 continue; 957 958 if (!cursor_pipe_to_program) { 959 cursor_pipe_to_program = current_pipe; 960 961 if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update) { 962 block_sequence[*num_steps].params.begin_cursor_offload_update_params.dc = dc; 963 block_sequence[*num_steps].params.begin_cursor_offload_update_params.pipe_ctx = 964 current_pipe; 965 block_sequence[*num_steps].func = HWSS_BEGIN_CURSOR_OFFLOAD_UPDATE; 966 (*num_steps)++; 967 } else { 968 block_sequence[*num_steps].params.cursor_lock_params.dc = dc; 969 block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = current_pipe; 970 block_sequence[*num_steps].params.cursor_lock_params.lock = true; 971 block_sequence[*num_steps].func = HWSS_CURSOR_LOCK; 972 (*num_steps)++; 973 } 974 } 975 976 block_sequence[*num_steps].params.set_cursor_position_params.dc = dc; 977 block_sequence[*num_steps].params.set_cursor_position_params.pipe_ctx = current_pipe; 978 block_sequence[*num_steps].func = SET_CURSOR_POSITION; 979 (*num_steps)++; 980 981 if (enable_cursor_offload && dc->hwss.update_cursor_offload_pipe) { 982 block_sequence[*num_steps].params.update_cursor_offload_pipe_params.dc = dc; 983 block_sequence[*num_steps].params.update_cursor_offload_pipe_params.pipe_ctx = 984 current_pipe; 985 block_sequence[*num_steps].func = HWSS_UPDATE_CURSOR_OFFLOAD_PIPE; 986 (*num_steps)++; 987 } 988 989 if (dc->ctx->dmub_srv) { 990 block_sequence[*num_steps].params.send_cursor_info_to_dmu_params.pipe_ctx = 991 current_pipe; 992 block_sequence[*num_steps].params.send_cursor_info_to_dmu_params.pipe_idx = 993 current_pipe->pipe_idx; 994 block_sequence[*num_steps].func = DC_SEND_CURSOR_INFO_TO_DMU; 995 (*num_steps)++; 996 } 997 } 998 999 /* Unlock cursor position after all pipes have been programmed */ 1000 if (cursor_pipe_to_program) { 1001 if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update) { 1002 block_sequence[*num_steps].params.commit_cursor_offload_update_params.dc = dc; 1003 block_sequence[*num_steps].params.commit_cursor_offload_update_params.pipe_ctx = 1004 cursor_pipe_to_program; 1005 block_sequence[*num_steps].func = HWSS_COMMIT_CURSOR_OFFLOAD_UPDATE; 1006 (*num_steps)++; 1007 } else { 1008 block_sequence[*num_steps].params.cursor_lock_params.dc = dc; 1009 block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = cursor_pipe_to_program; 1010 block_sequence[*num_steps].params.cursor_lock_params.lock = false; 1011 block_sequence[*num_steps].func = HWSS_CURSOR_LOCK; 1012 (*num_steps)++; 1013 } 1014 } 1015 } 1016 1017 current_pipe = pipe_ctx; 1018 while (current_pipe) { 1019 if (current_pipe->stream->update_flags.bits.dither) { 1020 resource_build_bit_depth_reduction_params(current_pipe->stream, ¤t_pipe->stream->bit_depth_params); 1021 block_sequence[*num_steps].params.opp_program_fmt_params.opp = current_pipe->stream_res.opp; 1022 block_sequence[*num_steps].params.opp_program_fmt_params.fmt_bit_depth = ¤t_pipe->stream->bit_depth_params; 1023 block_sequence[*num_steps].params.opp_program_fmt_params.clamping = ¤t_pipe->stream->clamping; 1024 block_sequence[*num_steps].func = OPP_PROGRAM_FMT; 1025 (*num_steps)++; 1026 } 1027 1028 current_mpc_pipe = current_pipe; 1029 while (current_mpc_pipe) { 1030 if (current_mpc_pipe->plane_state) { 1031 if (dc->hwss.set_flip_control_gsl && current_mpc_pipe->plane_state->update_flags.raw) { 1032 block_sequence[*num_steps].params.set_flip_control_gsl_params.hubp = current_mpc_pipe->plane_res.hubp; 1033 block_sequence[*num_steps].params.set_flip_control_gsl_params.flip_immediate = current_mpc_pipe->plane_state->flip_immediate; 1034 block_sequence[*num_steps].func = HUBP_SET_FLIP_CONTROL_GSL; 1035 (*num_steps)++; 1036 } 1037 if (dc->hwss.program_triplebuffer && dc->debug.enable_tri_buf && current_mpc_pipe->plane_state->update_flags.raw) { 1038 block_sequence[*num_steps].params.program_triplebuffer_params.dc = dc; 1039 block_sequence[*num_steps].params.program_triplebuffer_params.pipe_ctx = current_mpc_pipe; 1040 block_sequence[*num_steps].params.program_triplebuffer_params.enableTripleBuffer = current_mpc_pipe->plane_state->triplebuffer_flips; 1041 block_sequence[*num_steps].func = HUBP_PROGRAM_TRIPLEBUFFER; 1042 (*num_steps)++; 1043 } 1044 if (dc->hwss.update_plane_addr && current_mpc_pipe->plane_state->update_flags.bits.addr_update) { 1045 if (resource_is_pipe_type(current_mpc_pipe, OTG_MASTER) && 1046 stream_status->mall_stream_config.type == SUBVP_MAIN) { 1047 block_sequence[*num_steps].params.subvp_save_surf_addr.dc_dmub_srv = dc->ctx->dmub_srv; 1048 block_sequence[*num_steps].params.subvp_save_surf_addr.addr = ¤t_mpc_pipe->plane_state->address; 1049 block_sequence[*num_steps].params.subvp_save_surf_addr.subvp_index = current_mpc_pipe->subvp_index; 1050 block_sequence[*num_steps].func = DMUB_SUBVP_SAVE_SURF_ADDR; 1051 (*num_steps)++; 1052 } 1053 1054 block_sequence[*num_steps].params.update_plane_addr_params.dc = dc; 1055 block_sequence[*num_steps].params.update_plane_addr_params.pipe_ctx = current_mpc_pipe; 1056 block_sequence[*num_steps].func = HUBP_UPDATE_PLANE_ADDR; 1057 (*num_steps)++; 1058 } 1059 1060 if (hws->funcs.set_input_transfer_func && current_mpc_pipe->plane_state->update_flags.bits.gamma_change) { 1061 block_sequence[*num_steps].params.set_input_transfer_func_params.dc = dc; 1062 block_sequence[*num_steps].params.set_input_transfer_func_params.pipe_ctx = current_mpc_pipe; 1063 block_sequence[*num_steps].params.set_input_transfer_func_params.plane_state = current_mpc_pipe->plane_state; 1064 block_sequence[*num_steps].func = DPP_SET_INPUT_TRANSFER_FUNC; 1065 (*num_steps)++; 1066 } 1067 1068 if (dc->hwss.program_gamut_remap && 1069 (current_mpc_pipe->plane_state->update_flags.bits.gamut_remap_change || 1070 current_mpc_pipe->stream->update_flags.bits.gamut_remap)) { 1071 block_sequence[*num_steps].params.program_gamut_remap_params.pipe_ctx = current_mpc_pipe; 1072 block_sequence[*num_steps].func = DPP_PROGRAM_GAMUT_REMAP; 1073 (*num_steps)++; 1074 } 1075 if (current_mpc_pipe->plane_state->update_flags.bits.input_csc_change) { 1076 block_sequence[*num_steps].params.setup_dpp_params.pipe_ctx = current_mpc_pipe; 1077 block_sequence[*num_steps].func = DPP_SETUP_DPP; 1078 (*num_steps)++; 1079 } 1080 if (current_mpc_pipe->plane_state->update_flags.bits.coeff_reduction_change) { 1081 block_sequence[*num_steps].params.program_bias_and_scale_params.pipe_ctx = current_mpc_pipe; 1082 block_sequence[*num_steps].func = DPP_PROGRAM_BIAS_AND_SCALE; 1083 (*num_steps)++; 1084 } 1085 if (current_mpc_pipe->plane_state->update_flags.bits.cm_hist_change) { 1086 block_sequence[*num_steps].params.control_cm_hist_params.dpp 1087 = current_mpc_pipe->plane_res.dpp; 1088 block_sequence[*num_steps].params.control_cm_hist_params.cm_hist_control 1089 = current_mpc_pipe->plane_state->cm_hist_control; 1090 block_sequence[*num_steps].params.control_cm_hist_params.color_space 1091 = current_mpc_pipe->plane_state->color_space; 1092 block_sequence[*num_steps].func = DPP_PROGRAM_CM_HIST; 1093 (*num_steps)++; 1094 } 1095 1096 if (current_mpc_pipe->plane_res.dpp && 1097 current_mpc_pipe->plane_res.dpp->funcs->set_cursor_matrix && 1098 current_mpc_pipe->plane_state->update_flags.bits.cursor_csc_color_matrix_change) { 1099 block_sequence[*num_steps].params.dpp_set_cursor_matrix_params.dpp = current_mpc_pipe->plane_res.dpp; 1100 block_sequence[*num_steps].params.dpp_set_cursor_matrix_params.color_space = current_mpc_pipe->plane_state->color_space; 1101 block_sequence[*num_steps].params.dpp_set_cursor_matrix_params.cursor_csc_color_matrix = ¤t_mpc_pipe->plane_state->cursor_csc_color_matrix; 1102 block_sequence[*num_steps].func = DPP_SET_CURSOR_MATRIX; 1103 (*num_steps)++; 1104 } 1105 } 1106 if (hws->funcs.set_output_transfer_func && current_mpc_pipe->stream->update_flags.bits.out_tf) { 1107 block_sequence[*num_steps].params.set_output_transfer_func_params.dc = dc; 1108 block_sequence[*num_steps].params.set_output_transfer_func_params.pipe_ctx = current_mpc_pipe; 1109 block_sequence[*num_steps].params.set_output_transfer_func_params.stream = current_mpc_pipe->stream; 1110 block_sequence[*num_steps].func = DPP_SET_OUTPUT_TRANSFER_FUNC; 1111 (*num_steps)++; 1112 } 1113 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && 1114 dc->hwss.update_visual_confirm_color) { 1115 block_sequence[*num_steps].params.update_visual_confirm_params.dc = dc; 1116 block_sequence[*num_steps].params.update_visual_confirm_params.pipe_ctx = current_mpc_pipe; 1117 block_sequence[*num_steps].params.update_visual_confirm_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst; 1118 block_sequence[*num_steps].func = MPC_UPDATE_VISUAL_CONFIRM; 1119 (*num_steps)++; 1120 } 1121 if (current_mpc_pipe->stream->update_flags.bits.out_csc) { 1122 block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpc = dc->res_pool->mpc; 1123 block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst; 1124 block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.power_on = true; 1125 block_sequence[*num_steps].func = MPC_POWER_ON_MPC_MEM_PWR; 1126 (*num_steps)++; 1127 1128 if (current_mpc_pipe->stream->csc_color_matrix.enable_adjustment == true) { 1129 block_sequence[*num_steps].params.set_output_csc_params.mpc = dc->res_pool->mpc; 1130 block_sequence[*num_steps].params.set_output_csc_params.opp_id = current_mpc_pipe->stream_res.opp->inst; 1131 block_sequence[*num_steps].params.set_output_csc_params.regval = current_mpc_pipe->stream->csc_color_matrix.matrix; 1132 block_sequence[*num_steps].params.set_output_csc_params.ocsc_mode = MPC_OUTPUT_CSC_COEF_A; 1133 block_sequence[*num_steps].func = MPC_SET_OUTPUT_CSC; 1134 (*num_steps)++; 1135 } else { 1136 block_sequence[*num_steps].params.set_ocsc_default_params.mpc = dc->res_pool->mpc; 1137 block_sequence[*num_steps].params.set_ocsc_default_params.opp_id = current_mpc_pipe->stream_res.opp->inst; 1138 block_sequence[*num_steps].params.set_ocsc_default_params.color_space = current_mpc_pipe->stream->output_color_space; 1139 block_sequence[*num_steps].params.set_ocsc_default_params.ocsc_mode = MPC_OUTPUT_CSC_COEF_A; 1140 block_sequence[*num_steps].func = MPC_SET_OCSC_DEFAULT; 1141 (*num_steps)++; 1142 } 1143 } 1144 current_mpc_pipe = current_mpc_pipe->bottom_pipe; 1145 } 1146 current_pipe = current_pipe->next_odm_pipe; 1147 } 1148 1149 if (dc->hwss.pipe_control_lock) { 1150 block_sequence[*num_steps].params.pipe_control_lock_params.dc = dc; 1151 block_sequence[*num_steps].params.pipe_control_lock_params.lock = false; 1152 block_sequence[*num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx; 1153 block_sequence[*num_steps].func = OPTC_PIPE_CONTROL_LOCK; 1154 (*num_steps)++; 1155 } 1156 if (dc->hwss.subvp_pipe_control_lock_fast) { 1157 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc; 1158 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = false; 1159 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.subvp_immediate_flip = 1160 plane->flip_immediate && stream_status->mall_stream_config.type == SUBVP_MAIN; 1161 block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST; 1162 (*num_steps)++; 1163 } 1164 if (dc->hwss.dmub_hw_control_lock_fast) { 1165 block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.dc = dc; 1166 block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.lock = false; 1167 block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.is_required = is_dmub_lock_required; 1168 block_sequence[*num_steps].func = DMUB_HW_CONTROL_LOCK_FAST; 1169 (*num_steps)++; 1170 } 1171 1172 current_pipe = pipe_ctx; 1173 while (current_pipe) { 1174 current_mpc_pipe = current_pipe; 1175 1176 while (current_mpc_pipe) { 1177 if (!current_mpc_pipe->bottom_pipe && !current_mpc_pipe->next_odm_pipe && 1178 current_mpc_pipe->stream && current_mpc_pipe->plane_state && 1179 current_mpc_pipe->plane_state->update_flags.bits.addr_update && 1180 !current_mpc_pipe->plane_state->skip_manual_trigger) { 1181 if (dc->hwss.program_cursor_offload_now) { 1182 block_sequence[*num_steps].params.program_cursor_update_now_params.dc = dc; 1183 block_sequence[*num_steps].params.program_cursor_update_now_params.pipe_ctx = current_mpc_pipe; 1184 block_sequence[*num_steps].func = PROGRAM_CURSOR_UPDATE_NOW; 1185 (*num_steps)++; 1186 } 1187 1188 block_sequence[*num_steps].params.program_manual_trigger_params.pipe_ctx = current_mpc_pipe; 1189 block_sequence[*num_steps].func = OPTC_PROGRAM_MANUAL_TRIGGER; 1190 (*num_steps)++; 1191 } 1192 current_mpc_pipe = current_mpc_pipe->bottom_pipe; 1193 } 1194 current_pipe = current_pipe->next_odm_pipe; 1195 } 1196 } 1197 1198 void hwss_execute_sequence(struct dc *dc, 1199 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE], 1200 int num_steps) 1201 { 1202 int i; 1203 union block_sequence_params *params; 1204 struct dce_hwseq *hws = dc->hwseq; 1205 1206 for (i = 0; i < num_steps; i++) { 1207 params = &(block_sequence[i].params); 1208 switch (block_sequence[i].func) { 1209 1210 case DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST: 1211 dc->hwss.subvp_pipe_control_lock_fast(params); 1212 break; 1213 case OPTC_PIPE_CONTROL_LOCK: 1214 dc->hwss.pipe_control_lock(params->pipe_control_lock_params.dc, 1215 params->pipe_control_lock_params.pipe_ctx, 1216 params->pipe_control_lock_params.lock); 1217 break; 1218 case HUBP_SET_FLIP_CONTROL_GSL: 1219 params->set_flip_control_gsl_params.hubp->funcs->hubp_set_flip_control_surface_gsl( 1220 params->set_flip_control_gsl_params.hubp, 1221 params->set_flip_control_gsl_params.flip_immediate); 1222 break; 1223 case HUBP_PROGRAM_TRIPLEBUFFER: 1224 dc->hwss.program_triplebuffer(params->program_triplebuffer_params.dc, 1225 params->program_triplebuffer_params.pipe_ctx, 1226 params->program_triplebuffer_params.enableTripleBuffer); 1227 break; 1228 case HUBP_UPDATE_PLANE_ADDR: 1229 dc->hwss.update_plane_addr(params->update_plane_addr_params.dc, 1230 params->update_plane_addr_params.pipe_ctx); 1231 break; 1232 case DPP_SET_INPUT_TRANSFER_FUNC: 1233 hws->funcs.set_input_transfer_func(params->set_input_transfer_func_params.dc, 1234 params->set_input_transfer_func_params.pipe_ctx, 1235 params->set_input_transfer_func_params.plane_state); 1236 break; 1237 case DPP_PROGRAM_GAMUT_REMAP: 1238 hwss_program_gamut_remap(params); 1239 break; 1240 case HUBP_ENABLE_3DLUT_FL: 1241 hwss_hubp_enable_3dlut_fl(params); 1242 break; 1243 case OTG_SETUP_VERTICAL_INTERRUPT: 1244 hwss_tg_setup_vertical_interrupt0(params); 1245 break; 1246 case HWSS_SETUP_PERIODIC_INTERRUPT: 1247 hwss_setup_periodic_interrupt(dc, params); 1248 break; 1249 case HWSS_UPDATE_INFO_FRAME: 1250 hwss_update_info_frame(dc, params); 1251 break; 1252 case HUBP_SET_DMDATA_ATTRIBUTES: 1253 hwss_set_dmdata_attributes(params); 1254 break; 1255 case DPP_SETUP_DPP: 1256 hwss_setup_dpp(params); 1257 break; 1258 case DPP_PROGRAM_BIAS_AND_SCALE: 1259 hwss_program_bias_and_scale(params); 1260 break; 1261 case OPTC_PROGRAM_MANUAL_TRIGGER: 1262 hwss_program_manual_trigger(params); 1263 break; 1264 case DPP_SET_OUTPUT_TRANSFER_FUNC: 1265 hws->funcs.set_output_transfer_func(params->set_output_transfer_func_params.dc, 1266 params->set_output_transfer_func_params.pipe_ctx, 1267 params->set_output_transfer_func_params.stream); 1268 break; 1269 case MPC_UPDATE_VISUAL_CONFIRM: 1270 dc->hwss.update_visual_confirm_color(params->update_visual_confirm_params.dc, 1271 params->update_visual_confirm_params.pipe_ctx, 1272 params->update_visual_confirm_params.mpcc_id); 1273 break; 1274 case MPC_POWER_ON_MPC_MEM_PWR: 1275 hwss_power_on_mpc_mem_pwr(params); 1276 break; 1277 case MPC_SET_OUTPUT_CSC: 1278 hwss_set_output_csc(params); 1279 break; 1280 case MPC_SET_OCSC_DEFAULT: 1281 hwss_set_ocsc_default(params); 1282 break; 1283 case DMUB_SEND_DMCUB_CMD: 1284 hwss_send_dmcub_cmd(params); 1285 break; 1286 case DMUB_SUBVP_SAVE_SURF_ADDR: 1287 hwss_subvp_save_surf_addr(params); 1288 break; 1289 case HUBP_WAIT_FOR_DCC_META_PROP: 1290 dc->hwss.wait_for_dcc_meta_propagation( 1291 params->wait_for_dcc_meta_propagation_params.dc, 1292 params->wait_for_dcc_meta_propagation_params.top_pipe_to_program); 1293 break; 1294 case DMUB_HW_CONTROL_LOCK_FAST: 1295 dc->hwss.dmub_hw_control_lock_fast(params); 1296 break; 1297 case HUBP_PROGRAM_SURFACE_CONFIG: 1298 hwss_program_surface_config(params); 1299 break; 1300 case HUBP_PROGRAM_MCACHE_ID: 1301 hwss_program_mcache_id_and_split_coordinate(params); 1302 break; 1303 case DPP_PROGRAM_CM_HIST: 1304 hwss_program_cm_hist(params); 1305 break; 1306 case PROGRAM_CURSOR_UPDATE_NOW: 1307 dc->hwss.program_cursor_offload_now( 1308 params->program_cursor_update_now_params.dc, 1309 params->program_cursor_update_now_params.pipe_ctx); 1310 break; 1311 case HUBP_WAIT_PIPE_READ_START: 1312 params->hubp_wait_pipe_read_start_params.hubp->funcs->hubp_wait_pipe_read_start( 1313 params->hubp_wait_pipe_read_start_params.hubp); 1314 break; 1315 case HWS_APPLY_UPDATE_FLAGS_FOR_PHANTOM: 1316 dc->hwss.apply_update_flags_for_phantom(params->apply_update_flags_for_phantom_params.pipe_ctx); 1317 break; 1318 case HWS_UPDATE_PHANTOM_VP_POSITION: 1319 dc->hwss.update_phantom_vp_position(params->update_phantom_vp_position_params.dc, 1320 params->update_phantom_vp_position_params.context, 1321 params->update_phantom_vp_position_params.pipe_ctx); 1322 break; 1323 case OPTC_SET_ODM_COMBINE: 1324 hwss_set_odm_combine(params); 1325 break; 1326 case OPTC_SET_ODM_BYPASS: 1327 hwss_set_odm_bypass(params); 1328 break; 1329 case OPP_PIPE_CLOCK_CONTROL: 1330 hwss_opp_pipe_clock_control(params); 1331 break; 1332 case OPP_PROGRAM_LEFT_EDGE_EXTRA_PIXEL: 1333 hwss_opp_program_left_edge_extra_pixel(params); 1334 break; 1335 case DCCG_SET_DTO_DSCCLK: 1336 hwss_dccg_set_dto_dscclk(params); 1337 break; 1338 case DSC_SET_CONFIG: 1339 hwss_dsc_set_config(params); 1340 break; 1341 case DSC_ENABLE: 1342 hwss_dsc_enable(params); 1343 break; 1344 case TG_SET_DSC_CONFIG: 1345 hwss_tg_set_dsc_config(params); 1346 break; 1347 case DSC_DISCONNECT: 1348 hwss_dsc_disconnect(params); 1349 break; 1350 case DSC_READ_STATE: 1351 hwss_dsc_read_state(params); 1352 break; 1353 case DSC_CALCULATE_AND_SET_CONFIG: 1354 hwss_dsc_calculate_and_set_config(params); 1355 break; 1356 case DSC_ENABLE_WITH_OPP: 1357 hwss_dsc_enable_with_opp(params); 1358 break; 1359 case TG_PROGRAM_GLOBAL_SYNC: 1360 hwss_tg_program_global_sync(params); 1361 break; 1362 case TG_WAIT_FOR_STATE: 1363 hwss_tg_wait_for_state(params); 1364 break; 1365 case TG_SET_VTG_PARAMS: 1366 hwss_tg_set_vtg_params(params); 1367 break; 1368 case TG_SETUP_VERTICAL_INTERRUPT2: 1369 hwss_tg_setup_vertical_interrupt2(params); 1370 break; 1371 case DPP_SET_HDR_MULTIPLIER: 1372 hwss_dpp_set_hdr_multiplier(params); 1373 break; 1374 case HUBP_PROGRAM_DET_SIZE: 1375 hwss_program_det_size(params); 1376 break; 1377 case HUBP_PROGRAM_DET_SEGMENTS: 1378 hwss_program_det_segments(params); 1379 break; 1380 case OPP_SET_DYN_EXPANSION: 1381 hwss_opp_set_dyn_expansion(params); 1382 break; 1383 case OPP_PROGRAM_FMT: 1384 hwss_opp_program_fmt(params); 1385 break; 1386 case OPP_PROGRAM_BIT_DEPTH_REDUCTION: 1387 hwss_opp_program_bit_depth_reduction(params); 1388 break; 1389 case OPP_SET_DISP_PATTERN_GENERATOR: 1390 hwss_opp_set_disp_pattern_generator(params); 1391 break; 1392 case ABM_SET_PIPE: 1393 hwss_set_abm_pipe(params); 1394 break; 1395 case ABM_SET_LEVEL: 1396 hwss_set_abm_level(params); 1397 break; 1398 case ABM_SET_IMMEDIATE_DISABLE: 1399 hwss_set_abm_immediate_disable(params); 1400 break; 1401 case MPC_REMOVE_MPCC: 1402 hwss_mpc_remove_mpcc(params); 1403 break; 1404 case OPP_SET_MPCC_DISCONNECT_PENDING: 1405 hwss_opp_set_mpcc_disconnect_pending(params); 1406 break; 1407 case DC_SET_OPTIMIZED_REQUIRED: 1408 hwss_dc_set_optimized_required(params); 1409 break; 1410 case HUBP_DISCONNECT: 1411 hwss_hubp_disconnect(params); 1412 break; 1413 case HUBBUB_FORCE_PSTATE_CHANGE_CONTROL: 1414 hwss_hubbub_force_pstate_change_control(params); 1415 break; 1416 case TG_ENABLE_CRTC: 1417 hwss_tg_enable_crtc(params); 1418 break; 1419 case TG_SET_GSL: 1420 hwss_tg_set_gsl(params); 1421 break; 1422 case TG_SET_GSL_SOURCE_SELECT: 1423 hwss_tg_set_gsl_source_select(params); 1424 break; 1425 case HUBP_WAIT_FLIP_PENDING: 1426 hwss_hubp_wait_flip_pending(params); 1427 break; 1428 case TG_WAIT_DOUBLE_BUFFER_PENDING: 1429 hwss_tg_wait_double_buffer_pending(params); 1430 break; 1431 case UPDATE_FORCE_PSTATE: 1432 hwss_update_force_pstate(params); 1433 break; 1434 case HUBBUB_APPLY_DEDCN21_147_WA: 1435 hwss_hubbub_apply_dedcn21_147_wa(params); 1436 break; 1437 case HUBBUB_ALLOW_SELF_REFRESH_CONTROL: 1438 hwss_hubbub_allow_self_refresh_control(params); 1439 break; 1440 case TG_GET_FRAME_COUNT: 1441 hwss_tg_get_frame_count(params); 1442 break; 1443 case MPC_SET_DWB_MUX: 1444 hwss_mpc_set_dwb_mux(params); 1445 break; 1446 case MPC_DISABLE_DWB_MUX: 1447 hwss_mpc_disable_dwb_mux(params); 1448 break; 1449 case MCIF_WB_CONFIG_BUF: 1450 hwss_mcif_wb_config_buf(params); 1451 break; 1452 case MCIF_WB_CONFIG_ARB: 1453 hwss_mcif_wb_config_arb(params); 1454 break; 1455 case MCIF_WB_ENABLE: 1456 hwss_mcif_wb_enable(params); 1457 break; 1458 case MCIF_WB_DISABLE: 1459 hwss_mcif_wb_disable(params); 1460 break; 1461 case DWBC_ENABLE: 1462 hwss_dwbc_enable(params); 1463 break; 1464 case DWBC_DISABLE: 1465 hwss_dwbc_disable(params); 1466 break; 1467 case DWBC_UPDATE: 1468 hwss_dwbc_update(params); 1469 break; 1470 case HUBP_UPDATE_MALL_SEL: 1471 hwss_hubp_update_mall_sel(params); 1472 break; 1473 case HUBP_PREPARE_SUBVP_BUFFERING: 1474 hwss_hubp_prepare_subvp_buffering(params); 1475 break; 1476 case HUBP_SET_BLANK_EN: 1477 hwss_hubp_set_blank_en(params); 1478 break; 1479 case HUBP_DISABLE_CONTROL: 1480 hwss_hubp_disable_control(params); 1481 break; 1482 case HUBBUB_SOFT_RESET: 1483 hwss_hubbub_soft_reset(params); 1484 break; 1485 case HUBP_CLK_CNTL: 1486 hwss_hubp_clk_cntl(params); 1487 break; 1488 case HUBP_INIT: 1489 hwss_hubp_init(params); 1490 break; 1491 case HUBP_SET_VM_SYSTEM_APERTURE_SETTINGS: 1492 hwss_hubp_set_vm_system_aperture_settings(params); 1493 break; 1494 case HUBP_SET_FLIP_INT: 1495 hwss_hubp_set_flip_int(params); 1496 break; 1497 case DPP_DPPCLK_CONTROL: 1498 hwss_dpp_dppclk_control(params); 1499 break; 1500 case DISABLE_PHANTOM_CRTC: 1501 hwss_disable_phantom_crtc(params); 1502 break; 1503 case DSC_PG_STATUS: 1504 hwss_dsc_pg_status(params); 1505 break; 1506 case DSC_WAIT_DISCONNECT_PENDING_CLEAR: 1507 hwss_dsc_wait_disconnect_pending_clear(params); 1508 break; 1509 case DSC_DISABLE: 1510 hwss_dsc_disable(params); 1511 break; 1512 case DCCG_SET_REF_DSCCLK: 1513 hwss_dccg_set_ref_dscclk(params); 1514 break; 1515 case DPP_PG_CONTROL: 1516 hwss_dpp_pg_control(params); 1517 break; 1518 case HUBP_PG_CONTROL: 1519 hwss_hubp_pg_control(params); 1520 break; 1521 case HUBP_RESET: 1522 hwss_hubp_reset(params); 1523 break; 1524 case DPP_RESET: 1525 hwss_dpp_reset(params); 1526 break; 1527 case DPP_ROOT_CLOCK_CONTROL: 1528 hwss_dpp_root_clock_control(params); 1529 break; 1530 case DC_IP_REQUEST_CNTL: 1531 hwss_dc_ip_request_cntl(params); 1532 break; 1533 case DCCG_UPDATE_DPP_DTO: 1534 hwss_dccg_update_dpp_dto(params); 1535 break; 1536 case HUBP_VTG_SEL: 1537 hwss_hubp_vtg_sel(params); 1538 break; 1539 case HUBP_SETUP2: 1540 hwss_hubp_setup2(params); 1541 break; 1542 case HUBP_SETUP: 1543 hwss_hubp_setup(params); 1544 break; 1545 case HUBP_SET_UNBOUNDED_REQUESTING: 1546 hwss_hubp_set_unbounded_requesting(params); 1547 break; 1548 case HUBP_SETUP_INTERDEPENDENT2: 1549 hwss_hubp_setup_interdependent2(params); 1550 break; 1551 case HUBP_SETUP_INTERDEPENDENT: 1552 hwss_hubp_setup_interdependent(params); 1553 break; 1554 case DPP_SET_CURSOR_MATRIX: 1555 hwss_dpp_set_cursor_matrix(params); 1556 break; 1557 case MPC_UPDATE_BLENDING: 1558 hwss_mpc_update_blending(params); 1559 break; 1560 case MPC_ASSERT_IDLE_MPCC: 1561 hwss_mpc_assert_idle_mpcc(params); 1562 break; 1563 case MPC_INSERT_PLANE: 1564 hwss_mpc_insert_plane(params); 1565 break; 1566 case DPP_SET_SCALER: 1567 hwss_dpp_set_scaler(params); 1568 break; 1569 case HUBP_MEM_PROGRAM_VIEWPORT: 1570 hwss_hubp_mem_program_viewport(params); 1571 break; 1572 case ABORT_CURSOR_OFFLOAD_UPDATE: 1573 hwss_abort_cursor_offload_update(params); 1574 break; 1575 case HWSS_CURSOR_LOCK: 1576 hwss_cursor_lock(params); 1577 break; 1578 case HWSS_BEGIN_CURSOR_OFFLOAD_UPDATE: 1579 hwss_begin_cursor_offload_update(params); 1580 break; 1581 case HWSS_COMMIT_CURSOR_OFFLOAD_UPDATE: 1582 hwss_commit_cursor_offload_update(params); 1583 break; 1584 case HWSS_UPDATE_CURSOR_OFFLOAD_PIPE: 1585 hwss_update_cursor_offload_pipe(params); 1586 break; 1587 case DC_SEND_CURSOR_INFO_TO_DMU: 1588 hwss_send_cursor_info_to_dmu(params); 1589 break; 1590 case SET_CURSOR_ATTRIBUTE: 1591 hwss_set_cursor_attribute(params); 1592 break; 1593 case HUBP_SET_CURSOR_ATTRIBUTES: 1594 hwss_hubp_set_cursor_attributes(params); 1595 break; 1596 case DPP_SET_CURSOR_ATTRIBUTES: 1597 hwss_dpp_set_cursor_attributes(params); 1598 break; 1599 case SET_CURSOR_POSITION: 1600 hwss_set_cursor_position(params); 1601 break; 1602 case SET_CURSOR_SDR_WHITE_LEVEL: 1603 hwss_set_cursor_sdr_white_level(params); 1604 break; 1605 case PROGRAM_OUTPUT_CSC: 1606 hwss_program_output_csc(params); 1607 break; 1608 case HUBP_SET_BLANK: 1609 hwss_hubp_set_blank(params); 1610 break; 1611 case PHANTOM_HUBP_POST_ENABLE: 1612 hwss_phantom_hubp_post_enable(params); 1613 break; 1614 case STREAM_ENC_UPDATE_HDMI_INFO_PACKETS: 1615 hwss_stream_enc_update_hdmi_info_packets(params); 1616 break; 1617 case HPO_FRL_STREAM_ENC_UPDATE_HDMI_INFO_PACKETS: 1618 hwss_hpo_frl_stream_enc_update_hdmi_info_packets(params); 1619 break; 1620 case HPO_DP_STREAM_ENC_UPDATE_DP_INFO_PACKETS_SDP_LINE_NUM: 1621 hwss_hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num(params); 1622 break; 1623 case HPO_DP_STREAM_ENC_UPDATE_DP_INFO_PACKETS: 1624 hwss_hpo_dp_stream_enc_update_dp_info_packets(params); 1625 break; 1626 case STREAM_ENC_UPDATE_DP_INFO_PACKETS_SDP_LINE_NUM: 1627 hwss_stream_enc_update_dp_info_packets_sdp_line_num(params); 1628 break; 1629 case STREAM_ENC_UPDATE_DP_INFO_PACKETS: 1630 hwss_stream_enc_update_dp_info_packets(params); 1631 break; 1632 case DSC_SET_CONFIG_SIMPLE: 1633 hwss_dsc_set_config_simple(params); 1634 break; 1635 case STREAM_ENC_DP_SET_DSC_CONFIG: 1636 hwss_stream_enc_dp_set_dsc_config(params); 1637 break; 1638 case HPO_DP_STREAM_ENC_DP_SET_DSC_PPS_INFO_PACKET: 1639 hwss_hpo_dp_stream_enc_dp_set_dsc_pps_info_packet(params); 1640 break; 1641 case STREAM_ENC_DP_SET_DSC_PPS_INFO_PACKET: 1642 hwss_stream_enc_dp_set_dsc_pps_info_packet(params); 1643 break; 1644 case HPO_FRL_STREAM_ENC_SET_DSC_CONFIG: 1645 hwss_hpo_frl_stream_enc_set_dsc_config(params); 1646 break; 1647 case DP_TRACE_SOURCE_SEQUENCE: 1648 hwss_dp_trace_source_sequence(params); 1649 break; 1650 case LINK_INCREASE_MST_PAYLOAD: 1651 hwss_link_increase_mst_payload(params); 1652 break; 1653 case LINK_REDUCE_MST_PAYLOAD: 1654 hwss_link_reduce_mst_payload(params); 1655 break; 1656 case DP_SET_TEST_PATTERN: 1657 hwss_dp_set_test_pattern(params); 1658 break; 1659 case LINK_SET_DPMS_OFF: 1660 hwss_link_set_dpms_off(params); 1661 break; 1662 case DISABLE_AUDIO_STREAM: 1663 hwss_disable_audio_stream(dc, params); 1664 break; 1665 case PREPARE_BANDWIDTH: 1666 hwss_prepare_bandwidth(dc, params); 1667 break; 1668 case LINK_SET_DPMS_ON: 1669 hwss_link_set_dpms_on(params); 1670 break; 1671 default: 1672 ASSERT(false); 1673 break; 1674 } 1675 } 1676 } 1677 1678 /* 1679 * Helper function to add OPTC pipe control lock to block sequence 1680 */ 1681 void hwss_add_optc_pipe_control_lock(struct block_sequence_state *seq_state, 1682 struct dc *dc, 1683 struct pipe_ctx *pipe_ctx, 1684 bool lock) 1685 { 1686 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1687 seq_state->steps[*seq_state->num_steps].params.pipe_control_lock_params.dc = dc; 1688 seq_state->steps[*seq_state->num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx; 1689 seq_state->steps[*seq_state->num_steps].params.pipe_control_lock_params.lock = lock; 1690 seq_state->steps[*seq_state->num_steps].func = OPTC_PIPE_CONTROL_LOCK; 1691 (*seq_state->num_steps)++; 1692 } 1693 } 1694 1695 /* 1696 * Helper function to add HUBP set flip control GSL to block sequence 1697 */ 1698 void hwss_add_hubp_set_flip_control_gsl(struct block_sequence_state *seq_state, 1699 struct hubp *hubp, 1700 bool flip_immediate) 1701 { 1702 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1703 seq_state->steps[*seq_state->num_steps].params.set_flip_control_gsl_params.hubp = hubp; 1704 seq_state->steps[*seq_state->num_steps].params.set_flip_control_gsl_params.flip_immediate = flip_immediate; 1705 seq_state->steps[*seq_state->num_steps].func = HUBP_SET_FLIP_CONTROL_GSL; 1706 (*seq_state->num_steps)++; 1707 } 1708 } 1709 1710 /* 1711 * Helper function to add HUBP program triplebuffer to block sequence 1712 */ 1713 void hwss_add_hubp_program_triplebuffer(struct block_sequence_state *seq_state, 1714 struct dc *dc, 1715 struct pipe_ctx *pipe_ctx, 1716 bool enableTripleBuffer) 1717 { 1718 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1719 seq_state->steps[*seq_state->num_steps].params.program_triplebuffer_params.dc = dc; 1720 seq_state->steps[*seq_state->num_steps].params.program_triplebuffer_params.pipe_ctx = pipe_ctx; 1721 seq_state->steps[*seq_state->num_steps].params.program_triplebuffer_params.enableTripleBuffer = enableTripleBuffer; 1722 seq_state->steps[*seq_state->num_steps].func = HUBP_PROGRAM_TRIPLEBUFFER; 1723 (*seq_state->num_steps)++; 1724 } 1725 } 1726 1727 /* 1728 * Helper function to add HUBP update plane address to block sequence 1729 */ 1730 void hwss_add_hubp_update_plane_addr(struct block_sequence_state *seq_state, 1731 struct dc *dc, 1732 struct pipe_ctx *pipe_ctx) 1733 { 1734 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1735 seq_state->steps[*seq_state->num_steps].params.update_plane_addr_params.dc = dc; 1736 seq_state->steps[*seq_state->num_steps].params.update_plane_addr_params.pipe_ctx = pipe_ctx; 1737 seq_state->steps[*seq_state->num_steps].func = HUBP_UPDATE_PLANE_ADDR; 1738 (*seq_state->num_steps)++; 1739 } 1740 } 1741 1742 /* 1743 * Helper function to add DPP set input transfer function to block sequence 1744 */ 1745 void hwss_add_dpp_set_input_transfer_func(struct block_sequence_state *seq_state, 1746 struct dc *dc, 1747 struct pipe_ctx *pipe_ctx, 1748 struct dc_plane_state *plane_state) 1749 { 1750 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1751 seq_state->steps[*seq_state->num_steps].params.set_input_transfer_func_params.dc = dc; 1752 seq_state->steps[*seq_state->num_steps].params.set_input_transfer_func_params.pipe_ctx = pipe_ctx; 1753 seq_state->steps[*seq_state->num_steps].params.set_input_transfer_func_params.plane_state = plane_state; 1754 seq_state->steps[*seq_state->num_steps].func = DPP_SET_INPUT_TRANSFER_FUNC; 1755 (*seq_state->num_steps)++; 1756 } 1757 } 1758 1759 /* 1760 * Helper function to add DPP program gamut remap to block sequence 1761 */ 1762 void hwss_add_dpp_program_gamut_remap(struct block_sequence_state *seq_state, 1763 struct pipe_ctx *pipe_ctx) 1764 { 1765 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1766 seq_state->steps[*seq_state->num_steps].params.program_gamut_remap_params.pipe_ctx = pipe_ctx; 1767 seq_state->steps[*seq_state->num_steps].func = DPP_PROGRAM_GAMUT_REMAP; 1768 (*seq_state->num_steps)++; 1769 } 1770 } 1771 1772 /* 1773 * Helper function to add DPP program bias and scale to block sequence 1774 */ 1775 void hwss_add_dpp_program_bias_and_scale(struct block_sequence_state *seq_state, struct pipe_ctx *pipe_ctx) 1776 { 1777 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1778 seq_state->steps[*seq_state->num_steps].params.program_bias_and_scale_params.pipe_ctx = pipe_ctx; 1779 seq_state->steps[*seq_state->num_steps].func = DPP_PROGRAM_BIAS_AND_SCALE; 1780 (*seq_state->num_steps)++; 1781 } 1782 } 1783 1784 /* 1785 * Helper function to add OPTC program manual trigger to block sequence 1786 */ 1787 void hwss_add_optc_program_manual_trigger(struct block_sequence_state *seq_state, 1788 struct pipe_ctx *pipe_ctx) 1789 { 1790 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1791 seq_state->steps[*seq_state->num_steps].params.program_manual_trigger_params.pipe_ctx = pipe_ctx; 1792 seq_state->steps[*seq_state->num_steps].func = OPTC_PROGRAM_MANUAL_TRIGGER; 1793 (*seq_state->num_steps)++; 1794 } 1795 } 1796 1797 /* 1798 * Helper function to add DPP set output transfer function to block sequence 1799 */ 1800 void hwss_add_dpp_set_output_transfer_func(struct block_sequence_state *seq_state, 1801 struct dc *dc, 1802 struct pipe_ctx *pipe_ctx, 1803 struct dc_stream_state *stream) 1804 { 1805 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1806 seq_state->steps[*seq_state->num_steps].params.set_output_transfer_func_params.dc = dc; 1807 seq_state->steps[*seq_state->num_steps].params.set_output_transfer_func_params.pipe_ctx = pipe_ctx; 1808 seq_state->steps[*seq_state->num_steps].params.set_output_transfer_func_params.stream = stream; 1809 seq_state->steps[*seq_state->num_steps].func = DPP_SET_OUTPUT_TRANSFER_FUNC; 1810 (*seq_state->num_steps)++; 1811 } 1812 } 1813 1814 /* 1815 * Helper function to add MPC update visual confirm to block sequence 1816 */ 1817 void hwss_add_mpc_update_visual_confirm(struct block_sequence_state *seq_state, 1818 struct dc *dc, 1819 struct pipe_ctx *pipe_ctx, 1820 int mpcc_id) 1821 { 1822 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1823 seq_state->steps[*seq_state->num_steps].params.update_visual_confirm_params.dc = dc; 1824 seq_state->steps[*seq_state->num_steps].params.update_visual_confirm_params.pipe_ctx = pipe_ctx; 1825 seq_state->steps[*seq_state->num_steps].params.update_visual_confirm_params.mpcc_id = mpcc_id; 1826 seq_state->steps[*seq_state->num_steps].func = MPC_UPDATE_VISUAL_CONFIRM; 1827 (*seq_state->num_steps)++; 1828 } 1829 } 1830 1831 /* 1832 * Helper function to add MPC power on MPC mem PWR to block sequence 1833 */ 1834 void hwss_add_mpc_power_on_mpc_mem_pwr(struct block_sequence_state *seq_state, 1835 struct mpc *mpc, 1836 int mpcc_id, 1837 bool power_on) 1838 { 1839 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1840 seq_state->steps[*seq_state->num_steps].params.power_on_mpc_mem_pwr_params.mpc = mpc; 1841 seq_state->steps[*seq_state->num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = mpcc_id; 1842 seq_state->steps[*seq_state->num_steps].params.power_on_mpc_mem_pwr_params.power_on = power_on; 1843 seq_state->steps[*seq_state->num_steps].func = MPC_POWER_ON_MPC_MEM_PWR; 1844 (*seq_state->num_steps)++; 1845 } 1846 } 1847 1848 /* 1849 * Helper function to add MPC set output CSC to block sequence 1850 */ 1851 void hwss_add_mpc_set_output_csc(struct block_sequence_state *seq_state, 1852 struct mpc *mpc, 1853 int opp_id, 1854 const uint16_t *regval, 1855 enum mpc_output_csc_mode ocsc_mode) 1856 { 1857 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1858 seq_state->steps[*seq_state->num_steps].params.set_output_csc_params.mpc = mpc; 1859 seq_state->steps[*seq_state->num_steps].params.set_output_csc_params.opp_id = opp_id; 1860 seq_state->steps[*seq_state->num_steps].params.set_output_csc_params.regval = regval; 1861 seq_state->steps[*seq_state->num_steps].params.set_output_csc_params.ocsc_mode = ocsc_mode; 1862 seq_state->steps[*seq_state->num_steps].func = MPC_SET_OUTPUT_CSC; 1863 (*seq_state->num_steps)++; 1864 } 1865 } 1866 1867 /* 1868 * Helper function to add MPC set OCSC default to block sequence 1869 */ 1870 void hwss_add_mpc_set_ocsc_default(struct block_sequence_state *seq_state, 1871 struct mpc *mpc, 1872 int opp_id, 1873 enum dc_color_space colorspace, 1874 enum mpc_output_csc_mode ocsc_mode) 1875 { 1876 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1877 seq_state->steps[*seq_state->num_steps].params.set_ocsc_default_params.mpc = mpc; 1878 seq_state->steps[*seq_state->num_steps].params.set_ocsc_default_params.opp_id = opp_id; 1879 seq_state->steps[*seq_state->num_steps].params.set_ocsc_default_params.color_space = colorspace; 1880 seq_state->steps[*seq_state->num_steps].params.set_ocsc_default_params.ocsc_mode = ocsc_mode; 1881 seq_state->steps[*seq_state->num_steps].func = MPC_SET_OCSC_DEFAULT; 1882 (*seq_state->num_steps)++; 1883 } 1884 } 1885 1886 /* 1887 * Helper function to add DMUB send DMCUB command to block sequence 1888 */ 1889 void hwss_add_dmub_send_dmcub_cmd(struct block_sequence_state *seq_state, 1890 struct dc_context *ctx, 1891 union dmub_rb_cmd *cmd, 1892 enum dm_dmub_wait_type wait_type) 1893 { 1894 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1895 seq_state->steps[*seq_state->num_steps].params.send_dmcub_cmd_params.ctx = ctx; 1896 seq_state->steps[*seq_state->num_steps].params.send_dmcub_cmd_params.cmd = cmd; 1897 seq_state->steps[*seq_state->num_steps].params.send_dmcub_cmd_params.wait_type = wait_type; 1898 seq_state->steps[*seq_state->num_steps].func = DMUB_SEND_DMCUB_CMD; 1899 (*seq_state->num_steps)++; 1900 } 1901 } 1902 1903 /* 1904 * Helper function to add DMUB SubVP save surface address to block sequence 1905 */ 1906 void hwss_add_dmub_subvp_save_surf_addr(struct block_sequence_state *seq_state, 1907 struct dc_dmub_srv *dc_dmub_srv, 1908 struct dc_plane_address *addr, 1909 uint8_t subvp_index) 1910 { 1911 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1912 seq_state->steps[*seq_state->num_steps].params.subvp_save_surf_addr.dc_dmub_srv = dc_dmub_srv; 1913 seq_state->steps[*seq_state->num_steps].params.subvp_save_surf_addr.addr = addr; 1914 seq_state->steps[*seq_state->num_steps].params.subvp_save_surf_addr.subvp_index = subvp_index; 1915 seq_state->steps[*seq_state->num_steps].func = DMUB_SUBVP_SAVE_SURF_ADDR; 1916 (*seq_state->num_steps)++; 1917 } 1918 } 1919 1920 /* 1921 * Helper function to add HUBP wait for DCC meta propagation to block sequence 1922 */ 1923 void hwss_add_hubp_wait_for_dcc_meta_prop(struct block_sequence_state *seq_state, 1924 struct dc *dc, 1925 struct pipe_ctx *top_pipe_to_program) 1926 { 1927 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1928 seq_state->steps[*seq_state->num_steps].params.wait_for_dcc_meta_propagation_params.dc = dc; 1929 seq_state->steps[*seq_state->num_steps].params.wait_for_dcc_meta_propagation_params.top_pipe_to_program = top_pipe_to_program; 1930 seq_state->steps[*seq_state->num_steps].func = HUBP_WAIT_FOR_DCC_META_PROP; 1931 (*seq_state->num_steps)++; 1932 } 1933 } 1934 1935 /* 1936 * Helper function to add HUBP wait pipe read start to block sequence 1937 */ 1938 void hwss_add_hubp_wait_pipe_read_start(struct block_sequence_state *seq_state, 1939 struct hubp *hubp) 1940 { 1941 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1942 seq_state->steps[*seq_state->num_steps].params.hubp_wait_pipe_read_start_params.hubp = hubp; 1943 seq_state->steps[*seq_state->num_steps].func = HUBP_WAIT_PIPE_READ_START; 1944 (*seq_state->num_steps)++; 1945 } 1946 } 1947 1948 /* 1949 * Helper function to add HWS apply update flags for phantom to block sequence 1950 */ 1951 void hwss_add_hws_apply_update_flags_for_phantom(struct block_sequence_state *seq_state, 1952 struct pipe_ctx *pipe_ctx) 1953 { 1954 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1955 seq_state->steps[*seq_state->num_steps].params.apply_update_flags_for_phantom_params.pipe_ctx = pipe_ctx; 1956 seq_state->steps[*seq_state->num_steps].func = HWS_APPLY_UPDATE_FLAGS_FOR_PHANTOM; 1957 (*seq_state->num_steps)++; 1958 } 1959 } 1960 1961 /* 1962 * Helper function to add HWS update phantom VP position to block sequence 1963 */ 1964 void hwss_add_hws_update_phantom_vp_position(struct block_sequence_state *seq_state, 1965 struct dc *dc, 1966 struct dc_state *context, 1967 struct pipe_ctx *pipe_ctx) 1968 { 1969 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1970 seq_state->steps[*seq_state->num_steps].params.update_phantom_vp_position_params.dc = dc; 1971 seq_state->steps[*seq_state->num_steps].params.update_phantom_vp_position_params.context = context; 1972 seq_state->steps[*seq_state->num_steps].params.update_phantom_vp_position_params.pipe_ctx = pipe_ctx; 1973 seq_state->steps[*seq_state->num_steps].func = HWS_UPDATE_PHANTOM_VP_POSITION; 1974 (*seq_state->num_steps)++; 1975 } 1976 } 1977 1978 /* 1979 * Helper function to add OPTC set ODM combine to block sequence 1980 */ 1981 void hwss_add_optc_set_odm_combine(struct block_sequence_state *seq_state, 1982 struct timing_generator *tg, int opp_inst[MAX_PIPES], int opp_head_count, 1983 int odm_slice_width, int last_odm_slice_width) 1984 { 1985 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 1986 seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.tg = tg; 1987 memcpy(seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.opp_inst, opp_inst, sizeof(int) * MAX_PIPES); 1988 seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.opp_head_count = opp_head_count; 1989 seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.odm_slice_width = odm_slice_width; 1990 seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.last_odm_slice_width = last_odm_slice_width; 1991 seq_state->steps[*seq_state->num_steps].func = OPTC_SET_ODM_COMBINE; 1992 (*seq_state->num_steps)++; 1993 } 1994 } 1995 1996 /* 1997 * Helper function to add OPTC set ODM bypass to block sequence 1998 */ 1999 void hwss_add_optc_set_odm_bypass(struct block_sequence_state *seq_state, 2000 struct timing_generator *tg, struct dc_crtc_timing *timing) 2001 { 2002 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2003 seq_state->steps[*seq_state->num_steps].params.set_odm_bypass_params.tg = tg; 2004 seq_state->steps[*seq_state->num_steps].params.set_odm_bypass_params.timing = timing; 2005 seq_state->steps[*seq_state->num_steps].func = OPTC_SET_ODM_BYPASS; 2006 (*seq_state->num_steps)++; 2007 } 2008 } 2009 2010 void hwss_send_dmcub_cmd(union block_sequence_params *params) 2011 { 2012 struct dc_context *ctx = params->send_dmcub_cmd_params.ctx; 2013 union dmub_rb_cmd *cmd = params->send_dmcub_cmd_params.cmd; 2014 enum dm_dmub_wait_type wait_type = params->send_dmcub_cmd_params.wait_type; 2015 2016 dc_wake_and_execute_dmub_cmd(ctx, cmd, wait_type); 2017 } 2018 2019 /* 2020 * Helper function to add TG program global sync to block sequence 2021 */ 2022 void hwss_add_tg_program_global_sync(struct block_sequence_state *seq_state, 2023 struct timing_generator *tg, 2024 int vready_offset, 2025 unsigned int vstartup_lines, 2026 unsigned int vupdate_offset_pixels, 2027 unsigned int vupdate_vupdate_width_pixels, 2028 unsigned int pstate_keepout_start_lines) 2029 { 2030 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2031 seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.tg = tg; 2032 seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.vready_offset = vready_offset; 2033 seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.vstartup_lines = vstartup_lines; 2034 seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.vupdate_offset_pixels = vupdate_offset_pixels; 2035 seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.vupdate_vupdate_width_pixels = vupdate_vupdate_width_pixels; 2036 seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.pstate_keepout_start_lines = pstate_keepout_start_lines; 2037 seq_state->steps[*seq_state->num_steps].func = TG_PROGRAM_GLOBAL_SYNC; 2038 (*seq_state->num_steps)++; 2039 } 2040 } 2041 2042 /* 2043 * Helper function to add TG wait for state to block sequence 2044 */ 2045 void hwss_add_tg_wait_for_state(struct block_sequence_state *seq_state, 2046 struct timing_generator *tg, 2047 enum crtc_state state) 2048 { 2049 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2050 seq_state->steps[*seq_state->num_steps].params.tg_wait_for_state_params.tg = tg; 2051 seq_state->steps[*seq_state->num_steps].params.tg_wait_for_state_params.state = state; 2052 seq_state->steps[*seq_state->num_steps].func = TG_WAIT_FOR_STATE; 2053 (*seq_state->num_steps)++; 2054 } 2055 } 2056 2057 /* 2058 * Helper function to add TG set VTG params to block sequence 2059 */ 2060 void hwss_add_tg_set_vtg_params(struct block_sequence_state *seq_state, 2061 struct timing_generator *tg, 2062 struct dc_crtc_timing *dc_crtc_timing, 2063 bool program_fp2) 2064 { 2065 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2066 seq_state->steps[*seq_state->num_steps].params.tg_set_vtg_params_params.tg = tg; 2067 seq_state->steps[*seq_state->num_steps].params.tg_set_vtg_params_params.timing = dc_crtc_timing; 2068 seq_state->steps[*seq_state->num_steps].params.tg_set_vtg_params_params.program_fp2 = program_fp2; 2069 seq_state->steps[*seq_state->num_steps].func = TG_SET_VTG_PARAMS; 2070 (*seq_state->num_steps)++; 2071 } 2072 } 2073 2074 /* 2075 * Helper function to add OTG setup vertical interrupt0 to block sequence 2076 */ 2077 void hwss_add_vertical_interrupt_setup(struct block_sequence_state *seq_state, 2078 struct timing_generator *tg, uint32_t start_line, uint32_t end_line) 2079 { 2080 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2081 seq_state->steps[*seq_state->num_steps].params.tg_setup_vertical_interrupt0_params.tg = tg; 2082 seq_state->steps[*seq_state->num_steps].params.tg_setup_vertical_interrupt0_params.start_line = start_line; 2083 seq_state->steps[*seq_state->num_steps].params.tg_setup_vertical_interrupt0_params.end_line = end_line; 2084 seq_state->steps[*seq_state->num_steps].func = OTG_SETUP_VERTICAL_INTERRUPT; 2085 (*seq_state->num_steps)++; 2086 } 2087 } 2088 2089 /* 2090 * Helper function to add TG setup vertical interrupt2 to block sequence 2091 */ 2092 void hwss_add_tg_setup_vertical_interrupt2(struct block_sequence_state *seq_state, 2093 struct timing_generator *tg, int start_line) 2094 { 2095 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2096 seq_state->steps[*seq_state->num_steps].params.tg_setup_vertical_interrupt2_params.tg = tg; 2097 seq_state->steps[*seq_state->num_steps].params.tg_setup_vertical_interrupt2_params.start_line = start_line; 2098 seq_state->steps[*seq_state->num_steps].func = TG_SETUP_VERTICAL_INTERRUPT2; 2099 (*seq_state->num_steps)++; 2100 } 2101 } 2102 2103 /* 2104 * Helper function to add DPP set HDR multiplier to block sequence 2105 */ 2106 void hwss_add_dpp_set_hdr_multiplier(struct block_sequence_state *seq_state, 2107 struct dpp *dpp, uint32_t hw_mult) 2108 { 2109 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2110 seq_state->steps[*seq_state->num_steps].params.dpp_set_hdr_multiplier_params.dpp = dpp; 2111 seq_state->steps[*seq_state->num_steps].params.dpp_set_hdr_multiplier_params.hw_mult = hw_mult; 2112 seq_state->steps[*seq_state->num_steps].func = DPP_SET_HDR_MULTIPLIER; 2113 (*seq_state->num_steps)++; 2114 } 2115 } 2116 2117 /* 2118 * Helper function to add HUBP program DET size to block sequence 2119 */ 2120 void hwss_add_hubp_program_det_size(struct block_sequence_state *seq_state, 2121 struct hubbub *hubbub, 2122 unsigned int hubp_inst, 2123 unsigned int det_buffer_size_kb) 2124 { 2125 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2126 seq_state->steps[*seq_state->num_steps].params.program_det_size_params.hubbub = hubbub; 2127 seq_state->steps[*seq_state->num_steps].params.program_det_size_params.hubp_inst = hubp_inst; 2128 seq_state->steps[*seq_state->num_steps].params.program_det_size_params.det_buffer_size_kb = det_buffer_size_kb; 2129 seq_state->steps[*seq_state->num_steps].func = HUBP_PROGRAM_DET_SIZE; 2130 (*seq_state->num_steps)++; 2131 } 2132 } 2133 2134 void hwss_add_hubp_program_mcache_id(struct block_sequence_state *seq_state, 2135 struct hubp *hubp, 2136 struct dml2_hubp_pipe_mcache_regs *mcache_regs) 2137 { 2138 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2139 seq_state->steps[*seq_state->num_steps].params.program_mcache_id_and_split_coordinate.hubp = hubp; 2140 seq_state->steps[*seq_state->num_steps].params.program_mcache_id_and_split_coordinate.mcache_regs = mcache_regs; 2141 seq_state->steps[*seq_state->num_steps].func = HUBP_PROGRAM_MCACHE_ID; 2142 (*seq_state->num_steps)++; 2143 } 2144 } 2145 2146 void hwss_add_hubbub_force_pstate_change_control(struct block_sequence_state *seq_state, 2147 struct hubbub *hubbub, 2148 bool enable, 2149 bool wait) 2150 { 2151 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2152 seq_state->steps[*seq_state->num_steps].params.hubbub_force_pstate_change_control_params.hubbub = hubbub; 2153 seq_state->steps[*seq_state->num_steps].params.hubbub_force_pstate_change_control_params.enable = enable; 2154 seq_state->steps[*seq_state->num_steps].params.hubbub_force_pstate_change_control_params.wait = wait; 2155 seq_state->steps[*seq_state->num_steps].func = HUBBUB_FORCE_PSTATE_CHANGE_CONTROL; 2156 (*seq_state->num_steps)++; 2157 } 2158 } 2159 2160 /* 2161 * Helper function to add HUBP program DET segments to block sequence 2162 */ 2163 void hwss_add_hubp_program_det_segments(struct block_sequence_state *seq_state, 2164 struct hubbub *hubbub, 2165 unsigned int hubp_inst, 2166 unsigned int det_size) 2167 { 2168 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2169 seq_state->steps[*seq_state->num_steps].params.program_det_segments_params.hubbub = hubbub; 2170 seq_state->steps[*seq_state->num_steps].params.program_det_segments_params.hubp_inst = hubp_inst; 2171 seq_state->steps[*seq_state->num_steps].params.program_det_segments_params.det_size = det_size; 2172 seq_state->steps[*seq_state->num_steps].func = HUBP_PROGRAM_DET_SEGMENTS; 2173 (*seq_state->num_steps)++; 2174 } 2175 } 2176 2177 /* 2178 * Helper function to add OPP set dynamic expansion to block sequence 2179 */ 2180 void hwss_add_opp_set_dyn_expansion(struct block_sequence_state *seq_state, 2181 struct output_pixel_processor *opp, 2182 enum dc_color_space color_space, 2183 enum dc_color_depth color_depth, 2184 enum signal_type signal) 2185 { 2186 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2187 seq_state->steps[*seq_state->num_steps].params.opp_set_dyn_expansion_params.opp = opp; 2188 seq_state->steps[*seq_state->num_steps].params.opp_set_dyn_expansion_params.color_space = color_space; 2189 seq_state->steps[*seq_state->num_steps].params.opp_set_dyn_expansion_params.color_depth = color_depth; 2190 seq_state->steps[*seq_state->num_steps].params.opp_set_dyn_expansion_params.signal = signal; 2191 seq_state->steps[*seq_state->num_steps].func = OPP_SET_DYN_EXPANSION; 2192 (*seq_state->num_steps)++; 2193 } 2194 } 2195 2196 /* 2197 * Helper function to add OPP program FMT to block sequence 2198 */ 2199 void hwss_add_opp_program_fmt(struct block_sequence_state *seq_state, 2200 struct output_pixel_processor *opp, 2201 struct bit_depth_reduction_params *fmt_bit_depth, 2202 struct clamping_and_pixel_encoding_params *clamping) 2203 { 2204 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2205 seq_state->steps[*seq_state->num_steps].params.opp_program_fmt_params.opp = opp; 2206 seq_state->steps[*seq_state->num_steps].params.opp_program_fmt_params.fmt_bit_depth = fmt_bit_depth; 2207 seq_state->steps[*seq_state->num_steps].params.opp_program_fmt_params.clamping = clamping; 2208 seq_state->steps[*seq_state->num_steps].func = OPP_PROGRAM_FMT; 2209 (*seq_state->num_steps)++; 2210 } 2211 } 2212 2213 void hwss_add_opp_program_left_edge_extra_pixel(struct block_sequence_state *seq_state, 2214 struct output_pixel_processor *opp, 2215 enum dc_pixel_encoding pixel_encoding, 2216 bool is_otg_master) 2217 { 2218 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2219 seq_state->steps[*seq_state->num_steps].func = OPP_PROGRAM_LEFT_EDGE_EXTRA_PIXEL; 2220 seq_state->steps[*seq_state->num_steps].params.opp_program_left_edge_extra_pixel_params.opp = opp; 2221 seq_state->steps[*seq_state->num_steps].params.opp_program_left_edge_extra_pixel_params.pixel_encoding = pixel_encoding; 2222 seq_state->steps[*seq_state->num_steps].params.opp_program_left_edge_extra_pixel_params.is_otg_master = is_otg_master; 2223 (*seq_state->num_steps)++; 2224 } 2225 } 2226 2227 /* 2228 * Helper function to add ABM set pipe to block sequence 2229 */ 2230 void hwss_add_abm_set_pipe(struct block_sequence_state *seq_state, 2231 struct dc *dc, 2232 struct pipe_ctx *pipe_ctx) 2233 { 2234 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2235 seq_state->steps[*seq_state->num_steps].params.set_abm_pipe_params.dc = dc; 2236 seq_state->steps[*seq_state->num_steps].params.set_abm_pipe_params.pipe_ctx = pipe_ctx; 2237 seq_state->steps[*seq_state->num_steps].func = ABM_SET_PIPE; 2238 (*seq_state->num_steps)++; 2239 } 2240 } 2241 2242 /* 2243 * Helper function to add ABM set level to block sequence 2244 */ 2245 void hwss_add_abm_set_level(struct block_sequence_state *seq_state, 2246 struct abm *abm, 2247 uint32_t abm_level) 2248 { 2249 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2250 seq_state->steps[*seq_state->num_steps].params.set_abm_level_params.abm = abm; 2251 seq_state->steps[*seq_state->num_steps].params.set_abm_level_params.abm_level = abm_level; 2252 seq_state->steps[*seq_state->num_steps].func = ABM_SET_LEVEL; 2253 (*seq_state->num_steps)++; 2254 } 2255 } 2256 2257 /* 2258 * Helper function to add TG enable CRTC to block sequence 2259 */ 2260 void hwss_add_tg_enable_crtc(struct block_sequence_state *seq_state, 2261 struct timing_generator *tg) 2262 { 2263 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2264 seq_state->steps[*seq_state->num_steps].params.tg_enable_crtc_params.tg = tg; 2265 seq_state->steps[*seq_state->num_steps].func = TG_ENABLE_CRTC; 2266 (*seq_state->num_steps)++; 2267 } 2268 } 2269 2270 /* 2271 * Helper function to add HUBP wait flip pending to block sequence 2272 */ 2273 void hwss_add_hubp_wait_flip_pending(struct block_sequence_state *seq_state, 2274 struct hubp *hubp, 2275 unsigned int timeout_us, 2276 unsigned int polling_interval_us) 2277 { 2278 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2279 seq_state->steps[*seq_state->num_steps].params.hubp_wait_flip_pending_params.hubp = hubp; 2280 seq_state->steps[*seq_state->num_steps].params.hubp_wait_flip_pending_params.timeout_us = timeout_us; 2281 seq_state->steps[*seq_state->num_steps].params.hubp_wait_flip_pending_params.polling_interval_us = polling_interval_us; 2282 seq_state->steps[*seq_state->num_steps].func = HUBP_WAIT_FLIP_PENDING; 2283 (*seq_state->num_steps)++; 2284 } 2285 } 2286 2287 /* 2288 * Helper function to add TG wait double buffer pending to block sequence 2289 */ 2290 void hwss_add_tg_wait_double_buffer_pending(struct block_sequence_state *seq_state, 2291 struct timing_generator *tg, 2292 unsigned int timeout_us, 2293 unsigned int polling_interval_us) 2294 { 2295 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2296 seq_state->steps[*seq_state->num_steps].params.tg_wait_double_buffer_pending_params.tg = tg; 2297 seq_state->steps[*seq_state->num_steps].params.tg_wait_double_buffer_pending_params.timeout_us = timeout_us; 2298 seq_state->steps[*seq_state->num_steps].params.tg_wait_double_buffer_pending_params.polling_interval_us = polling_interval_us; 2299 seq_state->steps[*seq_state->num_steps].func = TG_WAIT_DOUBLE_BUFFER_PENDING; 2300 (*seq_state->num_steps)++; 2301 } 2302 } 2303 2304 void hwss_add_hubp_enable_3dlut_fl(struct block_sequence_state *seq_state, 2305 struct hubp *hubp) 2306 { 2307 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 2308 seq_state->steps[*seq_state->num_steps].params.hubp_enable_3dlut_fl_params.hubp = hubp; 2309 seq_state->steps[*seq_state->num_steps].func = HUBP_ENABLE_3DLUT_FL; 2310 (*seq_state->num_steps)++; 2311 } 2312 } 2313 2314 void hwss_program_manual_trigger(union block_sequence_params *params) 2315 { 2316 struct pipe_ctx *pipe_ctx = params->program_manual_trigger_params.pipe_ctx; 2317 2318 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger) 2319 pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg); 2320 } 2321 2322 void hwss_setup_dpp(union block_sequence_params *params) 2323 { 2324 struct pipe_ctx *pipe_ctx = params->setup_dpp_params.pipe_ctx; 2325 struct dpp *dpp = pipe_ctx->plane_res.dpp; 2326 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2327 2328 if (!plane_state) 2329 return; 2330 2331 if (dpp && dpp->funcs->dpp_setup) { 2332 // program the input csc 2333 dpp->funcs->dpp_setup(dpp, 2334 plane_state->format, 2335 EXPANSION_MODE_ZERO, 2336 plane_state->input_csc_color_matrix, 2337 plane_state->color_space, 2338 NULL); 2339 } 2340 } 2341 2342 void hwss_program_bias_and_scale(union block_sequence_params *params) 2343 { 2344 struct pipe_ctx *pipe_ctx = params->program_bias_and_scale_params.pipe_ctx; 2345 struct dpp *dpp = pipe_ctx->plane_res.dpp; 2346 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2347 struct dc_bias_and_scale bns_params = plane_state->bias_and_scale; 2348 2349 //TODO :for CNVC set scale and bias registers if necessary 2350 if (dpp->funcs->dpp_program_bias_and_scale) 2351 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); 2352 } 2353 2354 void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params) 2355 { 2356 struct mpc *mpc = params->power_on_mpc_mem_pwr_params.mpc; 2357 int mpcc_id = params->power_on_mpc_mem_pwr_params.mpcc_id; 2358 bool power_on = params->power_on_mpc_mem_pwr_params.power_on; 2359 2360 if (mpc->funcs->power_on_mpc_mem_pwr) 2361 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, power_on); 2362 } 2363 2364 void hwss_set_output_csc(union block_sequence_params *params) 2365 { 2366 struct mpc *mpc = params->set_output_csc_params.mpc; 2367 int opp_id = params->set_output_csc_params.opp_id; 2368 const uint16_t *matrix = params->set_output_csc_params.regval; 2369 enum mpc_output_csc_mode ocsc_mode = params->set_output_csc_params.ocsc_mode; 2370 2371 if (mpc->funcs->set_output_csc != NULL) 2372 mpc->funcs->set_output_csc(mpc, 2373 opp_id, 2374 matrix, 2375 ocsc_mode); 2376 } 2377 2378 void hwss_set_ocsc_default(union block_sequence_params *params) 2379 { 2380 struct mpc *mpc = params->set_ocsc_default_params.mpc; 2381 int opp_id = params->set_ocsc_default_params.opp_id; 2382 enum dc_color_space colorspace = params->set_ocsc_default_params.color_space; 2383 enum mpc_output_csc_mode ocsc_mode = params->set_ocsc_default_params.ocsc_mode; 2384 2385 if (mpc->funcs->set_ocsc_default != NULL) 2386 mpc->funcs->set_ocsc_default(mpc, 2387 opp_id, 2388 colorspace, 2389 ocsc_mode); 2390 } 2391 2392 void hwss_subvp_save_surf_addr(union block_sequence_params *params) 2393 { 2394 struct dc_dmub_srv *dc_dmub_srv = params->subvp_save_surf_addr.dc_dmub_srv; 2395 const struct dc_plane_address *addr = params->subvp_save_surf_addr.addr; 2396 uint8_t subvp_index = params->subvp_save_surf_addr.subvp_index; 2397 2398 dc_dmub_srv_subvp_save_surf_addr(dc_dmub_srv, addr, subvp_index); 2399 } 2400 2401 void hwss_program_surface_config(union block_sequence_params *params) 2402 { 2403 struct hubp *hubp = params->program_surface_config_params.hubp; 2404 enum surface_pixel_format format = params->program_surface_config_params.format; 2405 struct dc_tiling_info *tiling_info = params->program_surface_config_params.tiling_info; 2406 struct plane_size size = params->program_surface_config_params.plane_size; 2407 enum dc_rotation_angle rotation = params->program_surface_config_params.rotation; 2408 struct dc_plane_dcc_param *dcc = params->program_surface_config_params.dcc; 2409 bool horizontal_mirror = params->program_surface_config_params.horizontal_mirror; 2410 int compat_level = params->program_surface_config_params.compat_level; 2411 2412 hubp->funcs->hubp_program_surface_config( 2413 hubp, 2414 format, 2415 tiling_info, 2416 &size, 2417 rotation, 2418 dcc, 2419 horizontal_mirror, 2420 compat_level); 2421 2422 hubp->power_gated = false; 2423 } 2424 2425 void hwss_program_mcache_id_and_split_coordinate(union block_sequence_params *params) 2426 { 2427 struct hubp *hubp = params->program_mcache_id_and_split_coordinate.hubp; 2428 struct dml2_hubp_pipe_mcache_regs *mcache_regs = params->program_mcache_id_and_split_coordinate.mcache_regs; 2429 2430 hubp->funcs->hubp_program_mcache_id_and_split_coordinate(hubp, mcache_regs); 2431 2432 } 2433 2434 void hwss_program_cm_hist(union block_sequence_params *params) 2435 { 2436 struct dpp *dpp = params->control_cm_hist_params.dpp; 2437 2438 if (dpp && dpp->funcs->dpp_cm_hist_control) 2439 dpp->funcs->dpp_cm_hist_control(dpp, 2440 params->control_cm_hist_params.cm_hist_control, 2441 params->control_cm_hist_params.color_space); 2442 } 2443 2444 void get_surface_tile_visual_confirm_color( 2445 struct pipe_ctx *pipe_ctx, 2446 struct tg_color *color) 2447 { 2448 uint32_t color_value = MAX_TG_COLOR_VALUE; 2449 /* Determine the overscan color based on the bottom-most plane's context */ 2450 struct pipe_ctx *bottom_pipe_ctx = pipe_ctx; 2451 2452 while (bottom_pipe_ctx->bottom_pipe != NULL) 2453 bottom_pipe_ctx = bottom_pipe_ctx->bottom_pipe; 2454 2455 switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) { 2456 case DC_SW_LINEAR: 2457 /* LINEAR Surface - set border color to red */ 2458 color->color_r_cr = (uint16_t)color_value; 2459 break; 2460 default: 2461 break; 2462 } 2463 } 2464 2465 /** 2466 * hwss_wait_for_all_blank_complete - wait for all active OPPs to finish pending blank 2467 * pattern updates 2468 * 2469 * @dc: [in] dc reference 2470 * @context: [in] hardware context in use 2471 */ 2472 void hwss_wait_for_all_blank_complete(struct dc *dc, 2473 struct dc_state *context) 2474 { 2475 struct pipe_ctx *opp_head; 2476 struct dce_hwseq *hws = dc->hwseq; 2477 int i; 2478 2479 if (!hws->funcs.wait_for_blank_complete) 2480 return; 2481 2482 for (i = 0; i < MAX_PIPES; i++) { 2483 opp_head = &context->res_ctx.pipe_ctx[i]; 2484 2485 if (!resource_is_pipe_type(opp_head, OPP_HEAD) || 2486 dc_state_get_pipe_subvp_type(context, opp_head) == SUBVP_PHANTOM) 2487 continue; 2488 2489 hws->funcs.wait_for_blank_complete(opp_head->stream_res.opp); 2490 } 2491 } 2492 2493 void hwss_wait_for_odm_update_pending_complete(struct dc *dc, struct dc_state *context) 2494 { 2495 struct pipe_ctx *otg_master; 2496 struct timing_generator *tg; 2497 int i; 2498 2499 for (i = 0; i < MAX_PIPES; i++) { 2500 otg_master = &context->res_ctx.pipe_ctx[i]; 2501 if (!resource_is_pipe_type(otg_master, OTG_MASTER) || 2502 dc_state_get_pipe_subvp_type(context, otg_master) == SUBVP_PHANTOM) 2503 continue; 2504 tg = otg_master->stream_res.tg; 2505 if (tg->funcs->wait_odm_doublebuffer_pending_clear) 2506 tg->funcs->wait_odm_doublebuffer_pending_clear(tg); 2507 if (tg->funcs->wait_otg_disable) 2508 tg->funcs->wait_otg_disable(tg); 2509 } 2510 2511 /* ODM update may require to reprogram blank pattern for each OPP */ 2512 hwss_wait_for_all_blank_complete(dc, context); 2513 } 2514 2515 void hwss_wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context) 2516 { 2517 int i; 2518 2519 for (i = 0; i < MAX_PIPES; i++) { 2520 int count = 0; 2521 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2522 2523 if (!pipe->plane_state || dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) 2524 continue; 2525 2526 /* Timeout 100 ms */ 2527 while (count < 100000) { 2528 /* Must set to false to start with, due to OR in update function */ 2529 pipe->plane_state->status.is_flip_pending = false; 2530 dc->hwss.update_pending_status(pipe); 2531 if (!pipe->plane_state->status.is_flip_pending) 2532 break; 2533 udelay(1); 2534 count++; 2535 } 2536 ASSERT(!pipe->plane_state->status.is_flip_pending); 2537 } 2538 } 2539 2540 void hwss_wait_for_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_context) 2541 { 2542 /* 2543 * This function calls HWSS to wait for any potentially double buffered 2544 * operations to complete. It should be invoked as a pre-amble prior 2545 * to full update programming before asserting any HW locks. 2546 */ 2547 unsigned int pipe_idx; 2548 int opp_inst; 2549 int opp_count = dc->res_pool->res_cap->num_opp; 2550 struct hubp *hubp; 2551 int mpcc_inst; 2552 const struct pipe_ctx *pipe_ctx; 2553 2554 for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) { 2555 pipe_ctx = &dc_context->res_ctx.pipe_ctx[pipe_idx]; 2556 2557 if (!pipe_ctx->stream) 2558 continue; 2559 2560 /* For full update we must wait for all double buffer updates, not just DRR updates. This 2561 * is particularly important for minimal transitions. Only check for OTG_MASTER pipes, 2562 * as non-OTG Master pipes share the same OTG as 2563 */ 2564 if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && dc->hwss.wait_for_all_pending_updates) { 2565 dc->hwss.wait_for_all_pending_updates(pipe_ctx); 2566 } 2567 2568 hubp = pipe_ctx->plane_res.hubp; 2569 if (!hubp) 2570 continue; 2571 2572 mpcc_inst = hubp->inst; 2573 // MPCC inst is equal to pipe index in practice 2574 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) { 2575 if ((dc->res_pool->opps[opp_inst] != NULL) && 2576 (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst])) { 2577 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst); 2578 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false; 2579 break; 2580 } 2581 } 2582 } 2583 hwss_wait_for_odm_update_pending_complete(dc, dc_context); 2584 } 2585 2586 void hwss_process_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_context) 2587 { 2588 /* wait for outstanding updates */ 2589 hwss_wait_for_outstanding_hw_updates(dc, dc_context); 2590 2591 /* perform outstanding post update programming */ 2592 if (dc->hwss.program_outstanding_updates) 2593 dc->hwss.program_outstanding_updates(dc, dc_context); 2594 } 2595 2596 void hwss_set_odm_combine(union block_sequence_params *params) 2597 { 2598 struct timing_generator *tg = params->set_odm_combine_params.tg; 2599 int *opp_inst = params->set_odm_combine_params.opp_inst; 2600 int opp_head_count = params->set_odm_combine_params.opp_head_count; 2601 int odm_slice_width = params->set_odm_combine_params.odm_slice_width; 2602 int last_odm_slice_width = params->set_odm_combine_params.last_odm_slice_width; 2603 2604 if (tg && tg->funcs->set_odm_combine) 2605 tg->funcs->set_odm_combine(tg, opp_inst, opp_head_count, 2606 odm_slice_width, last_odm_slice_width); 2607 } 2608 2609 void hwss_set_odm_bypass(union block_sequence_params *params) 2610 { 2611 struct timing_generator *tg = params->set_odm_bypass_params.tg; 2612 const struct dc_crtc_timing *timing = params->set_odm_bypass_params.timing; 2613 2614 if (tg && tg->funcs->set_odm_bypass) 2615 tg->funcs->set_odm_bypass(tg, timing); 2616 } 2617 2618 void hwss_opp_pipe_clock_control(union block_sequence_params *params) 2619 { 2620 struct output_pixel_processor *opp = params->opp_pipe_clock_control_params.opp; 2621 bool enable = params->opp_pipe_clock_control_params.enable; 2622 2623 if (opp && opp->funcs->opp_pipe_clock_control) 2624 opp->funcs->opp_pipe_clock_control(opp, enable); 2625 } 2626 2627 void hwss_opp_program_left_edge_extra_pixel(union block_sequence_params *params) 2628 { 2629 struct output_pixel_processor *opp = params->opp_program_left_edge_extra_pixel_params.opp; 2630 enum dc_pixel_encoding pixel_encoding = params->opp_program_left_edge_extra_pixel_params.pixel_encoding; 2631 bool is_otg_master = params->opp_program_left_edge_extra_pixel_params.is_otg_master; 2632 2633 if (opp && opp->funcs->opp_program_left_edge_extra_pixel) 2634 opp->funcs->opp_program_left_edge_extra_pixel(opp, pixel_encoding, is_otg_master); 2635 } 2636 2637 void hwss_dccg_set_dto_dscclk(union block_sequence_params *params) 2638 { 2639 struct dccg *dccg = params->dccg_set_dto_dscclk_params.dccg; 2640 int inst = params->dccg_set_dto_dscclk_params.inst; 2641 int num_slices_h = params->dccg_set_dto_dscclk_params.num_slices_h; 2642 2643 if (dccg && dccg->funcs->set_dto_dscclk) 2644 dccg->funcs->set_dto_dscclk(dccg, inst, num_slices_h); 2645 } 2646 2647 void hwss_dsc_set_config(union block_sequence_params *params) 2648 { 2649 struct display_stream_compressor *dsc = params->dsc_set_config_params.dsc; 2650 struct dsc_config *dsc_cfg = params->dsc_set_config_params.dsc_cfg; 2651 struct dsc_optc_config *dsc_optc_cfg = params->dsc_set_config_params.dsc_optc_cfg; 2652 2653 if (dsc && dsc->funcs->dsc_set_config) 2654 dsc->funcs->dsc_set_config(dsc, dsc_cfg, dsc_optc_cfg); 2655 } 2656 2657 void hwss_dsc_enable(union block_sequence_params *params) 2658 { 2659 struct display_stream_compressor *dsc = params->dsc_enable_params.dsc; 2660 int opp_inst = params->dsc_enable_params.opp_inst; 2661 2662 if (dsc && dsc->funcs->dsc_enable) 2663 dsc->funcs->dsc_enable(dsc, opp_inst); 2664 } 2665 2666 void hwss_tg_set_dsc_config(union block_sequence_params *params) 2667 { 2668 struct timing_generator *tg = params->tg_set_dsc_config_params.tg; 2669 enum optc_dsc_mode optc_dsc_mode = OPTC_DSC_DISABLED; 2670 uint32_t bytes_per_pixel = 0; 2671 uint32_t slice_width = 0; 2672 2673 if (params->tg_set_dsc_config_params.enable) { 2674 struct dsc_optc_config *dsc_optc_cfg = params->tg_set_dsc_config_params.dsc_optc_cfg; 2675 2676 if (dsc_optc_cfg) { 2677 bytes_per_pixel = dsc_optc_cfg->bytes_per_pixel; 2678 slice_width = dsc_optc_cfg->slice_width; 2679 optc_dsc_mode = dsc_optc_cfg->is_pixel_format_444 ? 2680 OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 2681 } 2682 } 2683 2684 if (tg && tg->funcs->set_dsc_config) 2685 tg->funcs->set_dsc_config(tg, optc_dsc_mode, bytes_per_pixel, slice_width); 2686 } 2687 2688 void hwss_dsc_disconnect(union block_sequence_params *params) 2689 { 2690 struct display_stream_compressor *dsc = params->dsc_disconnect_params.dsc; 2691 2692 if (dsc && dsc->funcs->dsc_disconnect) 2693 dsc->funcs->dsc_disconnect(dsc); 2694 } 2695 2696 void hwss_dsc_read_state(union block_sequence_params *params) 2697 { 2698 struct display_stream_compressor *dsc = params->dsc_read_state_params.dsc; 2699 struct dcn_dsc_state *dsc_state = params->dsc_read_state_params.dsc_state; 2700 2701 if (dsc && dsc->funcs->dsc_read_state) 2702 dsc->funcs->dsc_read_state(dsc, dsc_state); 2703 } 2704 2705 void hwss_dsc_calculate_and_set_config(union block_sequence_params *params) 2706 { 2707 struct pipe_ctx *pipe_ctx = params->dsc_calculate_and_set_config_params.pipe_ctx; 2708 struct pipe_ctx *top_pipe = pipe_ctx; 2709 bool enable = params->dsc_calculate_and_set_config_params.enable; 2710 int opp_cnt = params->dsc_calculate_and_set_config_params.opp_cnt; 2711 2712 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 2713 struct dc_stream_state *stream = pipe_ctx->stream; 2714 2715 if (!dsc || !enable) 2716 return; 2717 2718 /* Calculate DSC configuration - extracted from dcn32_update_dsc_on_stream */ 2719 struct dsc_config dsc_cfg; 2720 2721 while (top_pipe->prev_odm_pipe) 2722 top_pipe = top_pipe->prev_odm_pipe; 2723 2724 dsc_cfg.pic_width = (stream->timing.h_addressable + top_pipe->dsc_padding_params.dsc_hactive_padding + 2725 stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 2726 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 2727 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 2728 dsc_cfg.color_depth = stream->timing.display_color_depth; 2729 dsc_cfg.is_odm = top_pipe->next_odm_pipe ? true : false; 2730 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 2731 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 2732 dsc_cfg.dsc_padding = top_pipe->dsc_padding_params.dsc_hactive_padding; 2733 2734 /* Set DSC configuration */ 2735 if (dsc->funcs->dsc_set_config) 2736 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, 2737 ¶ms->dsc_calculate_and_set_config_params.dsc_optc_cfg); 2738 } 2739 2740 void hwss_dsc_enable_with_opp(union block_sequence_params *params) 2741 { 2742 struct pipe_ctx *pipe_ctx = params->dsc_enable_with_opp_params.pipe_ctx; 2743 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 2744 2745 if (dsc && dsc->funcs->dsc_enable) 2746 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 2747 } 2748 2749 void hwss_tg_program_global_sync(union block_sequence_params *params) 2750 { 2751 struct timing_generator *tg = params->tg_program_global_sync_params.tg; 2752 int vready_offset = params->tg_program_global_sync_params.vready_offset; 2753 unsigned int vstartup_lines = params->tg_program_global_sync_params.vstartup_lines; 2754 unsigned int vupdate_offset_pixels = params->tg_program_global_sync_params.vupdate_offset_pixels; 2755 unsigned int vupdate_vupdate_width_pixels = params->tg_program_global_sync_params.vupdate_vupdate_width_pixels; 2756 unsigned int pstate_keepout_start_lines = params->tg_program_global_sync_params.pstate_keepout_start_lines; 2757 2758 if (tg->funcs->program_global_sync) { 2759 tg->funcs->program_global_sync(tg, vready_offset, vstartup_lines, 2760 vupdate_offset_pixels, vupdate_vupdate_width_pixels, pstate_keepout_start_lines); 2761 } 2762 } 2763 2764 void hwss_tg_wait_for_state(union block_sequence_params *params) 2765 { 2766 struct timing_generator *tg = params->tg_wait_for_state_params.tg; 2767 enum crtc_state state = params->tg_wait_for_state_params.state; 2768 2769 if (tg->funcs->wait_for_state) 2770 tg->funcs->wait_for_state(tg, state); 2771 } 2772 2773 void hwss_tg_set_vtg_params(union block_sequence_params *params) 2774 { 2775 struct timing_generator *tg = params->tg_set_vtg_params_params.tg; 2776 struct dc_crtc_timing *timing = params->tg_set_vtg_params_params.timing; 2777 bool program_fp2 = params->tg_set_vtg_params_params.program_fp2; 2778 2779 if (tg->funcs->set_vtg_params) 2780 tg->funcs->set_vtg_params(tg, timing, program_fp2); 2781 } 2782 2783 void hwss_hubp_enable_3dlut_fl(union block_sequence_params *params) 2784 { 2785 struct hubp *hubp = params->hubp_enable_3dlut_fl_params.hubp; 2786 2787 if (hubp->funcs->hubp_enable_3dlut_fl) 2788 hubp->funcs->hubp_enable_3dlut_fl(hubp, true); 2789 } 2790 2791 void hwss_update_info_frame(struct dc *dc, union block_sequence_params *params) 2792 { 2793 struct pipe_ctx *pipe_ctx = params->update_info_frame_params.pipe_ctx; 2794 2795 if (dc->hwss.update_info_frame) 2796 dc->hwss.update_info_frame(pipe_ctx); 2797 } 2798 2799 void hwss_setup_periodic_interrupt(struct dc *dc, union block_sequence_params *params) 2800 { 2801 struct pipe_ctx *pipe_ctx = params->setup_periodic_interrupt_params.pipe_ctx; 2802 2803 if (dc->hwss.setup_periodic_interrupt) 2804 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx); 2805 } 2806 2807 void hwss_tg_setup_vertical_interrupt0(union block_sequence_params *params) 2808 { 2809 struct timing_generator *tg = params->tg_setup_vertical_interrupt0_params.tg; 2810 uint32_t start_line = params->tg_setup_vertical_interrupt0_params.start_line; 2811 uint32_t end_line = params->tg_setup_vertical_interrupt0_params.end_line; 2812 2813 if (tg->funcs->setup_vertical_interrupt0) 2814 tg->funcs->setup_vertical_interrupt0(tg, start_line, end_line); 2815 } 2816 2817 void hwss_tg_setup_vertical_interrupt2(union block_sequence_params *params) 2818 { 2819 struct timing_generator *tg = params->tg_setup_vertical_interrupt2_params.tg; 2820 int start_line = params->tg_setup_vertical_interrupt2_params.start_line; 2821 2822 if (tg->funcs->setup_vertical_interrupt2) 2823 tg->funcs->setup_vertical_interrupt2(tg, start_line); 2824 } 2825 2826 void hwss_dpp_set_hdr_multiplier(union block_sequence_params *params) 2827 { 2828 struct dpp *dpp = params->dpp_set_hdr_multiplier_params.dpp; 2829 uint32_t hw_mult = params->dpp_set_hdr_multiplier_params.hw_mult; 2830 2831 if (dpp->funcs->dpp_set_hdr_multiplier) 2832 dpp->funcs->dpp_set_hdr_multiplier(dpp, hw_mult); 2833 } 2834 2835 void hwss_program_det_size(union block_sequence_params *params) 2836 { 2837 struct hubbub *hubbub = params->program_det_size_params.hubbub; 2838 unsigned int hubp_inst = params->program_det_size_params.hubp_inst; 2839 unsigned int det_buffer_size_kb = params->program_det_size_params.det_buffer_size_kb; 2840 2841 if (hubbub->funcs->program_det_size) 2842 hubbub->funcs->program_det_size(hubbub, hubp_inst, det_buffer_size_kb); 2843 } 2844 2845 void hwss_program_det_segments(union block_sequence_params *params) 2846 { 2847 struct hubbub *hubbub = params->program_det_segments_params.hubbub; 2848 unsigned int hubp_inst = params->program_det_segments_params.hubp_inst; 2849 unsigned int det_size = params->program_det_segments_params.det_size; 2850 2851 if (hubbub->funcs->program_det_segments) 2852 hubbub->funcs->program_det_segments(hubbub, hubp_inst, det_size); 2853 } 2854 2855 void hwss_opp_set_dyn_expansion(union block_sequence_params *params) 2856 { 2857 struct output_pixel_processor *opp = params->opp_set_dyn_expansion_params.opp; 2858 enum dc_color_space color_space = params->opp_set_dyn_expansion_params.color_space; 2859 enum dc_color_depth color_depth = params->opp_set_dyn_expansion_params.color_depth; 2860 enum signal_type signal = params->opp_set_dyn_expansion_params.signal; 2861 2862 if (opp->funcs->opp_set_dyn_expansion) 2863 opp->funcs->opp_set_dyn_expansion(opp, color_space, color_depth, signal); 2864 } 2865 2866 void hwss_opp_program_fmt(union block_sequence_params *params) 2867 { 2868 struct output_pixel_processor *opp = params->opp_program_fmt_params.opp; 2869 struct bit_depth_reduction_params *fmt_bit_depth = params->opp_program_fmt_params.fmt_bit_depth; 2870 struct clamping_and_pixel_encoding_params *clamping = params->opp_program_fmt_params.clamping; 2871 2872 if (opp->funcs->opp_program_fmt) 2873 opp->funcs->opp_program_fmt(opp, fmt_bit_depth, clamping); 2874 } 2875 2876 void hwss_opp_program_bit_depth_reduction(union block_sequence_params *params) 2877 { 2878 struct output_pixel_processor *opp = params->opp_program_bit_depth_reduction_params.opp; 2879 bool use_default_params = params->opp_program_bit_depth_reduction_params.use_default_params; 2880 struct pipe_ctx *pipe_ctx = params->opp_program_bit_depth_reduction_params.pipe_ctx; 2881 struct bit_depth_reduction_params bit_depth_params; 2882 2883 if (use_default_params) 2884 memset(&bit_depth_params, 0, sizeof(bit_depth_params)); 2885 else 2886 resource_build_bit_depth_reduction_params(pipe_ctx->stream, &bit_depth_params); 2887 2888 if (opp->funcs->opp_program_bit_depth_reduction) 2889 opp->funcs->opp_program_bit_depth_reduction(opp, &bit_depth_params); 2890 } 2891 2892 void hwss_opp_set_disp_pattern_generator(union block_sequence_params *params) 2893 { 2894 struct output_pixel_processor *opp = params->opp_set_disp_pattern_generator_params.opp; 2895 enum controller_dp_test_pattern test_pattern = params->opp_set_disp_pattern_generator_params.test_pattern; 2896 enum controller_dp_color_space color_space = params->opp_set_disp_pattern_generator_params.color_space; 2897 enum dc_color_depth color_depth = params->opp_set_disp_pattern_generator_params.color_depth; 2898 struct tg_color *solid_color = params->opp_set_disp_pattern_generator_params.use_solid_color ? 2899 ¶ms->opp_set_disp_pattern_generator_params.solid_color : NULL; 2900 int width = params->opp_set_disp_pattern_generator_params.width; 2901 int height = params->opp_set_disp_pattern_generator_params.height; 2902 int offset = params->opp_set_disp_pattern_generator_params.offset; 2903 2904 if (opp && opp->funcs->opp_set_disp_pattern_generator) { 2905 opp->funcs->opp_set_disp_pattern_generator(opp, test_pattern, color_space, 2906 color_depth, solid_color, width, height, offset); 2907 } 2908 } 2909 2910 void hwss_set_abm_pipe(union block_sequence_params *params) 2911 { 2912 struct dc *dc = params->set_abm_pipe_params.dc; 2913 struct pipe_ctx *pipe_ctx = params->set_abm_pipe_params.pipe_ctx; 2914 2915 dc->hwss.set_pipe(pipe_ctx); 2916 } 2917 2918 void hwss_set_abm_level(union block_sequence_params *params) 2919 { 2920 struct abm *abm = params->set_abm_level_params.abm; 2921 unsigned int abm_level = params->set_abm_level_params.abm_level; 2922 2923 if (abm->funcs->set_abm_level) 2924 abm->funcs->set_abm_level(abm, abm_level); 2925 } 2926 2927 void hwss_set_abm_immediate_disable(union block_sequence_params *params) 2928 { 2929 struct dc *dc = params->set_abm_immediate_disable_params.dc; 2930 struct pipe_ctx *pipe_ctx = params->set_abm_immediate_disable_params.pipe_ctx; 2931 2932 if (dc && dc->hwss.set_abm_immediate_disable) 2933 dc->hwss.set_abm_immediate_disable(pipe_ctx); 2934 } 2935 2936 void hwss_mpc_remove_mpcc(union block_sequence_params *params) 2937 { 2938 struct mpc *mpc = params->mpc_remove_mpcc_params.mpc; 2939 struct mpc_tree *mpc_tree_params = params->mpc_remove_mpcc_params.mpc_tree_params; 2940 struct mpcc *mpcc_to_remove = params->mpc_remove_mpcc_params.mpcc_to_remove; 2941 2942 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove); 2943 } 2944 2945 void hwss_opp_set_mpcc_disconnect_pending(union block_sequence_params *params) 2946 { 2947 struct output_pixel_processor *opp = params->opp_set_mpcc_disconnect_pending_params.opp; 2948 int mpcc_inst = params->opp_set_mpcc_disconnect_pending_params.mpcc_inst; 2949 bool pending = params->opp_set_mpcc_disconnect_pending_params.pending; 2950 2951 opp->mpcc_disconnect_pending[mpcc_inst] = pending; 2952 } 2953 2954 void hwss_dc_set_optimized_required(union block_sequence_params *params) 2955 { 2956 struct dc *dc = params->dc_set_optimized_required_params.dc; 2957 bool optimized_required = params->dc_set_optimized_required_params.optimized_required; 2958 2959 dc->optimized_required = optimized_required; 2960 } 2961 2962 void hwss_hubp_disconnect(union block_sequence_params *params) 2963 { 2964 struct hubp *hubp = params->hubp_disconnect_params.hubp; 2965 2966 if (hubp->funcs->hubp_disconnect) 2967 hubp->funcs->hubp_disconnect(hubp); 2968 } 2969 2970 void hwss_hubbub_force_pstate_change_control(union block_sequence_params *params) 2971 { 2972 struct hubbub *hubbub = params->hubbub_force_pstate_change_control_params.hubbub; 2973 bool enable = params->hubbub_force_pstate_change_control_params.enable; 2974 bool wait = params->hubbub_force_pstate_change_control_params.wait; 2975 2976 if (hubbub->funcs->force_pstate_change_control) { 2977 hubbub->funcs->force_pstate_change_control(hubbub, enable, wait); 2978 /* Add delay when enabling pstate change control */ 2979 if (enable) 2980 udelay(500); 2981 } 2982 } 2983 2984 void hwss_tg_enable_crtc(union block_sequence_params *params) 2985 { 2986 struct timing_generator *tg = params->tg_enable_crtc_params.tg; 2987 2988 if (tg->funcs->enable_crtc) 2989 tg->funcs->enable_crtc(tg); 2990 } 2991 2992 void hwss_tg_set_gsl(union block_sequence_params *params) 2993 { 2994 struct timing_generator *tg = params->tg_set_gsl_params.tg; 2995 struct gsl_params *gsl = ¶ms->tg_set_gsl_params.gsl; 2996 2997 if (tg->funcs->set_gsl) 2998 tg->funcs->set_gsl(tg, gsl); 2999 } 3000 3001 void hwss_tg_set_gsl_source_select(union block_sequence_params *params) 3002 { 3003 struct timing_generator *tg = params->tg_set_gsl_source_select_params.tg; 3004 int group_idx = params->tg_set_gsl_source_select_params.group_idx; 3005 uint32_t gsl_ready_signal = params->tg_set_gsl_source_select_params.gsl_ready_signal; 3006 3007 if (tg->funcs->set_gsl_source_select) 3008 tg->funcs->set_gsl_source_select(tg, group_idx, gsl_ready_signal); 3009 } 3010 3011 void hwss_hubp_wait_flip_pending(union block_sequence_params *params) 3012 { 3013 struct hubp *hubp = params->hubp_wait_flip_pending_params.hubp; 3014 unsigned int timeout_us = params->hubp_wait_flip_pending_params.timeout_us; 3015 unsigned int polling_interval_us = params->hubp_wait_flip_pending_params.polling_interval_us; 3016 unsigned int j = 0; 3017 3018 for (j = 0; j < timeout_us / polling_interval_us 3019 && hubp->funcs->hubp_is_flip_pending(hubp); j++) 3020 udelay(polling_interval_us); 3021 } 3022 3023 void hwss_tg_wait_double_buffer_pending(union block_sequence_params *params) 3024 { 3025 struct timing_generator *tg = params->tg_wait_double_buffer_pending_params.tg; 3026 unsigned int timeout_us = params->tg_wait_double_buffer_pending_params.timeout_us; 3027 unsigned int polling_interval_us = params->tg_wait_double_buffer_pending_params.polling_interval_us; 3028 unsigned int j = 0; 3029 3030 if (tg->funcs->get_optc_double_buffer_pending) { 3031 for (j = 0; j < timeout_us / polling_interval_us 3032 && tg->funcs->get_optc_double_buffer_pending(tg); j++) 3033 udelay(polling_interval_us); 3034 } 3035 } 3036 3037 void hwss_update_force_pstate(union block_sequence_params *params) 3038 { 3039 struct dc *dc = params->update_force_pstate_params.dc; 3040 struct dc_state *context = params->update_force_pstate_params.context; 3041 struct dce_hwseq *hwseq = dc->hwseq; 3042 3043 if (hwseq->funcs.update_force_pstate) 3044 hwseq->funcs.update_force_pstate(dc, context); 3045 } 3046 3047 void hwss_hubbub_apply_dedcn21_147_wa(union block_sequence_params *params) 3048 { 3049 struct hubbub *hubbub = params->hubbub_apply_dedcn21_147_wa_params.hubbub; 3050 3051 hubbub->funcs->apply_DEDCN21_147_wa(hubbub); 3052 } 3053 3054 void hwss_hubbub_allow_self_refresh_control(union block_sequence_params *params) 3055 { 3056 struct hubbub *hubbub = params->hubbub_allow_self_refresh_control_params.hubbub; 3057 bool allow = params->hubbub_allow_self_refresh_control_params.allow; 3058 3059 hubbub->funcs->allow_self_refresh_control(hubbub, allow); 3060 3061 if (!allow && params->hubbub_allow_self_refresh_control_params.disallow_self_refresh_applied) 3062 *params->hubbub_allow_self_refresh_control_params.disallow_self_refresh_applied = true; 3063 } 3064 3065 void hwss_tg_get_frame_count(union block_sequence_params *params) 3066 { 3067 struct timing_generator *tg = params->tg_get_frame_count_params.tg; 3068 unsigned int *frame_count = params->tg_get_frame_count_params.frame_count; 3069 3070 *frame_count = tg->funcs->get_frame_count(tg); 3071 } 3072 3073 void hwss_mpc_set_dwb_mux(union block_sequence_params *params) 3074 { 3075 struct mpc *mpc = params->mpc_set_dwb_mux_params.mpc; 3076 int dwb_id = params->mpc_set_dwb_mux_params.dwb_id; 3077 int mpcc_id = params->mpc_set_dwb_mux_params.mpcc_id; 3078 3079 if (mpc->funcs->set_dwb_mux) 3080 mpc->funcs->set_dwb_mux(mpc, dwb_id, mpcc_id); 3081 } 3082 3083 void hwss_mpc_disable_dwb_mux(union block_sequence_params *params) 3084 { 3085 struct mpc *mpc = params->mpc_disable_dwb_mux_params.mpc; 3086 unsigned int dwb_id = params->mpc_disable_dwb_mux_params.dwb_id; 3087 3088 if (mpc->funcs->disable_dwb_mux) 3089 mpc->funcs->disable_dwb_mux(mpc, dwb_id); 3090 } 3091 3092 void hwss_mcif_wb_config_buf(union block_sequence_params *params) 3093 { 3094 struct mcif_wb *mcif_wb = params->mcif_wb_config_buf_params.mcif_wb; 3095 struct mcif_buf_params *mcif_buf_params = params->mcif_wb_config_buf_params.mcif_buf_params; 3096 unsigned int dest_height = params->mcif_wb_config_buf_params.dest_height; 3097 3098 if (mcif_wb->funcs->config_mcif_buf) 3099 mcif_wb->funcs->config_mcif_buf(mcif_wb, mcif_buf_params, dest_height); 3100 } 3101 3102 void hwss_mcif_wb_config_arb(union block_sequence_params *params) 3103 { 3104 struct mcif_wb *mcif_wb = params->mcif_wb_config_arb_params.mcif_wb; 3105 struct mcif_arb_params *mcif_arb_params = params->mcif_wb_config_arb_params.mcif_arb_params; 3106 3107 if (mcif_wb->funcs->config_mcif_arb) 3108 mcif_wb->funcs->config_mcif_arb(mcif_wb, mcif_arb_params); 3109 } 3110 3111 void hwss_mcif_wb_enable(union block_sequence_params *params) 3112 { 3113 struct mcif_wb *mcif_wb = params->mcif_wb_enable_params.mcif_wb; 3114 3115 if (mcif_wb->funcs->enable_mcif) 3116 mcif_wb->funcs->enable_mcif(mcif_wb); 3117 } 3118 3119 void hwss_mcif_wb_disable(union block_sequence_params *params) 3120 { 3121 struct mcif_wb *mcif_wb = params->mcif_wb_disable_params.mcif_wb; 3122 3123 if (mcif_wb->funcs->disable_mcif) 3124 mcif_wb->funcs->disable_mcif(mcif_wb); 3125 } 3126 3127 void hwss_dwbc_enable(union block_sequence_params *params) 3128 { 3129 struct dwbc *dwb = params->dwbc_enable_params.dwb; 3130 struct dc_dwb_params *dwb_params = params->dwbc_enable_params.dwb_params; 3131 3132 if (dwb->funcs->enable) 3133 dwb->funcs->enable(dwb, dwb_params); 3134 } 3135 3136 void hwss_dwbc_disable(union block_sequence_params *params) 3137 { 3138 struct dwbc *dwb = params->dwbc_disable_params.dwb; 3139 3140 if (dwb->funcs->disable) 3141 dwb->funcs->disable(dwb); 3142 } 3143 3144 void hwss_dwbc_update(union block_sequence_params *params) 3145 { 3146 struct dwbc *dwb = params->dwbc_update_params.dwb; 3147 struct dc_dwb_params *dwb_params = params->dwbc_update_params.dwb_params; 3148 3149 if (dwb->funcs->update) 3150 dwb->funcs->update(dwb, dwb_params); 3151 } 3152 3153 void hwss_hubp_update_mall_sel(union block_sequence_params *params) 3154 { 3155 struct hubp *hubp = params->hubp_update_mall_sel_params.hubp; 3156 uint32_t mall_sel = params->hubp_update_mall_sel_params.mall_sel; 3157 bool cache_cursor = params->hubp_update_mall_sel_params.cache_cursor; 3158 3159 if (hubp && hubp->funcs->hubp_update_mall_sel) 3160 hubp->funcs->hubp_update_mall_sel(hubp, mall_sel, cache_cursor); 3161 } 3162 3163 void hwss_hubp_prepare_subvp_buffering(union block_sequence_params *params) 3164 { 3165 struct hubp *hubp = params->hubp_prepare_subvp_buffering_params.hubp; 3166 bool enable = params->hubp_prepare_subvp_buffering_params.enable; 3167 3168 if (hubp && hubp->funcs->hubp_prepare_subvp_buffering) 3169 hubp->funcs->hubp_prepare_subvp_buffering(hubp, enable); 3170 } 3171 3172 void hwss_hubp_set_blank_en(union block_sequence_params *params) 3173 { 3174 struct hubp *hubp = params->hubp_set_blank_en_params.hubp; 3175 bool enable = params->hubp_set_blank_en_params.enable; 3176 3177 if (hubp && hubp->funcs->set_hubp_blank_en) 3178 hubp->funcs->set_hubp_blank_en(hubp, enable); 3179 } 3180 3181 void hwss_hubp_disable_control(union block_sequence_params *params) 3182 { 3183 struct hubp *hubp = params->hubp_disable_control_params.hubp; 3184 bool disable = params->hubp_disable_control_params.disable; 3185 3186 if (hubp && hubp->funcs->hubp_disable_control) 3187 hubp->funcs->hubp_disable_control(hubp, disable); 3188 } 3189 3190 void hwss_hubbub_soft_reset(union block_sequence_params *params) 3191 { 3192 struct hubbub *hubbub = params->hubbub_soft_reset_params.hubbub; 3193 bool reset = params->hubbub_soft_reset_params.reset; 3194 3195 if (hubbub) 3196 params->hubbub_soft_reset_params.hubbub_soft_reset(hubbub, reset); 3197 } 3198 3199 void hwss_hubp_clk_cntl(union block_sequence_params *params) 3200 { 3201 struct hubp *hubp = params->hubp_clk_cntl_params.hubp; 3202 bool enable = params->hubp_clk_cntl_params.enable; 3203 3204 if (hubp && hubp->funcs->hubp_clk_cntl) { 3205 hubp->funcs->hubp_clk_cntl(hubp, enable); 3206 hubp->power_gated = !enable; 3207 } 3208 } 3209 3210 void hwss_hubp_init(union block_sequence_params *params) 3211 { 3212 struct hubp *hubp = params->hubp_init_params.hubp; 3213 3214 if (hubp && hubp->funcs->hubp_init) 3215 hubp->funcs->hubp_init(hubp); 3216 } 3217 3218 void hwss_hubp_set_vm_system_aperture_settings(union block_sequence_params *params) 3219 { 3220 struct hubp *hubp = params->hubp_set_vm_system_aperture_settings_params.hubp; 3221 struct vm_system_aperture_param apt; 3222 3223 apt.sys_default = params->hubp_set_vm_system_aperture_settings_params.sys_default; 3224 apt.sys_high = params->hubp_set_vm_system_aperture_settings_params.sys_high; 3225 apt.sys_low = params->hubp_set_vm_system_aperture_settings_params.sys_low; 3226 3227 if (hubp && hubp->funcs->hubp_set_vm_system_aperture_settings) 3228 hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt); 3229 } 3230 3231 void hwss_hubp_set_flip_int(union block_sequence_params *params) 3232 { 3233 struct hubp *hubp = params->hubp_set_flip_int_params.hubp; 3234 3235 if (hubp && hubp->funcs->hubp_set_flip_int) 3236 hubp->funcs->hubp_set_flip_int(hubp); 3237 } 3238 3239 void hwss_dpp_dppclk_control(union block_sequence_params *params) 3240 { 3241 struct dpp *dpp = params->dpp_dppclk_control_params.dpp; 3242 bool dppclk_div = params->dpp_dppclk_control_params.dppclk_div; 3243 bool enable = params->dpp_dppclk_control_params.enable; 3244 3245 if (dpp && dpp->funcs->dpp_dppclk_control) 3246 dpp->funcs->dpp_dppclk_control(dpp, dppclk_div, enable); 3247 } 3248 3249 void hwss_disable_phantom_crtc(union block_sequence_params *params) 3250 { 3251 struct timing_generator *tg = params->disable_phantom_crtc_params.tg; 3252 3253 if (tg && tg->funcs->disable_phantom_crtc) 3254 tg->funcs->disable_phantom_crtc(tg); 3255 } 3256 3257 void hwss_dsc_pg_status(union block_sequence_params *params) 3258 { 3259 struct dce_hwseq *hws = params->dsc_pg_status_params.hws; 3260 int dsc_inst = params->dsc_pg_status_params.dsc_inst; 3261 3262 if (hws && hws->funcs.dsc_pg_status) 3263 params->dsc_pg_status_params.is_ungated = hws->funcs.dsc_pg_status(hws, dsc_inst); 3264 } 3265 3266 void hwss_dsc_wait_disconnect_pending_clear(union block_sequence_params *params) 3267 { 3268 struct display_stream_compressor *dsc = params->dsc_wait_disconnect_pending_clear_params.dsc; 3269 3270 if (!params->dsc_wait_disconnect_pending_clear_params.is_ungated) 3271 return; 3272 if (*params->dsc_wait_disconnect_pending_clear_params.is_ungated == false) 3273 return; 3274 3275 if (dsc && dsc->funcs->dsc_wait_disconnect_pending_clear) 3276 dsc->funcs->dsc_wait_disconnect_pending_clear(dsc); 3277 } 3278 3279 void hwss_dsc_disable(union block_sequence_params *params) 3280 { 3281 struct display_stream_compressor *dsc = params->dsc_disable_params.dsc; 3282 3283 if (!params->dsc_disable_params.is_ungated) 3284 return; 3285 if (*params->dsc_disable_params.is_ungated == false) 3286 return; 3287 3288 if (dsc && dsc->funcs->dsc_disable) 3289 dsc->funcs->dsc_disable(dsc); 3290 } 3291 3292 void hwss_dccg_set_ref_dscclk(union block_sequence_params *params) 3293 { 3294 struct dccg *dccg = params->dccg_set_ref_dscclk_params.dccg; 3295 int dsc_inst = params->dccg_set_ref_dscclk_params.dsc_inst; 3296 3297 if (!params->dccg_set_ref_dscclk_params.is_ungated) 3298 return; 3299 if (*params->dccg_set_ref_dscclk_params.is_ungated == false) 3300 return; 3301 3302 if (dccg && dccg->funcs->set_ref_dscclk) 3303 dccg->funcs->set_ref_dscclk(dccg, dsc_inst); 3304 } 3305 3306 void hwss_dpp_pg_control(union block_sequence_params *params) 3307 { 3308 struct dce_hwseq *hws = params->dpp_pg_control_params.hws; 3309 unsigned int dpp_inst = params->dpp_pg_control_params.dpp_inst; 3310 bool power_on = params->dpp_pg_control_params.power_on; 3311 3312 if (hws->funcs.dpp_pg_control) 3313 hws->funcs.dpp_pg_control(hws, dpp_inst, power_on); 3314 } 3315 3316 void hwss_hubp_pg_control(union block_sequence_params *params) 3317 { 3318 struct dce_hwseq *hws = params->hubp_pg_control_params.hws; 3319 unsigned int hubp_inst = params->hubp_pg_control_params.hubp_inst; 3320 bool power_on = params->hubp_pg_control_params.power_on; 3321 3322 if (hws->funcs.hubp_pg_control) 3323 hws->funcs.hubp_pg_control(hws, hubp_inst, power_on); 3324 } 3325 3326 void hwss_hubp_reset(union block_sequence_params *params) 3327 { 3328 struct hubp *hubp = params->hubp_reset_params.hubp; 3329 3330 if (hubp && hubp->funcs->hubp_reset) 3331 hubp->funcs->hubp_reset(hubp); 3332 } 3333 3334 void hwss_dpp_reset(union block_sequence_params *params) 3335 { 3336 struct dpp *dpp = params->dpp_reset_params.dpp; 3337 3338 if (dpp && dpp->funcs->dpp_reset) 3339 dpp->funcs->dpp_reset(dpp); 3340 } 3341 3342 void hwss_dpp_root_clock_control(union block_sequence_params *params) 3343 { 3344 struct dce_hwseq *hws = params->dpp_root_clock_control_params.hws; 3345 unsigned int dpp_inst = params->dpp_root_clock_control_params.dpp_inst; 3346 bool clock_on = params->dpp_root_clock_control_params.clock_on; 3347 3348 if (hws->funcs.dpp_root_clock_control) 3349 hws->funcs.dpp_root_clock_control(hws, dpp_inst, clock_on); 3350 } 3351 3352 void hwss_dc_ip_request_cntl(union block_sequence_params *params) 3353 { 3354 struct dc *dc = params->dc_ip_request_cntl_params.dc; 3355 bool enable = params->dc_ip_request_cntl_params.enable; 3356 struct dce_hwseq *hws = dc->hwseq; 3357 3358 if (hws->funcs.dc_ip_request_cntl) 3359 hws->funcs.dc_ip_request_cntl(dc, enable); 3360 } 3361 3362 void hwss_dccg_update_dpp_dto(union block_sequence_params *params) 3363 { 3364 struct dccg *dccg = params->dccg_update_dpp_dto_params.dccg; 3365 int dpp_inst = params->dccg_update_dpp_dto_params.dpp_inst; 3366 int dppclk_khz = params->dccg_update_dpp_dto_params.dppclk_khz; 3367 3368 if (dccg && dccg->funcs->update_dpp_dto) 3369 dccg->funcs->update_dpp_dto(dccg, dpp_inst, dppclk_khz); 3370 } 3371 3372 void hwss_hubp_vtg_sel(union block_sequence_params *params) 3373 { 3374 struct hubp *hubp = params->hubp_vtg_sel_params.hubp; 3375 uint32_t otg_inst = params->hubp_vtg_sel_params.otg_inst; 3376 3377 if (hubp && hubp->funcs->hubp_vtg_sel) 3378 hubp->funcs->hubp_vtg_sel(hubp, otg_inst); 3379 } 3380 3381 void hwss_hubp_setup2(union block_sequence_params *params) 3382 { 3383 struct hubp *hubp = params->hubp_setup2_params.hubp; 3384 struct dml2_dchub_per_pipe_register_set *hubp_regs = params->hubp_setup2_params.hubp_regs; 3385 union dml2_global_sync_programming *global_sync = params->hubp_setup2_params.global_sync; 3386 struct dc_crtc_timing *timing = params->hubp_setup2_params.timing; 3387 3388 if (hubp && hubp->funcs->hubp_setup2) 3389 hubp->funcs->hubp_setup2(hubp, hubp_regs, global_sync, timing); 3390 } 3391 3392 void hwss_hubp_setup(union block_sequence_params *params) 3393 { 3394 struct hubp *hubp = params->hubp_setup_params.hubp; 3395 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = params->hubp_setup_params.dlg_regs; 3396 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = params->hubp_setup_params.ttu_regs; 3397 struct _vcs_dpi_display_rq_regs_st *rq_regs = params->hubp_setup_params.rq_regs; 3398 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest = params->hubp_setup_params.pipe_dest; 3399 3400 if (hubp && hubp->funcs->hubp_setup) 3401 hubp->funcs->hubp_setup(hubp, dlg_regs, ttu_regs, rq_regs, pipe_dest); 3402 } 3403 3404 void hwss_hubp_set_unbounded_requesting(union block_sequence_params *params) 3405 { 3406 struct hubp *hubp = params->hubp_set_unbounded_requesting_params.hubp; 3407 bool unbounded_req = params->hubp_set_unbounded_requesting_params.unbounded_req; 3408 3409 if (hubp && hubp->funcs->set_unbounded_requesting) 3410 hubp->funcs->set_unbounded_requesting(hubp, unbounded_req); 3411 } 3412 3413 void hwss_hubp_setup_interdependent2(union block_sequence_params *params) 3414 { 3415 struct hubp *hubp = params->hubp_setup_interdependent2_params.hubp; 3416 struct dml2_dchub_per_pipe_register_set *hubp_regs = params->hubp_setup_interdependent2_params.hubp_regs; 3417 3418 if (hubp && hubp->funcs->hubp_setup_interdependent2) 3419 hubp->funcs->hubp_setup_interdependent2(hubp, hubp_regs); 3420 } 3421 3422 void hwss_hubp_setup_interdependent(union block_sequence_params *params) 3423 { 3424 struct hubp *hubp = params->hubp_setup_interdependent_params.hubp; 3425 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = params->hubp_setup_interdependent_params.dlg_regs; 3426 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = params->hubp_setup_interdependent_params.ttu_regs; 3427 3428 if (hubp && hubp->funcs->hubp_setup_interdependent) 3429 hubp->funcs->hubp_setup_interdependent(hubp, dlg_regs, ttu_regs); 3430 } 3431 3432 void hwss_dpp_set_cursor_matrix(union block_sequence_params *params) 3433 { 3434 struct dpp *dpp = params->dpp_set_cursor_matrix_params.dpp; 3435 enum dc_color_space color_space = params->dpp_set_cursor_matrix_params.color_space; 3436 struct dc_csc_transform *cursor_csc_color_matrix = params->dpp_set_cursor_matrix_params.cursor_csc_color_matrix; 3437 3438 if (dpp && dpp->funcs->set_cursor_matrix) 3439 dpp->funcs->set_cursor_matrix(dpp, color_space, *cursor_csc_color_matrix); 3440 } 3441 3442 void hwss_mpc_update_mpcc(union block_sequence_params *params) 3443 { 3444 struct dc *dc = params->mpc_update_mpcc_params.dc; 3445 struct pipe_ctx *pipe_ctx = params->mpc_update_mpcc_params.pipe_ctx; 3446 struct dce_hwseq *hws = dc->hwseq; 3447 3448 if (hws->funcs.update_mpcc) 3449 hws->funcs.update_mpcc(dc, pipe_ctx); 3450 } 3451 3452 void hwss_mpc_update_blending(union block_sequence_params *params) 3453 { 3454 struct mpc *mpc = params->mpc_update_blending_params.mpc; 3455 struct mpcc_blnd_cfg *blnd_cfg = ¶ms->mpc_update_blending_params.blnd_cfg; 3456 int mpcc_id = params->mpc_update_blending_params.mpcc_id; 3457 3458 if (mpc && mpc->funcs->update_blending) 3459 mpc->funcs->update_blending(mpc, blnd_cfg, mpcc_id); 3460 } 3461 3462 void hwss_mpc_assert_idle_mpcc(union block_sequence_params *params) 3463 { 3464 struct mpc *mpc = params->mpc_assert_idle_mpcc_params.mpc; 3465 int mpcc_id = params->mpc_assert_idle_mpcc_params.mpcc_id; 3466 3467 if (mpc && mpc->funcs->wait_for_idle) 3468 mpc->funcs->wait_for_idle(mpc, mpcc_id); 3469 } 3470 3471 void hwss_mpc_insert_plane(union block_sequence_params *params) 3472 { 3473 struct mpc *mpc = params->mpc_insert_plane_params.mpc; 3474 struct mpc_tree *tree = params->mpc_insert_plane_params.mpc_tree_params; 3475 struct mpcc_blnd_cfg *blnd_cfg = ¶ms->mpc_insert_plane_params.blnd_cfg; 3476 struct mpcc_sm_cfg *sm_cfg = params->mpc_insert_plane_params.sm_cfg; 3477 struct mpcc *insert_above_mpcc = params->mpc_insert_plane_params.insert_above_mpcc; 3478 int mpcc_id = params->mpc_insert_plane_params.mpcc_id; 3479 int dpp_id = params->mpc_insert_plane_params.dpp_id; 3480 3481 if (mpc && mpc->funcs->insert_plane) 3482 mpc->funcs->insert_plane(mpc, tree, blnd_cfg, sm_cfg, insert_above_mpcc, 3483 dpp_id, mpcc_id); 3484 } 3485 3486 void hwss_dpp_set_scaler(union block_sequence_params *params) 3487 { 3488 struct dpp *dpp = params->dpp_set_scaler_params.dpp; 3489 const struct scaler_data *scl_data = params->dpp_set_scaler_params.scl_data; 3490 3491 if (dpp && dpp->funcs->dpp_set_scaler) 3492 dpp->funcs->dpp_set_scaler(dpp, scl_data); 3493 } 3494 3495 void hwss_hubp_mem_program_viewport(union block_sequence_params *params) 3496 { 3497 struct hubp *hubp = params->hubp_mem_program_viewport_params.hubp; 3498 const struct rect *viewport = params->hubp_mem_program_viewport_params.viewport; 3499 const struct rect *viewport_c = params->hubp_mem_program_viewport_params.viewport_c; 3500 3501 if (hubp && hubp->funcs->mem_program_viewport) 3502 hubp->funcs->mem_program_viewport(hubp, viewport, viewport_c); 3503 } 3504 3505 void hwss_abort_cursor_offload_update(union block_sequence_params *params) 3506 { 3507 struct dc *dc = params->abort_cursor_offload_update_params.dc; 3508 struct pipe_ctx *pipe_ctx = params->abort_cursor_offload_update_params.pipe_ctx; 3509 3510 if (dc && dc->hwss.abort_cursor_offload_update) 3511 dc->hwss.abort_cursor_offload_update(dc, pipe_ctx); 3512 } 3513 3514 void hwss_cursor_lock(union block_sequence_params *params) 3515 { 3516 struct dc *dc = params->cursor_lock_params.dc; 3517 struct pipe_ctx *pipe_ctx = params->cursor_lock_params.pipe_ctx; 3518 bool lock = params->cursor_lock_params.lock; 3519 3520 if (dc && dc->hwss.cursor_lock) 3521 dc->hwss.cursor_lock(dc, pipe_ctx, lock); 3522 } 3523 3524 void hwss_begin_cursor_offload_update(union block_sequence_params *params) 3525 { 3526 struct dc *dc = params->begin_cursor_offload_update_params.dc; 3527 struct pipe_ctx *pipe_ctx = params->begin_cursor_offload_update_params.pipe_ctx; 3528 3529 if (dc && dc->hwss.begin_cursor_offload_update) 3530 dc->hwss.begin_cursor_offload_update(dc, pipe_ctx); 3531 } 3532 3533 void hwss_commit_cursor_offload_update(union block_sequence_params *params) 3534 { 3535 struct dc *dc = params->commit_cursor_offload_update_params.dc; 3536 struct pipe_ctx *pipe_ctx = params->commit_cursor_offload_update_params.pipe_ctx; 3537 3538 if (dc && dc->hwss.commit_cursor_offload_update) 3539 dc->hwss.commit_cursor_offload_update(dc, pipe_ctx); 3540 } 3541 3542 void hwss_update_cursor_offload_pipe(union block_sequence_params *params) 3543 { 3544 struct dc *dc = params->update_cursor_offload_pipe_params.dc; 3545 struct pipe_ctx *pipe_ctx = params->update_cursor_offload_pipe_params.pipe_ctx; 3546 3547 if (dc && dc->hwss.update_cursor_offload_pipe) 3548 dc->hwss.update_cursor_offload_pipe(dc, pipe_ctx); 3549 } 3550 3551 void hwss_send_cursor_info_to_dmu(union block_sequence_params *params) 3552 { 3553 struct pipe_ctx *pipe_ctx = params->send_cursor_info_to_dmu_params.pipe_ctx; 3554 int pipe_idx = params->send_cursor_info_to_dmu_params.pipe_idx; 3555 3556 dc_send_update_cursor_info_to_dmu(pipe_ctx, (uint8_t)pipe_idx); 3557 } 3558 3559 void hwss_set_cursor_attribute(union block_sequence_params *params) 3560 { 3561 struct dc *dc = params->set_cursor_attribute_params.dc; 3562 struct pipe_ctx *pipe_ctx = params->set_cursor_attribute_params.pipe_ctx; 3563 3564 if (dc && dc->hwss.set_cursor_attribute) 3565 dc->hwss.set_cursor_attribute(pipe_ctx); 3566 } 3567 3568 void hwss_hubp_set_cursor_attributes(union block_sequence_params *params) 3569 { 3570 struct hubp *hubp = params->hubp_set_cursor_attributes_params.hubp; 3571 const struct dc_cursor_attributes *attributes = params->hubp_set_cursor_attributes_params.attributes; 3572 3573 if (hubp && hubp->funcs->set_cursor_attributes) 3574 hubp->funcs->set_cursor_attributes(hubp, attributes); 3575 } 3576 3577 void hwss_dpp_set_cursor_attributes(union block_sequence_params *params) 3578 { 3579 struct dpp *dpp = params->dpp_set_cursor_attributes_params.dpp; 3580 struct dc_cursor_attributes *attributes = params->dpp_set_cursor_attributes_params.attributes; 3581 3582 if (dpp && dpp->funcs->set_cursor_attributes) 3583 dpp->funcs->set_cursor_attributes(dpp, attributes); 3584 } 3585 3586 void hwss_set_cursor_position(union block_sequence_params *params) 3587 { 3588 struct dc *dc = params->set_cursor_position_params.dc; 3589 struct pipe_ctx *pipe_ctx = params->set_cursor_position_params.pipe_ctx; 3590 3591 if (dc && dc->hwss.set_cursor_position) 3592 dc->hwss.set_cursor_position(pipe_ctx); 3593 } 3594 3595 void hwss_set_cursor_sdr_white_level(union block_sequence_params *params) 3596 { 3597 struct dc *dc = params->set_cursor_sdr_white_level_params.dc; 3598 struct pipe_ctx *pipe_ctx = params->set_cursor_sdr_white_level_params.pipe_ctx; 3599 3600 if (dc && dc->hwss.set_cursor_sdr_white_level) 3601 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); 3602 } 3603 3604 void hwss_program_gamut_remap(union block_sequence_params *params) 3605 { 3606 struct dc *dc = params->program_gamut_remap_params.pipe_ctx->stream->ctx->dc; 3607 3608 if (dc && dc->hwss.program_gamut_remap) 3609 dc->hwss.program_gamut_remap(params->program_gamut_remap_params.pipe_ctx); 3610 } 3611 3612 void hwss_program_output_csc(union block_sequence_params *params) 3613 { 3614 struct dc *dc = params->program_output_csc_params.dc; 3615 struct pipe_ctx *pipe_ctx = params->program_output_csc_params.pipe_ctx; 3616 enum dc_color_space colorspace = params->program_output_csc_params.colorspace; 3617 uint16_t *matrix = params->program_output_csc_params.matrix; 3618 int opp_id = params->program_output_csc_params.opp_id; 3619 3620 if (dc && dc->hwss.program_output_csc) 3621 dc->hwss.program_output_csc(dc, pipe_ctx, colorspace, matrix, opp_id); 3622 } 3623 3624 void hwss_hubp_set_blank(union block_sequence_params *params) 3625 { 3626 struct hubp *hubp = params->hubp_set_blank_params.hubp; 3627 bool blank = params->hubp_set_blank_params.blank; 3628 3629 if (hubp && hubp->funcs->set_blank) 3630 hubp->funcs->set_blank(hubp, blank); 3631 } 3632 3633 void hwss_phantom_hubp_post_enable(union block_sequence_params *params) 3634 { 3635 struct hubp *hubp = params->phantom_hubp_post_enable_params.hubp; 3636 3637 if (hubp && hubp->funcs->phantom_hubp_post_enable) 3638 hubp->funcs->phantom_hubp_post_enable(hubp); 3639 } 3640 3641 void hwss_stream_enc_update_hdmi_info_packets(union block_sequence_params *params) 3642 { 3643 if (params->stream_enc_update_hdmi_info_packets_params.pipe_ctx->stream_res.stream_enc && 3644 params->stream_enc_update_hdmi_info_packets_params.pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets) 3645 params->stream_enc_update_hdmi_info_packets_params.pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 3646 params->stream_enc_update_hdmi_info_packets_params.pipe_ctx->stream_res.stream_enc, 3647 ¶ms->stream_enc_update_hdmi_info_packets_params.pipe_ctx->stream_res.encoder_info_frame); 3648 } 3649 3650 void hwss_hpo_frl_stream_enc_update_hdmi_info_packets(union block_sequence_params *params) 3651 { 3652 if (params->hpo_frl_stream_enc_update_hdmi_info_packets_params.pipe_ctx->stream_res.hpo_frl_stream_enc && 3653 params->hpo_frl_stream_enc_update_hdmi_info_packets_params.pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->update_hdmi_info_packets) 3654 params->hpo_frl_stream_enc_update_hdmi_info_packets_params.pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->update_hdmi_info_packets( 3655 params->hpo_frl_stream_enc_update_hdmi_info_packets_params.pipe_ctx->stream_res.hpo_frl_stream_enc, 3656 ¶ms->hpo_frl_stream_enc_update_hdmi_info_packets_params.pipe_ctx->stream_res.encoder_info_frame); 3657 } 3658 3659 void hwss_hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num(union block_sequence_params *params) 3660 { 3661 if (params->hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.hpo_dp_stream_enc && 3662 params->hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets_sdp_line_num) 3663 params->hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets_sdp_line_num( 3664 params->hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.hpo_dp_stream_enc, 3665 ¶ms->hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.encoder_info_frame); 3666 } 3667 3668 void hwss_hpo_dp_stream_enc_update_dp_info_packets(union block_sequence_params *params) 3669 { 3670 if (params->hpo_dp_stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.hpo_dp_stream_enc && 3671 params->hpo_dp_stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets) 3672 params->hpo_dp_stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets( 3673 params->hpo_dp_stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.hpo_dp_stream_enc, 3674 ¶ms->hpo_dp_stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.encoder_info_frame); 3675 } 3676 3677 void hwss_stream_enc_update_dp_info_packets_sdp_line_num(union block_sequence_params *params) 3678 { 3679 if (params->stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.stream_enc && 3680 params->stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num) 3681 params->stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num( 3682 params->stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.stream_enc, 3683 ¶ms->stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.encoder_info_frame); 3684 } 3685 3686 void hwss_stream_enc_update_dp_info_packets(union block_sequence_params *params) 3687 { 3688 if (params->stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.stream_enc && 3689 params->stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets) 3690 params->stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 3691 params->stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.stream_enc, 3692 ¶ms->stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.encoder_info_frame); 3693 } 3694 3695 void hwss_stream_enc_dp_set_dsc_config(union block_sequence_params *params) 3696 { 3697 if (params->stream_enc_dp_set_dsc_config_params.stream_enc && 3698 params->stream_enc_dp_set_dsc_config_params.stream_enc->funcs->dp_set_dsc_config) { 3699 enum optc_dsc_mode dsc_mode = OPTC_DSC_DISABLED; 3700 uint32_t dsc_bytes_per_pixel = 0; 3701 uint32_t dsc_slice_width = 0; 3702 const struct dsc_optc_config *dsc_optc_cfg = params->stream_enc_dp_set_dsc_config_params.dsc_optc_cfg; 3703 3704 if (dsc_optc_cfg) { 3705 dsc_mode = dsc_optc_cfg->is_pixel_format_444 ? 3706 OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 3707 dsc_bytes_per_pixel = dsc_optc_cfg->bytes_per_pixel; 3708 dsc_slice_width = dsc_optc_cfg->slice_width; 3709 } 3710 3711 params->stream_enc_dp_set_dsc_config_params.stream_enc->funcs->dp_set_dsc_config( 3712 params->stream_enc_dp_set_dsc_config_params.stream_enc, 3713 dsc_mode, dsc_bytes_per_pixel, dsc_slice_width); 3714 } 3715 } 3716 3717 void hwss_hpo_dp_stream_enc_dp_set_dsc_pps_info_packet(union block_sequence_params *params) 3718 { 3719 if (params->hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.hpo_dp_stream_enc && 3720 params->hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet) 3721 params->hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 3722 params->hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.hpo_dp_stream_enc, 3723 params->hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.immediate_update, 3724 params->hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.dsc_packed_pps, 3725 params->hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.pps_sdp_stream); 3726 } 3727 3728 void hwss_stream_enc_dp_set_dsc_pps_info_packet(union block_sequence_params *params) 3729 { 3730 if (params->stream_enc_dp_set_dsc_pps_info_packet_params.stream_enc && 3731 params->stream_enc_dp_set_dsc_pps_info_packet_params.stream_enc->funcs->dp_set_dsc_pps_info_packet) 3732 params->stream_enc_dp_set_dsc_pps_info_packet_params.stream_enc->funcs->dp_set_dsc_pps_info_packet( 3733 params->stream_enc_dp_set_dsc_pps_info_packet_params.stream_enc, 3734 params->stream_enc_dp_set_dsc_pps_info_packet_params.immediate_update, 3735 params->stream_enc_dp_set_dsc_pps_info_packet_params.dsc_packed_pps, 3736 params->stream_enc_dp_set_dsc_pps_info_packet_params.pps_sdp_stream); 3737 } 3738 3739 void hwss_hpo_frl_stream_enc_set_dsc_config(union block_sequence_params *params) 3740 { 3741 if (params->hpo_frl_stream_enc_set_dsc_config_params.hpo_frl_stream_enc && 3742 params->hpo_frl_stream_enc_set_dsc_config_params.hpo_frl_stream_enc->funcs->hdmi_frl_set_dsc_config) 3743 params->hpo_frl_stream_enc_set_dsc_config_params.hpo_frl_stream_enc->funcs->hdmi_frl_set_dsc_config( 3744 params->hpo_frl_stream_enc_set_dsc_config_params.hpo_frl_stream_enc, 3745 (struct dc_crtc_timing *)params->hpo_frl_stream_enc_set_dsc_config_params.timing, 3746 params->hpo_frl_stream_enc_set_dsc_config_params.dsc_packed_pps); 3747 } 3748 3749 void hwss_set_dmdata_attributes(union block_sequence_params *params) 3750 { 3751 struct hubp *hubp = params->set_dmdata_attributes_params.hubp; 3752 3753 if (!hubp || !hubp->funcs->dmdata_set_attributes) 3754 return; 3755 3756 hubp->funcs->dmdata_set_attributes(hubp, 3757 ¶ms->set_dmdata_attributes_params.attr); 3758 } 3759 3760 void hwss_dp_trace_source_sequence(union block_sequence_params *params) 3761 { 3762 struct dc_link *link = params->dp_trace_source_sequence_params.link; 3763 enum dpcd_source_sequence source = params->dp_trace_source_sequence_params.source; 3764 3765 if (link && link->dc && link->dc->link_srv && link->dc->link_srv->dp_trace_source_sequence) 3766 link->dc->link_srv->dp_trace_source_sequence(link, source); 3767 } 3768 3769 void hwss_link_increase_mst_payload(union block_sequence_params *params) 3770 { 3771 struct pipe_ctx *pipe_ctx = params->link_increase_mst_payload_params.pipe_ctx; 3772 uint32_t mst_stream_bw = params->link_increase_mst_payload_params.mst_stream_bw; 3773 3774 if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link && 3775 pipe_ctx->stream->link->dc && pipe_ctx->stream->link->dc->link_srv && 3776 pipe_ctx->stream->link->dc->link_srv->increase_mst_payload) 3777 pipe_ctx->stream->link->dc->link_srv->increase_mst_payload(pipe_ctx, mst_stream_bw); 3778 } 3779 3780 void hwss_link_reduce_mst_payload(union block_sequence_params *params) 3781 { 3782 struct pipe_ctx *pipe_ctx = params->link_reduce_mst_payload_params.pipe_ctx; 3783 uint32_t mst_stream_bw = params->link_reduce_mst_payload_params.mst_stream_bw; 3784 3785 if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link && 3786 pipe_ctx->stream->link->dc && pipe_ctx->stream->link->dc->link_srv && 3787 pipe_ctx->stream->link->dc->link_srv->reduce_mst_payload) 3788 pipe_ctx->stream->link->dc->link_srv->reduce_mst_payload(pipe_ctx, mst_stream_bw); 3789 } 3790 3791 void hwss_dp_set_test_pattern(union block_sequence_params *params) 3792 { 3793 struct dc_link *link = params->dp_set_test_pattern_params.link; 3794 enum dp_test_pattern test_pattern = params->dp_set_test_pattern_params.test_pattern; 3795 enum dp_test_pattern_color_space test_pattern_color_space = 3796 params->dp_set_test_pattern_params.test_pattern_color_space; 3797 const struct link_training_settings *p_link_settings = 3798 params->dp_set_test_pattern_params.p_link_settings; 3799 const unsigned char *p_custom_pattern = params->dp_set_test_pattern_params.p_custom_pattern; 3800 unsigned int cust_pattern_size = params->dp_set_test_pattern_params.cust_pattern_size; 3801 3802 if (link && link->dc && link->dc->link_srv && link->dc->link_srv->dp_set_test_pattern) 3803 link->dc->link_srv->dp_set_test_pattern(link, test_pattern, test_pattern_color_space, 3804 p_link_settings, p_custom_pattern, cust_pattern_size); 3805 } 3806 3807 void hwss_link_set_dpms_off(union block_sequence_params *params) 3808 { 3809 struct pipe_ctx *pipe_ctx = params->link_set_dpms_off_params.pipe_ctx; 3810 3811 if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link && 3812 pipe_ctx->stream->link->dc && pipe_ctx->stream->link->dc->link_srv && 3813 pipe_ctx->stream->link->dc->link_srv->set_dpms_off) 3814 pipe_ctx->stream->link->dc->link_srv->set_dpms_off(pipe_ctx); 3815 } 3816 3817 void hwss_disable_audio_stream(struct dc *dc, union block_sequence_params *params) 3818 { 3819 if (dc->hwss.disable_audio_stream) 3820 dc->hwss.disable_audio_stream( 3821 params->disable_audio_stream_params.pipe_ctx); 3822 } 3823 3824 void hwss_prepare_bandwidth(struct dc *dc, union block_sequence_params *params) 3825 { 3826 if (dc && dc->hwss.prepare_bandwidth) 3827 dc->hwss.prepare_bandwidth(dc, 3828 params->prepare_bandwidth_params.context); 3829 } 3830 3831 void hwss_link_set_dpms_on(union block_sequence_params *params) 3832 { 3833 struct dc_state *state = params->link_set_dpms_on_params.state; 3834 struct pipe_ctx *pipe_ctx = params->link_set_dpms_on_params.pipe_ctx; 3835 3836 if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link && 3837 pipe_ctx->stream->link->dc && pipe_ctx->stream->link->dc->link_srv && 3838 pipe_ctx->stream->link->dc->link_srv->set_dpms_on) 3839 pipe_ctx->stream->link->dc->link_srv->set_dpms_on(state, pipe_ctx); 3840 } 3841 3842 void hwss_dsc_set_config_simple(union block_sequence_params *params) 3843 { 3844 struct display_stream_compressor *dsc = params->dsc_set_config_simple_params.dsc; 3845 struct dsc_config *dsc_cfg = ¶ms->dsc_set_config_simple_params.dsc_cfg; 3846 struct dsc_optc_config *dsc_optc_cfg = ¶ms->dsc_set_config_simple_params.dsc_optc_cfg; 3847 3848 if (dsc && dsc->funcs && dsc->funcs->dsc_set_config) 3849 dsc->funcs->dsc_set_config(dsc, dsc_cfg, dsc_optc_cfg); 3850 } 3851 3852 void hwss_add_dccg_set_dto_dscclk(struct block_sequence_state *seq_state, 3853 struct dccg *dccg, int inst, int num_slices_h) 3854 { 3855 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 3856 seq_state->steps[*seq_state->num_steps].func = DCCG_SET_DTO_DSCCLK; 3857 seq_state->steps[*seq_state->num_steps].params.dccg_set_dto_dscclk_params.dccg = dccg; 3858 seq_state->steps[*seq_state->num_steps].params.dccg_set_dto_dscclk_params.inst = inst; 3859 seq_state->steps[*seq_state->num_steps].params.dccg_set_dto_dscclk_params.num_slices_h = num_slices_h; 3860 (*seq_state->num_steps)++; 3861 } 3862 } 3863 3864 void hwss_add_dsc_calculate_and_set_config(struct block_sequence_state *seq_state, 3865 struct pipe_ctx *pipe_ctx, bool enable, int opp_cnt) 3866 { 3867 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 3868 seq_state->steps[*seq_state->num_steps].func = DSC_CALCULATE_AND_SET_CONFIG; 3869 seq_state->steps[*seq_state->num_steps].params.dsc_calculate_and_set_config_params.pipe_ctx = pipe_ctx; 3870 seq_state->steps[*seq_state->num_steps].params.dsc_calculate_and_set_config_params.enable = enable; 3871 seq_state->steps[*seq_state->num_steps].params.dsc_calculate_and_set_config_params.opp_cnt = opp_cnt; 3872 (*seq_state->num_steps)++; 3873 } 3874 } 3875 3876 void hwss_add_mpc_remove_mpcc(struct block_sequence_state *seq_state, 3877 struct mpc *mpc, struct mpc_tree *mpc_tree_params, struct mpcc *mpcc_to_remove) 3878 { 3879 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 3880 seq_state->steps[*seq_state->num_steps].func = MPC_REMOVE_MPCC; 3881 seq_state->steps[*seq_state->num_steps].params.mpc_remove_mpcc_params.mpc = mpc; 3882 seq_state->steps[*seq_state->num_steps].params.mpc_remove_mpcc_params.mpc_tree_params = mpc_tree_params; 3883 seq_state->steps[*seq_state->num_steps].params.mpc_remove_mpcc_params.mpcc_to_remove = mpcc_to_remove; 3884 (*seq_state->num_steps)++; 3885 } 3886 } 3887 3888 void hwss_add_opp_set_mpcc_disconnect_pending(struct block_sequence_state *seq_state, 3889 struct output_pixel_processor *opp, int mpcc_inst, bool pending) 3890 { 3891 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 3892 seq_state->steps[*seq_state->num_steps].func = OPP_SET_MPCC_DISCONNECT_PENDING; 3893 seq_state->steps[*seq_state->num_steps].params.opp_set_mpcc_disconnect_pending_params.opp = opp; 3894 seq_state->steps[*seq_state->num_steps].params.opp_set_mpcc_disconnect_pending_params.mpcc_inst = mpcc_inst; 3895 seq_state->steps[*seq_state->num_steps].params.opp_set_mpcc_disconnect_pending_params.pending = pending; 3896 (*seq_state->num_steps)++; 3897 } 3898 } 3899 3900 void hwss_add_hubp_disconnect(struct block_sequence_state *seq_state, 3901 struct hubp *hubp) 3902 { 3903 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 3904 seq_state->steps[*seq_state->num_steps].func = HUBP_DISCONNECT; 3905 seq_state->steps[*seq_state->num_steps].params.hubp_disconnect_params.hubp = hubp; 3906 (*seq_state->num_steps)++; 3907 } 3908 } 3909 3910 void hwss_add_dsc_enable_with_opp(struct block_sequence_state *seq_state, 3911 struct pipe_ctx *pipe_ctx) 3912 { 3913 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 3914 seq_state->steps[*seq_state->num_steps].func = DSC_ENABLE_WITH_OPP; 3915 seq_state->steps[*seq_state->num_steps].params.dsc_enable_with_opp_params.pipe_ctx = pipe_ctx; 3916 (*seq_state->num_steps)++; 3917 } 3918 } 3919 3920 void hwss_add_tg_set_dsc_config(struct block_sequence_state *seq_state, 3921 struct timing_generator *tg, struct dsc_optc_config *dsc_optc_cfg, bool enable) 3922 { 3923 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 3924 seq_state->steps[*seq_state->num_steps].func = TG_SET_DSC_CONFIG; 3925 seq_state->steps[*seq_state->num_steps].params.tg_set_dsc_config_params.tg = tg; 3926 seq_state->steps[*seq_state->num_steps].params.tg_set_dsc_config_params.dsc_optc_cfg = dsc_optc_cfg; 3927 seq_state->steps[*seq_state->num_steps].params.tg_set_dsc_config_params.enable = enable; 3928 (*seq_state->num_steps)++; 3929 } 3930 } 3931 3932 void hwss_add_dsc_disconnect(struct block_sequence_state *seq_state, 3933 struct display_stream_compressor *dsc) 3934 { 3935 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 3936 seq_state->steps[*seq_state->num_steps].func = DSC_DISCONNECT; 3937 seq_state->steps[*seq_state->num_steps].params.dsc_disconnect_params.dsc = dsc; 3938 (*seq_state->num_steps)++; 3939 } 3940 } 3941 3942 void hwss_add_dc_set_optimized_required(struct block_sequence_state *seq_state, 3943 struct dc *dc, bool optimized_required) 3944 { 3945 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 3946 seq_state->steps[*seq_state->num_steps].func = DC_SET_OPTIMIZED_REQUIRED; 3947 seq_state->steps[*seq_state->num_steps].params.dc_set_optimized_required_params.dc = dc; 3948 seq_state->steps[*seq_state->num_steps].params.dc_set_optimized_required_params.optimized_required = optimized_required; 3949 (*seq_state->num_steps)++; 3950 } 3951 } 3952 3953 void hwss_add_abm_set_immediate_disable(struct block_sequence_state *seq_state, 3954 struct dc *dc, struct pipe_ctx *pipe_ctx) 3955 { 3956 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 3957 seq_state->steps[*seq_state->num_steps].func = ABM_SET_IMMEDIATE_DISABLE; 3958 seq_state->steps[*seq_state->num_steps].params.set_abm_immediate_disable_params.dc = dc; 3959 seq_state->steps[*seq_state->num_steps].params.set_abm_immediate_disable_params.pipe_ctx = pipe_ctx; 3960 (*seq_state->num_steps)++; 3961 } 3962 } 3963 3964 void hwss_add_opp_set_disp_pattern_generator(struct block_sequence_state *seq_state, 3965 struct output_pixel_processor *opp, 3966 enum controller_dp_test_pattern test_pattern, 3967 enum controller_dp_color_space color_space, 3968 enum dc_color_depth color_depth, 3969 struct tg_color solid_color, 3970 bool use_solid_color, 3971 int width, 3972 int height, 3973 int offset) 3974 { 3975 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 3976 seq_state->steps[*seq_state->num_steps].func = OPP_SET_DISP_PATTERN_GENERATOR; 3977 seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.opp = opp; 3978 seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.test_pattern = test_pattern; 3979 seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.color_space = color_space; 3980 seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.color_depth = color_depth; 3981 seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.solid_color = solid_color; 3982 seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.use_solid_color = use_solid_color; 3983 seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.width = width; 3984 seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.height = height; 3985 seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.offset = offset; 3986 (*seq_state->num_steps)++; 3987 } 3988 } 3989 3990 /* 3991 * Helper function to add MPC update blending to block sequence 3992 */ 3993 void hwss_add_mpc_update_blending(struct block_sequence_state *seq_state, 3994 struct mpc *mpc, 3995 struct mpcc_blnd_cfg blnd_cfg, 3996 int mpcc_id) 3997 { 3998 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 3999 seq_state->steps[*seq_state->num_steps].func = MPC_UPDATE_BLENDING; 4000 seq_state->steps[*seq_state->num_steps].params.mpc_update_blending_params.mpc = mpc; 4001 seq_state->steps[*seq_state->num_steps].params.mpc_update_blending_params.blnd_cfg = blnd_cfg; 4002 seq_state->steps[*seq_state->num_steps].params.mpc_update_blending_params.mpcc_id = mpcc_id; 4003 (*seq_state->num_steps)++; 4004 } 4005 } 4006 4007 /* 4008 * Helper function to add MPC insert plane to block sequence 4009 */ 4010 void hwss_add_mpc_insert_plane(struct block_sequence_state *seq_state, 4011 struct mpc *mpc, 4012 struct mpc_tree *mpc_tree_params, 4013 struct mpcc_blnd_cfg blnd_cfg, 4014 struct mpcc_sm_cfg *sm_cfg, 4015 struct mpcc *insert_above_mpcc, 4016 int dpp_id, 4017 int mpcc_id) 4018 { 4019 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4020 seq_state->steps[*seq_state->num_steps].func = MPC_INSERT_PLANE; 4021 seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.mpc = mpc; 4022 seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.mpc_tree_params = mpc_tree_params; 4023 seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.blnd_cfg = blnd_cfg; 4024 seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.sm_cfg = sm_cfg; 4025 seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.insert_above_mpcc = insert_above_mpcc; 4026 seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.dpp_id = dpp_id; 4027 seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.mpcc_id = mpcc_id; 4028 (*seq_state->num_steps)++; 4029 } 4030 } 4031 4032 /* 4033 * Helper function to add MPC assert idle MPCC to block sequence 4034 */ 4035 void hwss_add_mpc_assert_idle_mpcc(struct block_sequence_state *seq_state, 4036 struct mpc *mpc, 4037 int mpcc_id) 4038 { 4039 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4040 seq_state->steps[*seq_state->num_steps].func = MPC_ASSERT_IDLE_MPCC; 4041 seq_state->steps[*seq_state->num_steps].params.mpc_assert_idle_mpcc_params.mpc = mpc; 4042 seq_state->steps[*seq_state->num_steps].params.mpc_assert_idle_mpcc_params.mpcc_id = mpcc_id; 4043 (*seq_state->num_steps)++; 4044 } 4045 } 4046 4047 /* 4048 * Helper function to add HUBP set blank to block sequence 4049 */ 4050 void hwss_add_hubp_set_blank(struct block_sequence_state *seq_state, 4051 struct hubp *hubp, 4052 bool blank) 4053 { 4054 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4055 seq_state->steps[*seq_state->num_steps].func = HUBP_SET_BLANK; 4056 seq_state->steps[*seq_state->num_steps].params.hubp_set_blank_params.hubp = hubp; 4057 seq_state->steps[*seq_state->num_steps].params.hubp_set_blank_params.blank = blank; 4058 (*seq_state->num_steps)++; 4059 } 4060 } 4061 4062 void hwss_add_opp_program_bit_depth_reduction(struct block_sequence_state *seq_state, 4063 struct output_pixel_processor *opp, 4064 bool use_default_params, 4065 struct pipe_ctx *pipe_ctx) 4066 { 4067 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4068 seq_state->steps[*seq_state->num_steps].func = OPP_PROGRAM_BIT_DEPTH_REDUCTION; 4069 seq_state->steps[*seq_state->num_steps].params.opp_program_bit_depth_reduction_params.opp = opp; 4070 seq_state->steps[*seq_state->num_steps].params.opp_program_bit_depth_reduction_params.use_default_params = use_default_params; 4071 seq_state->steps[*seq_state->num_steps].params.opp_program_bit_depth_reduction_params.pipe_ctx = pipe_ctx; 4072 (*seq_state->num_steps)++; 4073 } 4074 } 4075 4076 void hwss_add_dpp_program_cm_hist(struct block_sequence_state *seq_state, 4077 struct dpp *dpp, 4078 struct cm_hist_control cm_hist_control, 4079 enum dc_color_space color_space) 4080 { 4081 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4082 seq_state->steps[*seq_state->num_steps].func = DPP_PROGRAM_CM_HIST; 4083 seq_state->steps[*seq_state->num_steps].params.control_cm_hist_params.dpp = dpp; 4084 seq_state->steps[*seq_state->num_steps].params.control_cm_hist_params.cm_hist_control = cm_hist_control; 4085 seq_state->steps[*seq_state->num_steps].params.control_cm_hist_params.color_space = color_space; 4086 (*seq_state->num_steps)++; 4087 } 4088 } 4089 4090 void hwss_add_dc_ip_request_cntl(struct block_sequence_state *seq_state, 4091 struct dc *dc, 4092 bool enable) 4093 { 4094 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4095 seq_state->steps[*seq_state->num_steps].func = DC_IP_REQUEST_CNTL; 4096 seq_state->steps[*seq_state->num_steps].params.dc_ip_request_cntl_params.dc = dc; 4097 seq_state->steps[*seq_state->num_steps].params.dc_ip_request_cntl_params.enable = enable; 4098 (*seq_state->num_steps)++; 4099 } 4100 } 4101 4102 void hwss_add_dwbc_update(struct block_sequence_state *seq_state, 4103 struct dwbc *dwb, 4104 struct dc_dwb_params *dwb_params) 4105 { 4106 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4107 seq_state->steps[*seq_state->num_steps].func = DWBC_UPDATE; 4108 seq_state->steps[*seq_state->num_steps].params.dwbc_update_params.dwb = dwb; 4109 seq_state->steps[*seq_state->num_steps].params.dwbc_update_params.dwb_params = dwb_params; 4110 (*seq_state->num_steps)++; 4111 } 4112 } 4113 4114 void hwss_add_mcif_wb_config_buf(struct block_sequence_state *seq_state, 4115 struct mcif_wb *mcif_wb, 4116 struct mcif_buf_params *mcif_buf_params, 4117 unsigned int dest_height) 4118 { 4119 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4120 seq_state->steps[*seq_state->num_steps].func = MCIF_WB_CONFIG_BUF; 4121 seq_state->steps[*seq_state->num_steps].params.mcif_wb_config_buf_params.mcif_wb = mcif_wb; 4122 seq_state->steps[*seq_state->num_steps].params.mcif_wb_config_buf_params.mcif_buf_params = mcif_buf_params; 4123 seq_state->steps[*seq_state->num_steps].params.mcif_wb_config_buf_params.dest_height = dest_height; 4124 (*seq_state->num_steps)++; 4125 } 4126 } 4127 4128 void hwss_add_mcif_wb_config_arb(struct block_sequence_state *seq_state, 4129 struct mcif_wb *mcif_wb, 4130 struct mcif_arb_params *mcif_arb_params) 4131 { 4132 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4133 seq_state->steps[*seq_state->num_steps].func = MCIF_WB_CONFIG_ARB; 4134 seq_state->steps[*seq_state->num_steps].params.mcif_wb_config_arb_params.mcif_wb = mcif_wb; 4135 seq_state->steps[*seq_state->num_steps].params.mcif_wb_config_arb_params.mcif_arb_params = mcif_arb_params; 4136 (*seq_state->num_steps)++; 4137 } 4138 } 4139 4140 void hwss_add_mcif_wb_enable(struct block_sequence_state *seq_state, 4141 struct mcif_wb *mcif_wb) 4142 { 4143 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4144 seq_state->steps[*seq_state->num_steps].func = MCIF_WB_ENABLE; 4145 seq_state->steps[*seq_state->num_steps].params.mcif_wb_enable_params.mcif_wb = mcif_wb; 4146 (*seq_state->num_steps)++; 4147 } 4148 } 4149 4150 void hwss_add_mcif_wb_disable(struct block_sequence_state *seq_state, 4151 struct mcif_wb *mcif_wb) 4152 { 4153 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4154 seq_state->steps[*seq_state->num_steps].func = MCIF_WB_DISABLE; 4155 seq_state->steps[*seq_state->num_steps].params.mcif_wb_disable_params.mcif_wb = mcif_wb; 4156 (*seq_state->num_steps)++; 4157 } 4158 } 4159 4160 void hwss_add_mpc_set_dwb_mux(struct block_sequence_state *seq_state, 4161 struct mpc *mpc, 4162 int dwb_id, 4163 int mpcc_id) 4164 { 4165 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4166 seq_state->steps[*seq_state->num_steps].func = MPC_SET_DWB_MUX; 4167 seq_state->steps[*seq_state->num_steps].params.mpc_set_dwb_mux_params.mpc = mpc; 4168 seq_state->steps[*seq_state->num_steps].params.mpc_set_dwb_mux_params.dwb_id = dwb_id; 4169 seq_state->steps[*seq_state->num_steps].params.mpc_set_dwb_mux_params.mpcc_id = mpcc_id; 4170 (*seq_state->num_steps)++; 4171 } 4172 } 4173 4174 void hwss_add_mpc_disable_dwb_mux(struct block_sequence_state *seq_state, 4175 struct mpc *mpc, 4176 unsigned int dwb_id) 4177 { 4178 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4179 seq_state->steps[*seq_state->num_steps].func = MPC_DISABLE_DWB_MUX; 4180 seq_state->steps[*seq_state->num_steps].params.mpc_disable_dwb_mux_params.mpc = mpc; 4181 seq_state->steps[*seq_state->num_steps].params.mpc_disable_dwb_mux_params.dwb_id = dwb_id; 4182 (*seq_state->num_steps)++; 4183 } 4184 } 4185 4186 void hwss_add_dwbc_enable(struct block_sequence_state *seq_state, 4187 struct dwbc *dwb, 4188 struct dc_dwb_params *dwb_params) 4189 { 4190 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4191 seq_state->steps[*seq_state->num_steps].func = DWBC_ENABLE; 4192 seq_state->steps[*seq_state->num_steps].params.dwbc_enable_params.dwb = dwb; 4193 seq_state->steps[*seq_state->num_steps].params.dwbc_enable_params.dwb_params = dwb_params; 4194 (*seq_state->num_steps)++; 4195 } 4196 } 4197 4198 void hwss_add_dwbc_disable(struct block_sequence_state *seq_state, 4199 struct dwbc *dwb) 4200 { 4201 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4202 seq_state->steps[*seq_state->num_steps].func = DWBC_DISABLE; 4203 seq_state->steps[*seq_state->num_steps].params.dwbc_disable_params.dwb = dwb; 4204 (*seq_state->num_steps)++; 4205 } 4206 } 4207 4208 void hwss_add_tg_set_gsl(struct block_sequence_state *seq_state, 4209 struct timing_generator *tg, 4210 struct gsl_params gsl) 4211 { 4212 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4213 seq_state->steps[*seq_state->num_steps].func = TG_SET_GSL; 4214 seq_state->steps[*seq_state->num_steps].params.tg_set_gsl_params.tg = tg; 4215 seq_state->steps[*seq_state->num_steps].params.tg_set_gsl_params.gsl = gsl; 4216 (*seq_state->num_steps)++; 4217 } 4218 } 4219 4220 void hwss_add_tg_set_gsl_source_select(struct block_sequence_state *seq_state, 4221 struct timing_generator *tg, 4222 int group_idx, 4223 uint32_t gsl_ready_signal) 4224 { 4225 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4226 seq_state->steps[*seq_state->num_steps].func = TG_SET_GSL_SOURCE_SELECT; 4227 seq_state->steps[*seq_state->num_steps].params.tg_set_gsl_source_select_params.tg = tg; 4228 seq_state->steps[*seq_state->num_steps].params.tg_set_gsl_source_select_params.group_idx = group_idx; 4229 seq_state->steps[*seq_state->num_steps].params.tg_set_gsl_source_select_params.gsl_ready_signal = gsl_ready_signal; 4230 (*seq_state->num_steps)++; 4231 } 4232 } 4233 4234 void hwss_add_hubp_update_mall_sel(struct block_sequence_state *seq_state, 4235 struct hubp *hubp, 4236 uint32_t mall_sel, 4237 bool cache_cursor) 4238 { 4239 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4240 seq_state->steps[*seq_state->num_steps].func = HUBP_UPDATE_MALL_SEL; 4241 seq_state->steps[*seq_state->num_steps].params.hubp_update_mall_sel_params.hubp = hubp; 4242 seq_state->steps[*seq_state->num_steps].params.hubp_update_mall_sel_params.mall_sel = mall_sel; 4243 seq_state->steps[*seq_state->num_steps].params.hubp_update_mall_sel_params.cache_cursor = cache_cursor; 4244 (*seq_state->num_steps)++; 4245 } 4246 } 4247 4248 void hwss_add_hubp_prepare_subvp_buffering(struct block_sequence_state *seq_state, 4249 struct hubp *hubp, 4250 bool enable) 4251 { 4252 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4253 seq_state->steps[*seq_state->num_steps].func = HUBP_PREPARE_SUBVP_BUFFERING; 4254 seq_state->steps[*seq_state->num_steps].params.hubp_prepare_subvp_buffering_params.hubp = hubp; 4255 seq_state->steps[*seq_state->num_steps].params.hubp_prepare_subvp_buffering_params.enable = enable; 4256 (*seq_state->num_steps)++; 4257 } 4258 } 4259 4260 void hwss_add_hubp_set_blank_en(struct block_sequence_state *seq_state, 4261 struct hubp *hubp, 4262 bool enable) 4263 { 4264 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4265 seq_state->steps[*seq_state->num_steps].func = HUBP_SET_BLANK_EN; 4266 seq_state->steps[*seq_state->num_steps].params.hubp_set_blank_en_params.hubp = hubp; 4267 seq_state->steps[*seq_state->num_steps].params.hubp_set_blank_en_params.enable = enable; 4268 (*seq_state->num_steps)++; 4269 } 4270 } 4271 4272 void hwss_add_hubp_disable_control(struct block_sequence_state *seq_state, 4273 struct hubp *hubp, 4274 bool disable) 4275 { 4276 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4277 seq_state->steps[*seq_state->num_steps].func = HUBP_DISABLE_CONTROL; 4278 seq_state->steps[*seq_state->num_steps].params.hubp_disable_control_params.hubp = hubp; 4279 seq_state->steps[*seq_state->num_steps].params.hubp_disable_control_params.disable = disable; 4280 (*seq_state->num_steps)++; 4281 } 4282 } 4283 4284 void hwss_add_hubbub_soft_reset(struct block_sequence_state *seq_state, 4285 struct hubbub *hubbub, 4286 void (*hubbub_soft_reset)(struct hubbub *hubbub, bool reset), 4287 bool reset) 4288 { 4289 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4290 seq_state->steps[*seq_state->num_steps].func = HUBBUB_SOFT_RESET; 4291 seq_state->steps[*seq_state->num_steps].params.hubbub_soft_reset_params.hubbub = hubbub; 4292 seq_state->steps[*seq_state->num_steps].params.hubbub_soft_reset_params.hubbub_soft_reset = hubbub_soft_reset; 4293 seq_state->steps[*seq_state->num_steps].params.hubbub_soft_reset_params.reset = reset; 4294 (*seq_state->num_steps)++; 4295 } 4296 } 4297 4298 void hwss_add_hubp_clk_cntl(struct block_sequence_state *seq_state, 4299 struct hubp *hubp, 4300 bool enable) 4301 { 4302 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4303 seq_state->steps[*seq_state->num_steps].func = HUBP_CLK_CNTL; 4304 seq_state->steps[*seq_state->num_steps].params.hubp_clk_cntl_params.hubp = hubp; 4305 seq_state->steps[*seq_state->num_steps].params.hubp_clk_cntl_params.enable = enable; 4306 (*seq_state->num_steps)++; 4307 } 4308 } 4309 4310 void hwss_add_dpp_dppclk_control(struct block_sequence_state *seq_state, 4311 struct dpp *dpp, 4312 bool dppclk_div, 4313 bool enable) 4314 { 4315 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4316 seq_state->steps[*seq_state->num_steps].func = DPP_DPPCLK_CONTROL; 4317 seq_state->steps[*seq_state->num_steps].params.dpp_dppclk_control_params.dpp = dpp; 4318 seq_state->steps[*seq_state->num_steps].params.dpp_dppclk_control_params.dppclk_div = dppclk_div; 4319 seq_state->steps[*seq_state->num_steps].params.dpp_dppclk_control_params.enable = enable; 4320 (*seq_state->num_steps)++; 4321 } 4322 } 4323 4324 void hwss_add_disable_phantom_crtc(struct block_sequence_state *seq_state, 4325 struct timing_generator *tg) 4326 { 4327 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4328 seq_state->steps[*seq_state->num_steps].func = DISABLE_PHANTOM_CRTC; 4329 seq_state->steps[*seq_state->num_steps].params.disable_phantom_crtc_params.tg = tg; 4330 (*seq_state->num_steps)++; 4331 } 4332 } 4333 4334 void hwss_add_dsc_pg_status(struct block_sequence_state *seq_state, 4335 struct dce_hwseq *hws, 4336 int dsc_inst, 4337 bool is_ungated) 4338 { 4339 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4340 seq_state->steps[*seq_state->num_steps].func = DSC_PG_STATUS; 4341 seq_state->steps[*seq_state->num_steps].params.dsc_pg_status_params.hws = hws; 4342 seq_state->steps[*seq_state->num_steps].params.dsc_pg_status_params.dsc_inst = dsc_inst; 4343 seq_state->steps[*seq_state->num_steps].params.dsc_pg_status_params.is_ungated = is_ungated; 4344 (*seq_state->num_steps)++; 4345 } 4346 } 4347 4348 void hwss_add_dsc_wait_disconnect_pending_clear(struct block_sequence_state *seq_state, 4349 struct display_stream_compressor *dsc, 4350 bool *is_ungated) 4351 { 4352 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4353 seq_state->steps[*seq_state->num_steps].func = DSC_WAIT_DISCONNECT_PENDING_CLEAR; 4354 seq_state->steps[*seq_state->num_steps].params.dsc_wait_disconnect_pending_clear_params.dsc = dsc; 4355 seq_state->steps[*seq_state->num_steps].params.dsc_wait_disconnect_pending_clear_params.is_ungated = is_ungated; 4356 (*seq_state->num_steps)++; 4357 } 4358 } 4359 4360 void hwss_add_dsc_disable(struct block_sequence_state *seq_state, 4361 struct display_stream_compressor *dsc, 4362 bool *is_ungated) 4363 { 4364 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4365 seq_state->steps[*seq_state->num_steps].func = DSC_DISABLE; 4366 seq_state->steps[*seq_state->num_steps].params.dsc_disable_params.dsc = dsc; 4367 seq_state->steps[*seq_state->num_steps].params.dsc_disable_params.is_ungated = is_ungated; 4368 (*seq_state->num_steps)++; 4369 } 4370 } 4371 4372 void hwss_add_dccg_set_ref_dscclk(struct block_sequence_state *seq_state, 4373 struct dccg *dccg, 4374 int dsc_inst, 4375 bool *is_ungated) 4376 { 4377 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4378 seq_state->steps[*seq_state->num_steps].func = DCCG_SET_REF_DSCCLK; 4379 seq_state->steps[*seq_state->num_steps].params.dccg_set_ref_dscclk_params.dccg = dccg; 4380 seq_state->steps[*seq_state->num_steps].params.dccg_set_ref_dscclk_params.dsc_inst = dsc_inst; 4381 seq_state->steps[*seq_state->num_steps].params.dccg_set_ref_dscclk_params.is_ungated = is_ungated; 4382 (*seq_state->num_steps)++; 4383 } 4384 } 4385 4386 void hwss_add_dpp_root_clock_control(struct block_sequence_state *seq_state, 4387 struct dce_hwseq *hws, 4388 unsigned int dpp_inst, 4389 bool clock_on) 4390 { 4391 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4392 seq_state->steps[*seq_state->num_steps].func = DPP_ROOT_CLOCK_CONTROL; 4393 seq_state->steps[*seq_state->num_steps].params.dpp_root_clock_control_params.hws = hws; 4394 seq_state->steps[*seq_state->num_steps].params.dpp_root_clock_control_params.dpp_inst = dpp_inst; 4395 seq_state->steps[*seq_state->num_steps].params.dpp_root_clock_control_params.clock_on = clock_on; 4396 (*seq_state->num_steps)++; 4397 } 4398 } 4399 4400 void hwss_add_dpp_pg_control(struct block_sequence_state *seq_state, 4401 struct dce_hwseq *hws, 4402 unsigned int dpp_inst, 4403 bool power_on) 4404 { 4405 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4406 seq_state->steps[*seq_state->num_steps].func = DPP_PG_CONTROL; 4407 seq_state->steps[*seq_state->num_steps].params.dpp_pg_control_params.hws = hws; 4408 seq_state->steps[*seq_state->num_steps].params.dpp_pg_control_params.dpp_inst = dpp_inst; 4409 seq_state->steps[*seq_state->num_steps].params.dpp_pg_control_params.power_on = power_on; 4410 (*seq_state->num_steps)++; 4411 } 4412 } 4413 4414 void hwss_add_hubp_pg_control(struct block_sequence_state *seq_state, 4415 struct dce_hwseq *hws, 4416 unsigned int hubp_inst, 4417 bool power_on) 4418 { 4419 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4420 seq_state->steps[*seq_state->num_steps].func = HUBP_PG_CONTROL; 4421 seq_state->steps[*seq_state->num_steps].params.hubp_pg_control_params.hws = hws; 4422 seq_state->steps[*seq_state->num_steps].params.hubp_pg_control_params.hubp_inst = hubp_inst; 4423 seq_state->steps[*seq_state->num_steps].params.hubp_pg_control_params.power_on = power_on; 4424 (*seq_state->num_steps)++; 4425 } 4426 } 4427 4428 void hwss_add_hubp_init(struct block_sequence_state *seq_state, 4429 struct hubp *hubp) 4430 { 4431 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4432 seq_state->steps[*seq_state->num_steps].func = HUBP_INIT; 4433 seq_state->steps[*seq_state->num_steps].params.hubp_init_params.hubp = hubp; 4434 (*seq_state->num_steps)++; 4435 } 4436 } 4437 4438 void hwss_add_hubp_reset(struct block_sequence_state *seq_state, 4439 struct hubp *hubp) 4440 { 4441 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4442 seq_state->steps[*seq_state->num_steps].func = HUBP_RESET; 4443 seq_state->steps[*seq_state->num_steps].params.hubp_reset_params.hubp = hubp; 4444 (*seq_state->num_steps)++; 4445 } 4446 } 4447 4448 void hwss_add_dpp_reset(struct block_sequence_state *seq_state, 4449 struct dpp *dpp) 4450 { 4451 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4452 seq_state->steps[*seq_state->num_steps].func = DPP_RESET; 4453 seq_state->steps[*seq_state->num_steps].params.dpp_reset_params.dpp = dpp; 4454 (*seq_state->num_steps)++; 4455 } 4456 } 4457 4458 void hwss_add_opp_pipe_clock_control(struct block_sequence_state *seq_state, 4459 struct output_pixel_processor *opp, 4460 bool enable) 4461 { 4462 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4463 seq_state->steps[*seq_state->num_steps].func = OPP_PIPE_CLOCK_CONTROL; 4464 seq_state->steps[*seq_state->num_steps].params.opp_pipe_clock_control_params.opp = opp; 4465 seq_state->steps[*seq_state->num_steps].params.opp_pipe_clock_control_params.enable = enable; 4466 (*seq_state->num_steps)++; 4467 } 4468 } 4469 4470 void hwss_add_hubp_set_vm_system_aperture_settings(struct block_sequence_state *seq_state, 4471 struct hubp *hubp, 4472 uint64_t sys_default, 4473 uint64_t sys_low, 4474 uint64_t sys_high) 4475 { 4476 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4477 seq_state->steps[*seq_state->num_steps].func = HUBP_SET_VM_SYSTEM_APERTURE_SETTINGS; 4478 seq_state->steps[*seq_state->num_steps].params.hubp_set_vm_system_aperture_settings_params.hubp = hubp; 4479 seq_state->steps[*seq_state->num_steps].params.hubp_set_vm_system_aperture_settings_params.sys_default.quad_part = sys_default; 4480 seq_state->steps[*seq_state->num_steps].params.hubp_set_vm_system_aperture_settings_params.sys_low.quad_part = sys_low; 4481 seq_state->steps[*seq_state->num_steps].params.hubp_set_vm_system_aperture_settings_params.sys_high.quad_part = sys_high; 4482 (*seq_state->num_steps)++; 4483 } 4484 } 4485 4486 void hwss_add_hubp_set_flip_int(struct block_sequence_state *seq_state, 4487 struct hubp *hubp) 4488 { 4489 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4490 seq_state->steps[*seq_state->num_steps].func = HUBP_SET_FLIP_INT; 4491 seq_state->steps[*seq_state->num_steps].params.hubp_set_flip_int_params.hubp = hubp; 4492 (*seq_state->num_steps)++; 4493 } 4494 } 4495 4496 void hwss_add_dccg_update_dpp_dto(struct block_sequence_state *seq_state, 4497 struct dccg *dccg, 4498 int dpp_inst, 4499 int dppclk_khz) 4500 { 4501 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4502 seq_state->steps[*seq_state->num_steps].func = DCCG_UPDATE_DPP_DTO; 4503 seq_state->steps[*seq_state->num_steps].params.dccg_update_dpp_dto_params.dccg = dccg; 4504 seq_state->steps[*seq_state->num_steps].params.dccg_update_dpp_dto_params.dpp_inst = dpp_inst; 4505 seq_state->steps[*seq_state->num_steps].params.dccg_update_dpp_dto_params.dppclk_khz = dppclk_khz; 4506 (*seq_state->num_steps)++; 4507 } 4508 } 4509 4510 void hwss_add_hubp_vtg_sel(struct block_sequence_state *seq_state, 4511 struct hubp *hubp, 4512 uint32_t otg_inst) 4513 { 4514 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4515 seq_state->steps[*seq_state->num_steps].func = HUBP_VTG_SEL; 4516 seq_state->steps[*seq_state->num_steps].params.hubp_vtg_sel_params.hubp = hubp; 4517 seq_state->steps[*seq_state->num_steps].params.hubp_vtg_sel_params.otg_inst = otg_inst; 4518 (*seq_state->num_steps)++; 4519 } 4520 } 4521 4522 void hwss_add_hubp_setup2(struct block_sequence_state *seq_state, 4523 struct hubp *hubp, 4524 struct dml2_dchub_per_pipe_register_set *hubp_regs, 4525 union dml2_global_sync_programming *global_sync, 4526 struct dc_crtc_timing *timing) 4527 { 4528 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4529 seq_state->steps[*seq_state->num_steps].func = HUBP_SETUP2; 4530 seq_state->steps[*seq_state->num_steps].params.hubp_setup2_params.hubp = hubp; 4531 seq_state->steps[*seq_state->num_steps].params.hubp_setup2_params.hubp_regs = hubp_regs; 4532 seq_state->steps[*seq_state->num_steps].params.hubp_setup2_params.global_sync = global_sync; 4533 seq_state->steps[*seq_state->num_steps].params.hubp_setup2_params.timing = timing; 4534 (*seq_state->num_steps)++; 4535 } 4536 } 4537 4538 void hwss_add_hubp_setup(struct block_sequence_state *seq_state, 4539 struct hubp *hubp, 4540 struct _vcs_dpi_display_dlg_regs_st *dlg_regs, 4541 struct _vcs_dpi_display_ttu_regs_st *ttu_regs, 4542 struct _vcs_dpi_display_rq_regs_st *rq_regs, 4543 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 4544 { 4545 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4546 seq_state->steps[*seq_state->num_steps].func = HUBP_SETUP; 4547 seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.hubp = hubp; 4548 seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.dlg_regs = dlg_regs; 4549 seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.ttu_regs = ttu_regs; 4550 seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.rq_regs = rq_regs; 4551 seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.pipe_dest = pipe_dest; 4552 (*seq_state->num_steps)++; 4553 } 4554 } 4555 4556 void hwss_add_hubp_set_unbounded_requesting(struct block_sequence_state *seq_state, 4557 struct hubp *hubp, 4558 bool unbounded_req) 4559 { 4560 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4561 seq_state->steps[*seq_state->num_steps].func = HUBP_SET_UNBOUNDED_REQUESTING; 4562 seq_state->steps[*seq_state->num_steps].params.hubp_set_unbounded_requesting_params.hubp = hubp; 4563 seq_state->steps[*seq_state->num_steps].params.hubp_set_unbounded_requesting_params.unbounded_req = unbounded_req; 4564 (*seq_state->num_steps)++; 4565 } 4566 } 4567 4568 void hwss_add_hubp_setup_interdependent2(struct block_sequence_state *seq_state, 4569 struct hubp *hubp, 4570 struct dml2_dchub_per_pipe_register_set *hubp_regs) 4571 { 4572 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4573 seq_state->steps[*seq_state->num_steps].func = HUBP_SETUP_INTERDEPENDENT2; 4574 seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent2_params.hubp = hubp; 4575 seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent2_params.hubp_regs = hubp_regs; 4576 (*seq_state->num_steps)++; 4577 } 4578 } 4579 4580 void hwss_add_hubp_setup_interdependent(struct block_sequence_state *seq_state, 4581 struct hubp *hubp, 4582 struct _vcs_dpi_display_dlg_regs_st *dlg_regs, 4583 struct _vcs_dpi_display_ttu_regs_st *ttu_regs) 4584 { 4585 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4586 seq_state->steps[*seq_state->num_steps].func = HUBP_SETUP_INTERDEPENDENT; 4587 seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent_params.hubp = hubp; 4588 seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent_params.dlg_regs = dlg_regs; 4589 seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent_params.ttu_regs = ttu_regs; 4590 (*seq_state->num_steps)++; 4591 } 4592 } 4593 4594 void hwss_add_hubp_program_surface_config(struct block_sequence_state *seq_state, 4595 struct hubp *hubp, 4596 enum surface_pixel_format format, 4597 struct dc_tiling_info *tiling_info, 4598 struct plane_size plane_size, 4599 enum dc_rotation_angle rotation, 4600 struct dc_plane_dcc_param *dcc, 4601 bool horizontal_mirror, 4602 int compat_level) 4603 { 4604 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4605 seq_state->steps[*seq_state->num_steps].func = HUBP_PROGRAM_SURFACE_CONFIG; 4606 seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.hubp = hubp; 4607 seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.format = format; 4608 seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.tiling_info = tiling_info; 4609 seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.plane_size = plane_size; 4610 seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.rotation = rotation; 4611 seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.dcc = dcc; 4612 seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.horizontal_mirror = horizontal_mirror; 4613 seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.compat_level = compat_level; 4614 (*seq_state->num_steps)++; 4615 } 4616 } 4617 4618 void hwss_add_dpp_setup_dpp(struct block_sequence_state *seq_state, 4619 struct pipe_ctx *pipe_ctx) 4620 { 4621 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4622 seq_state->steps[*seq_state->num_steps].func = DPP_SETUP_DPP; 4623 seq_state->steps[*seq_state->num_steps].params.setup_dpp_params.pipe_ctx = pipe_ctx; 4624 (*seq_state->num_steps)++; 4625 } 4626 } 4627 4628 void hwss_add_dpp_set_cursor_matrix(struct block_sequence_state *seq_state, 4629 struct dpp *dpp, 4630 enum dc_color_space color_space, 4631 struct dc_csc_transform *cursor_csc_color_matrix) 4632 { 4633 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4634 seq_state->steps[*seq_state->num_steps].func = DPP_SET_CURSOR_MATRIX; 4635 seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_matrix_params.dpp = dpp; 4636 seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_matrix_params.color_space = color_space; 4637 seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_matrix_params.cursor_csc_color_matrix = cursor_csc_color_matrix; 4638 (*seq_state->num_steps)++; 4639 } 4640 } 4641 4642 void hwss_add_dpp_set_scaler(struct block_sequence_state *seq_state, 4643 struct dpp *dpp, 4644 const struct scaler_data *scl_data) 4645 { 4646 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4647 seq_state->steps[*seq_state->num_steps].func = DPP_SET_SCALER; 4648 seq_state->steps[*seq_state->num_steps].params.dpp_set_scaler_params.dpp = dpp; 4649 seq_state->steps[*seq_state->num_steps].params.dpp_set_scaler_params.scl_data = scl_data; 4650 (*seq_state->num_steps)++; 4651 } 4652 } 4653 4654 void hwss_add_hubp_mem_program_viewport(struct block_sequence_state *seq_state, 4655 struct hubp *hubp, 4656 const struct rect *viewport, 4657 const struct rect *viewport_c) 4658 { 4659 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4660 seq_state->steps[*seq_state->num_steps].func = HUBP_MEM_PROGRAM_VIEWPORT; 4661 seq_state->steps[*seq_state->num_steps].params.hubp_mem_program_viewport_params.hubp = hubp; 4662 seq_state->steps[*seq_state->num_steps].params.hubp_mem_program_viewport_params.viewport = viewport; 4663 seq_state->steps[*seq_state->num_steps].params.hubp_mem_program_viewport_params.viewport_c = viewport_c; 4664 (*seq_state->num_steps)++; 4665 } 4666 } 4667 4668 void hwss_add_abort_cursor_offload_update(struct block_sequence_state *seq_state, 4669 struct dc *dc, 4670 struct pipe_ctx *pipe_ctx) 4671 { 4672 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4673 seq_state->steps[*seq_state->num_steps].func = ABORT_CURSOR_OFFLOAD_UPDATE; 4674 seq_state->steps[*seq_state->num_steps].params.abort_cursor_offload_update_params.dc = dc; 4675 seq_state->steps[*seq_state->num_steps].params.abort_cursor_offload_update_params.pipe_ctx = pipe_ctx; 4676 (*seq_state->num_steps)++; 4677 } 4678 } 4679 4680 void hwss_add_set_cursor_attribute(struct block_sequence_state *seq_state, 4681 struct dc *dc, 4682 struct pipe_ctx *pipe_ctx) 4683 { 4684 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4685 seq_state->steps[*seq_state->num_steps].func = SET_CURSOR_ATTRIBUTE; 4686 seq_state->steps[*seq_state->num_steps].params.set_cursor_attribute_params.dc = dc; 4687 seq_state->steps[*seq_state->num_steps].params.set_cursor_attribute_params.pipe_ctx = pipe_ctx; 4688 (*seq_state->num_steps)++; 4689 } 4690 } 4691 4692 void hwss_add_hubp_set_cursor_attributes(struct block_sequence_state *seq_state, 4693 struct hubp *hubp, 4694 const struct dc_cursor_attributes *attributes) 4695 { 4696 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4697 seq_state->steps[*seq_state->num_steps].func = HUBP_SET_CURSOR_ATTRIBUTES; 4698 seq_state->steps[*seq_state->num_steps].params.hubp_set_cursor_attributes_params.hubp = hubp; 4699 seq_state->steps[*seq_state->num_steps].params.hubp_set_cursor_attributes_params.attributes = attributes; 4700 (*seq_state->num_steps)++; 4701 } 4702 } 4703 4704 void hwss_add_dpp_set_cursor_attributes(struct block_sequence_state *seq_state, 4705 struct dpp *dpp, 4706 struct dc_cursor_attributes *attributes) 4707 { 4708 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4709 seq_state->steps[*seq_state->num_steps].func = DPP_SET_CURSOR_ATTRIBUTES; 4710 seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_attributes_params.dpp = dpp; 4711 seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_attributes_params.attributes = attributes; 4712 (*seq_state->num_steps)++; 4713 } 4714 } 4715 4716 void hwss_add_set_cursor_position(struct block_sequence_state *seq_state, 4717 struct dc *dc, 4718 struct pipe_ctx *pipe_ctx) 4719 { 4720 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4721 seq_state->steps[*seq_state->num_steps].func = SET_CURSOR_POSITION; 4722 seq_state->steps[*seq_state->num_steps].params.set_cursor_position_params.dc = dc; 4723 seq_state->steps[*seq_state->num_steps].params.set_cursor_position_params.pipe_ctx = pipe_ctx; 4724 (*seq_state->num_steps)++; 4725 } 4726 } 4727 4728 void hwss_add_set_cursor_sdr_white_level(struct block_sequence_state *seq_state, 4729 struct dc *dc, 4730 struct pipe_ctx *pipe_ctx) 4731 { 4732 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4733 seq_state->steps[*seq_state->num_steps].func = SET_CURSOR_SDR_WHITE_LEVEL; 4734 seq_state->steps[*seq_state->num_steps].params.set_cursor_sdr_white_level_params.dc = dc; 4735 seq_state->steps[*seq_state->num_steps].params.set_cursor_sdr_white_level_params.pipe_ctx = pipe_ctx; 4736 (*seq_state->num_steps)++; 4737 } 4738 } 4739 4740 void hwss_add_program_output_csc(struct block_sequence_state *seq_state, 4741 struct dc *dc, 4742 struct pipe_ctx *pipe_ctx, 4743 enum dc_color_space colorspace, 4744 uint16_t *matrix, 4745 int opp_id) 4746 { 4747 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4748 seq_state->steps[*seq_state->num_steps].func = PROGRAM_OUTPUT_CSC; 4749 seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.dc = dc; 4750 seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.pipe_ctx = pipe_ctx; 4751 seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.colorspace = colorspace; 4752 seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.matrix = matrix; 4753 seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.opp_id = opp_id; 4754 (*seq_state->num_steps)++; 4755 } 4756 } 4757 4758 void hwss_add_phantom_hubp_post_enable(struct block_sequence_state *seq_state, 4759 struct hubp *hubp) 4760 { 4761 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4762 seq_state->steps[*seq_state->num_steps].func = PHANTOM_HUBP_POST_ENABLE; 4763 seq_state->steps[*seq_state->num_steps].params.phantom_hubp_post_enable_params.hubp = hubp; 4764 (*seq_state->num_steps)++; 4765 } 4766 } 4767 4768 void hwss_add_update_force_pstate(struct block_sequence_state *seq_state, 4769 struct dc *dc, 4770 struct dc_state *context) 4771 { 4772 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4773 seq_state->steps[*seq_state->num_steps].func = UPDATE_FORCE_PSTATE; 4774 seq_state->steps[*seq_state->num_steps].params.update_force_pstate_params.dc = dc; 4775 seq_state->steps[*seq_state->num_steps].params.update_force_pstate_params.context = context; 4776 (*seq_state->num_steps)++; 4777 } 4778 } 4779 4780 void hwss_add_hubbub_apply_dedcn21_147_wa(struct block_sequence_state *seq_state, 4781 struct hubbub *hubbub) 4782 { 4783 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4784 seq_state->steps[*seq_state->num_steps].func = HUBBUB_APPLY_DEDCN21_147_WA; 4785 seq_state->steps[*seq_state->num_steps].params.hubbub_apply_dedcn21_147_wa_params.hubbub = hubbub; 4786 (*seq_state->num_steps)++; 4787 } 4788 } 4789 4790 void hwss_add_hubbub_allow_self_refresh_control(struct block_sequence_state *seq_state, 4791 struct hubbub *hubbub, 4792 bool allow, 4793 bool *disallow_self_refresh_applied) 4794 { 4795 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4796 seq_state->steps[*seq_state->num_steps].func = HUBBUB_ALLOW_SELF_REFRESH_CONTROL; 4797 seq_state->steps[*seq_state->num_steps].params.hubbub_allow_self_refresh_control_params.hubbub = hubbub; 4798 seq_state->steps[*seq_state->num_steps].params.hubbub_allow_self_refresh_control_params.allow = allow; 4799 seq_state->steps[*seq_state->num_steps].params.hubbub_allow_self_refresh_control_params.disallow_self_refresh_applied = disallow_self_refresh_applied; 4800 (*seq_state->num_steps)++; 4801 } 4802 } 4803 4804 void hwss_add_tg_get_frame_count(struct block_sequence_state *seq_state, 4805 struct timing_generator *tg, 4806 unsigned int *frame_count) 4807 { 4808 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4809 seq_state->steps[*seq_state->num_steps].func = TG_GET_FRAME_COUNT; 4810 seq_state->steps[*seq_state->num_steps].params.tg_get_frame_count_params.tg = tg; 4811 seq_state->steps[*seq_state->num_steps].params.tg_get_frame_count_params.frame_count = frame_count; 4812 (*seq_state->num_steps)++; 4813 } 4814 } 4815 4816 void hwss_add_begin_cursor_offload_update(struct block_sequence_state *seq_state, 4817 struct dc *dc, 4818 struct pipe_ctx *pipe_ctx) 4819 { 4820 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4821 seq_state->steps[*seq_state->num_steps].func = HWSS_BEGIN_CURSOR_OFFLOAD_UPDATE; 4822 seq_state->steps[*seq_state->num_steps].params.begin_cursor_offload_update_params.dc = dc; 4823 seq_state->steps[*seq_state->num_steps].params.begin_cursor_offload_update_params.pipe_ctx = pipe_ctx; 4824 (*seq_state->num_steps)++; 4825 } 4826 } 4827 4828 void hwss_add_cursor_lock(struct block_sequence_state *seq_state, 4829 struct dc *dc, 4830 struct pipe_ctx *pipe_ctx, 4831 bool lock) 4832 { 4833 /* cursor lock is per MPCC tree, so only need to lock one pipe per stream */ 4834 if (!pipe_ctx || pipe_ctx->top_pipe) 4835 return; 4836 4837 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4838 seq_state->steps[*seq_state->num_steps].func = HWSS_CURSOR_LOCK; 4839 seq_state->steps[*seq_state->num_steps].params.cursor_lock_params.dc = dc; 4840 seq_state->steps[*seq_state->num_steps].params.cursor_lock_params.pipe_ctx = pipe_ctx; 4841 seq_state->steps[*seq_state->num_steps].params.cursor_lock_params.lock = lock; 4842 (*seq_state->num_steps)++; 4843 } 4844 } 4845 4846 void hwss_add_send_update_cursor_info_to_dmu(struct block_sequence_state *seq_state, 4847 struct pipe_ctx *pipe_ctx, 4848 int index) 4849 { 4850 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4851 seq_state->steps[*seq_state->num_steps].func = DC_SEND_CURSOR_INFO_TO_DMU; 4852 seq_state->steps[*seq_state->num_steps].params.send_cursor_info_to_dmu_params.pipe_ctx = pipe_ctx; 4853 seq_state->steps[*seq_state->num_steps].params.send_cursor_info_to_dmu_params.pipe_idx = index; 4854 (*seq_state->num_steps)++; 4855 } 4856 } 4857 4858 void hwss_add_update_cursor_offload_pipe(struct block_sequence_state *seq_state, 4859 struct dc *dc, 4860 struct pipe_ctx *pipe_ctx) 4861 { 4862 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4863 seq_state->steps[*seq_state->num_steps].func = HWSS_UPDATE_CURSOR_OFFLOAD_PIPE; 4864 seq_state->steps[*seq_state->num_steps].params.update_cursor_offload_pipe_params.dc = dc; 4865 seq_state->steps[*seq_state->num_steps].params.update_cursor_offload_pipe_params.pipe_ctx = pipe_ctx; 4866 (*seq_state->num_steps)++; 4867 } 4868 } 4869 4870 void hwss_add_commit_cursor_offload_update(struct block_sequence_state *seq_state, 4871 struct dc *dc, 4872 struct pipe_ctx *pipe_ctx) 4873 { 4874 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4875 seq_state->steps[*seq_state->num_steps].func = HWSS_COMMIT_CURSOR_OFFLOAD_UPDATE; 4876 seq_state->steps[*seq_state->num_steps].params.commit_cursor_offload_update_params.dc = dc; 4877 seq_state->steps[*seq_state->num_steps].params.commit_cursor_offload_update_params.pipe_ctx = pipe_ctx; 4878 (*seq_state->num_steps)++; 4879 } 4880 } 4881 4882 void hwss_add_stream_enc_update_hdmi_info_packets(struct block_sequence_state *seq_state, 4883 struct pipe_ctx *pipe_ctx) 4884 { 4885 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4886 seq_state->steps[*seq_state->num_steps].func = STREAM_ENC_UPDATE_HDMI_INFO_PACKETS; 4887 seq_state->steps[*seq_state->num_steps].params.stream_enc_update_hdmi_info_packets_params.pipe_ctx = pipe_ctx; 4888 (*seq_state->num_steps)++; 4889 } 4890 } 4891 4892 void hwss_add_hpo_frl_stream_enc_update_hdmi_info_packets(struct block_sequence_state *seq_state, 4893 struct pipe_ctx *pipe_ctx) 4894 { 4895 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4896 seq_state->steps[*seq_state->num_steps].func = HPO_FRL_STREAM_ENC_UPDATE_HDMI_INFO_PACKETS; 4897 seq_state->steps[*seq_state->num_steps].params.hpo_frl_stream_enc_update_hdmi_info_packets_params.pipe_ctx = pipe_ctx; 4898 (*seq_state->num_steps)++; 4899 } 4900 } 4901 4902 void hwss_add_hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num(struct block_sequence_state *seq_state, 4903 struct pipe_ctx *pipe_ctx) 4904 { 4905 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4906 seq_state->steps[*seq_state->num_steps].func = HPO_DP_STREAM_ENC_UPDATE_DP_INFO_PACKETS_SDP_LINE_NUM; 4907 seq_state->steps[*seq_state->num_steps].params.hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx = pipe_ctx; 4908 (*seq_state->num_steps)++; 4909 } 4910 } 4911 4912 void hwss_add_hpo_dp_stream_enc_update_dp_info_packets(struct block_sequence_state *seq_state, 4913 struct pipe_ctx *pipe_ctx) 4914 { 4915 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4916 seq_state->steps[*seq_state->num_steps].func = HPO_DP_STREAM_ENC_UPDATE_DP_INFO_PACKETS; 4917 seq_state->steps[*seq_state->num_steps].params.hpo_dp_stream_enc_update_dp_info_packets_params.pipe_ctx = pipe_ctx; 4918 (*seq_state->num_steps)++; 4919 } 4920 } 4921 4922 void hwss_add_stream_enc_update_dp_info_packets_sdp_line_num(struct block_sequence_state *seq_state, 4923 struct pipe_ctx *pipe_ctx) 4924 { 4925 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4926 seq_state->steps[*seq_state->num_steps].func = STREAM_ENC_UPDATE_DP_INFO_PACKETS_SDP_LINE_NUM; 4927 seq_state->steps[*seq_state->num_steps].params.stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx = pipe_ctx; 4928 (*seq_state->num_steps)++; 4929 } 4930 } 4931 4932 void hwss_add_stream_enc_update_dp_info_packets(struct block_sequence_state *seq_state, 4933 struct pipe_ctx *pipe_ctx) 4934 { 4935 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4936 seq_state->steps[*seq_state->num_steps].func = STREAM_ENC_UPDATE_DP_INFO_PACKETS; 4937 seq_state->steps[*seq_state->num_steps].params.stream_enc_update_dp_info_packets_params.pipe_ctx = pipe_ctx; 4938 (*seq_state->num_steps)++; 4939 } 4940 } 4941 4942 void hwss_add_dsc_set_config(struct block_sequence_state *seq_state, 4943 struct display_stream_compressor *dsc, 4944 const struct dsc_config *dsc_cfg, 4945 const struct dsc_optc_config *dsc_optc_cfg) 4946 { 4947 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4948 seq_state->steps[*seq_state->num_steps].func = DSC_SET_CONFIG_SIMPLE; 4949 seq_state->steps[*seq_state->num_steps].params.dsc_set_config_simple_params.dsc = dsc; 4950 seq_state->steps[*seq_state->num_steps].params.dsc_set_config_simple_params.dsc_cfg = *dsc_cfg; 4951 seq_state->steps[*seq_state->num_steps].params.dsc_set_config_simple_params.dsc_optc_cfg = *dsc_optc_cfg; 4952 (*seq_state->num_steps)++; 4953 } 4954 } 4955 4956 void hwss_add_stream_enc_dp_set_dsc_config(struct block_sequence_state *seq_state, 4957 struct stream_encoder *stream_enc, 4958 const struct dsc_optc_config *dsc_optc_cfg) 4959 { 4960 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4961 seq_state->steps[*seq_state->num_steps].func = STREAM_ENC_DP_SET_DSC_CONFIG; 4962 seq_state->steps[*seq_state->num_steps].params.stream_enc_dp_set_dsc_config_params.stream_enc = stream_enc; 4963 seq_state->steps[*seq_state->num_steps].params.stream_enc_dp_set_dsc_config_params.dsc_optc_cfg = dsc_optc_cfg; 4964 (*seq_state->num_steps)++; 4965 } 4966 } 4967 4968 void hwss_add_hpo_dp_stream_enc_dp_set_dsc_pps_info_packet(struct block_sequence_state *seq_state, 4969 struct hpo_dp_stream_encoder *hpo_dp_stream_enc, 4970 bool immediate_update, 4971 uint8_t *dsc_packed_pps, 4972 bool pps_sdp_stream) 4973 { 4974 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4975 seq_state->steps[*seq_state->num_steps].func = HPO_DP_STREAM_ENC_DP_SET_DSC_PPS_INFO_PACKET; 4976 seq_state->steps[*seq_state->num_steps].params.hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.hpo_dp_stream_enc = hpo_dp_stream_enc; 4977 seq_state->steps[*seq_state->num_steps].params.hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.immediate_update = immediate_update; 4978 seq_state->steps[*seq_state->num_steps].params.hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.dsc_packed_pps = dsc_packed_pps; 4979 seq_state->steps[*seq_state->num_steps].params.hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.pps_sdp_stream = pps_sdp_stream; 4980 (*seq_state->num_steps)++; 4981 } 4982 } 4983 4984 void hwss_add_stream_enc_dp_set_dsc_pps_info_packet(struct block_sequence_state *seq_state, 4985 struct stream_encoder *stream_enc, 4986 bool immediate_update, 4987 uint8_t *dsc_packed_pps, 4988 bool pps_sdp_stream) 4989 { 4990 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 4991 seq_state->steps[*seq_state->num_steps].func = STREAM_ENC_DP_SET_DSC_PPS_INFO_PACKET; 4992 seq_state->steps[*seq_state->num_steps].params.stream_enc_dp_set_dsc_pps_info_packet_params.stream_enc = stream_enc; 4993 seq_state->steps[*seq_state->num_steps].params.stream_enc_dp_set_dsc_pps_info_packet_params.immediate_update = immediate_update; 4994 seq_state->steps[*seq_state->num_steps].params.stream_enc_dp_set_dsc_pps_info_packet_params.dsc_packed_pps = dsc_packed_pps; 4995 seq_state->steps[*seq_state->num_steps].params.stream_enc_dp_set_dsc_pps_info_packet_params.pps_sdp_stream = pps_sdp_stream; 4996 (*seq_state->num_steps)++; 4997 } 4998 } 4999 5000 void hwss_add_hpo_frl_stream_enc_set_dsc_config(struct block_sequence_state *seq_state, 5001 struct hpo_frl_stream_encoder *hpo_frl_stream_enc, 5002 const struct dc_crtc_timing *timing, 5003 uint8_t *dsc_packed_pps) 5004 { 5005 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 5006 seq_state->steps[*seq_state->num_steps].func = HPO_FRL_STREAM_ENC_SET_DSC_CONFIG; 5007 seq_state->steps[*seq_state->num_steps].params.hpo_frl_stream_enc_set_dsc_config_params.hpo_frl_stream_enc = hpo_frl_stream_enc; 5008 seq_state->steps[*seq_state->num_steps].params.hpo_frl_stream_enc_set_dsc_config_params.timing = timing; 5009 seq_state->steps[*seq_state->num_steps].params.hpo_frl_stream_enc_set_dsc_config_params.dsc_packed_pps = dsc_packed_pps; 5010 (*seq_state->num_steps)++; 5011 } 5012 } 5013 5014 void hwss_add_setup_periodic_interrupt(struct block_sequence_state *seq_state, 5015 struct dc *dc, 5016 struct pipe_ctx *pipe_ctx) 5017 { 5018 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 5019 seq_state->steps[*seq_state->num_steps].func = HWSS_SETUP_PERIODIC_INTERRUPT; 5020 seq_state->steps[*seq_state->num_steps].params.setup_periodic_interrupt_params.dc = dc; 5021 seq_state->steps[*seq_state->num_steps].params.setup_periodic_interrupt_params.pipe_ctx = pipe_ctx; 5022 (*seq_state->num_steps)++; 5023 } 5024 } 5025 5026 void hwss_add_dp_trace_source_sequence(struct block_sequence_state *seq_state, 5027 struct dc_link *link, 5028 enum dpcd_source_sequence source) 5029 { 5030 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 5031 seq_state->steps[*seq_state->num_steps].func = DP_TRACE_SOURCE_SEQUENCE; 5032 seq_state->steps[*seq_state->num_steps].params.dp_trace_source_sequence_params.link = link; 5033 seq_state->steps[*seq_state->num_steps].params.dp_trace_source_sequence_params.source = source; 5034 (*seq_state->num_steps)++; 5035 } 5036 } 5037 5038 void hwss_add_set_dmdata_attributes(struct block_sequence_state *seq_state, 5039 struct pipe_ctx *pipe_ctx) 5040 { 5041 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 5042 struct dc_dmdata_attributes *attr = 5043 &seq_state->steps[*seq_state->num_steps].params.set_dmdata_attributes_params.attr; 5044 5045 memset(attr, 0, sizeof(*attr)); 5046 attr->dmdata_mode = DMDATA_HW_MODE; 5047 attr->dmdata_size = dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36; 5048 attr->address.quad_part = pipe_ctx->stream->dmdata_address.quad_part; 5049 attr->dmdata_repeat = 1; /* always repeat */ 5050 attr->dmdata_updated = 1; 5051 5052 seq_state->steps[*seq_state->num_steps].func = HUBP_SET_DMDATA_ATTRIBUTES; 5053 seq_state->steps[*seq_state->num_steps].params.set_dmdata_attributes_params.hubp = 5054 pipe_ctx->plane_res.hubp; 5055 (*seq_state->num_steps)++; 5056 } 5057 } 5058 5059 void hwss_add_link_increase_mst_payload(struct block_sequence_state *seq_state, 5060 struct pipe_ctx *pipe_ctx, 5061 uint32_t mst_stream_bw) 5062 { 5063 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 5064 seq_state->steps[*seq_state->num_steps].func = LINK_INCREASE_MST_PAYLOAD; 5065 seq_state->steps[*seq_state->num_steps].params.link_increase_mst_payload_params.pipe_ctx = pipe_ctx; 5066 seq_state->steps[*seq_state->num_steps].params.link_increase_mst_payload_params.mst_stream_bw = mst_stream_bw; 5067 (*seq_state->num_steps)++; 5068 } 5069 } 5070 5071 void hwss_add_link_reduce_mst_payload(struct block_sequence_state *seq_state, 5072 struct pipe_ctx *pipe_ctx, 5073 uint32_t mst_stream_bw) 5074 { 5075 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 5076 seq_state->steps[*seq_state->num_steps].func = LINK_REDUCE_MST_PAYLOAD; 5077 seq_state->steps[*seq_state->num_steps].params.link_reduce_mst_payload_params.pipe_ctx = pipe_ctx; 5078 seq_state->steps[*seq_state->num_steps].params.link_reduce_mst_payload_params.mst_stream_bw = mst_stream_bw; 5079 (*seq_state->num_steps)++; 5080 } 5081 } 5082 5083 void hwss_add_dp_set_test_pattern(struct block_sequence_state *seq_state, 5084 struct dc_link *link, 5085 enum dp_test_pattern test_pattern, 5086 enum dp_test_pattern_color_space test_pattern_color_space, 5087 const struct link_training_settings *p_link_settings, 5088 const unsigned char *p_custom_pattern, 5089 unsigned int cust_pattern_size) 5090 { 5091 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 5092 seq_state->steps[*seq_state->num_steps].func = DP_SET_TEST_PATTERN; 5093 seq_state->steps[*seq_state->num_steps].params.dp_set_test_pattern_params.link = link; 5094 seq_state->steps[*seq_state->num_steps].params.dp_set_test_pattern_params.test_pattern = test_pattern; 5095 seq_state->steps[*seq_state->num_steps].params.dp_set_test_pattern_params.test_pattern_color_space = test_pattern_color_space; 5096 seq_state->steps[*seq_state->num_steps].params.dp_set_test_pattern_params.p_link_settings = p_link_settings; 5097 seq_state->steps[*seq_state->num_steps].params.dp_set_test_pattern_params.p_custom_pattern = p_custom_pattern; 5098 seq_state->steps[*seq_state->num_steps].params.dp_set_test_pattern_params.cust_pattern_size = cust_pattern_size; 5099 (*seq_state->num_steps)++; 5100 } 5101 } 5102 5103 void hwss_add_link_set_dpms_off(struct block_sequence_state *seq_state, 5104 struct pipe_ctx *pipe_ctx) 5105 { 5106 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 5107 seq_state->steps[*seq_state->num_steps].func = LINK_SET_DPMS_OFF; 5108 seq_state->steps[*seq_state->num_steps].params.link_set_dpms_off_params.pipe_ctx = pipe_ctx; 5109 (*seq_state->num_steps)++; 5110 } 5111 } 5112 5113 void hwss_add_disable_audio_stream(struct block_sequence_state *seq_state, 5114 struct pipe_ctx *pipe_ctx) 5115 { 5116 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 5117 seq_state->steps[*seq_state->num_steps].func = DISABLE_AUDIO_STREAM; 5118 seq_state->steps[*seq_state->num_steps].params.disable_audio_stream_params.pipe_ctx = pipe_ctx; 5119 (*seq_state->num_steps)++; 5120 } 5121 } 5122 5123 void hwss_add_prepare_bandwidth(struct block_sequence_state *seq_state, 5124 struct dc *dc, 5125 struct dc_state *context) 5126 { 5127 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 5128 seq_state->steps[*seq_state->num_steps].func = PREPARE_BANDWIDTH; 5129 seq_state->steps[*seq_state->num_steps].params.prepare_bandwidth_params.dc = dc; 5130 seq_state->steps[*seq_state->num_steps].params.prepare_bandwidth_params.context = context; 5131 (*seq_state->num_steps)++; 5132 } 5133 } 5134 5135 void hwss_add_link_set_dpms_on(struct block_sequence_state *seq_state, 5136 struct dc_state *state, 5137 struct pipe_ctx *pipe_ctx) 5138 { 5139 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { 5140 seq_state->steps[*seq_state->num_steps].func = LINK_SET_DPMS_ON; 5141 seq_state->steps[*seq_state->num_steps].params.link_set_dpms_on_params.state = state; 5142 seq_state->steps[*seq_state->num_steps].params.link_set_dpms_on_params.pipe_ctx = pipe_ctx; 5143 (*seq_state->num_steps)++; 5144 } 5145 } 5146 5147 5148 void get_refresh_rate_confirm_color(struct pipe_ctx *pipe_ctx, struct tg_color *color) 5149 { 5150 uint32_t color_value = MAX_TG_COLOR_VALUE; 5151 unsigned int refresh_rate = 0; 5152 uint32_t scaling_factor = 0; 5153 if (pipe_ctx && pipe_ctx->stream && color) { 5154 refresh_rate = (pipe_ctx->stream->timing.pix_clk_100hz * 100) / (pipe_ctx->stream->adjust.v_total_max * pipe_ctx->stream->timing.h_total); 5155 5156 uint32_t min_refresh_rate = pipe_ctx->stream->timing.min_refresh_in_uhz / 1000000; 5157 uint32_t max_refresh_rate = pipe_ctx->stream->timing.max_refresh_in_uhz / 1000000; 5158 5159 if (max_refresh_rate - min_refresh_rate) 5160 scaling_factor = MAX_TG_COLOR_VALUE * (refresh_rate - min_refresh_rate) / (max_refresh_rate - min_refresh_rate); 5161 5162 pipe_ctx->visual_confirm_color.color_r_cr = (uint16_t)color_value; 5163 pipe_ctx->visual_confirm_color.color_g_y = (uint16_t)scaling_factor; 5164 pipe_ctx->visual_confirm_color.color_b_cb = (uint16_t)color_value; 5165 } 5166 } 5167