xref: /linux/arch/riscv/boot/dts/starfive/jh7110-common.dtsi (revision dd3802fc4f6b52201a93330d44981a66bd6ef883) 
1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
5 */
6
7/dts-v1/;
8#include "jh7110.dtsi"
9#include "jh7110-pinfunc.h"
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/leds/common.h>
12#include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
13
14/ {
15	aliases {
16		ethernet0 = &gmac0;
17		i2c0 = &i2c0;
18		i2c2 = &i2c2;
19		i2c5 = &i2c5;
20		i2c6 = &i2c6;
21		mmc0 = &mmc0;
22		mmc1 = &mmc1;
23		serial0 = &uart0;
24	};
25
26	chosen {
27		stdout-path = "serial0:115200n8";
28	};
29
30	memory@40000000 {
31		device_type = "memory";
32		reg = <0x0 0x40000000 0x1 0x0>;
33		bootph-pre-ram;
34	};
35
36	gpio-restart {
37		compatible = "gpio-restart";
38		gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
39		priority = <224>;
40	};
41
42	leds {
43		compatible = "gpio-leds";
44
45		led_status_power: led-0 {
46			gpios = <&aongpio 3 GPIO_ACTIVE_HIGH>;
47		};
48	};
49
50	pwmdac_codec: audio-codec {
51		compatible = "linux,spdif-dit";
52		#sound-dai-cells = <0>;
53	};
54
55	sound {
56		compatible = "simple-audio-card";
57		simple-audio-card,name = "StarFive-PWMDAC-Sound-Card";
58		#address-cells = <1>;
59		#size-cells = <0>;
60
61		simple-audio-card,dai-link@0 {
62			reg = <0>;
63			format = "left_j";
64			bitclock-master = <&sndcpu0>;
65			frame-master = <&sndcpu0>;
66
67			sndcpu0: cpu {
68				sound-dai = <&pwmdac>;
69			};
70
71			codec {
72				sound-dai = <&pwmdac_codec>;
73			};
74		};
75	};
76};
77
78&cpus {
79	timebase-frequency = <4000000>;
80};
81
82&dvp_clk {
83	clock-frequency = <74250000>;
84};
85
86&gmac0_rgmii_rxin {
87	clock-frequency = <125000000>;
88};
89
90&gmac0_rmii_refin {
91	clock-frequency = <50000000>;
92};
93
94&gmac1_rgmii_rxin {
95	clock-frequency = <125000000>;
96};
97
98&gmac1_rmii_refin {
99	clock-frequency = <50000000>;
100};
101
102&hdmitx0_pixelclk {
103	clock-frequency = <297000000>;
104};
105
106&i2srx_bclk_ext {
107	clock-frequency = <12288000>;
108};
109
110&i2srx_lrck_ext {
111	clock-frequency = <192000>;
112};
113
114&i2stx_bclk_ext {
115	clock-frequency = <12288000>;
116};
117
118&i2stx_lrck_ext {
119	clock-frequency = <192000>;
120};
121
122&mclk_ext {
123	clock-frequency = <12288000>;
124};
125
126&osc {
127	clock-frequency = <24000000>;
128};
129
130&rtc_osc {
131	clock-frequency = <32768>;
132};
133
134&tdm_ext {
135	clock-frequency = <49152000>;
136};
137
138&csi2rx {
139	assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>;
140	assigned-clock-rates = <297000000>;
141
142	ports {
143		#address-cells = <1>;
144		#size-cells = <0>;
145
146		port@0 {
147			reg = <0>;
148
149			/* remote MIPI sensor endpoint */
150		};
151
152		port@1 {
153			reg = <1>;
154
155			/* remote CAMSS endpoint */
156		};
157	};
158};
159
160&gmac0 {
161	phy-handle = <&phy0>;
162	phy-mode = "rgmii-id";
163
164	mdio {
165		#address-cells = <1>;
166		#size-cells = <0>;
167		compatible = "snps,dwmac-mdio";
168
169		phy0: ethernet-phy@0 {
170			reg = <0>;
171		};
172	};
173};
174
175&i2c0 {
176	clock-frequency = <100000>;
177	i2c-sda-hold-time-ns = <300>;
178	i2c-sda-falling-time-ns = <510>;
179	i2c-scl-falling-time-ns = <510>;
180	pinctrl-names = "default";
181	pinctrl-0 = <&i2c0_pins>;
182};
183
184&i2c2 {
185	clock-frequency = <100000>;
186	i2c-sda-hold-time-ns = <300>;
187	i2c-sda-falling-time-ns = <510>;
188	i2c-scl-falling-time-ns = <510>;
189	pinctrl-names = "default";
190	pinctrl-0 = <&i2c2_pins>;
191	status = "okay";
192};
193
194&i2c5 {
195	clock-frequency = <100000>;
196	i2c-sda-hold-time-ns = <300>;
197	i2c-sda-falling-time-ns = <510>;
198	i2c-scl-falling-time-ns = <510>;
199	pinctrl-names = "default";
200	pinctrl-0 = <&i2c5_pins>;
201	status = "okay";
202
203	axp15060: pmic@36 {
204		compatible = "x-powers,axp15060";
205		reg = <0x36>;
206		interrupt-controller;
207		#interrupt-cells = <1>;
208
209		regulators {
210			vcc_3v3: dcdc1 {
211				regulator-boot-on;
212				regulator-always-on;
213				regulator-min-microvolt = <3300000>;
214				regulator-max-microvolt = <3300000>;
215				regulator-name = "vcc_3v3";
216			};
217
218			vdd_cpu: dcdc2 {
219				regulator-always-on;
220				regulator-min-microvolt = <500000>;
221				regulator-max-microvolt = <1540000>;
222				regulator-name = "vdd_cpu";
223			};
224
225			emmc_vdd: aldo4 {
226				regulator-boot-on;
227				regulator-always-on;
228				regulator-min-microvolt = <1800000>;
229				regulator-max-microvolt = <3300000>;
230				regulator-name = "emmc_vdd";
231			};
232		};
233	};
234
235	eeprom@50 {
236		compatible = "atmel,24c04";
237		reg = <0x50>;
238		bootph-pre-ram;
239		pagesize = <16>;
240	};
241};
242
243&i2c6 {
244	clock-frequency = <100000>;
245	i2c-sda-hold-time-ns = <300>;
246	i2c-sda-falling-time-ns = <510>;
247	i2c-scl-falling-time-ns = <510>;
248	pinctrl-names = "default";
249	pinctrl-0 = <&i2c6_pins>;
250	status = "okay";
251};
252
253&mmc0 {
254	max-frequency = <100000000>;
255	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
256	assigned-clock-rates = <50000000>;
257	bus-width = <8>;
258	bootph-pre-ram;
259	pinctrl-names = "default";
260	pinctrl-0 = <&mmc0_pins>;
261	status = "okay";
262};
263
264&mmc1 {
265	max-frequency = <100000000>;
266	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
267	assigned-clock-rates = <50000000>;
268	bus-width = <4>;
269	bootph-pre-ram;
270	cap-sd-highspeed;
271	pinctrl-names = "default";
272	pinctrl-0 = <&mmc1_pins>;
273	status = "okay";
274};
275
276&pcie0 {
277	perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
278	phys = <&pciephy0>;
279	pinctrl-names = "default";
280	pinctrl-0 = <&pcie0_pins>;
281};
282
283&pcie1 {
284	perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
285	phys = <&pciephy1>;
286	pinctrl-names = "default";
287	pinctrl-0 = <&pcie1_pins>;
288};
289
290&pwmdac {
291	pinctrl-names = "default";
292	pinctrl-0 = <&pwmdac_pins>;
293};
294
295&qspi {
296	#address-cells = <1>;
297	#size-cells = <0>;
298	status = "okay";
299
300	nor_flash: flash@0 {
301		compatible = "jedec,spi-nor";
302		reg = <0>;
303		bootph-pre-ram;
304		cdns,read-delay = <2>;
305		spi-max-frequency = <100000000>;
306		cdns,tshsl-ns = <1>;
307		cdns,tsd2d-ns = <1>;
308		cdns,tchsh-ns = <1>;
309		cdns,tslch-ns = <1>;
310
311		partitions {
312			compatible = "fixed-partitions";
313			#address-cells = <1>;
314			#size-cells = <1>;
315
316			spl@0 {
317				reg = <0x0 0xf0000>;
318			};
319			uboot-env@f0000 {
320				reg = <0xf0000 0x10000>;
321			};
322			uboot@100000 {
323				reg = <0x100000 0xf00000>;
324			};
325		};
326	};
327};
328
329&pwm {
330	pinctrl-names = "default";
331	pinctrl-0 = <&pwm_pins>;
332};
333
334&spi0 {
335	pinctrl-names = "default";
336	pinctrl-0 = <&spi0_pins>;
337};
338
339&syscrg {
340	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
341			  <&syscrg JH7110_SYSCLK_BUS_ROOT>,
342			  <&syscrg JH7110_SYSCLK_PERH_ROOT>,
343			  <&syscrg JH7110_SYSCLK_QSPI_REF>,
344			  <&syscrg JH7110_SYSCLK_CPU_CORE>,
345			  <&pllclk JH7110_PLLCLK_PLL0_OUT>;
346	assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
347				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
348				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
349				 <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
350	assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1500000000>;
351};
352
353&sysgpio {
354	i2c0_pins: i2c0-0 {
355		i2c-pins {
356			pinmux = <GPIOMUX(57, GPOUT_LOW,
357					      GPOEN_SYS_I2C0_CLK,
358					      GPI_SYS_I2C0_CLK)>,
359				 <GPIOMUX(58, GPOUT_LOW,
360					      GPOEN_SYS_I2C0_DATA,
361					      GPI_SYS_I2C0_DATA)>;
362			bias-disable; /* external pull-up */
363			input-enable;
364			input-schmitt-enable;
365		};
366	};
367
368	i2c2_pins: i2c2-0 {
369		i2c-pins {
370			pinmux = <GPIOMUX(3, GPOUT_LOW,
371					     GPOEN_SYS_I2C2_CLK,
372					     GPI_SYS_I2C2_CLK)>,
373				 <GPIOMUX(2, GPOUT_LOW,
374					     GPOEN_SYS_I2C2_DATA,
375					     GPI_SYS_I2C2_DATA)>;
376			bias-disable; /* external pull-up */
377			input-enable;
378			input-schmitt-enable;
379		};
380	};
381
382	i2c5_pins: i2c5-0 {
383		bootph-pre-ram;
384
385		i2c-pins {
386			pinmux = <GPIOMUX(19, GPOUT_LOW,
387					      GPOEN_SYS_I2C5_CLK,
388					      GPI_SYS_I2C5_CLK)>,
389				 <GPIOMUX(20, GPOUT_LOW,
390					      GPOEN_SYS_I2C5_DATA,
391					      GPI_SYS_I2C5_DATA)>;
392			bias-disable; /* external pull-up */
393			bootph-pre-ram;
394			input-enable;
395			input-schmitt-enable;
396		};
397	};
398
399	i2c6_pins: i2c6-0 {
400		i2c-pins {
401			pinmux = <GPIOMUX(16, GPOUT_LOW,
402					      GPOEN_SYS_I2C6_CLK,
403					      GPI_SYS_I2C6_CLK)>,
404				 <GPIOMUX(17, GPOUT_LOW,
405					      GPOEN_SYS_I2C6_DATA,
406					      GPI_SYS_I2C6_DATA)>;
407			bias-disable; /* external pull-up */
408			input-enable;
409			input-schmitt-enable;
410		};
411	};
412
413	mmc0_pins: mmc0-0 {
414		mmc-pins {
415			pinmux = <PINMUX(PAD_SD0_CLK, 0)>,
416				 <PINMUX(PAD_SD0_CMD, 0)>,
417				 <PINMUX(PAD_SD0_DATA0, 0)>,
418				 <PINMUX(PAD_SD0_DATA1, 0)>,
419				 <PINMUX(PAD_SD0_DATA2, 0)>,
420				 <PINMUX(PAD_SD0_DATA3, 0)>,
421				 <PINMUX(PAD_SD0_DATA4, 0)>,
422				 <PINMUX(PAD_SD0_DATA5, 0)>,
423				 <PINMUX(PAD_SD0_DATA6, 0)>,
424				 <PINMUX(PAD_SD0_DATA7, 0)>;
425			bias-pull-up;
426			drive-strength = <12>;
427			input-enable;
428		};
429	};
430
431	mmc1_pins: mmc1-0 {
432		clk-pins {
433			pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
434					      GPOEN_ENABLE,
435					      GPI_NONE)>;
436			bias-pull-up;
437			drive-strength = <12>;
438			input-disable;
439			input-schmitt-disable;
440			slew-rate = <0>;
441		};
442
443		mmc-pins {
444			pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
445					     GPOEN_SYS_SDIO1_CMD,
446					     GPI_SYS_SDIO1_CMD)>,
447				 <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
448					      GPOEN_SYS_SDIO1_DATA0,
449					      GPI_SYS_SDIO1_DATA0)>,
450				 <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
451					      GPOEN_SYS_SDIO1_DATA1,
452					      GPI_SYS_SDIO1_DATA1)>,
453				 <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
454					     GPOEN_SYS_SDIO1_DATA2,
455					     GPI_SYS_SDIO1_DATA2)>,
456				 <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
457					     GPOEN_SYS_SDIO1_DATA3,
458					     GPI_SYS_SDIO1_DATA3)>;
459			bias-pull-up;
460			drive-strength = <12>;
461			input-enable;
462			input-schmitt-enable;
463			slew-rate = <0>;
464		};
465	};
466
467	pcie0_pins: pcie0-0 {
468		clkreq-pins {
469			pinmux = <GPIOMUX(27, GPOUT_LOW,
470					      GPOEN_DISABLE,
471					      GPI_NONE)>;
472			bias-pull-down;
473			drive-strength = <2>;
474			input-enable;
475			input-schmitt-disable;
476			slew-rate = <0>;
477		};
478
479		wake-pins {
480			pinmux = <GPIOMUX(32, GPOUT_LOW,
481					      GPOEN_DISABLE,
482					      GPI_NONE)>;
483			bias-pull-up;
484			drive-strength = <2>;
485			input-enable;
486			input-schmitt-disable;
487			slew-rate = <0>;
488		};
489	};
490
491	pcie1_pins: pcie1-0 {
492		clkreq-pins {
493			pinmux = <GPIOMUX(29, GPOUT_LOW,
494					      GPOEN_DISABLE,
495					      GPI_NONE)>;
496			bias-pull-down;
497			drive-strength = <2>;
498			input-enable;
499			input-schmitt-disable;
500			slew-rate = <0>;
501		};
502
503		wake-pins {
504			pinmux = <GPIOMUX(21, GPOUT_LOW,
505				      GPOEN_DISABLE,
506					      GPI_NONE)>;
507			bias-pull-up;
508			drive-strength = <2>;
509			input-enable;
510			input-schmitt-disable;
511			slew-rate = <0>;
512		};
513	};
514
515	pwmdac_pins: pwmdac-0 {
516		pwmdac-pins {
517			pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT,
518					      GPOEN_ENABLE,
519					      GPI_NONE)>,
520				 <GPIOMUX(34, GPOUT_SYS_PWMDAC_RIGHT,
521					      GPOEN_ENABLE,
522					      GPI_NONE)>;
523			bias-disable;
524			drive-strength = <2>;
525			input-disable;
526			input-schmitt-disable;
527			slew-rate = <0>;
528		};
529	};
530
531	pwm_pins: pwm-0 {
532		pwm-pins {
533			pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
534					      GPOEN_SYS_PWM0_CHANNEL0,
535					      GPI_NONE)>,
536				 <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
537					      GPOEN_SYS_PWM0_CHANNEL1,
538					      GPI_NONE)>;
539			bias-disable;
540			drive-strength = <12>;
541			input-disable;
542			input-schmitt-disable;
543			slew-rate = <0>;
544		};
545	};
546
547	spi0_pins: spi0-0 {
548		mosi-pins {
549			pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
550					      GPOEN_ENABLE,
551					      GPI_NONE)>;
552			bias-disable;
553			input-disable;
554			input-schmitt-disable;
555		};
556
557		miso-pins {
558			pinmux = <GPIOMUX(53, GPOUT_LOW,
559					      GPOEN_DISABLE,
560					      GPI_SYS_SPI0_RXD)>;
561			bias-pull-up;
562			input-enable;
563			input-schmitt-enable;
564		};
565
566		sck-pins {
567			pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_CLK,
568					      GPOEN_ENABLE,
569					      GPI_SYS_SPI0_CLK)>;
570			bias-disable;
571			input-disable;
572			input-schmitt-disable;
573		};
574
575		ss-pins {
576			pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS,
577					      GPOEN_ENABLE,
578					      GPI_SYS_SPI0_FSS)>;
579			bias-disable;
580			input-disable;
581			input-schmitt-disable;
582		};
583	};
584
585	uart0_pins: uart0-0 {
586		tx-pins {
587			pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
588					     GPOEN_ENABLE,
589					     GPI_NONE)>;
590			bias-disable;
591			drive-strength = <12>;
592			input-disable;
593			input-schmitt-disable;
594			slew-rate = <0>;
595		};
596
597		rx-pins {
598			pinmux = <GPIOMUX(6, GPOUT_LOW,
599					     GPOEN_DISABLE,
600					     GPI_SYS_UART0_RX)>;
601			bias-disable; /* external pull-up */
602			drive-strength = <2>;
603			input-enable;
604			input-schmitt-enable;
605			slew-rate = <0>;
606		};
607	};
608};
609
610&uart0 {
611	bootph-pre-ram;
612	pinctrl-names = "default";
613	pinctrl-0 = <&uart0_pins>;
614	status = "okay";
615};
616
617&U74_1 {
618	cpu-supply = <&vdd_cpu>;
619};
620
621&U74_2 {
622	cpu-supply = <&vdd_cpu>;
623};
624
625&U74_3 {
626	cpu-supply = <&vdd_cpu>;
627};
628
629&U74_4 {
630	cpu-supply = <&vdd_cpu>;
631};
632