xref: /linux/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts (revision 0cac5ce06e524755b3dac1e0a060b05992076d93) 
1// SPDX-License-Identifier:     GPL-2.0
2/*
3 * Copyright (C) 2025, Altera Corporation
4 */
5#include "socfpga_agilex5.dtsi"
6
7/ {
8	model = "SoCFPGA Agilex5 SoCDK NAND daughter board";
9	compatible = "intel,socfpga-agilex5-socdk-nand", "intel,socfpga-agilex5";
10
11	aliases {
12		serial0 = &uart0;
13		ethernet0 = &gmac0;
14	};
15
16	chosen {
17		stdout-path = "serial0:115200n8";
18	};
19
20	leds {
21		compatible = "gpio-leds";
22		led0 {
23			label = "hps_led0";
24			gpios = <&porta 6 GPIO_ACTIVE_HIGH>;
25		};
26
27		led1 {
28			label = "hps_led1";
29			gpios = <&porta 7 GPIO_ACTIVE_HIGH>;
30		};
31	};
32
33	memory@80000000 {
34		device_type = "memory";
35		/* We expect the bootloader to fill in the reg */
36		reg = <0x0 0x80000000 0x0 0x0>;
37	};
38};
39
40&gmac0 {
41	status = "okay";
42	phy-mode = "rgmii-id";
43	phy-handle = <&emac0_phy0>;
44	max-frame-size = <9000>;
45
46	mdio0 {
47		#address-cells = <1>;
48		#size-cells = <0>;
49		compatible = "snps,dwmac-mdio";
50
51		emac0_phy0: ethernet-phy@0 {
52			reg = <0>;
53		};
54	};
55};
56
57&gpio0 {
58	status = "okay";
59};
60
61&gpio1 {
62	status = "okay";
63};
64
65&i2c0 {
66	status = "okay";
67};
68
69&i3c0 {
70	status = "okay";
71};
72
73&i3c1 {
74	status = "okay";
75};
76
77&nand {
78	status = "okay";
79
80	nand@0 {
81		#address-cells = <1>;
82		#size-cells = <1>;
83		reg = <0>;
84		nand-bus-width = <8>;
85
86		partition@0 {
87			label = "u-boot";
88			reg = <0 0x200000>;
89		};
90		partition@200000 {
91			label = "root";
92			reg = <0x200000 0xffe00000>;
93		};
94	};
95};
96
97&osc1 {
98	clock-frequency = <25000000>;
99};
100
101&uart0 {
102	status = "okay";
103};
104
105&watchdog0 {
106	status = "okay";
107};
108