1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * sp5100_tco : TCO timer driver for sp5100 chipsets
4 *
5 * (c) Copyright 2009 Google Inc., All Rights Reserved.
6 *
7 * Based on i8xx_tco.c:
8 * (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights
9 * Reserved.
10 * https://www.kernelconcepts.de
11 *
12 * See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide",
13 * AMD Publication 44413 "AMD SP5100 Register Reference Guide"
14 * AMD Publication 45482 "AMD SB800-Series Southbridges Register
15 * Reference Guide"
16 * AMD Publication 48751 "BIOS and Kernel Developer’s Guide (BKDG)
17 * for AMD Family 16h Models 00h-0Fh Processors"
18 * AMD Publication 51192 "AMD Bolton FCH Register Reference Guide"
19 * AMD Publication 52740 "BIOS and Kernel Developer’s Guide (BKDG)
20 * for AMD Family 16h Models 30h-3Fh Processors"
21 * AMD Publication 55570-B1-PUB "Processor Programming Reference (PPR)
22 * for AMD Family 17h Model 18h, Revision B1
23 * Processors (PUB)
24 * AMD Publication 55772-A1-PUB "Processor Programming Reference (PPR)
25 * for AMD Family 17h Model 20h, Revision A1
26 * Processors (PUB)
27 */
28
29 /*
30 * Includes, defines, variables, module parameters, ...
31 */
32
33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
35 #include <linux/init.h>
36 #include <linux/io.h>
37 #include <linux/ioport.h>
38 #include <linux/module.h>
39 #include <linux/moduleparam.h>
40 #include <linux/pci.h>
41 #include <linux/platform_device.h>
42 #include <linux/types.h>
43 #include <linux/watchdog.h>
44
45 #include "sp5100_tco.h"
46
47 #define TCO_DRIVER_NAME "sp5100-tco"
48
49 /* internal variables */
50
51 enum tco_reg_layout {
52 sp5100, sb800, efch, efch_mmio
53 };
54
55 struct sp5100_tco {
56 struct watchdog_device wdd;
57 void __iomem *tcobase;
58 enum tco_reg_layout tco_reg_layout;
59 };
60
61 /* the watchdog platform device */
62 static struct platform_device *sp5100_tco_platform_device;
63 /* the associated PCI device */
64 static struct pci_dev *sp5100_tco_pci;
65
66 /* module parameters */
67
68 #define WATCHDOG_ACTION 0
69 static bool action = WATCHDOG_ACTION;
70 module_param(action, bool, 0);
71 MODULE_PARM_DESC(action, "Action taken when watchdog expires, 0 to reset, 1 to poweroff (default="
72 __MODULE_STRING(WATCHDOG_ACTION) ")");
73
74 #define WATCHDOG_HEARTBEAT 60 /* 60 sec default heartbeat. */
75 static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
76 module_param(heartbeat, int, 0);
77 MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (default="
78 __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
79
80 static bool nowayout = WATCHDOG_NOWAYOUT;
81 module_param(nowayout, bool, 0);
82 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started."
83 " (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
84
85 /*
86 * Some TCO specific functions
87 */
88
tco_reg_layout(struct pci_dev * dev)89 static enum tco_reg_layout tco_reg_layout(struct pci_dev *dev)
90 {
91 if (dev->vendor == PCI_VENDOR_ID_ATI &&
92 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
93 dev->revision < 0x40) {
94 return sp5100;
95 } else if ((dev->vendor == PCI_VENDOR_ID_AMD ||
96 dev->vendor == PCI_VENDOR_ID_HYGON) &&
97 sp5100_tco_pci->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
98 sp5100_tco_pci->revision >= AMD_ZEN_SMBUS_PCI_REV) {
99 return efch_mmio;
100 } else if ((dev->vendor == PCI_VENDOR_ID_AMD || dev->vendor == PCI_VENDOR_ID_HYGON) &&
101 ((dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
102 dev->revision >= 0x41) ||
103 (dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
104 dev->revision >= 0x49))) {
105 return efch;
106 }
107 return sb800;
108 }
109
tco_timer_start(struct watchdog_device * wdd)110 static int tco_timer_start(struct watchdog_device *wdd)
111 {
112 struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
113 u32 val;
114
115 val = readl(SP5100_WDT_CONTROL(tco->tcobase));
116 val |= SP5100_WDT_START_STOP_BIT;
117 writel(val, SP5100_WDT_CONTROL(tco->tcobase));
118
119 /* This must be a distinct write. */
120 val |= SP5100_WDT_TRIGGER_BIT;
121 writel(val, SP5100_WDT_CONTROL(tco->tcobase));
122
123 return 0;
124 }
125
tco_timer_stop(struct watchdog_device * wdd)126 static int tco_timer_stop(struct watchdog_device *wdd)
127 {
128 struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
129 u32 val;
130
131 val = readl(SP5100_WDT_CONTROL(tco->tcobase));
132 val &= ~SP5100_WDT_START_STOP_BIT;
133 writel(val, SP5100_WDT_CONTROL(tco->tcobase));
134
135 return 0;
136 }
137
tco_timer_ping(struct watchdog_device * wdd)138 static int tco_timer_ping(struct watchdog_device *wdd)
139 {
140 struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
141 u32 val;
142
143 val = readl(SP5100_WDT_CONTROL(tco->tcobase));
144 val |= SP5100_WDT_TRIGGER_BIT;
145 writel(val, SP5100_WDT_CONTROL(tco->tcobase));
146
147 return 0;
148 }
149
tco_timer_set_timeout(struct watchdog_device * wdd,unsigned int t)150 static int tco_timer_set_timeout(struct watchdog_device *wdd,
151 unsigned int t)
152 {
153 struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
154
155 /* Write new heartbeat to watchdog */
156 writel(t, SP5100_WDT_COUNT(tco->tcobase));
157
158 wdd->timeout = t;
159
160 return 0;
161 }
162
tco_timer_get_timeleft(struct watchdog_device * wdd)163 static unsigned int tco_timer_get_timeleft(struct watchdog_device *wdd)
164 {
165 struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
166
167 return readl(SP5100_WDT_COUNT(tco->tcobase));
168 }
169
sp5100_tco_read_pm_reg8(u8 index)170 static u8 sp5100_tco_read_pm_reg8(u8 index)
171 {
172 outb(index, SP5100_IO_PM_INDEX_REG);
173 return inb(SP5100_IO_PM_DATA_REG);
174 }
175
sp5100_tco_update_pm_reg8(u8 index,u8 reset,u8 set)176 static void sp5100_tco_update_pm_reg8(u8 index, u8 reset, u8 set)
177 {
178 u8 val;
179
180 outb(index, SP5100_IO_PM_INDEX_REG);
181 val = inb(SP5100_IO_PM_DATA_REG);
182 val &= reset;
183 val |= set;
184 outb(val, SP5100_IO_PM_DATA_REG);
185 }
186
tco_timer_enable(struct sp5100_tco * tco)187 static void tco_timer_enable(struct sp5100_tco *tco)
188 {
189 u32 val;
190
191 switch (tco->tco_reg_layout) {
192 case sb800:
193 /* For SB800 or later */
194 /* Set the Watchdog timer resolution to 1 sec */
195 sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONFIG,
196 0xff, SB800_PM_WATCHDOG_SECOND_RES);
197
198 /* Enable watchdog decode bit and watchdog timer */
199 sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONTROL,
200 ~SB800_PM_WATCHDOG_DISABLE,
201 SB800_PCI_WATCHDOG_DECODE_EN);
202 break;
203 case sp5100:
204 /* For SP5100 or SB7x0 */
205 /* Enable watchdog decode bit */
206 pci_read_config_dword(sp5100_tco_pci,
207 SP5100_PCI_WATCHDOG_MISC_REG,
208 &val);
209
210 val |= SP5100_PCI_WATCHDOG_DECODE_EN;
211
212 pci_write_config_dword(sp5100_tco_pci,
213 SP5100_PCI_WATCHDOG_MISC_REG,
214 val);
215
216 /* Enable Watchdog timer and set the resolution to 1 sec */
217 sp5100_tco_update_pm_reg8(SP5100_PM_WATCHDOG_CONTROL,
218 ~SP5100_PM_WATCHDOG_DISABLE,
219 SP5100_PM_WATCHDOG_SECOND_RES);
220 break;
221 case efch:
222 /* Set the Watchdog timer resolution to 1 sec and enable */
223 sp5100_tco_update_pm_reg8(EFCH_PM_DECODEEN3,
224 ~EFCH_PM_WATCHDOG_DISABLE,
225 EFCH_PM_DECODEEN_SECOND_RES);
226 break;
227 default:
228 break;
229 }
230 }
231
sp5100_tco_read_pm_reg32(u8 index)232 static u32 sp5100_tco_read_pm_reg32(u8 index)
233 {
234 u32 val = 0;
235 int i;
236
237 for (i = 3; i >= 0; i--)
238 val = (val << 8) + sp5100_tco_read_pm_reg8(index + i);
239
240 return val;
241 }
242
sp5100_tco_request_region(struct device * dev,u32 mmio_addr,const char * dev_name)243 static u32 sp5100_tco_request_region(struct device *dev,
244 u32 mmio_addr,
245 const char *dev_name)
246 {
247 if (!devm_request_mem_region(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE,
248 dev_name)) {
249 dev_dbg(dev, "MMIO address 0x%08x already in use\n", mmio_addr);
250 return 0;
251 }
252
253 return mmio_addr;
254 }
255
sp5100_tco_prepare_base(struct sp5100_tco * tco,u32 mmio_addr,u32 alt_mmio_addr,const char * dev_name)256 static u32 sp5100_tco_prepare_base(struct sp5100_tco *tco,
257 u32 mmio_addr,
258 u32 alt_mmio_addr,
259 const char *dev_name)
260 {
261 struct device *dev = tco->wdd.parent;
262
263 dev_dbg(dev, "Got 0x%08x from SBResource_MMIO register\n", mmio_addr);
264
265 if (!mmio_addr && !alt_mmio_addr)
266 return -ENODEV;
267
268 /* Check for MMIO address and alternate MMIO address conflicts */
269 if (mmio_addr)
270 mmio_addr = sp5100_tco_request_region(dev, mmio_addr, dev_name);
271
272 if (!mmio_addr && alt_mmio_addr)
273 mmio_addr = sp5100_tco_request_region(dev, alt_mmio_addr, dev_name);
274
275 if (!mmio_addr) {
276 dev_err(dev, "Failed to reserve MMIO or alternate MMIO region\n");
277 return -EBUSY;
278 }
279
280 tco->tcobase = devm_ioremap(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE);
281 if (!tco->tcobase) {
282 dev_err(dev, "MMIO address 0x%08x failed mapping\n", mmio_addr);
283 devm_release_mem_region(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE);
284 return -ENOMEM;
285 }
286
287 dev_info(dev, "Using 0x%08x for watchdog MMIO address\n", mmio_addr);
288
289 return 0;
290 }
291
sp5100_tco_timer_init(struct sp5100_tco * tco)292 static int sp5100_tco_timer_init(struct sp5100_tco *tco)
293 {
294 struct watchdog_device *wdd = &tco->wdd;
295 struct device *dev = wdd->parent;
296 u32 val;
297
298 val = readl(SP5100_WDT_CONTROL(tco->tcobase));
299 if (val & SP5100_WDT_DISABLED) {
300 dev_err(dev, "Watchdog hardware is disabled\n");
301 return -ENODEV;
302 }
303
304 /*
305 * Save WatchDogFired status, because WatchDogFired flag is
306 * cleared here.
307 */
308 if (val & SP5100_WDT_FIRED)
309 wdd->bootstatus = WDIOF_CARDRESET;
310
311 /* Set watchdog action */
312 if (action)
313 val |= SP5100_WDT_ACTION_RESET;
314 else
315 val &= ~SP5100_WDT_ACTION_RESET;
316 writel(val, SP5100_WDT_CONTROL(tco->tcobase));
317
318 /* Set a reasonable heartbeat before we stop the timer */
319 tco_timer_set_timeout(wdd, wdd->timeout);
320
321 /*
322 * Stop the TCO before we change anything so we don't race with
323 * a zeroed timer.
324 */
325 tco_timer_stop(wdd);
326
327 return 0;
328 }
329
efch_read_pm_reg8(void __iomem * addr,u8 index)330 static u8 efch_read_pm_reg8(void __iomem *addr, u8 index)
331 {
332 return readb(addr + index);
333 }
334
efch_update_pm_reg8(void __iomem * addr,u8 index,u8 reset,u8 set)335 static void efch_update_pm_reg8(void __iomem *addr, u8 index, u8 reset, u8 set)
336 {
337 u8 val;
338
339 val = readb(addr + index);
340 val &= reset;
341 val |= set;
342 writeb(val, addr + index);
343 }
344
tco_timer_enable_mmio(void __iomem * addr)345 static void tco_timer_enable_mmio(void __iomem *addr)
346 {
347 efch_update_pm_reg8(addr, EFCH_PM_DECODEEN3,
348 ~EFCH_PM_WATCHDOG_DISABLE,
349 EFCH_PM_DECODEEN_SECOND_RES);
350 }
351
sp5100_tco_setupdevice_mmio(struct device * dev,struct watchdog_device * wdd)352 static int sp5100_tco_setupdevice_mmio(struct device *dev,
353 struct watchdog_device *wdd)
354 {
355 struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
356 const char *dev_name = SB800_DEVNAME;
357 u32 mmio_addr = 0, alt_mmio_addr = 0;
358 struct resource *res;
359 void __iomem *addr;
360 int ret;
361 u32 val;
362
363 res = request_mem_region_muxed(EFCH_PM_ACPI_MMIO_PM_ADDR,
364 EFCH_PM_ACPI_MMIO_PM_SIZE,
365 "sp5100_tco");
366
367 if (!res) {
368 dev_err(dev,
369 "Memory region 0x%08x already in use\n",
370 EFCH_PM_ACPI_MMIO_PM_ADDR);
371 return -EBUSY;
372 }
373
374 addr = ioremap(EFCH_PM_ACPI_MMIO_PM_ADDR, EFCH_PM_ACPI_MMIO_PM_SIZE);
375 if (!addr) {
376 dev_err(dev, "Address mapping failed\n");
377 ret = -ENOMEM;
378 goto out;
379 }
380
381 /*
382 * EFCH_PM_DECODEEN_WDT_TMREN is dual purpose. This bitfield
383 * enables sp5100_tco register MMIO space decoding. The bitfield
384 * also starts the timer operation. Enable if not already enabled.
385 */
386 val = efch_read_pm_reg8(addr, EFCH_PM_DECODEEN);
387 if (!(val & EFCH_PM_DECODEEN_WDT_TMREN)) {
388 efch_update_pm_reg8(addr, EFCH_PM_DECODEEN, 0xff,
389 EFCH_PM_DECODEEN_WDT_TMREN);
390 }
391
392 /* Error if the timer could not be enabled */
393 val = efch_read_pm_reg8(addr, EFCH_PM_DECODEEN);
394 if (!(val & EFCH_PM_DECODEEN_WDT_TMREN)) {
395 dev_err(dev, "Failed to enable the timer\n");
396 ret = -EFAULT;
397 goto out;
398 }
399
400 mmio_addr = EFCH_PM_WDT_ADDR;
401
402 /* Determine alternate MMIO base address */
403 val = efch_read_pm_reg8(addr, EFCH_PM_ISACONTROL);
404 if (val & EFCH_PM_ISACONTROL_MMIOEN)
405 alt_mmio_addr = EFCH_PM_ACPI_MMIO_ADDR +
406 EFCH_PM_ACPI_MMIO_WDT_OFFSET;
407
408 ret = sp5100_tco_prepare_base(tco, mmio_addr, alt_mmio_addr, dev_name);
409 if (!ret) {
410 tco_timer_enable_mmio(addr);
411 ret = sp5100_tco_timer_init(tco);
412 }
413
414 out:
415 if (addr)
416 iounmap(addr);
417
418 release_resource(res);
419 kfree(res);
420
421 return ret;
422 }
423
sp5100_tco_setupdevice(struct device * dev,struct watchdog_device * wdd)424 static int sp5100_tco_setupdevice(struct device *dev,
425 struct watchdog_device *wdd)
426 {
427 struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
428 const char *dev_name;
429 u32 mmio_addr = 0, val;
430 u32 alt_mmio_addr = 0;
431 int ret;
432
433 if (tco->tco_reg_layout == efch_mmio)
434 return sp5100_tco_setupdevice_mmio(dev, wdd);
435
436 /* Request the IO ports used by this driver */
437 if (!request_muxed_region(SP5100_IO_PM_INDEX_REG,
438 SP5100_PM_IOPORTS_SIZE, "sp5100_tco")) {
439 dev_err(dev, "I/O address 0x%04x already in use\n",
440 SP5100_IO_PM_INDEX_REG);
441 return -EBUSY;
442 }
443
444 /*
445 * Determine type of southbridge chipset.
446 */
447 switch (tco->tco_reg_layout) {
448 case sp5100:
449 dev_name = SP5100_DEVNAME;
450 mmio_addr = sp5100_tco_read_pm_reg32(SP5100_PM_WATCHDOG_BASE) &
451 0xfffffff8;
452
453 /*
454 * Secondly, find the watchdog timer MMIO address
455 * from SBResource_MMIO register.
456 */
457
458 /* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */
459 pci_read_config_dword(sp5100_tco_pci,
460 SP5100_SB_RESOURCE_MMIO_BASE,
461 &val);
462
463 /* Verify MMIO is enabled and using bar0 */
464 if ((val & SB800_ACPI_MMIO_MASK) == SB800_ACPI_MMIO_DECODE_EN)
465 alt_mmio_addr = (val & ~0xfff) + SB800_PM_WDT_MMIO_OFFSET;
466 break;
467 case sb800:
468 dev_name = SB800_DEVNAME;
469 mmio_addr = sp5100_tco_read_pm_reg32(SB800_PM_WATCHDOG_BASE) &
470 0xfffffff8;
471
472 /* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */
473 val = sp5100_tco_read_pm_reg32(SB800_PM_ACPI_MMIO_EN);
474
475 /* Verify MMIO is enabled and using bar0 */
476 if ((val & SB800_ACPI_MMIO_MASK) == SB800_ACPI_MMIO_DECODE_EN)
477 alt_mmio_addr = (val & ~0xfff) + SB800_PM_WDT_MMIO_OFFSET;
478 break;
479 case efch:
480 dev_name = SB800_DEVNAME;
481 val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN);
482 if (val & EFCH_PM_DECODEEN_WDT_TMREN)
483 mmio_addr = EFCH_PM_WDT_ADDR;
484
485 val = sp5100_tco_read_pm_reg8(EFCH_PM_ISACONTROL);
486 if (val & EFCH_PM_ISACONTROL_MMIOEN)
487 alt_mmio_addr = EFCH_PM_ACPI_MMIO_ADDR +
488 EFCH_PM_ACPI_MMIO_WDT_OFFSET;
489 break;
490 default:
491 return -ENODEV;
492 }
493
494 ret = sp5100_tco_prepare_base(tco, mmio_addr, alt_mmio_addr, dev_name);
495 if (!ret) {
496 /* Setup the watchdog timer */
497 tco_timer_enable(tco);
498 ret = sp5100_tco_timer_init(tco);
499 }
500
501 release_region(SP5100_IO_PM_INDEX_REG, SP5100_PM_IOPORTS_SIZE);
502 return ret;
503 }
504
505 static struct watchdog_info sp5100_tco_wdt_info = {
506 .identity = "SP5100 TCO timer",
507 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
508 };
509
510 static const struct watchdog_ops sp5100_tco_wdt_ops = {
511 .owner = THIS_MODULE,
512 .start = tco_timer_start,
513 .stop = tco_timer_stop,
514 .ping = tco_timer_ping,
515 .set_timeout = tco_timer_set_timeout,
516 .get_timeleft = tco_timer_get_timeleft,
517 };
518
sp5100_tco_probe(struct platform_device * pdev)519 static int sp5100_tco_probe(struct platform_device *pdev)
520 {
521 struct device *dev = &pdev->dev;
522 struct watchdog_device *wdd;
523 struct sp5100_tco *tco;
524 int ret;
525
526 tco = devm_kzalloc(dev, sizeof(*tco), GFP_KERNEL);
527 if (!tco)
528 return -ENOMEM;
529
530 tco->tco_reg_layout = tco_reg_layout(sp5100_tco_pci);
531
532 wdd = &tco->wdd;
533 wdd->parent = dev;
534 wdd->info = &sp5100_tco_wdt_info;
535 wdd->ops = &sp5100_tco_wdt_ops;
536 wdd->timeout = WATCHDOG_HEARTBEAT;
537 wdd->min_timeout = 1;
538 wdd->max_timeout = 0xffff;
539
540 watchdog_init_timeout(wdd, heartbeat, NULL);
541 watchdog_set_nowayout(wdd, nowayout);
542 watchdog_stop_on_reboot(wdd);
543 watchdog_stop_on_unregister(wdd);
544 watchdog_set_drvdata(wdd, tco);
545
546 ret = sp5100_tco_setupdevice(dev, wdd);
547 if (ret)
548 return ret;
549
550 ret = devm_watchdog_register_device(dev, wdd);
551 if (ret)
552 return ret;
553
554 /* Show module parameters */
555 dev_info(dev, "initialized. heartbeat=%d sec (nowayout=%d)\n",
556 wdd->timeout, nowayout);
557
558 return 0;
559 }
560
561 static struct platform_driver sp5100_tco_driver = {
562 .probe = sp5100_tco_probe,
563 .driver = {
564 .name = TCO_DRIVER_NAME,
565 },
566 };
567
568 /*
569 * Data for PCI driver interface
570 *
571 * This data only exists for exporting the supported
572 * PCI ids via MODULE_DEVICE_TABLE. We do not actually
573 * register a pci_driver, because someone else might
574 * want to register another driver on the same PCI id.
575 */
576 static const struct pci_device_id sp5100_tco_pci_tbl[] = {
577 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, PCI_ANY_ID,
578 PCI_ANY_ID, },
579 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, PCI_ANY_ID,
580 PCI_ANY_ID, },
581 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, PCI_ANY_ID,
582 PCI_ANY_ID, },
583 { PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, PCI_ANY_ID,
584 PCI_ANY_ID, },
585 { 0, }, /* End of list */
586 };
587 MODULE_DEVICE_TABLE(pci, sp5100_tco_pci_tbl);
588
sp5100_tco_init(void)589 static int __init sp5100_tco_init(void)
590 {
591 struct pci_dev *dev = NULL;
592 int err;
593
594 /* Match the PCI device */
595 for_each_pci_dev(dev) {
596 if (pci_match_id(sp5100_tco_pci_tbl, dev) != NULL) {
597 sp5100_tco_pci = dev;
598 break;
599 }
600 }
601
602 if (!sp5100_tco_pci)
603 return -ENODEV;
604
605 pr_info("SP5100/SB800 TCO WatchDog Timer Driver\n");
606
607 err = platform_driver_register(&sp5100_tco_driver);
608 if (err) {
609 pci_dev_put(sp5100_tco_pci);
610 return err;
611 }
612
613 sp5100_tco_platform_device =
614 platform_device_register_simple(TCO_DRIVER_NAME, -1, NULL, 0);
615 if (IS_ERR(sp5100_tco_platform_device)) {
616 err = PTR_ERR(sp5100_tco_platform_device);
617 goto unreg_platform_driver;
618 }
619
620 return 0;
621
622 unreg_platform_driver:
623 platform_driver_unregister(&sp5100_tco_driver);
624 pci_dev_put(sp5100_tco_pci);
625 return err;
626 }
627
sp5100_tco_exit(void)628 static void __exit sp5100_tco_exit(void)
629 {
630 platform_device_unregister(sp5100_tco_platform_device);
631 platform_driver_unregister(&sp5100_tco_driver);
632 pci_dev_put(sp5100_tco_pci);
633 }
634
635 module_init(sp5100_tco_init);
636 module_exit(sp5100_tco_exit);
637
638 MODULE_AUTHOR("Priyanka Gupta");
639 MODULE_DESCRIPTION("TCO timer driver for SP5100/SB800 chipset");
640 MODULE_LICENSE("GPL");
641