1 /*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 /*************************************\
21 * EEPROM access functions and helpers *
22 \*************************************/
23
24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
26 #include <linux/slab.h>
27
28 #include "ath5k.h"
29 #include "reg.h"
30 #include "debug.h"
31
32
33 /******************\
34 * Helper functions *
35 \******************/
36
37 /*
38 * Translate binary channel representation in EEPROM to frequency
39 */
ath5k_eeprom_bin2freq(struct ath5k_eeprom_info * ee,u16 bin,unsigned int mode)40 static u16 ath5k_eeprom_bin2freq(struct ath5k_eeprom_info *ee, u16 bin,
41 unsigned int mode)
42 {
43 u16 val;
44
45 if (bin == AR5K_EEPROM_CHANNEL_DIS)
46 return bin;
47
48 if (mode == AR5K_EEPROM_MODE_11A) {
49 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
50 val = (5 * bin) + 4800;
51 else
52 val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 :
53 (bin * 10) + 5100;
54 } else {
55 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
56 val = bin + 2300;
57 else
58 val = bin + 2400;
59 }
60
61 return val;
62 }
63
64
65 /*********\
66 * Parsers *
67 \*********/
68
69 /*
70 * Initialize eeprom & capabilities structs
71 */
72 static int
ath5k_eeprom_init_header(struct ath5k_hw * ah)73 ath5k_eeprom_init_header(struct ath5k_hw *ah)
74 {
75 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
76 u16 val;
77 u32 cksum, offset, eep_max = AR5K_EEPROM_INFO_MAX;
78
79 /*
80 * Read values from EEPROM and store them in the capability structure
81 */
82 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic);
83 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect);
84 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain);
85 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version);
86 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header);
87
88 /* Return if we have an old EEPROM */
89 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_0)
90 return 0;
91
92 /*
93 * Validate the checksum of the EEPROM date. There are some
94 * devices with invalid EEPROMs.
95 */
96 AR5K_EEPROM_READ(AR5K_EEPROM_SIZE_UPPER, val);
97 if (val) {
98 eep_max = (val & AR5K_EEPROM_SIZE_UPPER_MASK) <<
99 AR5K_EEPROM_SIZE_ENDLOC_SHIFT;
100 AR5K_EEPROM_READ(AR5K_EEPROM_SIZE_LOWER, val);
101 eep_max = (eep_max | val) - AR5K_EEPROM_INFO_BASE;
102
103 /*
104 * Fail safe check to prevent stupid loops due
105 * to busted EEPROMs. XXX: This value is likely too
106 * big still, waiting on a better value.
107 */
108 if (eep_max > (3 * AR5K_EEPROM_INFO_MAX)) {
109 ATH5K_ERR(ah, "Invalid max custom EEPROM size: "
110 "%d (0x%04x) max expected: %d (0x%04x)\n",
111 eep_max, eep_max,
112 3 * AR5K_EEPROM_INFO_MAX,
113 3 * AR5K_EEPROM_INFO_MAX);
114 return -EIO;
115 }
116 }
117
118 for (cksum = 0, offset = 0; offset < eep_max; offset++) {
119 AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val);
120 cksum ^= val;
121 }
122 if (cksum != AR5K_EEPROM_INFO_CKSUM) {
123 ATH5K_ERR(ah, "Invalid EEPROM "
124 "checksum: 0x%04x eep_max: 0x%04x (%s)\n",
125 cksum, eep_max,
126 eep_max == AR5K_EEPROM_INFO_MAX ?
127 "default size" : "custom size");
128 return -EIO;
129 }
130
131 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(ah->ah_ee_version),
132 ee_ant_gain);
133
134 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
135 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0);
136 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1);
137
138 /* XXX: Don't know which versions include these two */
139 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC2, ee_misc2);
140
141 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3)
142 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC3, ee_misc3);
143
144 if (ee->ee_version >= AR5K_EEPROM_VERSION_5_0) {
145 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC4, ee_misc4);
146 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC5, ee_misc5);
147 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC6, ee_misc6);
148 }
149 }
150
151 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_3) {
152 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val);
153 ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7;
154 ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7;
155
156 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val);
157 ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
158 ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
159 }
160
161 AR5K_EEPROM_READ(AR5K_EEPROM_IS_HB63, val);
162
163 if ((ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4)) && val)
164 ee->ee_is_hb63 = true;
165 else
166 ee->ee_is_hb63 = false;
167
168 AR5K_EEPROM_READ(AR5K_EEPROM_RFKILL, val);
169 ee->ee_rfkill_pin = (u8) AR5K_REG_MS(val, AR5K_EEPROM_RFKILL_GPIO_SEL);
170 ee->ee_rfkill_pol = val & AR5K_EEPROM_RFKILL_POLARITY ? true : false;
171
172 /* Check if PCIE_OFFSET points to PCIE_SERDES_SECTION
173 * and enable serdes programming if needed.
174 *
175 * XXX: Serdes values seem to be fixed so
176 * no need to read them here, we write them
177 * during ath5k_hw_init */
178 AR5K_EEPROM_READ(AR5K_EEPROM_PCIE_OFFSET, val);
179 ee->ee_serdes = (val == AR5K_EEPROM_PCIE_SERDES_SECTION) ?
180 true : false;
181
182 return 0;
183 }
184
185
186 /*
187 * Read antenna infos from eeprom
188 */
ath5k_eeprom_read_ants(struct ath5k_hw * ah,u32 * offset,unsigned int mode)189 static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset,
190 unsigned int mode)
191 {
192 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
193 u32 o = *offset;
194 u16 val;
195 int i = 0;
196
197 AR5K_EEPROM_READ(o++, val);
198 ee->ee_switch_settling[mode] = (val >> 8) & 0x7f;
199 ee->ee_atn_tx_rx[mode] = (val >> 2) & 0x3f;
200 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
201
202 AR5K_EEPROM_READ(o++, val);
203 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
204 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
205 ee->ee_ant_control[mode][i++] = val & 0x3f;
206
207 AR5K_EEPROM_READ(o++, val);
208 ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f;
209 ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f;
210 ee->ee_ant_control[mode][i] = (val << 2) & 0x3f;
211
212 AR5K_EEPROM_READ(o++, val);
213 ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3;
214 ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f;
215 ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f;
216 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
217
218 AR5K_EEPROM_READ(o++, val);
219 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
220 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
221 ee->ee_ant_control[mode][i++] = val & 0x3f;
222
223 /* Get antenna switch tables */
224 ah->ah_ant_ctl[mode][AR5K_ANT_CTL] =
225 (ee->ee_ant_control[mode][0] << 4);
226 ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_A] =
227 ee->ee_ant_control[mode][1] |
228 (ee->ee_ant_control[mode][2] << 6) |
229 (ee->ee_ant_control[mode][3] << 12) |
230 (ee->ee_ant_control[mode][4] << 18) |
231 (ee->ee_ant_control[mode][5] << 24);
232 ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_B] =
233 ee->ee_ant_control[mode][6] |
234 (ee->ee_ant_control[mode][7] << 6) |
235 (ee->ee_ant_control[mode][8] << 12) |
236 (ee->ee_ant_control[mode][9] << 18) |
237 (ee->ee_ant_control[mode][10] << 24);
238
239 /* return new offset */
240 *offset = o;
241
242 return 0;
243 }
244
245 /*
246 * Read supported modes and some mode-specific calibration data
247 * from eeprom
248 */
ath5k_eeprom_read_modes(struct ath5k_hw * ah,u32 * offset,unsigned int mode)249 static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
250 unsigned int mode)
251 {
252 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
253 u32 o = *offset;
254 u16 val;
255
256 ee->ee_n_piers[mode] = 0;
257 AR5K_EEPROM_READ(o++, val);
258 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
259 switch (mode) {
260 case AR5K_EEPROM_MODE_11A:
261 ee->ee_ob[mode][3] = (val >> 5) & 0x7;
262 ee->ee_db[mode][3] = (val >> 2) & 0x7;
263 ee->ee_ob[mode][2] = (val << 1) & 0x7;
264
265 AR5K_EEPROM_READ(o++, val);
266 ee->ee_ob[mode][2] |= (val >> 15) & 0x1;
267 ee->ee_db[mode][2] = (val >> 12) & 0x7;
268 ee->ee_ob[mode][1] = (val >> 9) & 0x7;
269 ee->ee_db[mode][1] = (val >> 6) & 0x7;
270 ee->ee_ob[mode][0] = (val >> 3) & 0x7;
271 ee->ee_db[mode][0] = val & 0x7;
272 break;
273 case AR5K_EEPROM_MODE_11G:
274 case AR5K_EEPROM_MODE_11B:
275 ee->ee_ob[mode][1] = (val >> 4) & 0x7;
276 ee->ee_db[mode][1] = val & 0x7;
277 break;
278 }
279
280 AR5K_EEPROM_READ(o++, val);
281 ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff;
282 ee->ee_thr_62[mode] = val & 0xff;
283
284 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
285 ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
286
287 AR5K_EEPROM_READ(o++, val);
288 ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff;
289 ee->ee_tx_frm2xpa_enable[mode] = val & 0xff;
290
291 AR5K_EEPROM_READ(o++, val);
292 ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff;
293
294 if ((val & 0xff) & 0x80)
295 ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
296 else
297 ee->ee_noise_floor_thr[mode] = val & 0xff;
298
299 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
300 ee->ee_noise_floor_thr[mode] =
301 mode == AR5K_EEPROM_MODE_11A ? -54 : -1;
302
303 AR5K_EEPROM_READ(o++, val);
304 ee->ee_xlna_gain[mode] = (val >> 5) & 0xff;
305 ee->ee_x_gain[mode] = (val >> 1) & 0xf;
306 ee->ee_xpd[mode] = val & 0x1;
307
308 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
309 mode != AR5K_EEPROM_MODE_11B)
310 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
311
312 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) {
313 AR5K_EEPROM_READ(o++, val);
314 ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
315
316 if (mode == AR5K_EEPROM_MODE_11A)
317 ee->ee_xr_power[mode] = val & 0x3f;
318 else {
319 /* b_DB_11[bg] and b_OB_11[bg] */
320 ee->ee_ob[mode][0] = val & 0x7;
321 ee->ee_db[mode][0] = (val >> 3) & 0x7;
322 }
323 }
324
325 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_4) {
326 ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN;
327 ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA;
328 } else {
329 ee->ee_i_gain[mode] = (val >> 13) & 0x7;
330
331 AR5K_EEPROM_READ(o++, val);
332 ee->ee_i_gain[mode] |= (val << 3) & 0x38;
333
334 if (mode == AR5K_EEPROM_MODE_11G) {
335 ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff;
336 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_6)
337 ee->ee_scaled_cck_delta = (val >> 11) & 0x1f;
338 }
339 }
340
341 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
342 mode == AR5K_EEPROM_MODE_11A) {
343 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
344 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
345 }
346
347 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_0)
348 goto done;
349
350 /* Note: >= v5 have bg freq piers on another location
351 * so these freq piers are ignored for >= v5 (should be 0xff
352 * anyway) */
353 switch (mode) {
354 case AR5K_EEPROM_MODE_11A:
355 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_1)
356 break;
357
358 AR5K_EEPROM_READ(o++, val);
359 ee->ee_margin_tx_rx[mode] = val & 0x3f;
360 break;
361 case AR5K_EEPROM_MODE_11B:
362 AR5K_EEPROM_READ(o++, val);
363
364 ee->ee_pwr_cal_b[0].freq =
365 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
366 if (ee->ee_pwr_cal_b[0].freq != AR5K_EEPROM_CHANNEL_DIS)
367 ee->ee_n_piers[mode]++;
368
369 ee->ee_pwr_cal_b[1].freq =
370 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
371 if (ee->ee_pwr_cal_b[1].freq != AR5K_EEPROM_CHANNEL_DIS)
372 ee->ee_n_piers[mode]++;
373
374 AR5K_EEPROM_READ(o++, val);
375 ee->ee_pwr_cal_b[2].freq =
376 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
377 if (ee->ee_pwr_cal_b[2].freq != AR5K_EEPROM_CHANNEL_DIS)
378 ee->ee_n_piers[mode]++;
379
380 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
381 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
382 break;
383 case AR5K_EEPROM_MODE_11G:
384 AR5K_EEPROM_READ(o++, val);
385
386 ee->ee_pwr_cal_g[0].freq =
387 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
388 if (ee->ee_pwr_cal_g[0].freq != AR5K_EEPROM_CHANNEL_DIS)
389 ee->ee_n_piers[mode]++;
390
391 ee->ee_pwr_cal_g[1].freq =
392 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
393 if (ee->ee_pwr_cal_g[1].freq != AR5K_EEPROM_CHANNEL_DIS)
394 ee->ee_n_piers[mode]++;
395
396 AR5K_EEPROM_READ(o++, val);
397 ee->ee_turbo_max_power[mode] = val & 0x7f;
398 ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
399
400 AR5K_EEPROM_READ(o++, val);
401 ee->ee_pwr_cal_g[2].freq =
402 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
403 if (ee->ee_pwr_cal_g[2].freq != AR5K_EEPROM_CHANNEL_DIS)
404 ee->ee_n_piers[mode]++;
405
406 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
407 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
408
409 AR5K_EEPROM_READ(o++, val);
410 ee->ee_i_cal[mode] = (val >> 5) & 0x3f;
411 ee->ee_q_cal[mode] = val & 0x1f;
412
413 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) {
414 AR5K_EEPROM_READ(o++, val);
415 ee->ee_cck_ofdm_gain_delta = val & 0xff;
416 }
417 break;
418 }
419
420 /*
421 * Read turbo mode information on newer EEPROM versions
422 */
423 if (ee->ee_version < AR5K_EEPROM_VERSION_5_0)
424 goto done;
425
426 switch (mode) {
427 case AR5K_EEPROM_MODE_11A:
428 ee->ee_switch_settling_turbo[mode] = (val >> 6) & 0x7f;
429
430 ee->ee_atn_tx_rx_turbo[mode] = (val >> 13) & 0x7;
431 AR5K_EEPROM_READ(o++, val);
432 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x7) << 3;
433 ee->ee_margin_tx_rx_turbo[mode] = (val >> 3) & 0x3f;
434
435 ee->ee_adc_desired_size_turbo[mode] = (val >> 9) & 0x7f;
436 AR5K_EEPROM_READ(o++, val);
437 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x1) << 7;
438 ee->ee_pga_desired_size_turbo[mode] = (val >> 1) & 0xff;
439
440 if (AR5K_EEPROM_EEMAP(ee->ee_misc0) >= 2)
441 ee->ee_pd_gain_overlap = (val >> 9) & 0xf;
442 break;
443 case AR5K_EEPROM_MODE_11G:
444 ee->ee_switch_settling_turbo[mode] = (val >> 8) & 0x7f;
445
446 ee->ee_atn_tx_rx_turbo[mode] = (val >> 15) & 0x7;
447 AR5K_EEPROM_READ(o++, val);
448 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x1f) << 1;
449 ee->ee_margin_tx_rx_turbo[mode] = (val >> 5) & 0x3f;
450
451 ee->ee_adc_desired_size_turbo[mode] = (val >> 11) & 0x7f;
452 AR5K_EEPROM_READ(o++, val);
453 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x7) << 5;
454 ee->ee_pga_desired_size_turbo[mode] = (val >> 3) & 0xff;
455 break;
456 }
457
458 done:
459 /* return new offset */
460 *offset = o;
461
462 return 0;
463 }
464
465 /* Read mode-specific data (except power calibration data) */
466 static int
ath5k_eeprom_init_modes(struct ath5k_hw * ah)467 ath5k_eeprom_init_modes(struct ath5k_hw *ah)
468 {
469 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
470 u32 mode_offset[3];
471 unsigned int mode;
472 u32 offset;
473 int ret;
474
475 /*
476 * Get values for all modes
477 */
478 mode_offset[AR5K_EEPROM_MODE_11A] = AR5K_EEPROM_MODES_11A(ah->ah_ee_version);
479 mode_offset[AR5K_EEPROM_MODE_11B] = AR5K_EEPROM_MODES_11B(ah->ah_ee_version);
480 mode_offset[AR5K_EEPROM_MODE_11G] = AR5K_EEPROM_MODES_11G(ah->ah_ee_version);
481
482 ee->ee_turbo_max_power[AR5K_EEPROM_MODE_11A] =
483 AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
484
485 for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++) {
486 offset = mode_offset[mode];
487
488 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
489 if (ret)
490 return ret;
491
492 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
493 if (ret)
494 return ret;
495 }
496
497 /* override for older eeprom versions for better performance */
498 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) {
499 ee->ee_thr_62[AR5K_EEPROM_MODE_11A] = 15;
500 ee->ee_thr_62[AR5K_EEPROM_MODE_11B] = 28;
501 ee->ee_thr_62[AR5K_EEPROM_MODE_11G] = 28;
502 }
503
504 return 0;
505 }
506
507 /* Read the frequency piers for each mode (mostly used on newer eeproms with 0xff
508 * frequency mask) */
509 static inline int
ath5k_eeprom_read_freq_list(struct ath5k_hw * ah,int * offset,int max,struct ath5k_chan_pcal_info * pc,unsigned int mode)510 ath5k_eeprom_read_freq_list(struct ath5k_hw *ah, int *offset, int max,
511 struct ath5k_chan_pcal_info *pc, unsigned int mode)
512 {
513 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
514 int o = *offset;
515 int i = 0;
516 u8 freq1, freq2;
517 u16 val;
518
519 ee->ee_n_piers[mode] = 0;
520 while (i < max) {
521 AR5K_EEPROM_READ(o++, val);
522
523 freq1 = val & 0xff;
524 if (!freq1)
525 break;
526
527 pc[i++].freq = ath5k_eeprom_bin2freq(ee,
528 freq1, mode);
529 ee->ee_n_piers[mode]++;
530
531 freq2 = (val >> 8) & 0xff;
532 if (!freq2 || i >= max)
533 break;
534
535 pc[i++].freq = ath5k_eeprom_bin2freq(ee,
536 freq2, mode);
537 ee->ee_n_piers[mode]++;
538 }
539
540 /* return new offset */
541 *offset = o;
542
543 return 0;
544 }
545
546 /* Read frequency piers for 802.11a */
547 static int
ath5k_eeprom_init_11a_pcal_freq(struct ath5k_hw * ah,int offset)548 ath5k_eeprom_init_11a_pcal_freq(struct ath5k_hw *ah, int offset)
549 {
550 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
551 struct ath5k_chan_pcal_info *pcal = ee->ee_pwr_cal_a;
552 int i;
553 u16 val;
554 u8 mask;
555
556 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) {
557 ath5k_eeprom_read_freq_list(ah, &offset,
558 AR5K_EEPROM_N_5GHZ_CHAN, pcal,
559 AR5K_EEPROM_MODE_11A);
560 } else {
561 mask = AR5K_EEPROM_FREQ_M(ah->ah_ee_version);
562
563 AR5K_EEPROM_READ(offset++, val);
564 pcal[0].freq = (val >> 9) & mask;
565 pcal[1].freq = (val >> 2) & mask;
566 pcal[2].freq = (val << 5) & mask;
567
568 AR5K_EEPROM_READ(offset++, val);
569 pcal[2].freq |= (val >> 11) & 0x1f;
570 pcal[3].freq = (val >> 4) & mask;
571 pcal[4].freq = (val << 3) & mask;
572
573 AR5K_EEPROM_READ(offset++, val);
574 pcal[4].freq |= (val >> 13) & 0x7;
575 pcal[5].freq = (val >> 6) & mask;
576 pcal[6].freq = (val << 1) & mask;
577
578 AR5K_EEPROM_READ(offset++, val);
579 pcal[6].freq |= (val >> 15) & 0x1;
580 pcal[7].freq = (val >> 8) & mask;
581 pcal[8].freq = (val >> 1) & mask;
582 pcal[9].freq = (val << 6) & mask;
583
584 AR5K_EEPROM_READ(offset++, val);
585 pcal[9].freq |= (val >> 10) & 0x3f;
586
587 /* Fixed number of piers */
588 ee->ee_n_piers[AR5K_EEPROM_MODE_11A] = 10;
589
590 for (i = 0; i < AR5K_EEPROM_N_5GHZ_CHAN; i++) {
591 pcal[i].freq = ath5k_eeprom_bin2freq(ee,
592 pcal[i].freq, AR5K_EEPROM_MODE_11A);
593 }
594 }
595
596 return 0;
597 }
598
599 /* Read frequency piers for 802.11bg on eeprom versions >= 5 and eemap >= 2 */
600 static inline int
ath5k_eeprom_init_11bg_2413(struct ath5k_hw * ah,unsigned int mode,int offset)601 ath5k_eeprom_init_11bg_2413(struct ath5k_hw *ah, unsigned int mode, int offset)
602 {
603 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
604 struct ath5k_chan_pcal_info *pcal;
605
606 switch (mode) {
607 case AR5K_EEPROM_MODE_11B:
608 pcal = ee->ee_pwr_cal_b;
609 break;
610 case AR5K_EEPROM_MODE_11G:
611 pcal = ee->ee_pwr_cal_g;
612 break;
613 default:
614 return -EINVAL;
615 }
616
617 ath5k_eeprom_read_freq_list(ah, &offset,
618 AR5K_EEPROM_N_2GHZ_CHAN_2413, pcal,
619 mode);
620
621 return 0;
622 }
623
624
625 /*
626 * Read power calibration for RF5111 chips
627 *
628 * For RF5111 we have an XPD -eXternal Power Detector- curve
629 * for each calibrated channel. Each curve has 0,5dB Power steps
630 * on x axis and PCDAC steps (offsets) on y axis and looks like an
631 * exponential function. To recreate the curve we read 11 points
632 * here and interpolate later.
633 */
634
635 /* Used to match PCDAC steps with power values on RF5111 chips
636 * (eeprom versions < 4). For RF5111 we have 11 pre-defined PCDAC
637 * steps that match with the power values we read from eeprom. On
638 * older eeprom versions (< 3.2) these steps are equally spaced at
639 * 10% of the pcdac curve -until the curve reaches its maximum-
640 * (11 steps from 0 to 100%) but on newer eeprom versions (>= 3.2)
641 * these 11 steps are spaced in a different way. This function returns
642 * the pcdac steps based on eeprom version and curve min/max so that we
643 * can have pcdac/pwr points.
644 */
645 static inline void
ath5k_get_pcdac_intercepts(struct ath5k_hw * ah,u8 min,u8 max,u8 * vp)646 ath5k_get_pcdac_intercepts(struct ath5k_hw *ah, u8 min, u8 max, u8 *vp)
647 {
648 static const u16 intercepts3[] = {
649 0, 5, 10, 20, 30, 50, 70, 85, 90, 95, 100
650 };
651 static const u16 intercepts3_2[] = {
652 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100
653 };
654 const u16 *ip;
655 int i;
656
657 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_2)
658 ip = intercepts3_2;
659 else
660 ip = intercepts3;
661
662 for (i = 0; i < ARRAY_SIZE(intercepts3); i++)
663 vp[i] = (ip[i] * max + (100 - ip[i]) * min) / 100;
664 }
665
666 static int
ath5k_eeprom_free_pcal_info(struct ath5k_hw * ah,int mode)667 ath5k_eeprom_free_pcal_info(struct ath5k_hw *ah, int mode)
668 {
669 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
670 struct ath5k_chan_pcal_info *chinfo;
671 u8 pier, pdg;
672
673 switch (mode) {
674 case AR5K_EEPROM_MODE_11A:
675 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
676 return 0;
677 chinfo = ee->ee_pwr_cal_a;
678 break;
679 case AR5K_EEPROM_MODE_11B:
680 if (!AR5K_EEPROM_HDR_11B(ee->ee_header))
681 return 0;
682 chinfo = ee->ee_pwr_cal_b;
683 break;
684 case AR5K_EEPROM_MODE_11G:
685 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
686 return 0;
687 chinfo = ee->ee_pwr_cal_g;
688 break;
689 default:
690 return -EINVAL;
691 }
692
693 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
694 if (!chinfo[pier].pd_curves)
695 continue;
696
697 for (pdg = 0; pdg < AR5K_EEPROM_N_PD_CURVES; pdg++) {
698 struct ath5k_pdgain_info *pd =
699 &chinfo[pier].pd_curves[pdg];
700
701 kfree(pd->pd_step);
702 kfree(pd->pd_pwr);
703 }
704
705 kfree(chinfo[pier].pd_curves);
706 }
707
708 return 0;
709 }
710
711 /* Convert RF5111 specific data to generic raw data
712 * used by interpolation code */
713 static int
ath5k_eeprom_convert_pcal_info_5111(struct ath5k_hw * ah,int mode,struct ath5k_chan_pcal_info * chinfo)714 ath5k_eeprom_convert_pcal_info_5111(struct ath5k_hw *ah, int mode,
715 struct ath5k_chan_pcal_info *chinfo)
716 {
717 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
718 struct ath5k_chan_pcal_info_rf5111 *pcinfo;
719 struct ath5k_pdgain_info *pd;
720 u8 pier, point, idx;
721 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
722
723 /* Fill raw data for each calibration pier */
724 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
725
726 pcinfo = &chinfo[pier].rf5111_info;
727
728 /* Allocate pd_curves for this cal pier */
729 chinfo[pier].pd_curves =
730 kzalloc_objs(struct ath5k_pdgain_info,
731 AR5K_EEPROM_N_PD_CURVES);
732
733 if (!chinfo[pier].pd_curves)
734 goto err_out;
735
736 /* Only one curve for RF5111
737 * find out which one and place
738 * in pd_curves.
739 * Note: ee_x_gain is reversed here */
740 for (idx = 0; idx < AR5K_EEPROM_N_PD_CURVES; idx++) {
741
742 if (!((ee->ee_x_gain[mode] >> idx) & 0x1)) {
743 pdgain_idx[0] = idx;
744 break;
745 }
746 }
747
748 if (idx == AR5K_EEPROM_N_PD_CURVES)
749 goto err_out;
750
751 ee->ee_pd_gains[mode] = 1;
752
753 pd = &chinfo[pier].pd_curves[idx];
754
755 pd->pd_points = AR5K_EEPROM_N_PWR_POINTS_5111;
756
757 /* Allocate pd points for this curve */
758 pd->pd_step = kcalloc(AR5K_EEPROM_N_PWR_POINTS_5111,
759 sizeof(u8), GFP_KERNEL);
760 if (!pd->pd_step)
761 goto err_out;
762
763 pd->pd_pwr = kzalloc_objs(s16, AR5K_EEPROM_N_PWR_POINTS_5111);
764 if (!pd->pd_pwr)
765 goto err_out;
766
767 /* Fill raw dataset
768 * (convert power to 0.25dB units
769 * for RF5112 compatibility) */
770 for (point = 0; point < pd->pd_points; point++) {
771
772 /* Absolute values */
773 pd->pd_pwr[point] = 2 * pcinfo->pwr[point];
774
775 /* Already sorted */
776 pd->pd_step[point] = pcinfo->pcdac[point];
777 }
778
779 /* Set min/max pwr */
780 chinfo[pier].min_pwr = pd->pd_pwr[0];
781 chinfo[pier].max_pwr = pd->pd_pwr[10];
782
783 }
784
785 return 0;
786
787 err_out:
788 ath5k_eeprom_free_pcal_info(ah, mode);
789 return -ENOMEM;
790 }
791
792 /* Parse EEPROM data */
793 static int
ath5k_eeprom_read_pcal_info_5111(struct ath5k_hw * ah,int mode)794 ath5k_eeprom_read_pcal_info_5111(struct ath5k_hw *ah, int mode)
795 {
796 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
797 struct ath5k_chan_pcal_info *pcal;
798 int offset, ret;
799 int i;
800 u16 val;
801
802 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
803 switch (mode) {
804 case AR5K_EEPROM_MODE_11A:
805 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
806 return 0;
807
808 ret = ath5k_eeprom_init_11a_pcal_freq(ah,
809 offset + AR5K_EEPROM_GROUP1_OFFSET);
810 if (ret < 0)
811 return ret;
812
813 offset += AR5K_EEPROM_GROUP2_OFFSET;
814 pcal = ee->ee_pwr_cal_a;
815 break;
816 case AR5K_EEPROM_MODE_11B:
817 if (!AR5K_EEPROM_HDR_11B(ee->ee_header) &&
818 !AR5K_EEPROM_HDR_11G(ee->ee_header))
819 return 0;
820
821 pcal = ee->ee_pwr_cal_b;
822 offset += AR5K_EEPROM_GROUP3_OFFSET;
823
824 /* fixed piers */
825 pcal[0].freq = 2412;
826 pcal[1].freq = 2447;
827 pcal[2].freq = 2484;
828 ee->ee_n_piers[mode] = 3;
829 break;
830 case AR5K_EEPROM_MODE_11G:
831 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
832 return 0;
833
834 pcal = ee->ee_pwr_cal_g;
835 offset += AR5K_EEPROM_GROUP4_OFFSET;
836
837 /* fixed piers */
838 pcal[0].freq = 2312;
839 pcal[1].freq = 2412;
840 pcal[2].freq = 2484;
841 ee->ee_n_piers[mode] = 3;
842 break;
843 default:
844 return -EINVAL;
845 }
846
847 for (i = 0; i < ee->ee_n_piers[mode]; i++) {
848 struct ath5k_chan_pcal_info_rf5111 *cdata =
849 &pcal[i].rf5111_info;
850
851 AR5K_EEPROM_READ(offset++, val);
852 cdata->pcdac_max = ((val >> 10) & AR5K_EEPROM_PCDAC_M);
853 cdata->pcdac_min = ((val >> 4) & AR5K_EEPROM_PCDAC_M);
854 cdata->pwr[0] = ((val << 2) & AR5K_EEPROM_POWER_M);
855
856 AR5K_EEPROM_READ(offset++, val);
857 cdata->pwr[0] |= ((val >> 14) & 0x3);
858 cdata->pwr[1] = ((val >> 8) & AR5K_EEPROM_POWER_M);
859 cdata->pwr[2] = ((val >> 2) & AR5K_EEPROM_POWER_M);
860 cdata->pwr[3] = ((val << 4) & AR5K_EEPROM_POWER_M);
861
862 AR5K_EEPROM_READ(offset++, val);
863 cdata->pwr[3] |= ((val >> 12) & 0xf);
864 cdata->pwr[4] = ((val >> 6) & AR5K_EEPROM_POWER_M);
865 cdata->pwr[5] = (val & AR5K_EEPROM_POWER_M);
866
867 AR5K_EEPROM_READ(offset++, val);
868 cdata->pwr[6] = ((val >> 10) & AR5K_EEPROM_POWER_M);
869 cdata->pwr[7] = ((val >> 4) & AR5K_EEPROM_POWER_M);
870 cdata->pwr[8] = ((val << 2) & AR5K_EEPROM_POWER_M);
871
872 AR5K_EEPROM_READ(offset++, val);
873 cdata->pwr[8] |= ((val >> 14) & 0x3);
874 cdata->pwr[9] = ((val >> 8) & AR5K_EEPROM_POWER_M);
875 cdata->pwr[10] = ((val >> 2) & AR5K_EEPROM_POWER_M);
876
877 ath5k_get_pcdac_intercepts(ah, cdata->pcdac_min,
878 cdata->pcdac_max, cdata->pcdac);
879 }
880
881 return ath5k_eeprom_convert_pcal_info_5111(ah, mode, pcal);
882 }
883
884
885 /*
886 * Read power calibration for RF5112 chips
887 *
888 * For RF5112 we have 4 XPD -eXternal Power Detector- curves
889 * for each calibrated channel on 0, -6, -12 and -18dBm but we only
890 * use the higher (3) and the lower (0) curves. Each curve has 0.5dB
891 * power steps on x axis and PCDAC steps on y axis and looks like a
892 * linear function. To recreate the curve and pass the power values
893 * on hw, we read 4 points for xpd 0 (lower gain -> max power)
894 * and 3 points for xpd 3 (higher gain -> lower power) here and
895 * interpolate later.
896 *
897 * Note: Many vendors just use xpd 0 so xpd 3 is zeroed.
898 */
899
900 /* Convert RF5112 specific data to generic raw data
901 * used by interpolation code */
902 static int
ath5k_eeprom_convert_pcal_info_5112(struct ath5k_hw * ah,int mode,struct ath5k_chan_pcal_info * chinfo)903 ath5k_eeprom_convert_pcal_info_5112(struct ath5k_hw *ah, int mode,
904 struct ath5k_chan_pcal_info *chinfo)
905 {
906 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
907 struct ath5k_chan_pcal_info_rf5112 *pcinfo;
908 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
909 unsigned int pier, pdg, point;
910
911 /* Fill raw data for each calibration pier */
912 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
913
914 pcinfo = &chinfo[pier].rf5112_info;
915
916 /* Allocate pd_curves for this cal pier */
917 chinfo[pier].pd_curves =
918 kzalloc_objs(struct ath5k_pdgain_info,
919 AR5K_EEPROM_N_PD_CURVES);
920
921 if (!chinfo[pier].pd_curves)
922 goto err_out;
923
924 /* Fill pd_curves */
925 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
926
927 u8 idx = pdgain_idx[pdg];
928 struct ath5k_pdgain_info *pd =
929 &chinfo[pier].pd_curves[idx];
930
931 /* Lowest gain curve (max power) */
932 if (pdg == 0) {
933 /* One more point for better accuracy */
934 pd->pd_points = AR5K_EEPROM_N_XPD0_POINTS;
935
936 /* Allocate pd points for this curve */
937 pd->pd_step = kcalloc(pd->pd_points,
938 sizeof(u8), GFP_KERNEL);
939
940 if (!pd->pd_step)
941 goto err_out;
942
943 pd->pd_pwr = kzalloc_objs(s16, pd->pd_points);
944
945 if (!pd->pd_pwr)
946 goto err_out;
947
948 /* Fill raw dataset
949 * (all power levels are in 0.25dB units) */
950 pd->pd_step[0] = pcinfo->pcdac_x0[0];
951 pd->pd_pwr[0] = pcinfo->pwr_x0[0];
952
953 for (point = 1; point < pd->pd_points;
954 point++) {
955 /* Absolute values */
956 pd->pd_pwr[point] =
957 pcinfo->pwr_x0[point];
958
959 /* Deltas */
960 pd->pd_step[point] =
961 pd->pd_step[point - 1] +
962 pcinfo->pcdac_x0[point];
963 }
964
965 /* Set min power for this frequency */
966 chinfo[pier].min_pwr = pd->pd_pwr[0];
967
968 /* Highest gain curve (min power) */
969 } else if (pdg == 1) {
970
971 pd->pd_points = AR5K_EEPROM_N_XPD3_POINTS;
972
973 /* Allocate pd points for this curve */
974 pd->pd_step = kcalloc(pd->pd_points,
975 sizeof(u8), GFP_KERNEL);
976
977 if (!pd->pd_step)
978 goto err_out;
979
980 pd->pd_pwr = kzalloc_objs(s16, pd->pd_points);
981
982 if (!pd->pd_pwr)
983 goto err_out;
984
985 /* Fill raw dataset
986 * (all power levels are in 0.25dB units) */
987 for (point = 0; point < pd->pd_points;
988 point++) {
989 /* Absolute values */
990 pd->pd_pwr[point] =
991 pcinfo->pwr_x3[point];
992
993 /* Fixed points */
994 pd->pd_step[point] =
995 pcinfo->pcdac_x3[point];
996 }
997
998 /* Since we have a higher gain curve
999 * override min power */
1000 chinfo[pier].min_pwr = pd->pd_pwr[0];
1001 }
1002 }
1003 }
1004
1005 return 0;
1006
1007 err_out:
1008 ath5k_eeprom_free_pcal_info(ah, mode);
1009 return -ENOMEM;
1010 }
1011
1012 /* Parse EEPROM data */
1013 static int
ath5k_eeprom_read_pcal_info_5112(struct ath5k_hw * ah,int mode)1014 ath5k_eeprom_read_pcal_info_5112(struct ath5k_hw *ah, int mode)
1015 {
1016 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1017 struct ath5k_chan_pcal_info_rf5112 *chan_pcal_info;
1018 struct ath5k_chan_pcal_info *gen_chan_info;
1019 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
1020 u32 offset;
1021 u8 i, c;
1022 u16 val;
1023 u8 pd_gains = 0;
1024
1025 /* Count how many curves we have and
1026 * identify them (which one of the 4
1027 * available curves we have on each count).
1028 * Curves are stored from lower (x0) to
1029 * higher (x3) gain */
1030 for (i = 0; i < AR5K_EEPROM_N_PD_CURVES; i++) {
1031 /* ee_x_gain[mode] is x gain mask */
1032 if ((ee->ee_x_gain[mode] >> i) & 0x1)
1033 pdgain_idx[pd_gains++] = i;
1034 }
1035 ee->ee_pd_gains[mode] = pd_gains;
1036
1037 if (pd_gains == 0 || pd_gains > 2)
1038 return -EINVAL;
1039
1040 switch (mode) {
1041 case AR5K_EEPROM_MODE_11A:
1042 /*
1043 * Read 5GHz EEPROM channels
1044 */
1045 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
1046 ath5k_eeprom_init_11a_pcal_freq(ah, offset);
1047
1048 offset += AR5K_EEPROM_GROUP2_OFFSET;
1049 gen_chan_info = ee->ee_pwr_cal_a;
1050 break;
1051 case AR5K_EEPROM_MODE_11B:
1052 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
1053 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
1054 offset += AR5K_EEPROM_GROUP3_OFFSET;
1055
1056 /* NB: frequency piers parsed during mode init */
1057 gen_chan_info = ee->ee_pwr_cal_b;
1058 break;
1059 case AR5K_EEPROM_MODE_11G:
1060 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
1061 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
1062 offset += AR5K_EEPROM_GROUP4_OFFSET;
1063 else if (AR5K_EEPROM_HDR_11B(ee->ee_header))
1064 offset += AR5K_EEPROM_GROUP2_OFFSET;
1065
1066 /* NB: frequency piers parsed during mode init */
1067 gen_chan_info = ee->ee_pwr_cal_g;
1068 break;
1069 default:
1070 return -EINVAL;
1071 }
1072
1073 for (i = 0; i < ee->ee_n_piers[mode]; i++) {
1074 chan_pcal_info = &gen_chan_info[i].rf5112_info;
1075
1076 /* Power values in quarter dB
1077 * for the lower xpd gain curve
1078 * (0 dBm -> higher output power) */
1079 for (c = 0; c < AR5K_EEPROM_N_XPD0_POINTS; c++) {
1080 AR5K_EEPROM_READ(offset++, val);
1081 chan_pcal_info->pwr_x0[c] = (s8) (val & 0xff);
1082 chan_pcal_info->pwr_x0[++c] = (s8) ((val >> 8) & 0xff);
1083 }
1084
1085 /* PCDAC steps
1086 * corresponding to the above power
1087 * measurements */
1088 AR5K_EEPROM_READ(offset++, val);
1089 chan_pcal_info->pcdac_x0[1] = (val & 0x1f);
1090 chan_pcal_info->pcdac_x0[2] = ((val >> 5) & 0x1f);
1091 chan_pcal_info->pcdac_x0[3] = ((val >> 10) & 0x1f);
1092
1093 /* Power values in quarter dB
1094 * for the higher xpd gain curve
1095 * (18 dBm -> lower output power) */
1096 AR5K_EEPROM_READ(offset++, val);
1097 chan_pcal_info->pwr_x3[0] = (s8) (val & 0xff);
1098 chan_pcal_info->pwr_x3[1] = (s8) ((val >> 8) & 0xff);
1099
1100 AR5K_EEPROM_READ(offset++, val);
1101 chan_pcal_info->pwr_x3[2] = (val & 0xff);
1102
1103 /* PCDAC steps
1104 * corresponding to the above power
1105 * measurements (fixed) */
1106 chan_pcal_info->pcdac_x3[0] = 20;
1107 chan_pcal_info->pcdac_x3[1] = 35;
1108 chan_pcal_info->pcdac_x3[2] = 63;
1109
1110 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3) {
1111 chan_pcal_info->pcdac_x0[0] = ((val >> 8) & 0x3f);
1112
1113 /* Last xpd0 power level is also channel maximum */
1114 gen_chan_info[i].max_pwr = chan_pcal_info->pwr_x0[3];
1115 } else {
1116 chan_pcal_info->pcdac_x0[0] = 1;
1117 gen_chan_info[i].max_pwr = (s8) ((val >> 8) & 0xff);
1118 }
1119
1120 }
1121
1122 return ath5k_eeprom_convert_pcal_info_5112(ah, mode, gen_chan_info);
1123 }
1124
1125
1126 /*
1127 * Read power calibration for RF2413 chips
1128 *
1129 * For RF2413 we have a Power to PDDAC table (Power Detector)
1130 * instead of a PCDAC and 4 pd gain curves for each calibrated channel.
1131 * Each curve has power on x axis in 0.5 db steps and PDDADC steps on y
1132 * axis and looks like an exponential function like the RF5111 curve.
1133 *
1134 * To recreate the curves we read here the points and interpolate
1135 * later. Note that in most cases only 2 (higher and lower) curves are
1136 * used (like RF5112) but vendors have the opportunity to include all
1137 * 4 curves on eeprom. The final curve (higher power) has an extra
1138 * point for better accuracy like RF5112.
1139 */
1140
1141 /* For RF2413 power calibration data doesn't start on a fixed location and
1142 * if a mode is not supported, its section is missing -not zeroed-.
1143 * So we need to calculate the starting offset for each section by using
1144 * these two functions */
1145
1146 /* Return the size of each section based on the mode and the number of pd
1147 * gains available (maximum 4). */
1148 static inline unsigned int
ath5k_pdgains_size_2413(struct ath5k_eeprom_info * ee,unsigned int mode)1149 ath5k_pdgains_size_2413(struct ath5k_eeprom_info *ee, unsigned int mode)
1150 {
1151 static const unsigned int pdgains_size[] = { 4, 6, 9, 12 };
1152 unsigned int sz;
1153
1154 sz = pdgains_size[ee->ee_pd_gains[mode] - 1];
1155 sz *= ee->ee_n_piers[mode];
1156
1157 return sz;
1158 }
1159
1160 /* Return the starting offset for a section based on the modes supported
1161 * and each section's size. */
1162 static unsigned int
ath5k_cal_data_offset_2413(struct ath5k_eeprom_info * ee,int mode)1163 ath5k_cal_data_offset_2413(struct ath5k_eeprom_info *ee, int mode)
1164 {
1165 u32 offset = AR5K_EEPROM_CAL_DATA_START(ee->ee_misc4);
1166
1167 switch (mode) {
1168 case AR5K_EEPROM_MODE_11G:
1169 if (AR5K_EEPROM_HDR_11B(ee->ee_header))
1170 offset += ath5k_pdgains_size_2413(ee,
1171 AR5K_EEPROM_MODE_11B) +
1172 AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
1173 fallthrough;
1174 case AR5K_EEPROM_MODE_11B:
1175 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
1176 offset += ath5k_pdgains_size_2413(ee,
1177 AR5K_EEPROM_MODE_11A) +
1178 AR5K_EEPROM_N_5GHZ_CHAN / 2;
1179 fallthrough;
1180 case AR5K_EEPROM_MODE_11A:
1181 break;
1182 default:
1183 break;
1184 }
1185
1186 return offset;
1187 }
1188
1189 /* Convert RF2413 specific data to generic raw data
1190 * used by interpolation code */
1191 static int
ath5k_eeprom_convert_pcal_info_2413(struct ath5k_hw * ah,int mode,struct ath5k_chan_pcal_info * chinfo)1192 ath5k_eeprom_convert_pcal_info_2413(struct ath5k_hw *ah, int mode,
1193 struct ath5k_chan_pcal_info *chinfo)
1194 {
1195 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1196 struct ath5k_chan_pcal_info_rf2413 *pcinfo;
1197 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
1198 unsigned int pier, pdg, point;
1199
1200 /* Fill raw data for each calibration pier */
1201 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
1202
1203 pcinfo = &chinfo[pier].rf2413_info;
1204
1205 /* Allocate pd_curves for this cal pier */
1206 chinfo[pier].pd_curves =
1207 kzalloc_objs(struct ath5k_pdgain_info,
1208 AR5K_EEPROM_N_PD_CURVES);
1209
1210 if (!chinfo[pier].pd_curves)
1211 goto err_out;
1212
1213 /* Fill pd_curves */
1214 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
1215
1216 u8 idx = pdgain_idx[pdg];
1217 struct ath5k_pdgain_info *pd =
1218 &chinfo[pier].pd_curves[idx];
1219
1220 /* One more point for the highest power
1221 * curve (lowest gain) */
1222 if (pdg == ee->ee_pd_gains[mode] - 1)
1223 pd->pd_points = AR5K_EEPROM_N_PD_POINTS;
1224 else
1225 pd->pd_points = AR5K_EEPROM_N_PD_POINTS - 1;
1226
1227 /* Allocate pd points for this curve */
1228 pd->pd_step = kcalloc(pd->pd_points,
1229 sizeof(u8), GFP_KERNEL);
1230
1231 if (!pd->pd_step)
1232 goto err_out;
1233
1234 pd->pd_pwr = kzalloc_objs(s16, pd->pd_points);
1235
1236 if (!pd->pd_pwr)
1237 goto err_out;
1238
1239 /* Fill raw dataset
1240 * convert all pwr levels to
1241 * quarter dB for RF5112 compatibility */
1242 pd->pd_step[0] = pcinfo->pddac_i[pdg];
1243 pd->pd_pwr[0] = 4 * pcinfo->pwr_i[pdg];
1244
1245 for (point = 1; point < pd->pd_points; point++) {
1246
1247 pd->pd_pwr[point] = pd->pd_pwr[point - 1] +
1248 2 * pcinfo->pwr[pdg][point - 1];
1249
1250 pd->pd_step[point] = pd->pd_step[point - 1] +
1251 pcinfo->pddac[pdg][point - 1];
1252
1253 }
1254
1255 /* Highest gain curve -> min power */
1256 if (pdg == 0)
1257 chinfo[pier].min_pwr = pd->pd_pwr[0];
1258
1259 /* Lowest gain curve -> max power */
1260 if (pdg == ee->ee_pd_gains[mode] - 1)
1261 chinfo[pier].max_pwr =
1262 pd->pd_pwr[pd->pd_points - 1];
1263 }
1264 }
1265
1266 return 0;
1267
1268 err_out:
1269 ath5k_eeprom_free_pcal_info(ah, mode);
1270 return -ENOMEM;
1271 }
1272
1273 /* Parse EEPROM data */
1274 static int
ath5k_eeprom_read_pcal_info_2413(struct ath5k_hw * ah,int mode)1275 ath5k_eeprom_read_pcal_info_2413(struct ath5k_hw *ah, int mode)
1276 {
1277 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1278 struct ath5k_chan_pcal_info_rf2413 *pcinfo;
1279 struct ath5k_chan_pcal_info *chinfo;
1280 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
1281 u32 offset;
1282 int idx, i;
1283 u16 val;
1284 u8 pd_gains = 0;
1285
1286 /* Count how many curves we have and
1287 * identify them (which one of the 4
1288 * available curves we have on each count).
1289 * Curves are stored from higher to
1290 * lower gain so we go backwards */
1291 for (idx = AR5K_EEPROM_N_PD_CURVES - 1; idx >= 0; idx--) {
1292 /* ee_x_gain[mode] is x gain mask */
1293 if ((ee->ee_x_gain[mode] >> idx) & 0x1)
1294 pdgain_idx[pd_gains++] = idx;
1295
1296 }
1297 ee->ee_pd_gains[mode] = pd_gains;
1298
1299 if (pd_gains == 0)
1300 return -EINVAL;
1301
1302 offset = ath5k_cal_data_offset_2413(ee, mode);
1303 switch (mode) {
1304 case AR5K_EEPROM_MODE_11A:
1305 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
1306 return 0;
1307
1308 ath5k_eeprom_init_11a_pcal_freq(ah, offset);
1309 offset += AR5K_EEPROM_N_5GHZ_CHAN / 2;
1310 chinfo = ee->ee_pwr_cal_a;
1311 break;
1312 case AR5K_EEPROM_MODE_11B:
1313 if (!AR5K_EEPROM_HDR_11B(ee->ee_header))
1314 return 0;
1315
1316 ath5k_eeprom_init_11bg_2413(ah, mode, offset);
1317 offset += AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
1318 chinfo = ee->ee_pwr_cal_b;
1319 break;
1320 case AR5K_EEPROM_MODE_11G:
1321 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
1322 return 0;
1323
1324 ath5k_eeprom_init_11bg_2413(ah, mode, offset);
1325 offset += AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
1326 chinfo = ee->ee_pwr_cal_g;
1327 break;
1328 default:
1329 return -EINVAL;
1330 }
1331
1332 for (i = 0; i < ee->ee_n_piers[mode]; i++) {
1333 pcinfo = &chinfo[i].rf2413_info;
1334
1335 /*
1336 * Read pwr_i, pddac_i and the first
1337 * 2 pd points (pwr, pddac)
1338 */
1339 AR5K_EEPROM_READ(offset++, val);
1340 pcinfo->pwr_i[0] = val & 0x1f;
1341 pcinfo->pddac_i[0] = (val >> 5) & 0x7f;
1342 pcinfo->pwr[0][0] = (val >> 12) & 0xf;
1343
1344 AR5K_EEPROM_READ(offset++, val);
1345 pcinfo->pddac[0][0] = val & 0x3f;
1346 pcinfo->pwr[0][1] = (val >> 6) & 0xf;
1347 pcinfo->pddac[0][1] = (val >> 10) & 0x3f;
1348
1349 AR5K_EEPROM_READ(offset++, val);
1350 pcinfo->pwr[0][2] = val & 0xf;
1351 pcinfo->pddac[0][2] = (val >> 4) & 0x3f;
1352
1353 pcinfo->pwr[0][3] = 0;
1354 pcinfo->pddac[0][3] = 0;
1355
1356 if (pd_gains > 1) {
1357 /*
1358 * Pd gain 0 is not the last pd gain
1359 * so it only has 2 pd points.
1360 * Continue with pd gain 1.
1361 */
1362 pcinfo->pwr_i[1] = (val >> 10) & 0x1f;
1363
1364 pcinfo->pddac_i[1] = (val >> 15) & 0x1;
1365 AR5K_EEPROM_READ(offset++, val);
1366 pcinfo->pddac_i[1] |= (val & 0x3F) << 1;
1367
1368 pcinfo->pwr[1][0] = (val >> 6) & 0xf;
1369 pcinfo->pddac[1][0] = (val >> 10) & 0x3f;
1370
1371 AR5K_EEPROM_READ(offset++, val);
1372 pcinfo->pwr[1][1] = val & 0xf;
1373 pcinfo->pddac[1][1] = (val >> 4) & 0x3f;
1374 pcinfo->pwr[1][2] = (val >> 10) & 0xf;
1375
1376 pcinfo->pddac[1][2] = (val >> 14) & 0x3;
1377 AR5K_EEPROM_READ(offset++, val);
1378 pcinfo->pddac[1][2] |= (val & 0xF) << 2;
1379
1380 pcinfo->pwr[1][3] = 0;
1381 pcinfo->pddac[1][3] = 0;
1382 } else if (pd_gains == 1) {
1383 /*
1384 * Pd gain 0 is the last one so
1385 * read the extra point.
1386 */
1387 pcinfo->pwr[0][3] = (val >> 10) & 0xf;
1388
1389 pcinfo->pddac[0][3] = (val >> 14) & 0x3;
1390 AR5K_EEPROM_READ(offset++, val);
1391 pcinfo->pddac[0][3] |= (val & 0xF) << 2;
1392 }
1393
1394 /*
1395 * Proceed with the other pd_gains
1396 * as above.
1397 */
1398 if (pd_gains > 2) {
1399 pcinfo->pwr_i[2] = (val >> 4) & 0x1f;
1400 pcinfo->pddac_i[2] = (val >> 9) & 0x7f;
1401
1402 AR5K_EEPROM_READ(offset++, val);
1403 pcinfo->pwr[2][0] = (val >> 0) & 0xf;
1404 pcinfo->pddac[2][0] = (val >> 4) & 0x3f;
1405 pcinfo->pwr[2][1] = (val >> 10) & 0xf;
1406
1407 pcinfo->pddac[2][1] = (val >> 14) & 0x3;
1408 AR5K_EEPROM_READ(offset++, val);
1409 pcinfo->pddac[2][1] |= (val & 0xF) << 2;
1410
1411 pcinfo->pwr[2][2] = (val >> 4) & 0xf;
1412 pcinfo->pddac[2][2] = (val >> 8) & 0x3f;
1413
1414 pcinfo->pwr[2][3] = 0;
1415 pcinfo->pddac[2][3] = 0;
1416 } else if (pd_gains == 2) {
1417 pcinfo->pwr[1][3] = (val >> 4) & 0xf;
1418 pcinfo->pddac[1][3] = (val >> 8) & 0x3f;
1419 }
1420
1421 if (pd_gains > 3) {
1422 pcinfo->pwr_i[3] = (val >> 14) & 0x3;
1423 AR5K_EEPROM_READ(offset++, val);
1424 pcinfo->pwr_i[3] |= ((val >> 0) & 0x7) << 2;
1425
1426 pcinfo->pddac_i[3] = (val >> 3) & 0x7f;
1427 pcinfo->pwr[3][0] = (val >> 10) & 0xf;
1428 pcinfo->pddac[3][0] = (val >> 14) & 0x3;
1429
1430 AR5K_EEPROM_READ(offset++, val);
1431 pcinfo->pddac[3][0] |= (val & 0xF) << 2;
1432 pcinfo->pwr[3][1] = (val >> 4) & 0xf;
1433 pcinfo->pddac[3][1] = (val >> 8) & 0x3f;
1434
1435 pcinfo->pwr[3][2] = (val >> 14) & 0x3;
1436 AR5K_EEPROM_READ(offset++, val);
1437 pcinfo->pwr[3][2] |= ((val >> 0) & 0x3) << 2;
1438
1439 pcinfo->pddac[3][2] = (val >> 2) & 0x3f;
1440 pcinfo->pwr[3][3] = (val >> 8) & 0xf;
1441
1442 pcinfo->pddac[3][3] = (val >> 12) & 0xF;
1443 AR5K_EEPROM_READ(offset++, val);
1444 pcinfo->pddac[3][3] |= ((val >> 0) & 0x3) << 4;
1445 } else if (pd_gains == 3) {
1446 pcinfo->pwr[2][3] = (val >> 14) & 0x3;
1447 AR5K_EEPROM_READ(offset++, val);
1448 pcinfo->pwr[2][3] |= ((val >> 0) & 0x3) << 2;
1449
1450 pcinfo->pddac[2][3] = (val >> 2) & 0x3f;
1451 }
1452 }
1453
1454 return ath5k_eeprom_convert_pcal_info_2413(ah, mode, chinfo);
1455 }
1456
1457
1458 /*
1459 * Read per rate target power (this is the maximum tx power
1460 * supported by the card). This info is used when setting
1461 * tx power, no matter the channel.
1462 *
1463 * This also works for v5 EEPROMs.
1464 */
1465 static int
ath5k_eeprom_read_target_rate_pwr_info(struct ath5k_hw * ah,unsigned int mode)1466 ath5k_eeprom_read_target_rate_pwr_info(struct ath5k_hw *ah, unsigned int mode)
1467 {
1468 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1469 struct ath5k_rate_pcal_info *rate_pcal_info;
1470 u8 *rate_target_pwr_num;
1471 u32 offset;
1472 u16 val;
1473 int i;
1474
1475 offset = AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1);
1476 rate_target_pwr_num = &ee->ee_rate_target_pwr_num[mode];
1477 switch (mode) {
1478 case AR5K_EEPROM_MODE_11A:
1479 offset += AR5K_EEPROM_TARGET_PWR_OFF_11A(ee->ee_version);
1480 rate_pcal_info = ee->ee_rate_tpwr_a;
1481 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_5GHZ_RATE_CHAN;
1482 break;
1483 case AR5K_EEPROM_MODE_11B:
1484 offset += AR5K_EEPROM_TARGET_PWR_OFF_11B(ee->ee_version);
1485 rate_pcal_info = ee->ee_rate_tpwr_b;
1486 ee->ee_rate_target_pwr_num[mode] = 2; /* 3rd is g mode's 1st */
1487 break;
1488 case AR5K_EEPROM_MODE_11G:
1489 offset += AR5K_EEPROM_TARGET_PWR_OFF_11G(ee->ee_version);
1490 rate_pcal_info = ee->ee_rate_tpwr_g;
1491 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_2GHZ_CHAN;
1492 break;
1493 default:
1494 return -EINVAL;
1495 }
1496
1497 /* Different freq mask for older eeproms (<= v3.2) */
1498 if (ee->ee_version <= AR5K_EEPROM_VERSION_3_2) {
1499 for (i = 0; i < (*rate_target_pwr_num); i++) {
1500 AR5K_EEPROM_READ(offset++, val);
1501 rate_pcal_info[i].freq =
1502 ath5k_eeprom_bin2freq(ee, (val >> 9) & 0x7f, mode);
1503
1504 rate_pcal_info[i].target_power_6to24 = ((val >> 3) & 0x3f);
1505 rate_pcal_info[i].target_power_36 = (val << 3) & 0x3f;
1506
1507 AR5K_EEPROM_READ(offset++, val);
1508
1509 if (rate_pcal_info[i].freq == AR5K_EEPROM_CHANNEL_DIS ||
1510 val == 0) {
1511 (*rate_target_pwr_num) = i;
1512 break;
1513 }
1514
1515 rate_pcal_info[i].target_power_36 |= ((val >> 13) & 0x7);
1516 rate_pcal_info[i].target_power_48 = ((val >> 7) & 0x3f);
1517 rate_pcal_info[i].target_power_54 = ((val >> 1) & 0x3f);
1518 }
1519 } else {
1520 for (i = 0; i < (*rate_target_pwr_num); i++) {
1521 AR5K_EEPROM_READ(offset++, val);
1522 rate_pcal_info[i].freq =
1523 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
1524
1525 rate_pcal_info[i].target_power_6to24 = ((val >> 2) & 0x3f);
1526 rate_pcal_info[i].target_power_36 = (val << 4) & 0x3f;
1527
1528 AR5K_EEPROM_READ(offset++, val);
1529
1530 if (rate_pcal_info[i].freq == AR5K_EEPROM_CHANNEL_DIS ||
1531 val == 0) {
1532 (*rate_target_pwr_num) = i;
1533 break;
1534 }
1535
1536 rate_pcal_info[i].target_power_36 |= (val >> 12) & 0xf;
1537 rate_pcal_info[i].target_power_48 = ((val >> 6) & 0x3f);
1538 rate_pcal_info[i].target_power_54 = (val & 0x3f);
1539 }
1540 }
1541
1542 return 0;
1543 }
1544
1545
1546 /*
1547 * Read per channel calibration info from EEPROM
1548 *
1549 * This info is used to calibrate the baseband power table. Imagine
1550 * that for each channel there is a power curve that's hw specific
1551 * (depends on amplifier etc) and we try to "correct" this curve using
1552 * offsets we pass on to phy chip (baseband -> before amplifier) so that
1553 * it can use accurate power values when setting tx power (takes amplifier's
1554 * performance on each channel into account).
1555 *
1556 * EEPROM provides us with the offsets for some pre-calibrated channels
1557 * and we have to interpolate to create the full table for these channels and
1558 * also the table for any channel.
1559 */
1560 static int
ath5k_eeprom_read_pcal_info(struct ath5k_hw * ah)1561 ath5k_eeprom_read_pcal_info(struct ath5k_hw *ah)
1562 {
1563 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1564 int (*read_pcal)(struct ath5k_hw *hw, int mode);
1565 int mode;
1566 int err;
1567
1568 if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) &&
1569 (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 1))
1570 read_pcal = ath5k_eeprom_read_pcal_info_5112;
1571 else if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0) &&
1572 (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 2))
1573 read_pcal = ath5k_eeprom_read_pcal_info_2413;
1574 else
1575 read_pcal = ath5k_eeprom_read_pcal_info_5111;
1576
1577
1578 for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G;
1579 mode++) {
1580 err = read_pcal(ah, mode);
1581 if (err)
1582 return err;
1583
1584 err = ath5k_eeprom_read_target_rate_pwr_info(ah, mode);
1585 if (err < 0)
1586 return err;
1587 }
1588
1589 return 0;
1590 }
1591
1592 /* Read conformance test limits used for regulatory control */
1593 static int
ath5k_eeprom_read_ctl_info(struct ath5k_hw * ah)1594 ath5k_eeprom_read_ctl_info(struct ath5k_hw *ah)
1595 {
1596 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1597 struct ath5k_edge_power *rep;
1598 unsigned int fmask, pmask;
1599 unsigned int ctl_mode;
1600 int i, j;
1601 u32 offset;
1602 u16 val;
1603
1604 pmask = AR5K_EEPROM_POWER_M;
1605 fmask = AR5K_EEPROM_FREQ_M(ee->ee_version);
1606 offset = AR5K_EEPROM_CTL(ee->ee_version);
1607 ee->ee_ctls = AR5K_EEPROM_N_CTLS(ee->ee_version);
1608 for (i = 0; i < ee->ee_ctls; i += 2) {
1609 AR5K_EEPROM_READ(offset++, val);
1610 ee->ee_ctl[i] = (val >> 8) & 0xff;
1611 ee->ee_ctl[i + 1] = val & 0xff;
1612 }
1613
1614 offset = AR5K_EEPROM_GROUP8_OFFSET;
1615 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_0)
1616 offset += AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1) -
1617 AR5K_EEPROM_GROUP5_OFFSET;
1618 else
1619 offset += AR5K_EEPROM_GROUPS_START(ee->ee_version);
1620
1621 rep = ee->ee_ctl_pwr;
1622 for (i = 0; i < ee->ee_ctls; i++) {
1623 switch (ee->ee_ctl[i] & AR5K_CTL_MODE_M) {
1624 case AR5K_CTL_11A:
1625 case AR5K_CTL_TURBO:
1626 ctl_mode = AR5K_EEPROM_MODE_11A;
1627 break;
1628 default:
1629 ctl_mode = AR5K_EEPROM_MODE_11G;
1630 break;
1631 }
1632 if (ee->ee_ctl[i] == 0) {
1633 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3)
1634 offset += 8;
1635 else
1636 offset += 7;
1637 rep += AR5K_EEPROM_N_EDGES;
1638 continue;
1639 }
1640 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) {
1641 for (j = 0; j < AR5K_EEPROM_N_EDGES; j += 2) {
1642 AR5K_EEPROM_READ(offset++, val);
1643 rep[j].freq = (val >> 8) & fmask;
1644 rep[j + 1].freq = val & fmask;
1645 }
1646 for (j = 0; j < AR5K_EEPROM_N_EDGES; j += 2) {
1647 AR5K_EEPROM_READ(offset++, val);
1648 rep[j].edge = (val >> 8) & pmask;
1649 rep[j].flag = (val >> 14) & 1;
1650 rep[j + 1].edge = val & pmask;
1651 rep[j + 1].flag = (val >> 6) & 1;
1652 }
1653 } else {
1654 AR5K_EEPROM_READ(offset++, val);
1655 rep[0].freq = (val >> 9) & fmask;
1656 rep[1].freq = (val >> 2) & fmask;
1657 rep[2].freq = (val << 5) & fmask;
1658
1659 AR5K_EEPROM_READ(offset++, val);
1660 rep[2].freq |= (val >> 11) & 0x1f;
1661 rep[3].freq = (val >> 4) & fmask;
1662 rep[4].freq = (val << 3) & fmask;
1663
1664 AR5K_EEPROM_READ(offset++, val);
1665 rep[4].freq |= (val >> 13) & 0x7;
1666 rep[5].freq = (val >> 6) & fmask;
1667 rep[6].freq = (val << 1) & fmask;
1668
1669 AR5K_EEPROM_READ(offset++, val);
1670 rep[6].freq |= (val >> 15) & 0x1;
1671 rep[7].freq = (val >> 8) & fmask;
1672
1673 rep[0].edge = (val >> 2) & pmask;
1674 rep[1].edge = (val << 4) & pmask;
1675
1676 AR5K_EEPROM_READ(offset++, val);
1677 rep[1].edge |= (val >> 12) & 0xf;
1678 rep[2].edge = (val >> 6) & pmask;
1679 rep[3].edge = val & pmask;
1680
1681 AR5K_EEPROM_READ(offset++, val);
1682 rep[4].edge = (val >> 10) & pmask;
1683 rep[5].edge = (val >> 4) & pmask;
1684 rep[6].edge = (val << 2) & pmask;
1685
1686 AR5K_EEPROM_READ(offset++, val);
1687 rep[6].edge |= (val >> 14) & 0x3;
1688 rep[7].edge = (val >> 8) & pmask;
1689 }
1690 for (j = 0; j < AR5K_EEPROM_N_EDGES; j++) {
1691 rep[j].freq = ath5k_eeprom_bin2freq(ee,
1692 rep[j].freq, ctl_mode);
1693 }
1694 rep += AR5K_EEPROM_N_EDGES;
1695 }
1696
1697 return 0;
1698 }
1699
1700 static int
ath5k_eeprom_read_spur_chans(struct ath5k_hw * ah)1701 ath5k_eeprom_read_spur_chans(struct ath5k_hw *ah)
1702 {
1703 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1704 u32 offset;
1705 u16 val;
1706 int i;
1707
1708 offset = AR5K_EEPROM_CTL(ee->ee_version) +
1709 AR5K_EEPROM_N_CTLS(ee->ee_version);
1710
1711 if (ee->ee_version < AR5K_EEPROM_VERSION_5_3) {
1712 /* No spur info for 5GHz */
1713 ee->ee_spur_chans[0][0] = AR5K_EEPROM_NO_SPUR;
1714 /* 2 channels for 2GHz (2464/2420) */
1715 ee->ee_spur_chans[0][1] = AR5K_EEPROM_5413_SPUR_CHAN_1;
1716 ee->ee_spur_chans[1][1] = AR5K_EEPROM_5413_SPUR_CHAN_2;
1717 ee->ee_spur_chans[2][1] = AR5K_EEPROM_NO_SPUR;
1718 } else if (ee->ee_version >= AR5K_EEPROM_VERSION_5_3) {
1719 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
1720 AR5K_EEPROM_READ(offset, val);
1721 ee->ee_spur_chans[i][0] = val;
1722 AR5K_EEPROM_READ(offset + AR5K_EEPROM_N_SPUR_CHANS,
1723 val);
1724 ee->ee_spur_chans[i][1] = val;
1725 offset++;
1726 }
1727 }
1728
1729 return 0;
1730 }
1731
1732
1733 /***********************\
1734 * Init/Detach functions *
1735 \***********************/
1736
1737 /*
1738 * Initialize eeprom data structure
1739 */
1740 int
ath5k_eeprom_init(struct ath5k_hw * ah)1741 ath5k_eeprom_init(struct ath5k_hw *ah)
1742 {
1743 int err;
1744
1745 err = ath5k_eeprom_init_header(ah);
1746 if (err < 0)
1747 return err;
1748
1749 err = ath5k_eeprom_init_modes(ah);
1750 if (err < 0)
1751 return err;
1752
1753 err = ath5k_eeprom_read_pcal_info(ah);
1754 if (err < 0)
1755 return err;
1756
1757 err = ath5k_eeprom_read_ctl_info(ah);
1758 if (err < 0)
1759 return err;
1760
1761 err = ath5k_eeprom_read_spur_chans(ah);
1762 if (err < 0)
1763 return err;
1764
1765 return 0;
1766 }
1767
1768 void
ath5k_eeprom_detach(struct ath5k_hw * ah)1769 ath5k_eeprom_detach(struct ath5k_hw *ah)
1770 {
1771 u8 mode;
1772
1773 for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++)
1774 ath5k_eeprom_free_pcal_info(ah, mode);
1775 }
1776
1777 int
ath5k_eeprom_mode_from_channel(struct ath5k_hw * ah,struct ieee80211_channel * channel)1778 ath5k_eeprom_mode_from_channel(struct ath5k_hw *ah,
1779 struct ieee80211_channel *channel)
1780 {
1781 switch (channel->hw_value) {
1782 case AR5K_MODE_11A:
1783 return AR5K_EEPROM_MODE_11A;
1784 case AR5K_MODE_11G:
1785 return AR5K_EEPROM_MODE_11G;
1786 case AR5K_MODE_11B:
1787 return AR5K_EEPROM_MODE_11B;
1788 default:
1789 ATH5K_WARN(ah, "channel is not A/B/G!");
1790 return AR5K_EEPROM_MODE_11A;
1791 }
1792 }
1793