1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * smc91x.c
4 * This is a driver for SMSC's 91C9x/91C1xx single-chip Ethernet devices.
5 *
6 * Copyright (C) 1996 by Erik Stahlman
7 * Copyright (C) 2001 Standard Microsystems Corporation
8 * Developed by Simple Network Magic Corporation
9 * Copyright (C) 2003 Monta Vista Software, Inc.
10 * Unified SMC91x driver by Nicolas Pitre
11 *
12 * Arguments:
13 * io = for the base address
14 * irq = for the IRQ
15 * nowait = 0 for normal wait states, 1 eliminates additional wait states
16 *
17 * original author:
18 * Erik Stahlman <erik@vt.edu>
19 *
20 * hardware multicast code:
21 * Peter Cammaert <pc@denkart.be>
22 *
23 * contributors:
24 * Daris A Nevil <dnevil@snmc.com>
25 * Nicolas Pitre <nico@fluxnic.net>
26 * Russell King <rmk@arm.linux.org.uk>
27 *
28 * History:
29 * 08/20/00 Arnaldo Melo fix kfree(skb) in smc_hardware_send_packet
30 * 12/15/00 Christian Jullien fix "Warning: kfree_skb on hard IRQ"
31 * 03/16/01 Daris A Nevil modified smc9194.c for use with LAN91C111
32 * 08/22/01 Scott Anderson merge changes from smc9194 to smc91111
33 * 08/21/01 Pramod B Bhardwaj added support for RevB of LAN91C111
34 * 12/20/01 Jeff Sutherland initial port to Xscale PXA with DMA support
35 * 04/07/03 Nicolas Pitre unified SMC91x driver, killed irq races,
36 * more bus abstraction, big cleanup, etc.
37 * 29/09/03 Russell King - add driver model support
38 * - ethtool support
39 * - convert to use generic MII interface
40 * - add link up/down notification
41 * - don't try to handle full negotiation in
42 * smc_phy_configure
43 * - clean up (and fix stack overrun) in PHY
44 * MII read/write functions
45 * 22/09/04 Nicolas Pitre big update (see commit log for details)
46 */
47 static const char version[] =
48 "smc91x.c: v1.1, sep 22 2004 by Nicolas Pitre <nico@fluxnic.net>";
49
50 /* Debugging level */
51 #ifndef SMC_DEBUG
52 #define SMC_DEBUG 0
53 #endif
54
55
56 #include <linux/module.h>
57 #include <linux/kernel.h>
58 #include <linux/sched.h>
59 #include <linux/delay.h>
60 #include <linux/gpio/consumer.h>
61 #include <linux/interrupt.h>
62 #include <linux/irq.h>
63 #include <linux/errno.h>
64 #include <linux/ioport.h>
65 #include <linux/crc32.h>
66 #include <linux/platform_device.h>
67 #include <linux/spinlock.h>
68 #include <linux/ethtool.h>
69 #include <linux/mii.h>
70 #include <linux/workqueue.h>
71 #include <linux/of.h>
72 #include <linux/of_device.h>
73
74 #include <linux/netdevice.h>
75 #include <linux/etherdevice.h>
76 #include <linux/skbuff.h>
77
78 #include <asm/io.h>
79
80 #include "smc91x.h"
81
82 #if defined(CONFIG_ASSABET_NEPONSET)
83 #include <mach/assabet.h>
84 #include <mach/neponset.h>
85 #endif
86
87 #ifndef SMC_NOWAIT
88 # define SMC_NOWAIT 0
89 #endif
90 static int nowait = SMC_NOWAIT;
91 module_param(nowait, int, 0400);
92 MODULE_PARM_DESC(nowait, "set to 1 for no wait state");
93
94 /*
95 * Transmit timeout, default 5 seconds.
96 */
97 static int watchdog = 1000;
98 module_param(watchdog, int, 0400);
99 MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
100
101 MODULE_DESCRIPTION("SMC 91C9x/91C1xxx Ethernet driver");
102 MODULE_LICENSE("GPL");
103 MODULE_ALIAS("platform:smc91x");
104
105 /*
106 * The internal workings of the driver. If you are changing anything
107 * here with the SMC stuff, you should have the datasheet and know
108 * what you are doing.
109 */
110 #define CARDNAME "smc91x"
111
112 /*
113 * Use power-down feature of the chip
114 */
115 #define POWER_DOWN 1
116
117 /*
118 * Wait time for memory to be free. This probably shouldn't be
119 * tuned that much, as waiting for this means nothing else happens
120 * in the system
121 */
122 #define MEMORY_WAIT_TIME 16
123
124 /*
125 * The maximum number of processing loops allowed for each call to the
126 * IRQ handler.
127 */
128 #define MAX_IRQ_LOOPS 8
129
130 /*
131 * This selects whether TX packets are sent one by one to the SMC91x internal
132 * memory and throttled until transmission completes. This may prevent
133 * RX overruns a litle by keeping much of the memory free for RX packets
134 * but to the expense of reduced TX throughput and increased IRQ overhead.
135 * Note this is not a cure for a too slow data bus or too high IRQ latency.
136 */
137 #define THROTTLE_TX_PKTS 0
138
139 /*
140 * The MII clock high/low times. 2x this number gives the MII clock period
141 * in microseconds. (was 50, but this gives 6.4ms for each MII transaction!)
142 */
143 #define MII_DELAY 1
144
145 #define DBG(n, dev, fmt, ...) \
146 do { \
147 if (SMC_DEBUG >= (n)) \
148 netdev_dbg(dev, fmt, ##__VA_ARGS__); \
149 } while (0)
150
151 #define PRINTK(dev, fmt, ...) \
152 do { \
153 if (SMC_DEBUG > 0) \
154 netdev_info(dev, fmt, ##__VA_ARGS__); \
155 else \
156 netdev_dbg(dev, fmt, ##__VA_ARGS__); \
157 } while (0)
158
159 #if SMC_DEBUG > 3
PRINT_PKT(u_char * buf,int length)160 static void PRINT_PKT(u_char *buf, int length)
161 {
162 int i;
163 int remainder;
164 int lines;
165
166 lines = length / 16;
167 remainder = length % 16;
168
169 for (i = 0; i < lines ; i ++) {
170 int cur;
171 printk(KERN_DEBUG);
172 for (cur = 0; cur < 8; cur++) {
173 u_char a, b;
174 a = *buf++;
175 b = *buf++;
176 pr_cont("%02x%02x ", a, b);
177 }
178 pr_cont("\n");
179 }
180 printk(KERN_DEBUG);
181 for (i = 0; i < remainder/2 ; i++) {
182 u_char a, b;
183 a = *buf++;
184 b = *buf++;
185 pr_cont("%02x%02x ", a, b);
186 }
187 pr_cont("\n");
188 }
189 #else
PRINT_PKT(u_char * buf,int length)190 static inline void PRINT_PKT(u_char *buf, int length) { }
191 #endif
192
193
194 /* this enables an interrupt in the interrupt mask register */
195 #define SMC_ENABLE_INT(lp, x) do { \
196 unsigned char mask; \
197 unsigned long smc_enable_flags; \
198 spin_lock_irqsave(&lp->lock, smc_enable_flags); \
199 mask = SMC_GET_INT_MASK(lp); \
200 mask |= (x); \
201 SMC_SET_INT_MASK(lp, mask); \
202 spin_unlock_irqrestore(&lp->lock, smc_enable_flags); \
203 } while (0)
204
205 /* this disables an interrupt from the interrupt mask register */
206 #define SMC_DISABLE_INT(lp, x) do { \
207 unsigned char mask; \
208 unsigned long smc_disable_flags; \
209 spin_lock_irqsave(&lp->lock, smc_disable_flags); \
210 mask = SMC_GET_INT_MASK(lp); \
211 mask &= ~(x); \
212 SMC_SET_INT_MASK(lp, mask); \
213 spin_unlock_irqrestore(&lp->lock, smc_disable_flags); \
214 } while (0)
215
216 /*
217 * Wait while MMU is busy. This is usually in the order of a few nanosecs
218 * if at all, but let's avoid deadlocking the system if the hardware
219 * decides to go south.
220 */
221 #define SMC_WAIT_MMU_BUSY(lp) do { \
222 if (unlikely(SMC_GET_MMU_CMD(lp) & MC_BUSY)) { \
223 unsigned long timeout = jiffies + 2; \
224 while (SMC_GET_MMU_CMD(lp) & MC_BUSY) { \
225 if (time_after(jiffies, timeout)) { \
226 netdev_dbg(dev, "timeout %s line %d\n", \
227 __FILE__, __LINE__); \
228 break; \
229 } \
230 cpu_relax(); \
231 } \
232 } \
233 } while (0)
234
235
236 /*
237 * this does a soft reset on the device
238 */
smc_reset(struct net_device * dev)239 static void smc_reset(struct net_device *dev)
240 {
241 struct smc_local *lp = netdev_priv(dev);
242 void __iomem *ioaddr = lp->base;
243 unsigned int ctl, cfg;
244 struct sk_buff *pending_skb;
245
246 DBG(2, dev, "%s\n", __func__);
247
248 /* Disable all interrupts, block TX tasklet */
249 spin_lock_irq(&lp->lock);
250 SMC_SELECT_BANK(lp, 2);
251 SMC_SET_INT_MASK(lp, 0);
252 pending_skb = lp->pending_tx_skb;
253 lp->pending_tx_skb = NULL;
254 spin_unlock_irq(&lp->lock);
255
256 /* free any pending tx skb */
257 if (pending_skb) {
258 dev_kfree_skb(pending_skb);
259 dev->stats.tx_errors++;
260 dev->stats.tx_aborted_errors++;
261 }
262
263 /*
264 * This resets the registers mostly to defaults, but doesn't
265 * affect EEPROM. That seems unnecessary
266 */
267 SMC_SELECT_BANK(lp, 0);
268 SMC_SET_RCR(lp, RCR_SOFTRST);
269
270 /*
271 * Setup the Configuration Register
272 * This is necessary because the CONFIG_REG is not affected
273 * by a soft reset
274 */
275 SMC_SELECT_BANK(lp, 1);
276
277 cfg = CONFIG_DEFAULT;
278
279 /*
280 * Setup for fast accesses if requested. If the card/system
281 * can't handle it then there will be no recovery except for
282 * a hard reset or power cycle
283 */
284 if (lp->cfg.flags & SMC91X_NOWAIT)
285 cfg |= CONFIG_NO_WAIT;
286
287 /*
288 * Release from possible power-down state
289 * Configuration register is not affected by Soft Reset
290 */
291 cfg |= CONFIG_EPH_POWER_EN;
292
293 SMC_SET_CONFIG(lp, cfg);
294
295 /* this should pause enough for the chip to be happy */
296 /*
297 * elaborate? What does the chip _need_? --jgarzik
298 *
299 * This seems to be undocumented, but something the original
300 * driver(s) have always done. Suspect undocumented timing
301 * info/determined empirically. --rmk
302 */
303 udelay(1);
304
305 /* Disable transmit and receive functionality */
306 SMC_SELECT_BANK(lp, 0);
307 SMC_SET_RCR(lp, RCR_CLEAR);
308 SMC_SET_TCR(lp, TCR_CLEAR);
309
310 SMC_SELECT_BANK(lp, 1);
311 ctl = SMC_GET_CTL(lp) | CTL_LE_ENABLE;
312
313 /*
314 * Set the control register to automatically release successfully
315 * transmitted packets, to make the best use out of our limited
316 * memory
317 */
318 if(!THROTTLE_TX_PKTS)
319 ctl |= CTL_AUTO_RELEASE;
320 else
321 ctl &= ~CTL_AUTO_RELEASE;
322 SMC_SET_CTL(lp, ctl);
323
324 /* Reset the MMU */
325 SMC_SELECT_BANK(lp, 2);
326 SMC_SET_MMU_CMD(lp, MC_RESET);
327 SMC_WAIT_MMU_BUSY(lp);
328 }
329
330 /*
331 * Enable Interrupts, Receive, and Transmit
332 */
smc_enable(struct net_device * dev)333 static void smc_enable(struct net_device *dev)
334 {
335 struct smc_local *lp = netdev_priv(dev);
336 void __iomem *ioaddr = lp->base;
337 int mask;
338
339 DBG(2, dev, "%s\n", __func__);
340
341 /* see the header file for options in TCR/RCR DEFAULT */
342 SMC_SELECT_BANK(lp, 0);
343 SMC_SET_TCR(lp, lp->tcr_cur_mode);
344 SMC_SET_RCR(lp, lp->rcr_cur_mode);
345
346 SMC_SELECT_BANK(lp, 1);
347 SMC_SET_MAC_ADDR(lp, dev->dev_addr);
348
349 /* now, enable interrupts */
350 mask = IM_EPH_INT|IM_RX_OVRN_INT|IM_RCV_INT;
351 if (lp->version >= (CHIP_91100 << 4))
352 mask |= IM_MDINT;
353 SMC_SELECT_BANK(lp, 2);
354 SMC_SET_INT_MASK(lp, mask);
355
356 /*
357 * From this point the register bank must _NOT_ be switched away
358 * to something else than bank 2 without proper locking against
359 * races with any tasklet or interrupt handlers until smc_shutdown()
360 * or smc_reset() is called.
361 */
362 }
363
364 /*
365 * this puts the device in an inactive state
366 */
smc_shutdown(struct net_device * dev)367 static void smc_shutdown(struct net_device *dev)
368 {
369 struct smc_local *lp = netdev_priv(dev);
370 void __iomem *ioaddr = lp->base;
371 struct sk_buff *pending_skb;
372
373 DBG(2, dev, "%s: %s\n", CARDNAME, __func__);
374
375 /* no more interrupts for me */
376 spin_lock_irq(&lp->lock);
377 SMC_SELECT_BANK(lp, 2);
378 SMC_SET_INT_MASK(lp, 0);
379 pending_skb = lp->pending_tx_skb;
380 lp->pending_tx_skb = NULL;
381 spin_unlock_irq(&lp->lock);
382 dev_kfree_skb(pending_skb);
383
384 /* and tell the card to stay away from that nasty outside world */
385 SMC_SELECT_BANK(lp, 0);
386 SMC_SET_RCR(lp, RCR_CLEAR);
387 SMC_SET_TCR(lp, TCR_CLEAR);
388
389 #ifdef POWER_DOWN
390 /* finally, shut the chip down */
391 SMC_SELECT_BANK(lp, 1);
392 SMC_SET_CONFIG(lp, SMC_GET_CONFIG(lp) & ~CONFIG_EPH_POWER_EN);
393 #endif
394 }
395
396 /*
397 * This is the procedure to handle the receipt of a packet.
398 */
smc_rcv(struct net_device * dev)399 static inline void smc_rcv(struct net_device *dev)
400 {
401 struct smc_local *lp = netdev_priv(dev);
402 void __iomem *ioaddr = lp->base;
403 unsigned int packet_number, status, packet_len;
404
405 DBG(3, dev, "%s\n", __func__);
406
407 packet_number = SMC_GET_RXFIFO(lp);
408 if (unlikely(packet_number & RXFIFO_REMPTY)) {
409 PRINTK(dev, "smc_rcv with nothing on FIFO.\n");
410 return;
411 }
412
413 /* read from start of packet */
414 SMC_SET_PTR(lp, PTR_READ | PTR_RCV | PTR_AUTOINC);
415
416 /* First two words are status and packet length */
417 SMC_GET_PKT_HDR(lp, status, packet_len);
418 packet_len &= 0x07ff; /* mask off top bits */
419 DBG(2, dev, "RX PNR 0x%x STATUS 0x%04x LENGTH 0x%04x (%d)\n",
420 packet_number, status, packet_len, packet_len);
421
422 back:
423 if (unlikely(packet_len < 6 || status & RS_ERRORS)) {
424 if (status & RS_TOOLONG && packet_len <= (1514 + 4 + 6)) {
425 /* accept VLAN packets */
426 status &= ~RS_TOOLONG;
427 goto back;
428 }
429 if (packet_len < 6) {
430 /* bloody hardware */
431 netdev_err(dev, "fubar (rxlen %u status %x\n",
432 packet_len, status);
433 status |= RS_TOOSHORT;
434 }
435 SMC_WAIT_MMU_BUSY(lp);
436 SMC_SET_MMU_CMD(lp, MC_RELEASE);
437 dev->stats.rx_errors++;
438 if (status & RS_ALGNERR)
439 dev->stats.rx_frame_errors++;
440 if (status & (RS_TOOSHORT | RS_TOOLONG))
441 dev->stats.rx_length_errors++;
442 if (status & RS_BADCRC)
443 dev->stats.rx_crc_errors++;
444 } else {
445 struct sk_buff *skb;
446 unsigned char *data;
447 unsigned int data_len;
448
449 /* set multicast stats */
450 if (status & RS_MULTICAST)
451 dev->stats.multicast++;
452
453 /*
454 * Actual payload is packet_len - 6 (or 5 if odd byte).
455 * We want skb_reserve(2) and the final ctrl word
456 * (2 bytes, possibly containing the payload odd byte).
457 * Furthermore, we add 2 bytes to allow rounding up to
458 * multiple of 4 bytes on 32 bit buses.
459 * Hence packet_len - 6 + 2 + 2 + 2.
460 */
461 skb = netdev_alloc_skb(dev, packet_len);
462 if (unlikely(skb == NULL)) {
463 SMC_WAIT_MMU_BUSY(lp);
464 SMC_SET_MMU_CMD(lp, MC_RELEASE);
465 dev->stats.rx_dropped++;
466 return;
467 }
468
469 /* Align IP header to 32 bits */
470 skb_reserve(skb, 2);
471
472 /* BUG: the LAN91C111 rev A never sets this bit. Force it. */
473 if (lp->version == 0x90)
474 status |= RS_ODDFRAME;
475
476 /*
477 * If odd length: packet_len - 5,
478 * otherwise packet_len - 6.
479 * With the trailing ctrl byte it's packet_len - 4.
480 */
481 data_len = packet_len - ((status & RS_ODDFRAME) ? 5 : 6);
482 data = skb_put(skb, data_len);
483 SMC_PULL_DATA(lp, data, packet_len - 4);
484
485 SMC_WAIT_MMU_BUSY(lp);
486 SMC_SET_MMU_CMD(lp, MC_RELEASE);
487
488 PRINT_PKT(data, packet_len - 4);
489
490 skb->protocol = eth_type_trans(skb, dev);
491 netif_rx(skb);
492 dev->stats.rx_packets++;
493 dev->stats.rx_bytes += data_len;
494 }
495 }
496
497 #ifdef CONFIG_SMP
498 /*
499 * On SMP we have the following problem:
500 *
501 * A = smc_hardware_send_pkt()
502 * B = smc_hard_start_xmit()
503 * C = smc_interrupt()
504 *
505 * A and B can never be executed simultaneously. However, at least on UP,
506 * it is possible (and even desirable) for C to interrupt execution of
507 * A or B in order to have better RX reliability and avoid overruns.
508 * C, just like A and B, must have exclusive access to the chip and
509 * each of them must lock against any other concurrent access.
510 * Unfortunately this is not possible to have C suspend execution of A or
511 * B taking place on another CPU. On UP this is no an issue since A and B
512 * are run from softirq context and C from hard IRQ context, and there is
513 * no other CPU where concurrent access can happen.
514 * If ever there is a way to force at least B and C to always be executed
515 * on the same CPU then we could use read/write locks to protect against
516 * any other concurrent access and C would always interrupt B. But life
517 * isn't that easy in a SMP world...
518 */
519 #define smc_special_trylock(lock, flags) spin_trylock_irqsave(lock, flags)
520 #define smc_special_lock(lock, flags) spin_lock_irqsave(lock, flags)
521 #define smc_special_unlock(lock, flags) spin_unlock_irqrestore(lock, flags)
522 #else
523 #define smc_special_trylock(lock, flags) ((void)flags, true)
524 #define smc_special_lock(lock, flags) do { flags = 0; } while (0)
525 #define smc_special_unlock(lock, flags) do { flags = 0; } while (0)
526 #endif
527
528 /*
529 * This is called to actually send a packet to the chip.
530 */
smc_hardware_send_pkt(struct tasklet_struct * t)531 static void smc_hardware_send_pkt(struct tasklet_struct *t)
532 {
533 struct smc_local *lp = from_tasklet(lp, t, tx_task);
534 struct net_device *dev = lp->dev;
535 void __iomem *ioaddr = lp->base;
536 struct sk_buff *skb;
537 unsigned int packet_no, len;
538 unsigned char *buf;
539 unsigned long flags;
540
541 DBG(3, dev, "%s\n", __func__);
542
543 if (!smc_special_trylock(&lp->lock, flags)) {
544 netif_stop_queue(dev);
545 tasklet_schedule(&lp->tx_task);
546 return;
547 }
548
549 skb = lp->pending_tx_skb;
550 if (unlikely(!skb)) {
551 smc_special_unlock(&lp->lock, flags);
552 return;
553 }
554 lp->pending_tx_skb = NULL;
555
556 packet_no = SMC_GET_AR(lp);
557 if (unlikely(packet_no & AR_FAILED)) {
558 netdev_err(dev, "Memory allocation failed.\n");
559 dev->stats.tx_errors++;
560 dev->stats.tx_fifo_errors++;
561 smc_special_unlock(&lp->lock, flags);
562 goto done;
563 }
564
565 /* point to the beginning of the packet */
566 SMC_SET_PN(lp, packet_no);
567 SMC_SET_PTR(lp, PTR_AUTOINC);
568
569 buf = skb->data;
570 len = skb->len;
571 DBG(2, dev, "TX PNR 0x%x LENGTH 0x%04x (%d) BUF 0x%p\n",
572 packet_no, len, len, buf);
573 PRINT_PKT(buf, len);
574
575 /*
576 * Send the packet length (+6 for status words, length, and ctl.
577 * The card will pad to 64 bytes with zeroes if packet is too small.
578 */
579 SMC_PUT_PKT_HDR(lp, 0, len + 6);
580
581 /* send the actual data */
582 SMC_PUSH_DATA(lp, buf, len & ~1);
583
584 /* Send final ctl word with the last byte if there is one */
585 SMC_outw(lp, ((len & 1) ? (0x2000 | buf[len - 1]) : 0), ioaddr,
586 DATA_REG(lp));
587
588 /*
589 * If THROTTLE_TX_PKTS is set, we stop the queue here. This will
590 * have the effect of having at most one packet queued for TX
591 * in the chip's memory at all time.
592 *
593 * If THROTTLE_TX_PKTS is not set then the queue is stopped only
594 * when memory allocation (MC_ALLOC) does not succeed right away.
595 */
596 if (THROTTLE_TX_PKTS)
597 netif_stop_queue(dev);
598
599 /* queue the packet for TX */
600 SMC_SET_MMU_CMD(lp, MC_ENQUEUE);
601 smc_special_unlock(&lp->lock, flags);
602
603 netif_trans_update(dev);
604 dev->stats.tx_packets++;
605 dev->stats.tx_bytes += len;
606
607 SMC_ENABLE_INT(lp, IM_TX_INT | IM_TX_EMPTY_INT);
608
609 done: if (!THROTTLE_TX_PKTS)
610 netif_wake_queue(dev);
611
612 dev_consume_skb_any(skb);
613 }
614
615 /*
616 * Since I am not sure if I will have enough room in the chip's ram
617 * to store the packet, I call this routine which either sends it
618 * now, or set the card to generates an interrupt when ready
619 * for the packet.
620 */
621 static netdev_tx_t
smc_hard_start_xmit(struct sk_buff * skb,struct net_device * dev)622 smc_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
623 {
624 struct smc_local *lp = netdev_priv(dev);
625 void __iomem *ioaddr = lp->base;
626 unsigned int numPages, poll_count, status;
627 unsigned long flags;
628
629 DBG(3, dev, "%s\n", __func__);
630
631 BUG_ON(lp->pending_tx_skb != NULL);
632
633 /*
634 * The MMU wants the number of pages to be the number of 256 bytes
635 * 'pages', minus 1 (since a packet can't ever have 0 pages :))
636 *
637 * The 91C111 ignores the size bits, but earlier models don't.
638 *
639 * Pkt size for allocating is data length +6 (for additional status
640 * words, length and ctl)
641 *
642 * If odd size then last byte is included in ctl word.
643 */
644 numPages = ((skb->len & ~1) + (6 - 1)) >> 8;
645 if (unlikely(numPages > 7)) {
646 netdev_warn(dev, "Far too big packet error.\n");
647 dev->stats.tx_errors++;
648 dev->stats.tx_dropped++;
649 dev_kfree_skb_any(skb);
650 return NETDEV_TX_OK;
651 }
652
653 smc_special_lock(&lp->lock, flags);
654
655 /* now, try to allocate the memory */
656 SMC_SET_MMU_CMD(lp, MC_ALLOC | numPages);
657
658 /*
659 * Poll the chip for a short amount of time in case the
660 * allocation succeeds quickly.
661 */
662 poll_count = MEMORY_WAIT_TIME;
663 do {
664 status = SMC_GET_INT(lp);
665 if (status & IM_ALLOC_INT) {
666 SMC_ACK_INT(lp, IM_ALLOC_INT);
667 break;
668 }
669 } while (--poll_count);
670
671 smc_special_unlock(&lp->lock, flags);
672
673 lp->pending_tx_skb = skb;
674 if (!poll_count) {
675 /* oh well, wait until the chip finds memory later */
676 netif_stop_queue(dev);
677 DBG(2, dev, "TX memory allocation deferred.\n");
678 SMC_ENABLE_INT(lp, IM_ALLOC_INT);
679 } else {
680 /*
681 * Allocation succeeded: push packet to the chip's own memory
682 * immediately.
683 */
684 smc_hardware_send_pkt(&lp->tx_task);
685 }
686
687 return NETDEV_TX_OK;
688 }
689
690 /*
691 * This handles a TX interrupt, which is only called when:
692 * - a TX error occurred, or
693 * - CTL_AUTO_RELEASE is not set and TX of a packet completed.
694 */
smc_tx(struct net_device * dev)695 static void smc_tx(struct net_device *dev)
696 {
697 struct smc_local *lp = netdev_priv(dev);
698 void __iomem *ioaddr = lp->base;
699 unsigned int saved_packet, packet_no, tx_status;
700 unsigned int pkt_len __always_unused;
701
702 DBG(3, dev, "%s\n", __func__);
703
704 /* If the TX FIFO is empty then nothing to do */
705 packet_no = SMC_GET_TXFIFO(lp);
706 if (unlikely(packet_no & TXFIFO_TEMPTY)) {
707 PRINTK(dev, "smc_tx with nothing on FIFO.\n");
708 return;
709 }
710
711 /* select packet to read from */
712 saved_packet = SMC_GET_PN(lp);
713 SMC_SET_PN(lp, packet_no);
714
715 /* read the first word (status word) from this packet */
716 SMC_SET_PTR(lp, PTR_AUTOINC | PTR_READ);
717 SMC_GET_PKT_HDR(lp, tx_status, pkt_len);
718 DBG(2, dev, "TX STATUS 0x%04x PNR 0x%02x\n",
719 tx_status, packet_no);
720
721 if (!(tx_status & ES_TX_SUC))
722 dev->stats.tx_errors++;
723
724 if (tx_status & ES_LOSTCARR)
725 dev->stats.tx_carrier_errors++;
726
727 if (tx_status & (ES_LATCOL | ES_16COL)) {
728 PRINTK(dev, "%s occurred on last xmit\n",
729 (tx_status & ES_LATCOL) ?
730 "late collision" : "too many collisions");
731 dev->stats.tx_window_errors++;
732 if (!(dev->stats.tx_window_errors & 63) && net_ratelimit()) {
733 netdev_info(dev, "unexpectedly large number of bad collisions. Please check duplex setting.\n");
734 }
735 }
736
737 /* kill the packet */
738 SMC_WAIT_MMU_BUSY(lp);
739 SMC_SET_MMU_CMD(lp, MC_FREEPKT);
740
741 /* Don't restore Packet Number Reg until busy bit is cleared */
742 SMC_WAIT_MMU_BUSY(lp);
743 SMC_SET_PN(lp, saved_packet);
744
745 /* re-enable transmit */
746 SMC_SELECT_BANK(lp, 0);
747 SMC_SET_TCR(lp, lp->tcr_cur_mode);
748 SMC_SELECT_BANK(lp, 2);
749 }
750
751
752 /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
753
smc_mii_out(struct net_device * dev,unsigned int val,int bits)754 static void smc_mii_out(struct net_device *dev, unsigned int val, int bits)
755 {
756 struct smc_local *lp = netdev_priv(dev);
757 void __iomem *ioaddr = lp->base;
758 unsigned int mii_reg, mask;
759
760 mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO);
761 mii_reg |= MII_MDOE;
762
763 for (mask = 1 << (bits - 1); mask; mask >>= 1) {
764 if (val & mask)
765 mii_reg |= MII_MDO;
766 else
767 mii_reg &= ~MII_MDO;
768
769 SMC_SET_MII(lp, mii_reg);
770 udelay(MII_DELAY);
771 SMC_SET_MII(lp, mii_reg | MII_MCLK);
772 udelay(MII_DELAY);
773 }
774 }
775
smc_mii_in(struct net_device * dev,int bits)776 static unsigned int smc_mii_in(struct net_device *dev, int bits)
777 {
778 struct smc_local *lp = netdev_priv(dev);
779 void __iomem *ioaddr = lp->base;
780 unsigned int mii_reg, mask, val;
781
782 mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO);
783 SMC_SET_MII(lp, mii_reg);
784
785 for (mask = 1 << (bits - 1), val = 0; mask; mask >>= 1) {
786 if (SMC_GET_MII(lp) & MII_MDI)
787 val |= mask;
788
789 SMC_SET_MII(lp, mii_reg);
790 udelay(MII_DELAY);
791 SMC_SET_MII(lp, mii_reg | MII_MCLK);
792 udelay(MII_DELAY);
793 }
794
795 return val;
796 }
797
798 /*
799 * Reads a register from the MII Management serial interface
800 */
smc_phy_read(struct net_device * dev,int phyaddr,int phyreg)801 static int smc_phy_read(struct net_device *dev, int phyaddr, int phyreg)
802 {
803 struct smc_local *lp = netdev_priv(dev);
804 void __iomem *ioaddr = lp->base;
805 unsigned int phydata;
806
807 SMC_SELECT_BANK(lp, 3);
808
809 /* Idle - 32 ones */
810 smc_mii_out(dev, 0xffffffff, 32);
811
812 /* Start code (01) + read (10) + phyaddr + phyreg */
813 smc_mii_out(dev, 6 << 10 | phyaddr << 5 | phyreg, 14);
814
815 /* Turnaround (2bits) + phydata */
816 phydata = smc_mii_in(dev, 18);
817
818 /* Return to idle state */
819 SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO));
820
821 DBG(3, dev, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
822 __func__, phyaddr, phyreg, phydata);
823
824 SMC_SELECT_BANK(lp, 2);
825 return phydata;
826 }
827
828 /*
829 * Writes a register to the MII Management serial interface
830 */
smc_phy_write(struct net_device * dev,int phyaddr,int phyreg,int phydata)831 static void smc_phy_write(struct net_device *dev, int phyaddr, int phyreg,
832 int phydata)
833 {
834 struct smc_local *lp = netdev_priv(dev);
835 void __iomem *ioaddr = lp->base;
836
837 SMC_SELECT_BANK(lp, 3);
838
839 /* Idle - 32 ones */
840 smc_mii_out(dev, 0xffffffff, 32);
841
842 /* Start code (01) + write (01) + phyaddr + phyreg + turnaround + phydata */
843 smc_mii_out(dev, 5 << 28 | phyaddr << 23 | phyreg << 18 | 2 << 16 | phydata, 32);
844
845 /* Return to idle state */
846 SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO));
847
848 DBG(3, dev, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
849 __func__, phyaddr, phyreg, phydata);
850
851 SMC_SELECT_BANK(lp, 2);
852 }
853
854 /*
855 * Finds and reports the PHY address
856 */
smc_phy_detect(struct net_device * dev)857 static void smc_phy_detect(struct net_device *dev)
858 {
859 struct smc_local *lp = netdev_priv(dev);
860 int phyaddr;
861
862 DBG(2, dev, "%s\n", __func__);
863
864 lp->phy_type = 0;
865
866 /*
867 * Scan all 32 PHY addresses if necessary, starting at
868 * PHY#1 to PHY#31, and then PHY#0 last.
869 */
870 for (phyaddr = 1; phyaddr < 33; ++phyaddr) {
871 unsigned int id1, id2;
872
873 /* Read the PHY identifiers */
874 id1 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID1);
875 id2 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID2);
876
877 DBG(3, dev, "phy_id1=0x%x, phy_id2=0x%x\n",
878 id1, id2);
879
880 /* Make sure it is a valid identifier */
881 if (id1 != 0x0000 && id1 != 0xffff && id1 != 0x8000 &&
882 id2 != 0x0000 && id2 != 0xffff && id2 != 0x8000) {
883 /* Save the PHY's address */
884 lp->mii.phy_id = phyaddr & 31;
885 lp->phy_type = id1 << 16 | id2;
886 break;
887 }
888 }
889 }
890
891 /*
892 * Sets the PHY to a configuration as determined by the user
893 */
smc_phy_fixed(struct net_device * dev)894 static int smc_phy_fixed(struct net_device *dev)
895 {
896 struct smc_local *lp = netdev_priv(dev);
897 void __iomem *ioaddr = lp->base;
898 int phyaddr = lp->mii.phy_id;
899 int bmcr, cfg1;
900
901 DBG(3, dev, "%s\n", __func__);
902
903 /* Enter Link Disable state */
904 cfg1 = smc_phy_read(dev, phyaddr, PHY_CFG1_REG);
905 cfg1 |= PHY_CFG1_LNKDIS;
906 smc_phy_write(dev, phyaddr, PHY_CFG1_REG, cfg1);
907
908 /*
909 * Set our fixed capabilities
910 * Disable auto-negotiation
911 */
912 bmcr = 0;
913
914 if (lp->ctl_rfduplx)
915 bmcr |= BMCR_FULLDPLX;
916
917 if (lp->ctl_rspeed == 100)
918 bmcr |= BMCR_SPEED100;
919
920 /* Write our capabilities to the phy control register */
921 smc_phy_write(dev, phyaddr, MII_BMCR, bmcr);
922
923 /* Re-Configure the Receive/Phy Control register */
924 SMC_SELECT_BANK(lp, 0);
925 SMC_SET_RPC(lp, lp->rpc_cur_mode);
926 SMC_SELECT_BANK(lp, 2);
927
928 return 1;
929 }
930
931 /**
932 * smc_phy_reset - reset the phy
933 * @dev: net device
934 * @phy: phy address
935 *
936 * Issue a software reset for the specified PHY and
937 * wait up to 100ms for the reset to complete. We should
938 * not access the PHY for 50ms after issuing the reset.
939 *
940 * The time to wait appears to be dependent on the PHY.
941 *
942 * Must be called with lp->lock locked.
943 */
smc_phy_reset(struct net_device * dev,int phy)944 static int smc_phy_reset(struct net_device *dev, int phy)
945 {
946 struct smc_local *lp = netdev_priv(dev);
947 unsigned int bmcr;
948 int timeout;
949
950 smc_phy_write(dev, phy, MII_BMCR, BMCR_RESET);
951
952 for (timeout = 2; timeout; timeout--) {
953 spin_unlock_irq(&lp->lock);
954 msleep(50);
955 spin_lock_irq(&lp->lock);
956
957 bmcr = smc_phy_read(dev, phy, MII_BMCR);
958 if (!(bmcr & BMCR_RESET))
959 break;
960 }
961
962 return bmcr & BMCR_RESET;
963 }
964
965 /**
966 * smc_phy_powerdown - powerdown phy
967 * @dev: net device
968 *
969 * Power down the specified PHY
970 */
smc_phy_powerdown(struct net_device * dev)971 static void smc_phy_powerdown(struct net_device *dev)
972 {
973 struct smc_local *lp = netdev_priv(dev);
974 unsigned int bmcr;
975 int phy = lp->mii.phy_id;
976
977 if (lp->phy_type == 0)
978 return;
979
980 /* We need to ensure that no calls to smc_phy_configure are
981 pending.
982 */
983 cancel_work_sync(&lp->phy_configure);
984
985 bmcr = smc_phy_read(dev, phy, MII_BMCR);
986 smc_phy_write(dev, phy, MII_BMCR, bmcr | BMCR_PDOWN);
987 }
988
989 /**
990 * smc_phy_check_media - check the media status and adjust TCR
991 * @dev: net device
992 * @init: set true for initialisation
993 *
994 * Select duplex mode depending on negotiation state. This
995 * also updates our carrier state.
996 */
smc_phy_check_media(struct net_device * dev,int init)997 static void smc_phy_check_media(struct net_device *dev, int init)
998 {
999 struct smc_local *lp = netdev_priv(dev);
1000 void __iomem *ioaddr = lp->base;
1001
1002 if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) {
1003 /* duplex state has changed */
1004 if (lp->mii.full_duplex) {
1005 lp->tcr_cur_mode |= TCR_SWFDUP;
1006 } else {
1007 lp->tcr_cur_mode &= ~TCR_SWFDUP;
1008 }
1009
1010 SMC_SELECT_BANK(lp, 0);
1011 SMC_SET_TCR(lp, lp->tcr_cur_mode);
1012 }
1013 }
1014
1015 /*
1016 * Configures the specified PHY through the MII management interface
1017 * using Autonegotiation.
1018 * Calls smc_phy_fixed() if the user has requested a certain config.
1019 * If RPC ANEG bit is set, the media selection is dependent purely on
1020 * the selection by the MII (either in the MII BMCR reg or the result
1021 * of autonegotiation.) If the RPC ANEG bit is cleared, the selection
1022 * is controlled by the RPC SPEED and RPC DPLX bits.
1023 */
smc_phy_configure(struct work_struct * work)1024 static void smc_phy_configure(struct work_struct *work)
1025 {
1026 struct smc_local *lp =
1027 container_of(work, struct smc_local, phy_configure);
1028 struct net_device *dev = lp->dev;
1029 void __iomem *ioaddr = lp->base;
1030 int phyaddr = lp->mii.phy_id;
1031 int my_phy_caps; /* My PHY capabilities */
1032 int my_ad_caps; /* My Advertised capabilities */
1033
1034 DBG(3, dev, "smc_program_phy()\n");
1035
1036 spin_lock_irq(&lp->lock);
1037
1038 /*
1039 * We should not be called if phy_type is zero.
1040 */
1041 if (lp->phy_type == 0)
1042 goto smc_phy_configure_exit;
1043
1044 if (smc_phy_reset(dev, phyaddr)) {
1045 netdev_info(dev, "PHY reset timed out\n");
1046 goto smc_phy_configure_exit;
1047 }
1048
1049 /*
1050 * Enable PHY Interrupts (for register 18)
1051 * Interrupts listed here are disabled
1052 */
1053 smc_phy_write(dev, phyaddr, PHY_MASK_REG,
1054 PHY_INT_LOSSSYNC | PHY_INT_CWRD | PHY_INT_SSD |
1055 PHY_INT_ESD | PHY_INT_RPOL | PHY_INT_JAB |
1056 PHY_INT_SPDDET | PHY_INT_DPLXDET);
1057
1058 /* Configure the Receive/Phy Control register */
1059 SMC_SELECT_BANK(lp, 0);
1060 SMC_SET_RPC(lp, lp->rpc_cur_mode);
1061
1062 /* If the user requested no auto neg, then go set his request */
1063 if (lp->mii.force_media) {
1064 smc_phy_fixed(dev);
1065 goto smc_phy_configure_exit;
1066 }
1067
1068 /* Copy our capabilities from MII_BMSR to MII_ADVERTISE */
1069 my_phy_caps = smc_phy_read(dev, phyaddr, MII_BMSR);
1070
1071 if (!(my_phy_caps & BMSR_ANEGCAPABLE)) {
1072 netdev_info(dev, "Auto negotiation NOT supported\n");
1073 smc_phy_fixed(dev);
1074 goto smc_phy_configure_exit;
1075 }
1076
1077 my_ad_caps = ADVERTISE_CSMA; /* I am CSMA capable */
1078
1079 if (my_phy_caps & BMSR_100BASE4)
1080 my_ad_caps |= ADVERTISE_100BASE4;
1081 if (my_phy_caps & BMSR_100FULL)
1082 my_ad_caps |= ADVERTISE_100FULL;
1083 if (my_phy_caps & BMSR_100HALF)
1084 my_ad_caps |= ADVERTISE_100HALF;
1085 if (my_phy_caps & BMSR_10FULL)
1086 my_ad_caps |= ADVERTISE_10FULL;
1087 if (my_phy_caps & BMSR_10HALF)
1088 my_ad_caps |= ADVERTISE_10HALF;
1089
1090 /* Disable capabilities not selected by our user */
1091 if (lp->ctl_rspeed != 100)
1092 my_ad_caps &= ~(ADVERTISE_100BASE4|ADVERTISE_100FULL|ADVERTISE_100HALF);
1093
1094 if (!lp->ctl_rfduplx)
1095 my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL);
1096
1097 /* Update our Auto-Neg Advertisement Register */
1098 smc_phy_write(dev, phyaddr, MII_ADVERTISE, my_ad_caps);
1099 lp->mii.advertising = my_ad_caps;
1100
1101 /*
1102 * Read the register back. Without this, it appears that when
1103 * auto-negotiation is restarted, sometimes it isn't ready and
1104 * the link does not come up.
1105 */
1106 smc_phy_read(dev, phyaddr, MII_ADVERTISE);
1107
1108 DBG(2, dev, "phy caps=%x\n", my_phy_caps);
1109 DBG(2, dev, "phy advertised caps=%x\n", my_ad_caps);
1110
1111 /* Restart auto-negotiation process in order to advertise my caps */
1112 smc_phy_write(dev, phyaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1113
1114 smc_phy_check_media(dev, 1);
1115
1116 smc_phy_configure_exit:
1117 SMC_SELECT_BANK(lp, 2);
1118 spin_unlock_irq(&lp->lock);
1119 }
1120
1121 /*
1122 * smc_phy_interrupt
1123 *
1124 * Purpose: Handle interrupts relating to PHY register 18. This is
1125 * called from the "hard" interrupt handler under our private spinlock.
1126 */
smc_phy_interrupt(struct net_device * dev)1127 static void smc_phy_interrupt(struct net_device *dev)
1128 {
1129 struct smc_local *lp = netdev_priv(dev);
1130 int phyaddr = lp->mii.phy_id;
1131 int phy18;
1132
1133 DBG(2, dev, "%s\n", __func__);
1134
1135 if (lp->phy_type == 0)
1136 return;
1137
1138 for(;;) {
1139 smc_phy_check_media(dev, 0);
1140
1141 /* Read PHY Register 18, Status Output */
1142 phy18 = smc_phy_read(dev, phyaddr, PHY_INT_REG);
1143 if ((phy18 & PHY_INT_INT) == 0)
1144 break;
1145 }
1146 }
1147
1148 /*--- END PHY CONTROL AND CONFIGURATION-------------------------------------*/
1149
smc_10bt_check_media(struct net_device * dev,int init)1150 static void smc_10bt_check_media(struct net_device *dev, int init)
1151 {
1152 struct smc_local *lp = netdev_priv(dev);
1153 void __iomem *ioaddr = lp->base;
1154 unsigned int old_carrier, new_carrier;
1155
1156 old_carrier = netif_carrier_ok(dev) ? 1 : 0;
1157
1158 SMC_SELECT_BANK(lp, 0);
1159 new_carrier = (SMC_GET_EPH_STATUS(lp) & ES_LINK_OK) ? 1 : 0;
1160 SMC_SELECT_BANK(lp, 2);
1161
1162 if (init || (old_carrier != new_carrier)) {
1163 if (!new_carrier) {
1164 netif_carrier_off(dev);
1165 } else {
1166 netif_carrier_on(dev);
1167 }
1168 if (netif_msg_link(lp))
1169 netdev_info(dev, "link %s\n",
1170 new_carrier ? "up" : "down");
1171 }
1172 }
1173
smc_eph_interrupt(struct net_device * dev)1174 static void smc_eph_interrupt(struct net_device *dev)
1175 {
1176 struct smc_local *lp = netdev_priv(dev);
1177 void __iomem *ioaddr = lp->base;
1178 unsigned int ctl;
1179
1180 smc_10bt_check_media(dev, 0);
1181
1182 SMC_SELECT_BANK(lp, 1);
1183 ctl = SMC_GET_CTL(lp);
1184 SMC_SET_CTL(lp, ctl & ~CTL_LE_ENABLE);
1185 SMC_SET_CTL(lp, ctl);
1186 SMC_SELECT_BANK(lp, 2);
1187 }
1188
1189 /*
1190 * This is the main routine of the driver, to handle the device when
1191 * it needs some attention.
1192 */
smc_interrupt(int irq,void * dev_id)1193 static irqreturn_t smc_interrupt(int irq, void *dev_id)
1194 {
1195 struct net_device *dev = dev_id;
1196 struct smc_local *lp = netdev_priv(dev);
1197 void __iomem *ioaddr = lp->base;
1198 int status, mask, timeout, card_stats;
1199 int saved_pointer;
1200
1201 DBG(3, dev, "%s\n", __func__);
1202
1203 spin_lock(&lp->lock);
1204
1205 /* A preamble may be used when there is a potential race
1206 * between the interruptible transmit functions and this
1207 * ISR. */
1208 SMC_INTERRUPT_PREAMBLE;
1209
1210 saved_pointer = SMC_GET_PTR(lp);
1211 mask = SMC_GET_INT_MASK(lp);
1212 SMC_SET_INT_MASK(lp, 0);
1213
1214 /* set a timeout value, so I don't stay here forever */
1215 timeout = MAX_IRQ_LOOPS;
1216
1217 do {
1218 status = SMC_GET_INT(lp);
1219
1220 DBG(2, dev, "INT 0x%02x MASK 0x%02x MEM 0x%04x FIFO 0x%04x\n",
1221 status, mask,
1222 ({ int meminfo; SMC_SELECT_BANK(lp, 0);
1223 meminfo = SMC_GET_MIR(lp);
1224 SMC_SELECT_BANK(lp, 2); meminfo; }),
1225 SMC_GET_FIFO(lp));
1226
1227 status &= mask;
1228 if (!status)
1229 break;
1230
1231 if (status & IM_TX_INT) {
1232 /* do this before RX as it will free memory quickly */
1233 DBG(3, dev, "TX int\n");
1234 smc_tx(dev);
1235 SMC_ACK_INT(lp, IM_TX_INT);
1236 if (THROTTLE_TX_PKTS)
1237 netif_wake_queue(dev);
1238 } else if (status & IM_RCV_INT) {
1239 DBG(3, dev, "RX irq\n");
1240 smc_rcv(dev);
1241 } else if (status & IM_ALLOC_INT) {
1242 DBG(3, dev, "Allocation irq\n");
1243 tasklet_hi_schedule(&lp->tx_task);
1244 mask &= ~IM_ALLOC_INT;
1245 } else if (status & IM_TX_EMPTY_INT) {
1246 DBG(3, dev, "TX empty\n");
1247 mask &= ~IM_TX_EMPTY_INT;
1248
1249 /* update stats */
1250 SMC_SELECT_BANK(lp, 0);
1251 card_stats = SMC_GET_COUNTER(lp);
1252 SMC_SELECT_BANK(lp, 2);
1253
1254 /* single collisions */
1255 dev->stats.collisions += card_stats & 0xF;
1256 card_stats >>= 4;
1257
1258 /* multiple collisions */
1259 dev->stats.collisions += card_stats & 0xF;
1260 } else if (status & IM_RX_OVRN_INT) {
1261 DBG(1, dev, "RX overrun (EPH_ST 0x%04x)\n",
1262 ({ int eph_st; SMC_SELECT_BANK(lp, 0);
1263 eph_st = SMC_GET_EPH_STATUS(lp);
1264 SMC_SELECT_BANK(lp, 2); eph_st; }));
1265 SMC_ACK_INT(lp, IM_RX_OVRN_INT);
1266 dev->stats.rx_errors++;
1267 dev->stats.rx_fifo_errors++;
1268 } else if (status & IM_EPH_INT) {
1269 smc_eph_interrupt(dev);
1270 } else if (status & IM_MDINT) {
1271 SMC_ACK_INT(lp, IM_MDINT);
1272 smc_phy_interrupt(dev);
1273 } else if (status & IM_ERCV_INT) {
1274 SMC_ACK_INT(lp, IM_ERCV_INT);
1275 PRINTK(dev, "UNSUPPORTED: ERCV INTERRUPT\n");
1276 }
1277 } while (--timeout);
1278
1279 /* restore register states */
1280 SMC_SET_PTR(lp, saved_pointer);
1281 SMC_SET_INT_MASK(lp, mask);
1282 spin_unlock(&lp->lock);
1283
1284 #ifndef CONFIG_NET_POLL_CONTROLLER
1285 if (timeout == MAX_IRQ_LOOPS)
1286 PRINTK(dev, "spurious interrupt (mask = 0x%02x)\n",
1287 mask);
1288 #endif
1289 DBG(3, dev, "Interrupt done (%d loops)\n",
1290 MAX_IRQ_LOOPS - timeout);
1291
1292 /*
1293 * We return IRQ_HANDLED unconditionally here even if there was
1294 * nothing to do. There is a possibility that a packet might
1295 * get enqueued into the chip right after TX_EMPTY_INT is raised
1296 * but just before the CPU acknowledges the IRQ.
1297 * Better take an unneeded IRQ in some occasions than complexifying
1298 * the code for all cases.
1299 */
1300 return IRQ_HANDLED;
1301 }
1302
1303 #ifdef CONFIG_NET_POLL_CONTROLLER
1304 /*
1305 * Polling receive - used by netconsole and other diagnostic tools
1306 * to allow network i/o with interrupts disabled.
1307 */
smc_poll_controller(struct net_device * dev)1308 static void smc_poll_controller(struct net_device *dev)
1309 {
1310 disable_irq(dev->irq);
1311 smc_interrupt(dev->irq, dev);
1312 enable_irq(dev->irq);
1313 }
1314 #endif
1315
1316 /* Our watchdog timed out. Called by the networking layer */
smc_timeout(struct net_device * dev,unsigned int txqueue)1317 static void smc_timeout(struct net_device *dev, unsigned int txqueue)
1318 {
1319 struct smc_local *lp = netdev_priv(dev);
1320 void __iomem *ioaddr = lp->base;
1321 int status, mask, eph_st, meminfo, fifo;
1322
1323 DBG(2, dev, "%s\n", __func__);
1324
1325 spin_lock_irq(&lp->lock);
1326 status = SMC_GET_INT(lp);
1327 mask = SMC_GET_INT_MASK(lp);
1328 fifo = SMC_GET_FIFO(lp);
1329 SMC_SELECT_BANK(lp, 0);
1330 eph_st = SMC_GET_EPH_STATUS(lp);
1331 meminfo = SMC_GET_MIR(lp);
1332 SMC_SELECT_BANK(lp, 2);
1333 spin_unlock_irq(&lp->lock);
1334 PRINTK(dev, "TX timeout (INT 0x%02x INTMASK 0x%02x MEM 0x%04x FIFO 0x%04x EPH_ST 0x%04x)\n",
1335 status, mask, meminfo, fifo, eph_st);
1336
1337 smc_reset(dev);
1338 smc_enable(dev);
1339
1340 /*
1341 * Reconfiguring the PHY doesn't seem like a bad idea here, but
1342 * smc_phy_configure() calls msleep() which calls schedule_timeout()
1343 * which calls schedule(). Hence we use a work queue.
1344 */
1345 if (lp->phy_type != 0)
1346 schedule_work(&lp->phy_configure);
1347
1348 /* We can accept TX packets again */
1349 netif_trans_update(dev); /* prevent tx timeout */
1350 netif_wake_queue(dev);
1351 }
1352
1353 /*
1354 * This routine will, depending on the values passed to it,
1355 * either make it accept multicast packets, go into
1356 * promiscuous mode (for TCPDUMP and cousins) or accept
1357 * a select set of multicast packets
1358 */
smc_set_multicast_list(struct net_device * dev)1359 static void smc_set_multicast_list(struct net_device *dev)
1360 {
1361 struct smc_local *lp = netdev_priv(dev);
1362 void __iomem *ioaddr = lp->base;
1363 unsigned char multicast_table[8];
1364 int update_multicast = 0;
1365
1366 DBG(2, dev, "%s\n", __func__);
1367
1368 if (dev->flags & IFF_PROMISC) {
1369 DBG(2, dev, "RCR_PRMS\n");
1370 lp->rcr_cur_mode |= RCR_PRMS;
1371 }
1372
1373 /* BUG? I never disable promiscuous mode if multicasting was turned on.
1374 Now, I turn off promiscuous mode, but I don't do anything to multicasting
1375 when promiscuous mode is turned on.
1376 */
1377
1378 /*
1379 * Here, I am setting this to accept all multicast packets.
1380 * I don't need to zero the multicast table, because the flag is
1381 * checked before the table is
1382 */
1383 else if (dev->flags & IFF_ALLMULTI || netdev_mc_count(dev) > 16) {
1384 DBG(2, dev, "RCR_ALMUL\n");
1385 lp->rcr_cur_mode |= RCR_ALMUL;
1386 }
1387
1388 /*
1389 * This sets the internal hardware table to filter out unwanted
1390 * multicast packets before they take up memory.
1391 *
1392 * The SMC chip uses a hash table where the high 6 bits of the CRC of
1393 * address are the offset into the table. If that bit is 1, then the
1394 * multicast packet is accepted. Otherwise, it's dropped silently.
1395 *
1396 * To use the 6 bits as an offset into the table, the high 3 bits are
1397 * the number of the 8 bit register, while the low 3 bits are the bit
1398 * within that register.
1399 */
1400 else if (!netdev_mc_empty(dev)) {
1401 struct netdev_hw_addr *ha;
1402
1403 /* table for flipping the order of 3 bits */
1404 static const unsigned char invert3[] = {0, 4, 2, 6, 1, 5, 3, 7};
1405
1406 /* start with a table of all zeros: reject all */
1407 memset(multicast_table, 0, sizeof(multicast_table));
1408
1409 netdev_for_each_mc_addr(ha, dev) {
1410 int position;
1411
1412 /* only use the low order bits */
1413 position = crc32_le(~0, ha->addr, 6) & 0x3f;
1414
1415 /* do some messy swapping to put the bit in the right spot */
1416 multicast_table[invert3[position&7]] |=
1417 (1<<invert3[(position>>3)&7]);
1418 }
1419
1420 /* be sure I get rid of flags I might have set */
1421 lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL);
1422
1423 /* now, the table can be loaded into the chipset */
1424 update_multicast = 1;
1425 } else {
1426 DBG(2, dev, "~(RCR_PRMS|RCR_ALMUL)\n");
1427 lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL);
1428
1429 /*
1430 * since I'm disabling all multicast entirely, I need to
1431 * clear the multicast list
1432 */
1433 memset(multicast_table, 0, sizeof(multicast_table));
1434 update_multicast = 1;
1435 }
1436
1437 spin_lock_irq(&lp->lock);
1438 SMC_SELECT_BANK(lp, 0);
1439 SMC_SET_RCR(lp, lp->rcr_cur_mode);
1440 if (update_multicast) {
1441 SMC_SELECT_BANK(lp, 3);
1442 SMC_SET_MCAST(lp, multicast_table);
1443 }
1444 SMC_SELECT_BANK(lp, 2);
1445 spin_unlock_irq(&lp->lock);
1446 }
1447
1448
1449 /*
1450 * Open and Initialize the board
1451 *
1452 * Set up everything, reset the card, etc..
1453 */
1454 static int
smc_open(struct net_device * dev)1455 smc_open(struct net_device *dev)
1456 {
1457 struct smc_local *lp = netdev_priv(dev);
1458
1459 DBG(2, dev, "%s\n", __func__);
1460
1461 /* Setup the default Register Modes */
1462 lp->tcr_cur_mode = TCR_DEFAULT;
1463 lp->rcr_cur_mode = RCR_DEFAULT;
1464 lp->rpc_cur_mode = RPC_DEFAULT |
1465 lp->cfg.leda << RPC_LSXA_SHFT |
1466 lp->cfg.ledb << RPC_LSXB_SHFT;
1467
1468 /*
1469 * If we are not using a MII interface, we need to
1470 * monitor our own carrier signal to detect faults.
1471 */
1472 if (lp->phy_type == 0)
1473 lp->tcr_cur_mode |= TCR_MON_CSN;
1474
1475 /* reset the hardware */
1476 smc_reset(dev);
1477 smc_enable(dev);
1478
1479 /* Configure the PHY, initialize the link state */
1480 if (lp->phy_type != 0)
1481 smc_phy_configure(&lp->phy_configure);
1482 else {
1483 spin_lock_irq(&lp->lock);
1484 smc_10bt_check_media(dev, 1);
1485 spin_unlock_irq(&lp->lock);
1486 }
1487
1488 netif_start_queue(dev);
1489 return 0;
1490 }
1491
1492 /*
1493 * smc_close
1494 *
1495 * this makes the board clean up everything that it can
1496 * and not talk to the outside world. Caused by
1497 * an 'ifconfig ethX down'
1498 */
smc_close(struct net_device * dev)1499 static int smc_close(struct net_device *dev)
1500 {
1501 struct smc_local *lp = netdev_priv(dev);
1502
1503 DBG(2, dev, "%s\n", __func__);
1504
1505 netif_stop_queue(dev);
1506 netif_carrier_off(dev);
1507
1508 /* clear everything */
1509 smc_shutdown(dev);
1510 tasklet_kill(&lp->tx_task);
1511 smc_phy_powerdown(dev);
1512 return 0;
1513 }
1514
1515 /*
1516 * Ethtool support
1517 */
1518 static int
smc_ethtool_get_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * cmd)1519 smc_ethtool_get_link_ksettings(struct net_device *dev,
1520 struct ethtool_link_ksettings *cmd)
1521 {
1522 struct smc_local *lp = netdev_priv(dev);
1523
1524 if (lp->phy_type != 0) {
1525 spin_lock_irq(&lp->lock);
1526 mii_ethtool_get_link_ksettings(&lp->mii, cmd);
1527 spin_unlock_irq(&lp->lock);
1528 } else {
1529 u32 supported = SUPPORTED_10baseT_Half |
1530 SUPPORTED_10baseT_Full |
1531 SUPPORTED_TP | SUPPORTED_AUI;
1532
1533 if (lp->ctl_rspeed == 10)
1534 cmd->base.speed = SPEED_10;
1535 else if (lp->ctl_rspeed == 100)
1536 cmd->base.speed = SPEED_100;
1537
1538 cmd->base.autoneg = AUTONEG_DISABLE;
1539 cmd->base.port = 0;
1540 cmd->base.duplex = lp->tcr_cur_mode & TCR_SWFDUP ?
1541 DUPLEX_FULL : DUPLEX_HALF;
1542
1543 ethtool_convert_legacy_u32_to_link_mode(
1544 cmd->link_modes.supported, supported);
1545 }
1546
1547 return 0;
1548 }
1549
1550 static int
smc_ethtool_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * cmd)1551 smc_ethtool_set_link_ksettings(struct net_device *dev,
1552 const struct ethtool_link_ksettings *cmd)
1553 {
1554 struct smc_local *lp = netdev_priv(dev);
1555 int ret;
1556
1557 if (lp->phy_type != 0) {
1558 spin_lock_irq(&lp->lock);
1559 ret = mii_ethtool_set_link_ksettings(&lp->mii, cmd);
1560 spin_unlock_irq(&lp->lock);
1561 } else {
1562 if (cmd->base.autoneg != AUTONEG_DISABLE ||
1563 cmd->base.speed != SPEED_10 ||
1564 (cmd->base.duplex != DUPLEX_HALF &&
1565 cmd->base.duplex != DUPLEX_FULL) ||
1566 (cmd->base.port != PORT_TP && cmd->base.port != PORT_AUI))
1567 return -EINVAL;
1568
1569 lp->ctl_rfduplx = cmd->base.duplex == DUPLEX_FULL;
1570
1571 ret = 0;
1572 }
1573
1574 return ret;
1575 }
1576
1577 static void
smc_ethtool_getdrvinfo(struct net_device * dev,struct ethtool_drvinfo * info)1578 smc_ethtool_getdrvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1579 {
1580 strscpy(info->driver, CARDNAME, sizeof(info->driver));
1581 strscpy(info->version, version, sizeof(info->version));
1582 strscpy(info->bus_info, dev_name(dev->dev.parent),
1583 sizeof(info->bus_info));
1584 }
1585
smc_ethtool_nwayreset(struct net_device * dev)1586 static int smc_ethtool_nwayreset(struct net_device *dev)
1587 {
1588 struct smc_local *lp = netdev_priv(dev);
1589 int ret = -EINVAL;
1590
1591 if (lp->phy_type != 0) {
1592 spin_lock_irq(&lp->lock);
1593 ret = mii_nway_restart(&lp->mii);
1594 spin_unlock_irq(&lp->lock);
1595 }
1596
1597 return ret;
1598 }
1599
smc_ethtool_getmsglevel(struct net_device * dev)1600 static u32 smc_ethtool_getmsglevel(struct net_device *dev)
1601 {
1602 struct smc_local *lp = netdev_priv(dev);
1603 return lp->msg_enable;
1604 }
1605
smc_ethtool_setmsglevel(struct net_device * dev,u32 level)1606 static void smc_ethtool_setmsglevel(struct net_device *dev, u32 level)
1607 {
1608 struct smc_local *lp = netdev_priv(dev);
1609 lp->msg_enable = level;
1610 }
1611
smc_write_eeprom_word(struct net_device * dev,u16 addr,u16 word)1612 static int smc_write_eeprom_word(struct net_device *dev, u16 addr, u16 word)
1613 {
1614 u16 ctl;
1615 struct smc_local *lp = netdev_priv(dev);
1616 void __iomem *ioaddr = lp->base;
1617
1618 spin_lock_irq(&lp->lock);
1619 /* load word into GP register */
1620 SMC_SELECT_BANK(lp, 1);
1621 SMC_SET_GP(lp, word);
1622 /* set the address to put the data in EEPROM */
1623 SMC_SELECT_BANK(lp, 2);
1624 SMC_SET_PTR(lp, addr);
1625 /* tell it to write */
1626 SMC_SELECT_BANK(lp, 1);
1627 ctl = SMC_GET_CTL(lp);
1628 SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_STORE));
1629 /* wait for it to finish */
1630 do {
1631 udelay(1);
1632 } while (SMC_GET_CTL(lp) & CTL_STORE);
1633 /* clean up */
1634 SMC_SET_CTL(lp, ctl);
1635 SMC_SELECT_BANK(lp, 2);
1636 spin_unlock_irq(&lp->lock);
1637 return 0;
1638 }
1639
smc_read_eeprom_word(struct net_device * dev,u16 addr,u16 * word)1640 static int smc_read_eeprom_word(struct net_device *dev, u16 addr, u16 *word)
1641 {
1642 u16 ctl;
1643 struct smc_local *lp = netdev_priv(dev);
1644 void __iomem *ioaddr = lp->base;
1645
1646 spin_lock_irq(&lp->lock);
1647 /* set the EEPROM address to get the data from */
1648 SMC_SELECT_BANK(lp, 2);
1649 SMC_SET_PTR(lp, addr | PTR_READ);
1650 /* tell it to load */
1651 SMC_SELECT_BANK(lp, 1);
1652 SMC_SET_GP(lp, 0xffff); /* init to known */
1653 ctl = SMC_GET_CTL(lp);
1654 SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_RELOAD));
1655 /* wait for it to finish */
1656 do {
1657 udelay(1);
1658 } while (SMC_GET_CTL(lp) & CTL_RELOAD);
1659 /* read word from GP register */
1660 *word = SMC_GET_GP(lp);
1661 /* clean up */
1662 SMC_SET_CTL(lp, ctl);
1663 SMC_SELECT_BANK(lp, 2);
1664 spin_unlock_irq(&lp->lock);
1665 return 0;
1666 }
1667
smc_ethtool_geteeprom_len(struct net_device * dev)1668 static int smc_ethtool_geteeprom_len(struct net_device *dev)
1669 {
1670 return 0x23 * 2;
1671 }
1672
smc_ethtool_geteeprom(struct net_device * dev,struct ethtool_eeprom * eeprom,u8 * data)1673 static int smc_ethtool_geteeprom(struct net_device *dev,
1674 struct ethtool_eeprom *eeprom, u8 *data)
1675 {
1676 int i;
1677 int imax;
1678
1679 DBG(1, dev, "Reading %d bytes at %d(0x%x)\n",
1680 eeprom->len, eeprom->offset, eeprom->offset);
1681 imax = smc_ethtool_geteeprom_len(dev);
1682 for (i = 0; i < eeprom->len; i += 2) {
1683 int ret;
1684 u16 wbuf;
1685 int offset = i + eeprom->offset;
1686 if (offset > imax)
1687 break;
1688 ret = smc_read_eeprom_word(dev, offset >> 1, &wbuf);
1689 if (ret != 0)
1690 return ret;
1691 DBG(2, dev, "Read 0x%x from 0x%x\n", wbuf, offset >> 1);
1692 data[i] = (wbuf >> 8) & 0xff;
1693 data[i+1] = wbuf & 0xff;
1694 }
1695 return 0;
1696 }
1697
smc_ethtool_seteeprom(struct net_device * dev,struct ethtool_eeprom * eeprom,u8 * data)1698 static int smc_ethtool_seteeprom(struct net_device *dev,
1699 struct ethtool_eeprom *eeprom, u8 *data)
1700 {
1701 int i;
1702 int imax;
1703
1704 DBG(1, dev, "Writing %d bytes to %d(0x%x)\n",
1705 eeprom->len, eeprom->offset, eeprom->offset);
1706 imax = smc_ethtool_geteeprom_len(dev);
1707 for (i = 0; i < eeprom->len; i += 2) {
1708 int ret;
1709 u16 wbuf;
1710 int offset = i + eeprom->offset;
1711 if (offset > imax)
1712 break;
1713 wbuf = (data[i] << 8) | data[i + 1];
1714 DBG(2, dev, "Writing 0x%x to 0x%x\n", wbuf, offset >> 1);
1715 ret = smc_write_eeprom_word(dev, offset >> 1, wbuf);
1716 if (ret != 0)
1717 return ret;
1718 }
1719 return 0;
1720 }
1721
1722
1723 static const struct ethtool_ops smc_ethtool_ops = {
1724 .get_drvinfo = smc_ethtool_getdrvinfo,
1725
1726 .get_msglevel = smc_ethtool_getmsglevel,
1727 .set_msglevel = smc_ethtool_setmsglevel,
1728 .nway_reset = smc_ethtool_nwayreset,
1729 .get_link = ethtool_op_get_link,
1730 .get_eeprom_len = smc_ethtool_geteeprom_len,
1731 .get_eeprom = smc_ethtool_geteeprom,
1732 .set_eeprom = smc_ethtool_seteeprom,
1733 .get_link_ksettings = smc_ethtool_get_link_ksettings,
1734 .set_link_ksettings = smc_ethtool_set_link_ksettings,
1735 };
1736
1737 static const struct net_device_ops smc_netdev_ops = {
1738 .ndo_open = smc_open,
1739 .ndo_stop = smc_close,
1740 .ndo_start_xmit = smc_hard_start_xmit,
1741 .ndo_tx_timeout = smc_timeout,
1742 .ndo_set_rx_mode = smc_set_multicast_list,
1743 .ndo_validate_addr = eth_validate_addr,
1744 .ndo_set_mac_address = eth_mac_addr,
1745 #ifdef CONFIG_NET_POLL_CONTROLLER
1746 .ndo_poll_controller = smc_poll_controller,
1747 #endif
1748 };
1749
1750 /*
1751 * smc_findirq
1752 *
1753 * This routine has a simple purpose -- make the SMC chip generate an
1754 * interrupt, so an auto-detect routine can detect it, and find the IRQ,
1755 */
1756 /*
1757 * does this still work?
1758 *
1759 * I just deleted auto_irq.c, since it was never built...
1760 * --jgarzik
1761 */
smc_findirq(struct smc_local * lp)1762 static int smc_findirq(struct smc_local *lp)
1763 {
1764 void __iomem *ioaddr = lp->base;
1765 int timeout = 20;
1766 unsigned long cookie;
1767
1768 DBG(2, lp->dev, "%s: %s\n", CARDNAME, __func__);
1769
1770 cookie = probe_irq_on();
1771
1772 /*
1773 * What I try to do here is trigger an ALLOC_INT. This is done
1774 * by allocating a small chunk of memory, which will give an interrupt
1775 * when done.
1776 */
1777 /* enable ALLOCation interrupts ONLY */
1778 SMC_SELECT_BANK(lp, 2);
1779 SMC_SET_INT_MASK(lp, IM_ALLOC_INT);
1780
1781 /*
1782 * Allocate 512 bytes of memory. Note that the chip was just
1783 * reset so all the memory is available
1784 */
1785 SMC_SET_MMU_CMD(lp, MC_ALLOC | 1);
1786
1787 /*
1788 * Wait until positive that the interrupt has been generated
1789 */
1790 do {
1791 int int_status;
1792 udelay(10);
1793 int_status = SMC_GET_INT(lp);
1794 if (int_status & IM_ALLOC_INT)
1795 break; /* got the interrupt */
1796 } while (--timeout);
1797
1798 /*
1799 * there is really nothing that I can do here if timeout fails,
1800 * as autoirq_report will return a 0 anyway, which is what I
1801 * want in this case. Plus, the clean up is needed in both
1802 * cases.
1803 */
1804
1805 /* and disable all interrupts again */
1806 SMC_SET_INT_MASK(lp, 0);
1807
1808 /* and return what I found */
1809 return probe_irq_off(cookie);
1810 }
1811
1812 /*
1813 * Function: smc_probe(unsigned long ioaddr)
1814 *
1815 * Purpose:
1816 * Tests to see if a given ioaddr points to an SMC91x chip.
1817 * Returns a 0 on success
1818 *
1819 * Algorithm:
1820 * (1) see if the high byte of BANK_SELECT is 0x33
1821 * (2) compare the ioaddr with the base register's address
1822 * (3) see if I recognize the chip ID in the appropriate register
1823 *
1824 * Here I do typical initialization tasks.
1825 *
1826 * o Initialize the structure if needed
1827 * o print out my vanity message if not done so already
1828 * o print out what type of hardware is detected
1829 * o print out the ethernet address
1830 * o find the IRQ
1831 * o set up my private data
1832 * o configure the dev structure with my subroutines
1833 * o actually GRAB the irq.
1834 * o GRAB the region
1835 */
smc_probe(struct net_device * dev,void __iomem * ioaddr,unsigned long irq_flags)1836 static int smc_probe(struct net_device *dev, void __iomem *ioaddr,
1837 unsigned long irq_flags)
1838 {
1839 struct smc_local *lp = netdev_priv(dev);
1840 int retval;
1841 unsigned int val, revision_register;
1842 const char *version_string;
1843 u8 addr[ETH_ALEN];
1844
1845 DBG(2, dev, "%s: %s\n", CARDNAME, __func__);
1846
1847 /* First, see if the high byte is 0x33 */
1848 val = SMC_CURRENT_BANK(lp);
1849 DBG(2, dev, "%s: bank signature probe returned 0x%04x\n",
1850 CARDNAME, val);
1851 if ((val & 0xFF00) != 0x3300) {
1852 if ((val & 0xFF) == 0x33) {
1853 netdev_warn(dev,
1854 "%s: Detected possible byte-swapped interface at IOADDR %p\n",
1855 CARDNAME, ioaddr);
1856 }
1857 retval = -ENODEV;
1858 goto err_out;
1859 }
1860
1861 /*
1862 * The above MIGHT indicate a device, but I need to write to
1863 * further test this.
1864 */
1865 SMC_SELECT_BANK(lp, 0);
1866 val = SMC_CURRENT_BANK(lp);
1867 if ((val & 0xFF00) != 0x3300) {
1868 retval = -ENODEV;
1869 goto err_out;
1870 }
1871
1872 /*
1873 * well, we've already written once, so hopefully another
1874 * time won't hurt. This time, I need to switch the bank
1875 * register to bank 1, so I can access the base address
1876 * register
1877 */
1878 SMC_SELECT_BANK(lp, 1);
1879 val = SMC_GET_BASE(lp);
1880 val = ((val & 0x1F00) >> 3) << SMC_IO_SHIFT;
1881 if (((unsigned long)ioaddr & (0x3e0 << SMC_IO_SHIFT)) != val) {
1882 netdev_warn(dev, "%s: IOADDR %p doesn't match configuration (%x).\n",
1883 CARDNAME, ioaddr, val);
1884 }
1885
1886 /*
1887 * check if the revision register is something that I
1888 * recognize. These might need to be added to later,
1889 * as future revisions could be added.
1890 */
1891 SMC_SELECT_BANK(lp, 3);
1892 revision_register = SMC_GET_REV(lp);
1893 DBG(2, dev, "%s: revision = 0x%04x\n", CARDNAME, revision_register);
1894 version_string = chip_ids[ (revision_register >> 4) & 0xF];
1895 if (!version_string || (revision_register & 0xff00) != 0x3300) {
1896 /* I don't recognize this chip, so... */
1897 netdev_warn(dev, "%s: IO %p: Unrecognized revision register 0x%04x, Contact author.\n",
1898 CARDNAME, ioaddr, revision_register);
1899
1900 retval = -ENODEV;
1901 goto err_out;
1902 }
1903
1904 /* At this point I'll assume that the chip is an SMC91x. */
1905 pr_info_once("%s\n", version);
1906
1907 /* fill in some of the fields */
1908 dev->base_addr = (unsigned long)ioaddr;
1909 lp->base = ioaddr;
1910 lp->version = revision_register & 0xff;
1911 spin_lock_init(&lp->lock);
1912
1913 /* Get the MAC address */
1914 SMC_SELECT_BANK(lp, 1);
1915 SMC_GET_MAC_ADDR(lp, addr);
1916 eth_hw_addr_set(dev, addr);
1917
1918 /* now, reset the chip, and put it into a known state */
1919 smc_reset(dev);
1920
1921 /*
1922 * If dev->irq is 0, then the device has to be banged on to see
1923 * what the IRQ is.
1924 *
1925 * This banging doesn't always detect the IRQ, for unknown reasons.
1926 * a workaround is to reset the chip and try again.
1927 *
1928 * Interestingly, the DOS packet driver *SETS* the IRQ on the card to
1929 * be what is requested on the command line. I don't do that, mostly
1930 * because the card that I have uses a non-standard method of accessing
1931 * the IRQs, and because this _should_ work in most configurations.
1932 *
1933 * Specifying an IRQ is done with the assumption that the user knows
1934 * what (s)he is doing. No checking is done!!!!
1935 */
1936 if (dev->irq < 1) {
1937 int trials;
1938
1939 trials = 3;
1940 while (trials--) {
1941 dev->irq = smc_findirq(lp);
1942 if (dev->irq)
1943 break;
1944 /* kick the card and try again */
1945 smc_reset(dev);
1946 }
1947 }
1948 if (dev->irq == 0) {
1949 netdev_warn(dev, "Couldn't autodetect your IRQ. Use irq=xx.\n");
1950 retval = -ENODEV;
1951 goto err_out;
1952 }
1953 dev->irq = irq_canonicalize(dev->irq);
1954
1955 dev->watchdog_timeo = msecs_to_jiffies(watchdog);
1956 dev->netdev_ops = &smc_netdev_ops;
1957 dev->ethtool_ops = &smc_ethtool_ops;
1958
1959 tasklet_setup(&lp->tx_task, smc_hardware_send_pkt);
1960 INIT_WORK(&lp->phy_configure, smc_phy_configure);
1961 lp->dev = dev;
1962 lp->mii.phy_id_mask = 0x1f;
1963 lp->mii.reg_num_mask = 0x1f;
1964 lp->mii.force_media = 0;
1965 lp->mii.full_duplex = 0;
1966 lp->mii.dev = dev;
1967 lp->mii.mdio_read = smc_phy_read;
1968 lp->mii.mdio_write = smc_phy_write;
1969
1970 /*
1971 * Locate the phy, if any.
1972 */
1973 if (lp->version >= (CHIP_91100 << 4))
1974 smc_phy_detect(dev);
1975
1976 /* then shut everything down to save power */
1977 smc_shutdown(dev);
1978 smc_phy_powerdown(dev);
1979
1980 /* Set default parameters */
1981 lp->msg_enable = NETIF_MSG_LINK;
1982 lp->ctl_rfduplx = 0;
1983 lp->ctl_rspeed = 10;
1984
1985 if (lp->version >= (CHIP_91100 << 4)) {
1986 lp->ctl_rfduplx = 1;
1987 lp->ctl_rspeed = 100;
1988 }
1989
1990 /* Grab the IRQ */
1991 retval = request_irq(dev->irq, smc_interrupt, irq_flags, dev->name, dev);
1992 if (retval)
1993 goto err_out;
1994
1995 #ifdef CONFIG_ARCH_PXA
1996 # ifdef SMC_USE_PXA_DMA
1997 lp->cfg.flags |= SMC91X_USE_DMA;
1998 # endif
1999 if (lp->cfg.flags & SMC91X_USE_DMA) {
2000 dma_cap_mask_t mask;
2001
2002 dma_cap_zero(mask);
2003 dma_cap_set(DMA_SLAVE, mask);
2004 lp->dma_chan = dma_request_channel(mask, NULL, NULL);
2005 }
2006 #endif
2007
2008 retval = register_netdev(dev);
2009 if (retval == 0) {
2010 /* now, print out the card info, in a short format.. */
2011 netdev_info(dev, "%s (rev %d) at %p IRQ %d",
2012 version_string, revision_register & 0x0f,
2013 lp->base, dev->irq);
2014
2015 if (lp->dma_chan)
2016 pr_cont(" DMA %p", lp->dma_chan);
2017
2018 pr_cont("%s%s\n",
2019 lp->cfg.flags & SMC91X_NOWAIT ? " [nowait]" : "",
2020 THROTTLE_TX_PKTS ? " [throttle_tx]" : "");
2021
2022 if (!is_valid_ether_addr(dev->dev_addr)) {
2023 netdev_warn(dev, "Invalid ethernet MAC address. Please set using ifconfig\n");
2024 } else {
2025 /* Print the Ethernet address */
2026 netdev_info(dev, "Ethernet addr: %pM\n",
2027 dev->dev_addr);
2028 }
2029
2030 if (lp->phy_type == 0) {
2031 PRINTK(dev, "No PHY found\n");
2032 } else if ((lp->phy_type & 0xfffffff0) == 0x0016f840) {
2033 PRINTK(dev, "PHY LAN83C183 (LAN91C111 Internal)\n");
2034 } else if ((lp->phy_type & 0xfffffff0) == 0x02821c50) {
2035 PRINTK(dev, "PHY LAN83C180\n");
2036 }
2037 }
2038
2039 err_out:
2040 #ifdef CONFIG_ARCH_PXA
2041 if (retval && lp->dma_chan)
2042 dma_release_channel(lp->dma_chan);
2043 #endif
2044 return retval;
2045 }
2046
smc_enable_device(struct platform_device * pdev)2047 static int smc_enable_device(struct platform_device *pdev)
2048 {
2049 struct net_device *ndev = platform_get_drvdata(pdev);
2050 struct smc_local *lp = netdev_priv(ndev);
2051 unsigned long flags;
2052 unsigned char ecor, ecsr;
2053 void __iomem *addr;
2054 struct resource * res;
2055
2056 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib");
2057 if (!res)
2058 return 0;
2059
2060 /*
2061 * Map the attribute space. This is overkill, but clean.
2062 */
2063 addr = ioremap(res->start, ATTRIB_SIZE);
2064 if (!addr)
2065 return -ENOMEM;
2066
2067 /*
2068 * Reset the device. We must disable IRQs around this
2069 * since a reset causes the IRQ line become active.
2070 */
2071 local_irq_save(flags);
2072 ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET;
2073 writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT));
2074 readb(addr + (ECOR << SMC_IO_SHIFT));
2075
2076 /*
2077 * Wait 100us for the chip to reset.
2078 */
2079 udelay(100);
2080
2081 /*
2082 * The device will ignore all writes to the enable bit while
2083 * reset is asserted, even if the reset bit is cleared in the
2084 * same write. Must clear reset first, then enable the device.
2085 */
2086 writeb(ecor, addr + (ECOR << SMC_IO_SHIFT));
2087 writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT));
2088
2089 /*
2090 * Set the appropriate byte/word mode.
2091 */
2092 ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8;
2093 if (!SMC_16BIT(lp))
2094 ecsr |= ECSR_IOIS8;
2095 writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT));
2096 local_irq_restore(flags);
2097
2098 iounmap(addr);
2099
2100 /*
2101 * Wait for the chip to wake up. We could poll the control
2102 * register in the main register space, but that isn't mapped
2103 * yet. We know this is going to take 750us.
2104 */
2105 msleep(1);
2106
2107 return 0;
2108 }
2109
smc_request_attrib(struct platform_device * pdev,struct net_device * ndev)2110 static int smc_request_attrib(struct platform_device *pdev,
2111 struct net_device *ndev)
2112 {
2113 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib");
2114 struct smc_local *lp __maybe_unused = netdev_priv(ndev);
2115
2116 if (!res)
2117 return 0;
2118
2119 if (!request_mem_region(res->start, ATTRIB_SIZE, CARDNAME))
2120 return -EBUSY;
2121
2122 return 0;
2123 }
2124
smc_release_attrib(struct platform_device * pdev,struct net_device * ndev)2125 static void smc_release_attrib(struct platform_device *pdev,
2126 struct net_device *ndev)
2127 {
2128 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib");
2129 struct smc_local *lp __maybe_unused = netdev_priv(ndev);
2130
2131 if (res)
2132 release_mem_region(res->start, ATTRIB_SIZE);
2133 }
2134
smc_request_datacs(struct platform_device * pdev,struct net_device * ndev)2135 static inline void smc_request_datacs(struct platform_device *pdev, struct net_device *ndev)
2136 {
2137 if (SMC_CAN_USE_DATACS) {
2138 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32");
2139 struct smc_local *lp = netdev_priv(ndev);
2140
2141 if (!res)
2142 return;
2143
2144 if(!request_mem_region(res->start, SMC_DATA_EXTENT, CARDNAME)) {
2145 netdev_info(ndev, "%s: failed to request datacs memory region.\n",
2146 CARDNAME);
2147 return;
2148 }
2149
2150 lp->datacs = ioremap(res->start, SMC_DATA_EXTENT);
2151 }
2152 }
2153
smc_release_datacs(struct platform_device * pdev,struct net_device * ndev)2154 static void smc_release_datacs(struct platform_device *pdev, struct net_device *ndev)
2155 {
2156 if (SMC_CAN_USE_DATACS) {
2157 struct smc_local *lp = netdev_priv(ndev);
2158 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32");
2159
2160 if (lp->datacs)
2161 iounmap(lp->datacs);
2162
2163 lp->datacs = NULL;
2164
2165 if (res)
2166 release_mem_region(res->start, SMC_DATA_EXTENT);
2167 }
2168 }
2169
2170 static const struct acpi_device_id smc91x_acpi_match[] = {
2171 { "LNRO0003", 0 },
2172 { }
2173 };
2174 MODULE_DEVICE_TABLE(acpi, smc91x_acpi_match);
2175
2176 #if IS_BUILTIN(CONFIG_OF)
2177 static const struct of_device_id smc91x_match[] = {
2178 { .compatible = "smsc,lan91c94", },
2179 { .compatible = "smsc,lan91c111", },
2180 {},
2181 };
2182 MODULE_DEVICE_TABLE(of, smc91x_match);
2183
2184 /**
2185 * try_toggle_control_gpio - configure a gpio if it exists
2186 * @dev: net device
2187 * @desc: where to store the GPIO descriptor, if it exists
2188 * @name: name of the GPIO in DT
2189 * @index: index of the GPIO in DT
2190 * @value: set the GPIO to this value
2191 * @nsdelay: delay before setting the GPIO
2192 */
try_toggle_control_gpio(struct device * dev,struct gpio_desc ** desc,const char * name,int index,int value,unsigned int nsdelay)2193 static int try_toggle_control_gpio(struct device *dev,
2194 struct gpio_desc **desc,
2195 const char *name, int index,
2196 int value, unsigned int nsdelay)
2197 {
2198 struct gpio_desc *gpio;
2199 enum gpiod_flags flags = value ? GPIOD_OUT_LOW : GPIOD_OUT_HIGH;
2200
2201 gpio = devm_gpiod_get_index_optional(dev, name, index, flags);
2202 if (IS_ERR(gpio))
2203 return PTR_ERR(gpio);
2204
2205 if (gpio) {
2206 if (nsdelay)
2207 usleep_range(nsdelay, 2 * nsdelay);
2208 gpiod_set_value_cansleep(gpio, value);
2209 }
2210 *desc = gpio;
2211
2212 return 0;
2213 }
2214 #endif
2215
2216 /*
2217 * smc_init(void)
2218 * Input parameters:
2219 * dev->base_addr == 0, try to find all possible locations
2220 * dev->base_addr > 0x1ff, this is the address to check
2221 * dev->base_addr == <anything else>, return failure code
2222 *
2223 * Output:
2224 * 0 --> there is a device
2225 * anything else, error
2226 */
smc_drv_probe(struct platform_device * pdev)2227 static int smc_drv_probe(struct platform_device *pdev)
2228 {
2229 struct smc91x_platdata *pd = dev_get_platdata(&pdev->dev);
2230 const struct of_device_id *match = NULL;
2231 struct smc_local *lp;
2232 struct net_device *ndev;
2233 struct resource *res;
2234 unsigned int __iomem *addr;
2235 unsigned long irq_flags = SMC_IRQ_FLAGS;
2236 unsigned long irq_resflags;
2237 int ret;
2238
2239 ndev = alloc_etherdev(sizeof(struct smc_local));
2240 if (!ndev) {
2241 ret = -ENOMEM;
2242 goto out;
2243 }
2244 SET_NETDEV_DEV(ndev, &pdev->dev);
2245
2246 /* get configuration from platform data, only allow use of
2247 * bus width if both SMC_CAN_USE_xxx and SMC91X_USE_xxx are set.
2248 */
2249
2250 lp = netdev_priv(ndev);
2251 lp->cfg.flags = 0;
2252
2253 if (pd) {
2254 memcpy(&lp->cfg, pd, sizeof(lp->cfg));
2255 lp->io_shift = SMC91X_IO_SHIFT(lp->cfg.flags);
2256
2257 if (!SMC_8BIT(lp) && !SMC_16BIT(lp)) {
2258 dev_err(&pdev->dev,
2259 "at least one of 8-bit or 16-bit access support is required.\n");
2260 ret = -ENXIO;
2261 goto out_free_netdev;
2262 }
2263 }
2264
2265 #if IS_BUILTIN(CONFIG_OF)
2266 match = of_match_device(of_match_ptr(smc91x_match), &pdev->dev);
2267 if (match) {
2268 u32 val;
2269
2270 /* Optional pwrdwn GPIO configured? */
2271 ret = try_toggle_control_gpio(&pdev->dev, &lp->power_gpio,
2272 "power", 0, 0, 100);
2273 if (ret)
2274 goto out_free_netdev;
2275
2276 /*
2277 * Optional reset GPIO configured? Minimum 100 ns reset needed
2278 * according to LAN91C96 datasheet page 14.
2279 */
2280 ret = try_toggle_control_gpio(&pdev->dev, &lp->reset_gpio,
2281 "reset", 0, 0, 100);
2282 if (ret)
2283 goto out_free_netdev;
2284
2285 /*
2286 * Need to wait for optional EEPROM to load, max 750 us according
2287 * to LAN91C96 datasheet page 55.
2288 */
2289 if (lp->reset_gpio)
2290 usleep_range(750, 1000);
2291
2292 /* Combination of IO widths supported, default to 16-bit */
2293 if (!device_property_read_u32(&pdev->dev, "reg-io-width",
2294 &val)) {
2295 if (val & 1)
2296 lp->cfg.flags |= SMC91X_USE_8BIT;
2297 if ((val == 0) || (val & 2))
2298 lp->cfg.flags |= SMC91X_USE_16BIT;
2299 if (val & 4)
2300 lp->cfg.flags |= SMC91X_USE_32BIT;
2301 } else {
2302 lp->cfg.flags |= SMC91X_USE_16BIT;
2303 }
2304 if (!device_property_read_u32(&pdev->dev, "reg-shift",
2305 &val))
2306 lp->io_shift = val;
2307 lp->cfg.pxa_u16_align4 =
2308 device_property_read_bool(&pdev->dev, "pxa-u16-align4");
2309 }
2310 #endif
2311
2312 if (!pd && !match) {
2313 lp->cfg.flags |= (SMC_CAN_USE_8BIT) ? SMC91X_USE_8BIT : 0;
2314 lp->cfg.flags |= (SMC_CAN_USE_16BIT) ? SMC91X_USE_16BIT : 0;
2315 lp->cfg.flags |= (SMC_CAN_USE_32BIT) ? SMC91X_USE_32BIT : 0;
2316 lp->cfg.flags |= (nowait) ? SMC91X_NOWAIT : 0;
2317 }
2318
2319 if (!lp->cfg.leda && !lp->cfg.ledb) {
2320 lp->cfg.leda = RPC_LSA_DEFAULT;
2321 lp->cfg.ledb = RPC_LSB_DEFAULT;
2322 }
2323
2324 ndev->dma = (unsigned char)-1;
2325
2326 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs");
2327 if (!res)
2328 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2329 if (!res) {
2330 ret = -ENODEV;
2331 goto out_free_netdev;
2332 }
2333
2334
2335 if (!request_mem_region(res->start, SMC_IO_EXTENT, CARDNAME)) {
2336 ret = -EBUSY;
2337 goto out_free_netdev;
2338 }
2339
2340 ndev->irq = platform_get_irq(pdev, 0);
2341 if (ndev->irq < 0) {
2342 ret = ndev->irq;
2343 goto out_release_io;
2344 }
2345 /*
2346 * If this platform does not specify any special irqflags, or if
2347 * the resource supplies a trigger, override the irqflags with
2348 * the trigger flags from the resource.
2349 */
2350 irq_resflags = irq_get_trigger_type(ndev->irq);
2351 if (irq_flags == -1 || irq_resflags & IRQF_TRIGGER_MASK)
2352 irq_flags = irq_resflags & IRQF_TRIGGER_MASK;
2353
2354 ret = smc_request_attrib(pdev, ndev);
2355 if (ret)
2356 goto out_release_io;
2357 #if defined(CONFIG_ASSABET_NEPONSET)
2358 if (machine_is_assabet() && machine_has_neponset())
2359 neponset_ncr_set(NCR_ENET_OSC_EN);
2360 #endif
2361 platform_set_drvdata(pdev, ndev);
2362 ret = smc_enable_device(pdev);
2363 if (ret)
2364 goto out_release_attrib;
2365
2366 addr = ioremap(res->start, SMC_IO_EXTENT);
2367 if (!addr) {
2368 ret = -ENOMEM;
2369 goto out_release_attrib;
2370 }
2371
2372 #ifdef CONFIG_ARCH_PXA
2373 {
2374 struct smc_local *lp = netdev_priv(ndev);
2375 lp->device = &pdev->dev;
2376 lp->physaddr = res->start;
2377
2378 }
2379 #endif
2380
2381 ret = smc_probe(ndev, addr, irq_flags);
2382 if (ret != 0)
2383 goto out_iounmap;
2384
2385 smc_request_datacs(pdev, ndev);
2386
2387 return 0;
2388
2389 out_iounmap:
2390 iounmap(addr);
2391 out_release_attrib:
2392 smc_release_attrib(pdev, ndev);
2393 out_release_io:
2394 release_mem_region(res->start, SMC_IO_EXTENT);
2395 out_free_netdev:
2396 free_netdev(ndev);
2397 out:
2398 pr_info("%s: not found (%d).\n", CARDNAME, ret);
2399
2400 return ret;
2401 }
2402
smc_drv_remove(struct platform_device * pdev)2403 static void smc_drv_remove(struct platform_device *pdev)
2404 {
2405 struct net_device *ndev = platform_get_drvdata(pdev);
2406 struct smc_local *lp = netdev_priv(ndev);
2407 struct resource *res;
2408
2409 unregister_netdev(ndev);
2410
2411 free_irq(ndev->irq, ndev);
2412
2413 #ifdef CONFIG_ARCH_PXA
2414 if (lp->dma_chan)
2415 dma_release_channel(lp->dma_chan);
2416 #endif
2417 iounmap(lp->base);
2418
2419 smc_release_datacs(pdev,ndev);
2420 smc_release_attrib(pdev,ndev);
2421
2422 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs");
2423 if (!res)
2424 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2425 release_mem_region(res->start, SMC_IO_EXTENT);
2426
2427 free_netdev(ndev);
2428 }
2429
smc_drv_suspend(struct device * dev)2430 static int smc_drv_suspend(struct device *dev)
2431 {
2432 struct net_device *ndev = dev_get_drvdata(dev);
2433
2434 if (ndev) {
2435 if (netif_running(ndev)) {
2436 netif_device_detach(ndev);
2437 smc_shutdown(ndev);
2438 smc_phy_powerdown(ndev);
2439 }
2440 }
2441 return 0;
2442 }
2443
smc_drv_resume(struct device * dev)2444 static int smc_drv_resume(struct device *dev)
2445 {
2446 struct platform_device *pdev = to_platform_device(dev);
2447 struct net_device *ndev = platform_get_drvdata(pdev);
2448
2449 if (ndev) {
2450 struct smc_local *lp = netdev_priv(ndev);
2451 smc_enable_device(pdev);
2452 if (netif_running(ndev)) {
2453 smc_reset(ndev);
2454 smc_enable(ndev);
2455 if (lp->phy_type != 0)
2456 smc_phy_configure(&lp->phy_configure);
2457 netif_device_attach(ndev);
2458 }
2459 }
2460 return 0;
2461 }
2462
2463 static const struct dev_pm_ops smc_drv_pm_ops = {
2464 .suspend = smc_drv_suspend,
2465 .resume = smc_drv_resume,
2466 };
2467
2468 static struct platform_driver smc_driver = {
2469 .probe = smc_drv_probe,
2470 .remove = smc_drv_remove,
2471 .driver = {
2472 .name = CARDNAME,
2473 .pm = &smc_drv_pm_ops,
2474 .of_match_table = of_match_ptr(smc91x_match),
2475 .acpi_match_table = smc91x_acpi_match,
2476 },
2477 };
2478
2479 module_platform_driver(smc_driver);
2480