1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Freescale Integrated Flash Controller NAND driver
4 *
5 * Copyright 2011-2012 Freescale Semiconductor, Inc
6 *
7 * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
8 */
9
10 #include <linux/cleanup.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/types.h>
14 #include <linux/kernel.h>
15 #include <linux/of_address.h>
16 #include <linux/slab.h>
17 #include <linux/mtd/mtd.h>
18 #include <linux/mtd/rawnand.h>
19 #include <linux/mtd/partitions.h>
20 #include <linux/fsl_ifc.h>
21 #include <linux/iopoll.h>
22
23 #define ERR_BYTE 0xFF /* Value returned for read
24 bytes when read failed */
25 #define IFC_TIMEOUT_MSECS 1000 /* Maximum timeout to wait
26 for IFC NAND Machine */
27
28 struct fsl_ifc_ctrl;
29
30 /* mtd information per set */
31 struct fsl_ifc_mtd {
32 struct nand_chip chip;
33 struct fsl_ifc_ctrl *ctrl;
34
35 struct device *dev;
36 int bank; /* Chip select bank number */
37 unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
38 u8 __iomem *vbase; /* Chip select base virtual address */
39 };
40
41 /* overview of the fsl ifc controller */
42 struct fsl_ifc_nand_ctrl {
43 struct nand_controller controller;
44 struct fsl_ifc_mtd *chips[FSL_IFC_BANK_COUNT];
45
46 void __iomem *addr; /* Address of assigned IFC buffer */
47 unsigned int page; /* Last page written to / read from */
48 unsigned int read_bytes;/* Number of bytes read during command */
49 unsigned int column; /* Saved column from SEQIN */
50 unsigned int index; /* Pointer to next byte to 'read' */
51 unsigned int oob; /* Non zero if operating on OOB data */
52 unsigned int eccread; /* Non zero for a full-page ECC read */
53 unsigned int counter; /* counter for the initializations */
54 unsigned int max_bitflips; /* Saved during READ0 cmd */
55 };
56
57 static struct fsl_ifc_nand_ctrl *ifc_nand_ctrl;
58
59 /*
60 * Generic flash bbt descriptors
61 */
62 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
63 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
64
65 static struct nand_bbt_descr bbt_main_descr = {
66 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
67 NAND_BBT_2BIT | NAND_BBT_VERSION,
68 .offs = 2, /* 0 on 8-bit small page */
69 .len = 4,
70 .veroffs = 6,
71 .maxblocks = 4,
72 .pattern = bbt_pattern,
73 };
74
75 static struct nand_bbt_descr bbt_mirror_descr = {
76 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
77 NAND_BBT_2BIT | NAND_BBT_VERSION,
78 .offs = 2, /* 0 on 8-bit small page */
79 .len = 4,
80 .veroffs = 6,
81 .maxblocks = 4,
82 .pattern = mirror_pattern,
83 };
84
fsl_ifc_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)85 static int fsl_ifc_ooblayout_ecc(struct mtd_info *mtd, int section,
86 struct mtd_oob_region *oobregion)
87 {
88 struct nand_chip *chip = mtd_to_nand(mtd);
89
90 if (section)
91 return -ERANGE;
92
93 oobregion->offset = 8;
94 oobregion->length = chip->ecc.total;
95
96 return 0;
97 }
98
fsl_ifc_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)99 static int fsl_ifc_ooblayout_free(struct mtd_info *mtd, int section,
100 struct mtd_oob_region *oobregion)
101 {
102 struct nand_chip *chip = mtd_to_nand(mtd);
103
104 if (section > 1)
105 return -ERANGE;
106
107 if (mtd->writesize == 512 &&
108 !(chip->options & NAND_BUSWIDTH_16)) {
109 if (!section) {
110 oobregion->offset = 0;
111 oobregion->length = 5;
112 } else {
113 oobregion->offset = 6;
114 oobregion->length = 2;
115 }
116
117 return 0;
118 }
119
120 if (!section) {
121 oobregion->offset = 2;
122 oobregion->length = 6;
123 } else {
124 oobregion->offset = chip->ecc.total + 8;
125 oobregion->length = mtd->oobsize - oobregion->offset;
126 }
127
128 return 0;
129 }
130
131 static const struct mtd_ooblayout_ops fsl_ifc_ooblayout_ops = {
132 .ecc = fsl_ifc_ooblayout_ecc,
133 .free = fsl_ifc_ooblayout_free,
134 };
135
136 /*
137 * Set up the IFC hardware block and page address fields, and the ifc nand
138 * structure addr field to point to the correct IFC buffer in memory
139 */
set_addr(struct mtd_info * mtd,int column,int page_addr,int oob)140 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
141 {
142 struct nand_chip *chip = mtd_to_nand(mtd);
143 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
144 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
145 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
146 int buf_num;
147
148 ifc_nand_ctrl->page = page_addr;
149 /* Program ROW0/COL0 */
150 ifc_out32(page_addr, &ifc->ifc_nand.row0);
151 ifc_out32((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0);
152
153 buf_num = page_addr & priv->bufnum_mask;
154
155 ifc_nand_ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
156 ifc_nand_ctrl->index = column;
157
158 /* for OOB data point to the second half of the buffer */
159 if (oob)
160 ifc_nand_ctrl->index += mtd->writesize;
161 }
162
163 /* returns nonzero if entire page is blank */
check_read_ecc(struct mtd_info * mtd,struct fsl_ifc_ctrl * ctrl,u32 eccstat,unsigned int bufnum)164 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
165 u32 eccstat, unsigned int bufnum)
166 {
167 return (eccstat >> ((3 - bufnum % 4) * 8)) & 15;
168 }
169
170 /*
171 * execute IFC NAND command and wait for it to complete
172 */
fsl_ifc_run_command(struct mtd_info * mtd)173 static void fsl_ifc_run_command(struct mtd_info *mtd)
174 {
175 struct nand_chip *chip = mtd_to_nand(mtd);
176 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
177 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
178 struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
179 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
180 u32 eccstat;
181 int i;
182
183 /* set the chip select for NAND Transaction */
184 ifc_out32(priv->bank << IFC_NAND_CSEL_SHIFT,
185 &ifc->ifc_nand.nand_csel);
186
187 dev_vdbg(priv->dev,
188 "%s: fir0=%08x fcr0=%08x\n",
189 __func__,
190 ifc_in32(&ifc->ifc_nand.nand_fir0),
191 ifc_in32(&ifc->ifc_nand.nand_fcr0));
192
193 ctrl->nand_stat = 0;
194
195 /* start read/write seq */
196 ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
197
198 /* wait for command complete flag or timeout */
199 wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
200 msecs_to_jiffies(IFC_TIMEOUT_MSECS));
201
202 /* ctrl->nand_stat will be updated from IRQ context */
203 if (!ctrl->nand_stat)
204 dev_err(priv->dev, "Controller is not responding\n");
205 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_FTOER)
206 dev_err(priv->dev, "NAND Flash Timeout Error\n");
207 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_WPER)
208 dev_err(priv->dev, "NAND Flash Write Protect Error\n");
209
210 nctrl->max_bitflips = 0;
211
212 if (nctrl->eccread) {
213 int errors;
214 int bufnum = nctrl->page & priv->bufnum_mask;
215 int sector_start = bufnum * chip->ecc.steps;
216 int sector_end = sector_start + chip->ecc.steps - 1;
217 __be32 __iomem *eccstat_regs;
218
219 eccstat_regs = ifc->ifc_nand.nand_eccstat;
220 eccstat = ifc_in32(&eccstat_regs[sector_start / 4]);
221
222 for (i = sector_start; i <= sector_end; i++) {
223 if (i != sector_start && !(i % 4))
224 eccstat = ifc_in32(&eccstat_regs[i / 4]);
225
226 errors = check_read_ecc(mtd, ctrl, eccstat, i);
227
228 if (errors == 15) {
229 /*
230 * Uncorrectable error.
231 * We'll check for blank pages later.
232 *
233 * We disable ECCER reporting due to...
234 * erratum IFC-A002770 -- so report it now if we
235 * see an uncorrectable error in ECCSTAT.
236 */
237 ctrl->nand_stat |= IFC_NAND_EVTER_STAT_ECCER;
238 continue;
239 }
240
241 mtd->ecc_stats.corrected += errors;
242 nctrl->max_bitflips = max_t(unsigned int,
243 nctrl->max_bitflips,
244 errors);
245 }
246
247 nctrl->eccread = 0;
248 }
249 }
250
fsl_ifc_do_read(struct nand_chip * chip,int oob,struct mtd_info * mtd)251 static void fsl_ifc_do_read(struct nand_chip *chip,
252 int oob,
253 struct mtd_info *mtd)
254 {
255 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
256 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
257 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
258
259 /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
260 if (mtd->writesize > 512) {
261 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
262 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
263 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
264 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
265 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT),
266 &ifc->ifc_nand.nand_fir0);
267 ifc_out32(0x0, &ifc->ifc_nand.nand_fir1);
268
269 ifc_out32((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
270 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT),
271 &ifc->ifc_nand.nand_fcr0);
272 } else {
273 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
274 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
275 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
276 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT),
277 &ifc->ifc_nand.nand_fir0);
278 ifc_out32(0x0, &ifc->ifc_nand.nand_fir1);
279
280 if (oob)
281 ifc_out32(NAND_CMD_READOOB <<
282 IFC_NAND_FCR0_CMD0_SHIFT,
283 &ifc->ifc_nand.nand_fcr0);
284 else
285 ifc_out32(NAND_CMD_READ0 <<
286 IFC_NAND_FCR0_CMD0_SHIFT,
287 &ifc->ifc_nand.nand_fcr0);
288 }
289 }
290
291 /* cmdfunc send commands to the IFC NAND Machine */
fsl_ifc_cmdfunc(struct nand_chip * chip,unsigned int command,int column,int page_addr)292 static void fsl_ifc_cmdfunc(struct nand_chip *chip, unsigned int command,
293 int column, int page_addr) {
294 struct mtd_info *mtd = nand_to_mtd(chip);
295 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
296 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
297 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
298
299 /* clear the read buffer */
300 ifc_nand_ctrl->read_bytes = 0;
301 if (command != NAND_CMD_PAGEPROG)
302 ifc_nand_ctrl->index = 0;
303
304 switch (command) {
305 /* READ0 read the entire buffer to use hardware ECC. */
306 case NAND_CMD_READ0:
307 ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
308 set_addr(mtd, 0, page_addr, 0);
309
310 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
311 ifc_nand_ctrl->index += column;
312
313 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST)
314 ifc_nand_ctrl->eccread = 1;
315
316 fsl_ifc_do_read(chip, 0, mtd);
317 fsl_ifc_run_command(mtd);
318 return;
319
320 /* READOOB reads only the OOB because no ECC is performed. */
321 case NAND_CMD_READOOB:
322 ifc_out32(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr);
323 set_addr(mtd, column, page_addr, 1);
324
325 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
326
327 fsl_ifc_do_read(chip, 1, mtd);
328 fsl_ifc_run_command(mtd);
329
330 return;
331
332 case NAND_CMD_READID:
333 case NAND_CMD_PARAM: {
334 /*
335 * For READID, read 8 bytes that are currently used.
336 * For PARAM, read all 3 copies of 256-bytes pages.
337 */
338 int len = 8;
339 int timing = IFC_FIR_OP_RB;
340 if (command == NAND_CMD_PARAM) {
341 timing = IFC_FIR_OP_RBCD;
342 len = 256 * 3;
343 }
344
345 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
346 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
347 (timing << IFC_NAND_FIR0_OP2_SHIFT),
348 &ifc->ifc_nand.nand_fir0);
349 ifc_out32(command << IFC_NAND_FCR0_CMD0_SHIFT,
350 &ifc->ifc_nand.nand_fcr0);
351 ifc_out32(column, &ifc->ifc_nand.row3);
352
353 ifc_out32(len, &ifc->ifc_nand.nand_fbcr);
354 ifc_nand_ctrl->read_bytes = len;
355
356 set_addr(mtd, 0, 0, 0);
357 fsl_ifc_run_command(mtd);
358 return;
359 }
360
361 /* ERASE1 stores the block and page address */
362 case NAND_CMD_ERASE1:
363 set_addr(mtd, 0, page_addr, 0);
364 return;
365
366 /* ERASE2 uses the block and page address from ERASE1 */
367 case NAND_CMD_ERASE2:
368 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
369 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
370 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT),
371 &ifc->ifc_nand.nand_fir0);
372
373 ifc_out32((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
374 (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT),
375 &ifc->ifc_nand.nand_fcr0);
376
377 ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
378 ifc_nand_ctrl->read_bytes = 0;
379 fsl_ifc_run_command(mtd);
380 return;
381
382 /* SEQIN sets up the addr buffer and all registers except the length */
383 case NAND_CMD_SEQIN: {
384 u32 nand_fcr0;
385 ifc_nand_ctrl->column = column;
386 ifc_nand_ctrl->oob = 0;
387
388 if (mtd->writesize > 512) {
389 nand_fcr0 =
390 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
391 (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
392 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
393
394 ifc_out32(
395 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
396 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
397 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
398 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
399 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT),
400 &ifc->ifc_nand.nand_fir0);
401 ifc_out32(
402 (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
403 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP6_SHIFT) |
404 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT),
405 &ifc->ifc_nand.nand_fir1);
406 } else {
407 nand_fcr0 = ((NAND_CMD_PAGEPROG <<
408 IFC_NAND_FCR0_CMD1_SHIFT) |
409 (NAND_CMD_SEQIN <<
410 IFC_NAND_FCR0_CMD2_SHIFT) |
411 (NAND_CMD_STATUS <<
412 IFC_NAND_FCR0_CMD3_SHIFT));
413
414 ifc_out32(
415 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
416 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
417 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
418 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
419 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT),
420 &ifc->ifc_nand.nand_fir0);
421 ifc_out32(
422 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
423 (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
424 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP7_SHIFT) |
425 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT),
426 &ifc->ifc_nand.nand_fir1);
427
428 if (column >= mtd->writesize)
429 nand_fcr0 |=
430 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
431 else
432 nand_fcr0 |=
433 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
434 }
435
436 if (column >= mtd->writesize) {
437 /* OOB area --> READOOB */
438 column -= mtd->writesize;
439 ifc_nand_ctrl->oob = 1;
440 }
441 ifc_out32(nand_fcr0, &ifc->ifc_nand.nand_fcr0);
442 set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob);
443 return;
444 }
445
446 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
447 case NAND_CMD_PAGEPROG: {
448 if (ifc_nand_ctrl->oob) {
449 ifc_out32(ifc_nand_ctrl->index -
450 ifc_nand_ctrl->column,
451 &ifc->ifc_nand.nand_fbcr);
452 } else {
453 ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
454 }
455
456 fsl_ifc_run_command(mtd);
457 return;
458 }
459
460 case NAND_CMD_STATUS: {
461 void __iomem *addr;
462
463 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
464 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT),
465 &ifc->ifc_nand.nand_fir0);
466 ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
467 &ifc->ifc_nand.nand_fcr0);
468 ifc_out32(1, &ifc->ifc_nand.nand_fbcr);
469 set_addr(mtd, 0, 0, 0);
470 ifc_nand_ctrl->read_bytes = 1;
471
472 fsl_ifc_run_command(mtd);
473
474 /*
475 * The chip always seems to report that it is
476 * write-protected, even when it is not.
477 */
478 addr = ifc_nand_ctrl->addr;
479 if (chip->options & NAND_BUSWIDTH_16)
480 ifc_out16(ifc_in16(addr) | (NAND_STATUS_WP), addr);
481 else
482 ifc_out8(ifc_in8(addr) | (NAND_STATUS_WP), addr);
483 return;
484 }
485
486 case NAND_CMD_RESET:
487 ifc_out32(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT,
488 &ifc->ifc_nand.nand_fir0);
489 ifc_out32(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT,
490 &ifc->ifc_nand.nand_fcr0);
491 fsl_ifc_run_command(mtd);
492 return;
493
494 default:
495 dev_err(priv->dev, "%s: error, unsupported command 0x%x.\n",
496 __func__, command);
497 }
498 }
499
fsl_ifc_select_chip(struct nand_chip * chip,int cs)500 static void fsl_ifc_select_chip(struct nand_chip *chip, int cs)
501 {
502 /* The hardware does not seem to support multiple
503 * chips per bank.
504 */
505 }
506
507 /*
508 * Write buf to the IFC NAND Controller Data Buffer
509 */
fsl_ifc_write_buf(struct nand_chip * chip,const u8 * buf,int len)510 static void fsl_ifc_write_buf(struct nand_chip *chip, const u8 *buf, int len)
511 {
512 struct mtd_info *mtd = nand_to_mtd(chip);
513 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
514 unsigned int bufsize = mtd->writesize + mtd->oobsize;
515
516 if (len <= 0) {
517 dev_err(priv->dev, "%s: len %d bytes", __func__, len);
518 return;
519 }
520
521 if ((unsigned int)len > bufsize - ifc_nand_ctrl->index) {
522 dev_err(priv->dev,
523 "%s: beyond end of buffer (%d requested, %u available)\n",
524 __func__, len, bufsize - ifc_nand_ctrl->index);
525 len = bufsize - ifc_nand_ctrl->index;
526 }
527
528 memcpy_toio(ifc_nand_ctrl->addr + ifc_nand_ctrl->index, buf, len);
529 ifc_nand_ctrl->index += len;
530 }
531
532 /*
533 * Read a byte from either the IFC hardware buffer
534 * read function for 8-bit buswidth
535 */
fsl_ifc_read_byte(struct nand_chip * chip)536 static uint8_t fsl_ifc_read_byte(struct nand_chip *chip)
537 {
538 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
539 unsigned int offset;
540
541 /*
542 * If there are still bytes in the IFC buffer, then use the
543 * next byte.
544 */
545 if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
546 offset = ifc_nand_ctrl->index++;
547 return ifc_in8(ifc_nand_ctrl->addr + offset);
548 }
549
550 dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
551 return ERR_BYTE;
552 }
553
554 /*
555 * Read two bytes from the IFC hardware buffer
556 * read function for 16-bit buswith
557 */
fsl_ifc_read_byte16(struct nand_chip * chip)558 static uint8_t fsl_ifc_read_byte16(struct nand_chip *chip)
559 {
560 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
561 uint16_t data;
562
563 /*
564 * If there are still bytes in the IFC buffer, then use the
565 * next byte.
566 */
567 if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
568 data = ifc_in16(ifc_nand_ctrl->addr + ifc_nand_ctrl->index);
569 ifc_nand_ctrl->index += 2;
570 return (uint8_t) data;
571 }
572
573 dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
574 return ERR_BYTE;
575 }
576
577 /*
578 * Read from the IFC Controller Data Buffer
579 */
fsl_ifc_read_buf(struct nand_chip * chip,u8 * buf,int len)580 static void fsl_ifc_read_buf(struct nand_chip *chip, u8 *buf, int len)
581 {
582 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
583 int avail;
584
585 if (len < 0) {
586 dev_err(priv->dev, "%s: len %d bytes", __func__, len);
587 return;
588 }
589
590 avail = min((unsigned int)len,
591 ifc_nand_ctrl->read_bytes - ifc_nand_ctrl->index);
592 memcpy_fromio(buf, ifc_nand_ctrl->addr + ifc_nand_ctrl->index, avail);
593 ifc_nand_ctrl->index += avail;
594
595 if (len > avail)
596 dev_err(priv->dev,
597 "%s: beyond end of buffer (%d requested, %d available)\n",
598 __func__, len, avail);
599 }
600
601 /*
602 * This function is called after Program and Erase Operations to
603 * check for success or failure.
604 */
fsl_ifc_wait(struct nand_chip * chip)605 static int fsl_ifc_wait(struct nand_chip *chip)
606 {
607 struct mtd_info *mtd = nand_to_mtd(chip);
608 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
609 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
610 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
611 u32 nand_fsr;
612 int status;
613
614 /* Use READ_STATUS command, but wait for the device to be ready */
615 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
616 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT),
617 &ifc->ifc_nand.nand_fir0);
618 ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
619 &ifc->ifc_nand.nand_fcr0);
620 ifc_out32(1, &ifc->ifc_nand.nand_fbcr);
621 set_addr(mtd, 0, 0, 0);
622 ifc_nand_ctrl->read_bytes = 1;
623
624 fsl_ifc_run_command(mtd);
625
626 nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
627 status = nand_fsr >> 24;
628 /*
629 * The chip always seems to report that it is
630 * write-protected, even when it is not.
631 */
632 return status | NAND_STATUS_WP;
633 }
634
635 /*
636 * The controller does not check for bitflips in erased pages,
637 * therefore software must check instead.
638 */
check_erased_page(struct nand_chip * chip,u8 * buf)639 static int check_erased_page(struct nand_chip *chip, u8 *buf)
640 {
641 struct mtd_info *mtd = nand_to_mtd(chip);
642 u8 *ecc = chip->oob_poi;
643 const int ecc_size = chip->ecc.bytes;
644 const int pkt_size = chip->ecc.size;
645 int i, res, bitflips = 0;
646 struct mtd_oob_region oobregion = { };
647
648 mtd_ooblayout_ecc(mtd, 0, &oobregion);
649 ecc += oobregion.offset;
650
651 for (i = 0; i < chip->ecc.steps; ++i) {
652 res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size,
653 NULL, 0,
654 chip->ecc.strength);
655 if (res < 0)
656 mtd->ecc_stats.failed++;
657 else
658 mtd->ecc_stats.corrected += res;
659
660 bitflips = max(res, bitflips);
661 buf += pkt_size;
662 ecc += ecc_size;
663 }
664
665 return bitflips;
666 }
667
fsl_ifc_read_page(struct nand_chip * chip,uint8_t * buf,int oob_required,int page)668 static int fsl_ifc_read_page(struct nand_chip *chip, uint8_t *buf,
669 int oob_required, int page)
670 {
671 struct mtd_info *mtd = nand_to_mtd(chip);
672 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
673 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
674 struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
675
676 nand_read_page_op(chip, page, 0, buf, mtd->writesize);
677 if (oob_required)
678 fsl_ifc_read_buf(chip, chip->oob_poi, mtd->oobsize);
679
680 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_ECCER) {
681 if (!oob_required)
682 fsl_ifc_read_buf(chip, chip->oob_poi, mtd->oobsize);
683
684 return check_erased_page(chip, buf);
685 }
686
687 if (!ctrl->nand_stat) {
688 mtd->ecc_stats.failed++;
689 return -ETIMEDOUT;
690 }
691
692 if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC) {
693 mtd->ecc_stats.failed++;
694 return -EIO;
695 }
696
697 return nctrl->max_bitflips;
698 }
699
700 /* ECC will be calculated automatically, and errors will be detected in
701 * waitfunc.
702 */
fsl_ifc_write_page(struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)703 static int fsl_ifc_write_page(struct nand_chip *chip, const uint8_t *buf,
704 int oob_required, int page)
705 {
706 struct mtd_info *mtd = nand_to_mtd(chip);
707
708 nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
709 fsl_ifc_write_buf(chip, chip->oob_poi, mtd->oobsize);
710
711 return nand_prog_page_end_op(chip);
712 }
713
fsl_ifc_attach_chip(struct nand_chip * chip)714 static int fsl_ifc_attach_chip(struct nand_chip *chip)
715 {
716 struct mtd_info *mtd = nand_to_mtd(chip);
717 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
718 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
719 struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
720 u32 csor;
721
722 csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor);
723
724 /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
725 if (csor & CSOR_NAND_ECC_DEC_EN) {
726 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
727 mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops);
728
729 /* Hardware generates ECC per 512 Bytes */
730 chip->ecc.size = 512;
731 if ((csor & CSOR_NAND_ECC_MODE_MASK) == CSOR_NAND_ECC_MODE_4) {
732 chip->ecc.bytes = 8;
733 chip->ecc.strength = 4;
734 } else {
735 chip->ecc.bytes = 16;
736 chip->ecc.strength = 8;
737 }
738 } else {
739 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
740 chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
741 }
742
743 dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
744 nanddev_ntargets(&chip->base));
745 dev_dbg(priv->dev, "%s: nand->chipsize = %lld\n", __func__,
746 nanddev_target_size(&chip->base));
747 dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__,
748 chip->pagemask);
749 dev_dbg(priv->dev, "%s: nand->legacy.chip_delay = %d\n", __func__,
750 chip->legacy.chip_delay);
751 dev_dbg(priv->dev, "%s: nand->badblockpos = %d\n", __func__,
752 chip->badblockpos);
753 dev_dbg(priv->dev, "%s: nand->chip_shift = %d\n", __func__,
754 chip->chip_shift);
755 dev_dbg(priv->dev, "%s: nand->page_shift = %d\n", __func__,
756 chip->page_shift);
757 dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__,
758 chip->phys_erase_shift);
759 dev_dbg(priv->dev, "%s: nand->ecc.engine_type = %d\n", __func__,
760 chip->ecc.engine_type);
761 dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__,
762 chip->ecc.steps);
763 dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__,
764 chip->ecc.bytes);
765 dev_dbg(priv->dev, "%s: nand->ecc.total = %d\n", __func__,
766 chip->ecc.total);
767 dev_dbg(priv->dev, "%s: mtd->ooblayout = %p\n", __func__,
768 mtd->ooblayout);
769 dev_dbg(priv->dev, "%s: mtd->flags = %08x\n", __func__, mtd->flags);
770 dev_dbg(priv->dev, "%s: mtd->size = %lld\n", __func__, mtd->size);
771 dev_dbg(priv->dev, "%s: mtd->erasesize = %d\n", __func__,
772 mtd->erasesize);
773 dev_dbg(priv->dev, "%s: mtd->writesize = %d\n", __func__,
774 mtd->writesize);
775 dev_dbg(priv->dev, "%s: mtd->oobsize = %d\n", __func__,
776 mtd->oobsize);
777
778 return 0;
779 }
780
781 static const struct nand_controller_ops fsl_ifc_controller_ops = {
782 .attach_chip = fsl_ifc_attach_chip,
783 };
784
fsl_ifc_sram_init(struct fsl_ifc_mtd * priv)785 static int fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
786 {
787 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
788 struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs;
789 struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
790 uint32_t csor = 0, csor_8k = 0, csor_ext = 0;
791 uint32_t cs = priv->bank;
792
793 if (ctrl->version < FSL_IFC_VERSION_1_1_0)
794 return 0;
795
796 if (ctrl->version > FSL_IFC_VERSION_1_1_0) {
797 u32 ncfgr, status;
798 int ret;
799
800 /* Trigger auto initialization */
801 ncfgr = ifc_in32(&ifc_runtime->ifc_nand.ncfgr);
802 ifc_out32(ncfgr | IFC_NAND_NCFGR_SRAM_INIT_EN, &ifc_runtime->ifc_nand.ncfgr);
803
804 /* Wait until done */
805 ret = readx_poll_timeout(ifc_in32, &ifc_runtime->ifc_nand.ncfgr,
806 status, !(status & IFC_NAND_NCFGR_SRAM_INIT_EN),
807 10, IFC_TIMEOUT_MSECS * 1000);
808 if (ret)
809 dev_err(priv->dev, "Failed to initialize SRAM!\n");
810
811 return ret;
812 }
813
814 /* Save CSOR and CSOR_ext */
815 csor = ifc_in32(&ifc_global->csor_cs[cs].csor);
816 csor_ext = ifc_in32(&ifc_global->csor_cs[cs].csor_ext);
817
818 /* chage PageSize 8K and SpareSize 1K*/
819 csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
820 ifc_out32(csor_8k, &ifc_global->csor_cs[cs].csor);
821 ifc_out32(0x0000400, &ifc_global->csor_cs[cs].csor_ext);
822
823 /* READID */
824 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
825 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
826 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),
827 &ifc_runtime->ifc_nand.nand_fir0);
828 ifc_out32(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT,
829 &ifc_runtime->ifc_nand.nand_fcr0);
830 ifc_out32(0x0, &ifc_runtime->ifc_nand.row3);
831
832 ifc_out32(0x0, &ifc_runtime->ifc_nand.nand_fbcr);
833
834 /* Program ROW0/COL0 */
835 ifc_out32(0x0, &ifc_runtime->ifc_nand.row0);
836 ifc_out32(0x0, &ifc_runtime->ifc_nand.col0);
837
838 /* set the chip select for NAND Transaction */
839 ifc_out32(cs << IFC_NAND_CSEL_SHIFT,
840 &ifc_runtime->ifc_nand.nand_csel);
841
842 /* start read seq */
843 ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT,
844 &ifc_runtime->ifc_nand.nandseq_strt);
845
846 /* wait for command complete flag or timeout */
847 wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
848 msecs_to_jiffies(IFC_TIMEOUT_MSECS));
849
850 if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC) {
851 pr_err("fsl-ifc: Failed to Initialise SRAM\n");
852 return -ETIMEDOUT;
853 }
854
855 /* Restore CSOR and CSOR_ext */
856 ifc_out32(csor, &ifc_global->csor_cs[cs].csor);
857 ifc_out32(csor_ext, &ifc_global->csor_cs[cs].csor_ext);
858
859 return 0;
860 }
861
fsl_ifc_chip_init(struct fsl_ifc_mtd * priv)862 static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
863 {
864 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
865 struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
866 struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs;
867 struct nand_chip *chip = &priv->chip;
868 struct mtd_info *mtd = nand_to_mtd(&priv->chip);
869 u32 csor;
870 int ret;
871
872 /* Fill in fsl_ifc_mtd structure */
873 mtd->dev.parent = priv->dev;
874
875 struct device_node *np __free(device_node) =
876 of_get_next_child_with_prefix(priv->dev->of_node, NULL, "nand");
877
878 if (np)
879 nand_set_flash_node(chip, np);
880 else
881 nand_set_flash_node(chip, priv->dev->of_node);
882
883 /* fill in nand_chip structure */
884 /* set up function call table */
885 if ((ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr))
886 & CSPR_PORT_SIZE_16)
887 chip->legacy.read_byte = fsl_ifc_read_byte16;
888 else
889 chip->legacy.read_byte = fsl_ifc_read_byte;
890
891 chip->legacy.write_buf = fsl_ifc_write_buf;
892 chip->legacy.read_buf = fsl_ifc_read_buf;
893 chip->legacy.select_chip = fsl_ifc_select_chip;
894 chip->legacy.cmdfunc = fsl_ifc_cmdfunc;
895 chip->legacy.waitfunc = fsl_ifc_wait;
896 chip->legacy.set_features = nand_get_set_features_notsupp;
897 chip->legacy.get_features = nand_get_set_features_notsupp;
898
899 chip->bbt_td = &bbt_main_descr;
900 chip->bbt_md = &bbt_mirror_descr;
901
902 ifc_out32(0x0, &ifc_runtime->ifc_nand.ncfgr);
903
904 /* set up nand options */
905 chip->bbt_options = NAND_BBT_USE_FLASH;
906 chip->options = NAND_NO_SUBPAGE_WRITE;
907
908 if (ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr)
909 & CSPR_PORT_SIZE_16) {
910 chip->legacy.read_byte = fsl_ifc_read_byte16;
911 chip->options |= NAND_BUSWIDTH_16;
912 } else {
913 chip->legacy.read_byte = fsl_ifc_read_byte;
914 }
915
916 chip->controller = &ifc_nand_ctrl->controller;
917 nand_set_controller_data(chip, priv);
918
919 chip->ecc.read_page = fsl_ifc_read_page;
920 chip->ecc.write_page = fsl_ifc_write_page;
921
922 csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor);
923
924 switch (csor & CSOR_NAND_PGS_MASK) {
925 case CSOR_NAND_PGS_512:
926 if (!(chip->options & NAND_BUSWIDTH_16)) {
927 /* Avoid conflict with bad block marker */
928 bbt_main_descr.offs = 0;
929 bbt_mirror_descr.offs = 0;
930 }
931
932 priv->bufnum_mask = 15;
933 break;
934
935 case CSOR_NAND_PGS_2K:
936 priv->bufnum_mask = 3;
937 break;
938
939 case CSOR_NAND_PGS_4K:
940 priv->bufnum_mask = 1;
941 break;
942
943 case CSOR_NAND_PGS_8K:
944 priv->bufnum_mask = 0;
945 break;
946
947 default:
948 dev_err(priv->dev, "bad csor %#x: bad page size\n", csor);
949 return -ENODEV;
950 }
951
952 ret = fsl_ifc_sram_init(priv);
953 if (ret)
954 return ret;
955
956 /*
957 * As IFC version 2.0.0 has 16KB of internal SRAM as compared to older
958 * versions which had 8KB. Hence bufnum mask needs to be updated.
959 */
960 if (ctrl->version >= FSL_IFC_VERSION_2_0_0)
961 priv->bufnum_mask = (priv->bufnum_mask * 2) + 1;
962
963 return 0;
964 }
965
fsl_ifc_chip_remove(struct fsl_ifc_mtd * priv)966 static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv)
967 {
968 struct mtd_info *mtd = nand_to_mtd(&priv->chip);
969
970 kfree(mtd->name);
971
972 if (priv->vbase)
973 iounmap(priv->vbase);
974
975 ifc_nand_ctrl->chips[priv->bank] = NULL;
976
977 return 0;
978 }
979
match_bank(struct fsl_ifc_global __iomem * ifc_global,int bank,phys_addr_t addr)980 static int match_bank(struct fsl_ifc_global __iomem *ifc_global, int bank,
981 phys_addr_t addr)
982 {
983 u32 cspr = ifc_in32(&ifc_global->cspr_cs[bank].cspr);
984
985 if (!(cspr & CSPR_V))
986 return 0;
987 if ((cspr & CSPR_MSEL) != CSPR_MSEL_NAND)
988 return 0;
989
990 return (cspr & CSPR_BA) == convert_ifc_address(addr);
991 }
992
993 static DEFINE_MUTEX(fsl_ifc_nand_mutex);
994
fsl_ifc_nand_probe(struct platform_device * dev)995 static int fsl_ifc_nand_probe(struct platform_device *dev)
996 {
997 struct fsl_ifc_runtime __iomem *ifc;
998 struct fsl_ifc_mtd *priv;
999 struct resource res;
1000 static const char *part_probe_types[]
1001 = { "cmdlinepart", "RedBoot", "ofpart", NULL };
1002 int ret;
1003 int bank;
1004 struct device_node *node = dev->dev.of_node;
1005 struct mtd_info *mtd;
1006
1007 if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->rregs)
1008 return -ENODEV;
1009 ifc = fsl_ifc_ctrl_dev->rregs;
1010
1011 /* get, allocate and map the memory resource */
1012 ret = of_address_to_resource(node, 0, &res);
1013 if (ret) {
1014 dev_err(&dev->dev, "%s: failed to get resource\n", __func__);
1015 return ret;
1016 }
1017
1018 /* find which chip select it is connected to */
1019 for (bank = 0; bank < fsl_ifc_ctrl_dev->banks; bank++) {
1020 if (match_bank(fsl_ifc_ctrl_dev->gregs, bank, res.start))
1021 break;
1022 }
1023
1024 if (bank >= fsl_ifc_ctrl_dev->banks) {
1025 dev_err(&dev->dev, "%s: address did not match any chip selects\n",
1026 __func__);
1027 return -ENODEV;
1028 }
1029
1030 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1031 if (!priv)
1032 return -ENOMEM;
1033
1034 mutex_lock(&fsl_ifc_nand_mutex);
1035 if (!fsl_ifc_ctrl_dev->nand) {
1036 ifc_nand_ctrl = kzalloc_obj(*ifc_nand_ctrl);
1037 if (!ifc_nand_ctrl) {
1038 mutex_unlock(&fsl_ifc_nand_mutex);
1039 return -ENOMEM;
1040 }
1041
1042 ifc_nand_ctrl->read_bytes = 0;
1043 ifc_nand_ctrl->index = 0;
1044 ifc_nand_ctrl->addr = NULL;
1045 fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl;
1046
1047 nand_controller_init(&ifc_nand_ctrl->controller);
1048 } else {
1049 ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand;
1050 }
1051 mutex_unlock(&fsl_ifc_nand_mutex);
1052
1053 ifc_nand_ctrl->chips[bank] = priv;
1054 priv->bank = bank;
1055 priv->ctrl = fsl_ifc_ctrl_dev;
1056 priv->dev = &dev->dev;
1057
1058 priv->vbase = ioremap(res.start, resource_size(&res));
1059 if (!priv->vbase) {
1060 dev_err(priv->dev, "%s: failed to map chip region\n", __func__);
1061 ret = -ENOMEM;
1062 goto err;
1063 }
1064
1065 dev_set_drvdata(priv->dev, priv);
1066
1067 ifc_out32(IFC_NAND_EVTER_EN_OPC_EN |
1068 IFC_NAND_EVTER_EN_FTOER_EN |
1069 IFC_NAND_EVTER_EN_WPER_EN,
1070 &ifc->ifc_nand.nand_evter_en);
1071
1072 /* enable NAND Machine Interrupts */
1073 ifc_out32(IFC_NAND_EVTER_INTR_OPCIR_EN |
1074 IFC_NAND_EVTER_INTR_FTOERIR_EN |
1075 IFC_NAND_EVTER_INTR_WPERIR_EN,
1076 &ifc->ifc_nand.nand_evter_intr_en);
1077
1078 mtd = nand_to_mtd(&priv->chip);
1079 mtd->name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start);
1080 if (!mtd->name) {
1081 ret = -ENOMEM;
1082 goto err;
1083 }
1084
1085 ret = fsl_ifc_chip_init(priv);
1086 if (ret)
1087 goto err;
1088
1089 priv->chip.controller->ops = &fsl_ifc_controller_ops;
1090 ret = nand_scan(&priv->chip, 1);
1091 if (ret)
1092 goto err;
1093
1094 /* First look for RedBoot table or partitions on the command
1095 * line, these take precedence over device tree information */
1096 ret = mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0);
1097 if (ret)
1098 goto cleanup_nand;
1099
1100 dev_info(priv->dev, "IFC NAND device at 0x%llx, bank %d\n",
1101 (unsigned long long)res.start, priv->bank);
1102
1103 return 0;
1104
1105 cleanup_nand:
1106 nand_cleanup(&priv->chip);
1107 err:
1108 fsl_ifc_chip_remove(priv);
1109
1110 return ret;
1111 }
1112
fsl_ifc_nand_remove(struct platform_device * dev)1113 static void fsl_ifc_nand_remove(struct platform_device *dev)
1114 {
1115 struct fsl_ifc_mtd *priv = dev_get_drvdata(&dev->dev);
1116 struct nand_chip *chip = &priv->chip;
1117 int ret;
1118
1119 ret = mtd_device_unregister(nand_to_mtd(chip));
1120 WARN_ON(ret);
1121 nand_cleanup(chip);
1122
1123 fsl_ifc_chip_remove(priv);
1124
1125 mutex_lock(&fsl_ifc_nand_mutex);
1126 ifc_nand_ctrl->counter--;
1127 if (!ifc_nand_ctrl->counter) {
1128 fsl_ifc_ctrl_dev->nand = NULL;
1129 kfree(ifc_nand_ctrl);
1130 }
1131 mutex_unlock(&fsl_ifc_nand_mutex);
1132 }
1133
1134 static const struct of_device_id fsl_ifc_nand_match[] = {
1135 {
1136 .compatible = "fsl,ifc-nand",
1137 },
1138 {}
1139 };
1140 MODULE_DEVICE_TABLE(of, fsl_ifc_nand_match);
1141
1142 static struct platform_driver fsl_ifc_nand_driver = {
1143 .driver = {
1144 .name = "fsl,ifc-nand",
1145 .of_match_table = fsl_ifc_nand_match,
1146 },
1147 .probe = fsl_ifc_nand_probe,
1148 .remove = fsl_ifc_nand_remove,
1149 };
1150
1151 module_platform_driver(fsl_ifc_nand_driver);
1152
1153 MODULE_LICENSE("GPL");
1154 MODULE_AUTHOR("Freescale");
1155 MODULE_DESCRIPTION("Freescale Integrated Flash Controller MTD NAND driver");
1156