1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // mcp251xfd - Microchip MCP251xFD Family CAN controller driver
4 //
5 // Copyright (c) 2019, 2020, 2021, 2023 Pengutronix,
6 // Marc Kleine-Budde <kernel@pengutronix.de>
7 //
8 // Based on:
9 //
10 // CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
11 //
12 // Copyright (c) 2019 Martin Sperl <kernel@martin.sperl.org>
13 //
14
15 #include <linux/unaligned.h>
16 #include <linux/bitfield.h>
17 #include <linux/clk.h>
18 #include <linux/device.h>
19 #include <linux/module.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/property.h>
22
23 #include "mcp251xfd.h"
24
25 #define DEVICE_NAME "mcp251xfd"
26
27 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2517fd = {
28 .quirks = MCP251XFD_QUIRK_MAB_NO_WARN | MCP251XFD_QUIRK_CRC_REG |
29 MCP251XFD_QUIRK_CRC_RX | MCP251XFD_QUIRK_CRC_TX |
30 MCP251XFD_QUIRK_ECC,
31 .model = MCP251XFD_MODEL_MCP2517FD,
32 };
33
34 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2518fd = {
35 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX |
36 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC,
37 .model = MCP251XFD_MODEL_MCP2518FD,
38 };
39
40 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp251863 = {
41 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX |
42 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC,
43 .model = MCP251XFD_MODEL_MCP251863,
44 };
45
46 /* Autodetect model, start with CRC enabled. */
47 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp251xfd = {
48 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX |
49 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC,
50 .model = MCP251XFD_MODEL_MCP251XFD,
51 };
52
53 static const struct can_bittiming_const mcp251xfd_bittiming_const = {
54 .name = DEVICE_NAME,
55 .tseg1_min = 2,
56 .tseg1_max = 256,
57 .tseg2_min = 1,
58 .tseg2_max = 128,
59 .sjw_max = 128,
60 .brp_min = 1,
61 .brp_max = 256,
62 .brp_inc = 1,
63 };
64
65 static const struct can_bittiming_const mcp251xfd_data_bittiming_const = {
66 .name = DEVICE_NAME,
67 .tseg1_min = 1,
68 .tseg1_max = 32,
69 .tseg2_min = 1,
70 .tseg2_max = 16,
71 .sjw_max = 16,
72 .brp_min = 1,
73 .brp_max = 256,
74 .brp_inc = 1,
75 };
76
77 /* The datasheet of the mcp2518fd (DS20006027B) specifies a range of
78 * [-64,63] for TDCO, indicating a relative TDCO.
79 *
80 * Manual tests have shown, that using a relative TDCO configuration
81 * results in bus off, while an absolute configuration works.
82 *
83 * For TDCO use the max value (63) from the data sheet, but 0 as the
84 * minimum.
85 */
86 static const struct can_tdc_const mcp251xfd_tdc_const = {
87 .tdcv_min = 0,
88 .tdcv_max = 63,
89 .tdco_min = 0,
90 .tdco_max = 63,
91 .tdcf_min = 0,
92 .tdcf_max = 0,
93 };
94
__mcp251xfd_get_model_str(enum mcp251xfd_model model)95 static const char *__mcp251xfd_get_model_str(enum mcp251xfd_model model)
96 {
97 switch (model) {
98 case MCP251XFD_MODEL_MCP2517FD:
99 return "MCP2517FD";
100 case MCP251XFD_MODEL_MCP2518FD:
101 return "MCP2518FD";
102 case MCP251XFD_MODEL_MCP251863:
103 return "MCP251863";
104 case MCP251XFD_MODEL_MCP251XFD:
105 return "MCP251xFD";
106 }
107
108 return "<unknown>";
109 }
110
111 static inline const char *
mcp251xfd_get_model_str(const struct mcp251xfd_priv * priv)112 mcp251xfd_get_model_str(const struct mcp251xfd_priv *priv)
113 {
114 return __mcp251xfd_get_model_str(priv->devtype_data.model);
115 }
116
mcp251xfd_get_mode_str(const u8 mode)117 static const char *mcp251xfd_get_mode_str(const u8 mode)
118 {
119 switch (mode) {
120 case MCP251XFD_REG_CON_MODE_MIXED:
121 return "Mixed (CAN FD/CAN 2.0)";
122 case MCP251XFD_REG_CON_MODE_SLEEP:
123 return "Sleep";
124 case MCP251XFD_REG_CON_MODE_INT_LOOPBACK:
125 return "Internal Loopback";
126 case MCP251XFD_REG_CON_MODE_LISTENONLY:
127 return "Listen Only";
128 case MCP251XFD_REG_CON_MODE_CONFIG:
129 return "Configuration";
130 case MCP251XFD_REG_CON_MODE_EXT_LOOPBACK:
131 return "External Loopback";
132 case MCP251XFD_REG_CON_MODE_CAN2_0:
133 return "CAN 2.0";
134 case MCP251XFD_REG_CON_MODE_RESTRICTED:
135 return "Restricted Operation";
136 }
137
138 return "<unknown>";
139 }
140
141 static const char *
mcp251xfd_get_osc_str(const u32 osc,const u32 osc_reference)142 mcp251xfd_get_osc_str(const u32 osc, const u32 osc_reference)
143 {
144 switch (~osc & osc_reference &
145 (MCP251XFD_REG_OSC_OSCRDY | MCP251XFD_REG_OSC_PLLRDY)) {
146 case MCP251XFD_REG_OSC_PLLRDY:
147 return "PLL";
148 case MCP251XFD_REG_OSC_OSCRDY:
149 return "Oscillator";
150 case MCP251XFD_REG_OSC_PLLRDY | MCP251XFD_REG_OSC_OSCRDY:
151 return "Oscillator/PLL";
152 }
153
154 return "<unknown>";
155 }
156
mcp251xfd_vdd_enable(const struct mcp251xfd_priv * priv)157 static inline int mcp251xfd_vdd_enable(const struct mcp251xfd_priv *priv)
158 {
159 if (!priv->reg_vdd)
160 return 0;
161
162 return regulator_enable(priv->reg_vdd);
163 }
164
mcp251xfd_vdd_disable(const struct mcp251xfd_priv * priv)165 static inline int mcp251xfd_vdd_disable(const struct mcp251xfd_priv *priv)
166 {
167 if (!priv->reg_vdd)
168 return 0;
169
170 return regulator_disable(priv->reg_vdd);
171 }
172
173 static inline int
mcp251xfd_transceiver_enable(const struct mcp251xfd_priv * priv)174 mcp251xfd_transceiver_enable(const struct mcp251xfd_priv *priv)
175 {
176 if (!priv->reg_xceiver)
177 return 0;
178
179 return regulator_enable(priv->reg_xceiver);
180 }
181
182 static inline int
mcp251xfd_transceiver_disable(const struct mcp251xfd_priv * priv)183 mcp251xfd_transceiver_disable(const struct mcp251xfd_priv *priv)
184 {
185 if (!priv->reg_xceiver)
186 return 0;
187
188 return regulator_disable(priv->reg_xceiver);
189 }
190
mcp251xfd_clks_and_vdd_enable(const struct mcp251xfd_priv * priv)191 static int mcp251xfd_clks_and_vdd_enable(const struct mcp251xfd_priv *priv)
192 {
193 int err;
194
195 err = clk_prepare_enable(priv->clk);
196 if (err)
197 return err;
198
199 err = mcp251xfd_vdd_enable(priv);
200 if (err)
201 clk_disable_unprepare(priv->clk);
202
203 /* Wait for oscillator stabilisation time after power up */
204 usleep_range(MCP251XFD_OSC_STAB_SLEEP_US,
205 2 * MCP251XFD_OSC_STAB_SLEEP_US);
206
207 return err;
208 }
209
mcp251xfd_clks_and_vdd_disable(const struct mcp251xfd_priv * priv)210 static int mcp251xfd_clks_and_vdd_disable(const struct mcp251xfd_priv *priv)
211 {
212 int err;
213
214 err = mcp251xfd_vdd_disable(priv);
215 if (err)
216 return err;
217
218 clk_disable_unprepare(priv->clk);
219
220 return 0;
221 }
222
mcp251xfd_reg_invalid(u32 reg)223 static inline bool mcp251xfd_reg_invalid(u32 reg)
224 {
225 return reg == 0x0 || reg == 0xffffffff;
226 }
227
228 static inline int
mcp251xfd_chip_get_mode(const struct mcp251xfd_priv * priv,u8 * mode)229 mcp251xfd_chip_get_mode(const struct mcp251xfd_priv *priv, u8 *mode)
230 {
231 u32 val;
232 int err;
233
234 err = regmap_read(priv->map_reg, MCP251XFD_REG_CON, &val);
235 if (err)
236 return err;
237
238 *mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, val);
239
240 return 0;
241 }
242
243 static int
__mcp251xfd_chip_set_mode(const struct mcp251xfd_priv * priv,const u8 mode_req,bool nowait)244 __mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv,
245 const u8 mode_req, bool nowait)
246 {
247 const struct can_bittiming *bt = &priv->can.bittiming;
248 unsigned long timeout_us = MCP251XFD_POLL_TIMEOUT_US;
249 u32 con = 0, con_reqop, osc = 0;
250 u8 mode;
251 int err;
252
253 con_reqop = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK, mode_req);
254 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_CON,
255 MCP251XFD_REG_CON_REQOP_MASK, con_reqop);
256 if (err == -EBADMSG) {
257 netdev_err(priv->ndev,
258 "Failed to set Requested Operation Mode.\n");
259
260 return -ENODEV;
261 } else if (err) {
262 return err;
263 }
264
265 if (mode_req == MCP251XFD_REG_CON_MODE_SLEEP || nowait)
266 return 0;
267
268 if (bt->bitrate)
269 timeout_us = max_t(unsigned long, timeout_us,
270 MCP251XFD_FRAME_LEN_MAX_BITS * USEC_PER_SEC /
271 bt->bitrate);
272
273 err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_CON, con,
274 !mcp251xfd_reg_invalid(con) &&
275 FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK,
276 con) == mode_req,
277 MCP251XFD_POLL_SLEEP_US, timeout_us);
278 if (err != -ETIMEDOUT && err != -EBADMSG)
279 return err;
280
281 /* Ignore return value.
282 * Print below error messages, even if this fails.
283 */
284 regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc);
285
286 if (mcp251xfd_reg_invalid(con)) {
287 netdev_err(priv->ndev,
288 "Failed to read CAN Control Register (con=0x%08x, osc=0x%08x).\n",
289 con, osc);
290
291 return -ENODEV;
292 }
293
294 mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, con);
295 netdev_err(priv->ndev,
296 "Controller failed to enter mode %s Mode (%u) and stays in %s Mode (%u) (con=0x%08x, osc=0x%08x).\n",
297 mcp251xfd_get_mode_str(mode_req), mode_req,
298 mcp251xfd_get_mode_str(mode), mode,
299 con, osc);
300
301 return -ETIMEDOUT;
302 }
303
304 static inline int
mcp251xfd_chip_set_mode(const struct mcp251xfd_priv * priv,const u8 mode_req)305 mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv,
306 const u8 mode_req)
307 {
308 return __mcp251xfd_chip_set_mode(priv, mode_req, false);
309 }
310
311 static inline int __maybe_unused
mcp251xfd_chip_set_mode_nowait(const struct mcp251xfd_priv * priv,const u8 mode_req)312 mcp251xfd_chip_set_mode_nowait(const struct mcp251xfd_priv *priv,
313 const u8 mode_req)
314 {
315 return __mcp251xfd_chip_set_mode(priv, mode_req, true);
316 }
317
318 static int
mcp251xfd_chip_wait_for_osc_ready(const struct mcp251xfd_priv * priv,u32 osc_reference,u32 osc_mask)319 mcp251xfd_chip_wait_for_osc_ready(const struct mcp251xfd_priv *priv,
320 u32 osc_reference, u32 osc_mask)
321 {
322 u32 osc;
323 int err;
324
325 err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_OSC, osc,
326 !mcp251xfd_reg_invalid(osc) &&
327 (osc & osc_mask) == osc_reference,
328 MCP251XFD_OSC_STAB_SLEEP_US,
329 MCP251XFD_OSC_STAB_TIMEOUT_US);
330 if (err != -ETIMEDOUT)
331 return err;
332
333 if (mcp251xfd_reg_invalid(osc)) {
334 netdev_err(priv->ndev,
335 "Failed to read Oscillator Configuration Register (osc=0x%08x).\n",
336 osc);
337 return -ENODEV;
338 }
339
340 netdev_err(priv->ndev,
341 "Timeout waiting for %s ready (osc=0x%08x, osc_reference=0x%08x, osc_mask=0x%08x).\n",
342 mcp251xfd_get_osc_str(osc, osc_reference),
343 osc, osc_reference, osc_mask);
344
345 return -ETIMEDOUT;
346 }
347
mcp251xfd_chip_wake(const struct mcp251xfd_priv * priv)348 static int mcp251xfd_chip_wake(const struct mcp251xfd_priv *priv)
349 {
350 u32 osc, osc_reference, osc_mask;
351 int err;
352
353 /* For normal sleep on MCP2517FD and MCP2518FD, clearing
354 * "Oscillator Disable" will wake the chip. For low power mode
355 * on MCP2518FD, asserting the chip select will wake the
356 * chip. Writing to the Oscillator register will wake it in
357 * both cases.
358 */
359 osc = FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
360 MCP251XFD_REG_OSC_CLKODIV_10);
361
362 /* We cannot check for the PLL ready bit (either set or
363 * unset), as the PLL might be enabled. This can happen if the
364 * system reboots, while the mcp251xfd stays powered.
365 */
366 osc_reference = MCP251XFD_REG_OSC_OSCRDY;
367 osc_mask = MCP251XFD_REG_OSC_OSCRDY;
368
369 /* If the controller is in Sleep Mode the following write only
370 * removes the "Oscillator Disable" bit and powers it up. All
371 * other bits are unaffected.
372 */
373 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc);
374 if (err)
375 return err;
376
377 /* Sometimes the PLL is stuck enabled, the controller never
378 * sets the OSC Ready bit, and we get an -ETIMEDOUT. Our
379 * caller takes care of retry.
380 */
381 return mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask);
382 }
383
mcp251xfd_chip_sleep(const struct mcp251xfd_priv * priv)384 static inline int mcp251xfd_chip_sleep(const struct mcp251xfd_priv *priv)
385 {
386 if (priv->pll_enable) {
387 u32 osc;
388 int err;
389
390 /* Turn off PLL */
391 osc = FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
392 MCP251XFD_REG_OSC_CLKODIV_10);
393 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc);
394 if (err)
395 netdev_err(priv->ndev,
396 "Failed to disable PLL.\n");
397
398 priv->spi->max_speed_hz = priv->spi_max_speed_hz_slow;
399 }
400
401 return mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_SLEEP);
402 }
403
mcp251xfd_chip_softreset_do(const struct mcp251xfd_priv * priv)404 static int mcp251xfd_chip_softreset_do(const struct mcp251xfd_priv *priv)
405 {
406 const __be16 cmd = mcp251xfd_cmd_reset();
407 int err;
408
409 /* The Set Mode and SPI Reset command only works if the
410 * controller is not in Sleep Mode.
411 */
412 err = mcp251xfd_chip_wake(priv);
413 if (err)
414 return err;
415
416 err = mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_CONFIG);
417 if (err)
418 return err;
419
420 /* spi_write_then_read() works with non DMA-safe buffers */
421 return spi_write_then_read(priv->spi, &cmd, sizeof(cmd), NULL, 0);
422 }
423
mcp251xfd_chip_softreset_check(const struct mcp251xfd_priv * priv)424 static int mcp251xfd_chip_softreset_check(const struct mcp251xfd_priv *priv)
425 {
426 u32 osc_reference, osc_mask;
427 u8 mode;
428 int err;
429
430 /* Check for reset defaults of OSC reg.
431 * This will take care of stabilization period.
432 */
433 osc_reference = MCP251XFD_REG_OSC_OSCRDY |
434 FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
435 MCP251XFD_REG_OSC_CLKODIV_10);
436 osc_mask = osc_reference | MCP251XFD_REG_OSC_PLLRDY;
437 err = mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask);
438 if (err)
439 return err;
440
441 err = mcp251xfd_chip_get_mode(priv, &mode);
442 if (err)
443 return err;
444
445 if (mode != MCP251XFD_REG_CON_MODE_CONFIG) {
446 netdev_info(priv->ndev,
447 "Controller not in Config Mode after reset, but in %s Mode (%u).\n",
448 mcp251xfd_get_mode_str(mode), mode);
449 return -ETIMEDOUT;
450 }
451
452 return 0;
453 }
454
mcp251xfd_chip_softreset(const struct mcp251xfd_priv * priv)455 static int mcp251xfd_chip_softreset(const struct mcp251xfd_priv *priv)
456 {
457 int err, i;
458
459 for (i = 0; i < MCP251XFD_SOFTRESET_RETRIES_MAX; i++) {
460 if (i)
461 netdev_info(priv->ndev,
462 "Retrying to reset controller.\n");
463
464 err = mcp251xfd_chip_softreset_do(priv);
465 if (err == -ETIMEDOUT)
466 continue;
467 if (err)
468 return err;
469
470 err = mcp251xfd_chip_softreset_check(priv);
471 if (err == -ETIMEDOUT)
472 continue;
473 if (err)
474 return err;
475
476 return 0;
477 }
478
479 return err;
480 }
481
mcp251xfd_chip_clock_init(const struct mcp251xfd_priv * priv)482 static int mcp251xfd_chip_clock_init(const struct mcp251xfd_priv *priv)
483 {
484 u32 osc, osc_reference, osc_mask;
485 int err;
486
487 /* Activate Low Power Mode on Oscillator Disable. This only
488 * works on the MCP2518FD. The MCP2517FD will go into normal
489 * Sleep Mode instead.
490 */
491 osc = MCP251XFD_REG_OSC_LPMEN |
492 FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
493 MCP251XFD_REG_OSC_CLKODIV_10);
494 osc_reference = MCP251XFD_REG_OSC_OSCRDY;
495 osc_mask = MCP251XFD_REG_OSC_OSCRDY | MCP251XFD_REG_OSC_PLLRDY;
496
497 if (priv->pll_enable) {
498 osc |= MCP251XFD_REG_OSC_PLLEN;
499 osc_reference |= MCP251XFD_REG_OSC_PLLRDY;
500 }
501
502 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc);
503 if (err)
504 return err;
505
506 err = mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask);
507 if (err)
508 return err;
509
510 priv->spi->max_speed_hz = priv->spi_max_speed_hz_fast;
511
512 return 0;
513 }
514
mcp251xfd_chip_timestamp_init(const struct mcp251xfd_priv * priv)515 static int mcp251xfd_chip_timestamp_init(const struct mcp251xfd_priv *priv)
516 {
517 /* Set Time Base Counter Prescaler to 1.
518 *
519 * This means an overflow of the 32 bit Time Base Counter
520 * register at 40 MHz every 107 seconds.
521 */
522 return regmap_write(priv->map_reg, MCP251XFD_REG_TSCON,
523 MCP251XFD_REG_TSCON_TBCEN);
524 }
525
mcp251xfd_set_bittiming(const struct mcp251xfd_priv * priv)526 static int mcp251xfd_set_bittiming(const struct mcp251xfd_priv *priv)
527 {
528 const struct can_bittiming *bt = &priv->can.bittiming;
529 const struct can_bittiming *dbt = &priv->can.fd.data_bittiming;
530 u32 tdcmod, val = 0;
531 int err;
532
533 /* CAN Control Register
534 *
535 * - no transmit bandwidth sharing
536 * - config mode
537 * - disable transmit queue
538 * - store in transmit FIFO event
539 * - transition to restricted operation mode on system error
540 * - ESI is transmitted recessive when ESI of message is high or
541 * CAN controller error passive
542 * - restricted retransmission attempts,
543 * use TQXCON_TXAT and FIFOCON_TXAT
544 * - wake-up filter bits T11FILTER
545 * - use CAN bus line filter for wakeup
546 * - protocol exception is treated as a form error
547 * - Do not compare data bytes
548 */
549 val = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK,
550 MCP251XFD_REG_CON_MODE_CONFIG) |
551 MCP251XFD_REG_CON_STEF |
552 MCP251XFD_REG_CON_ESIGM |
553 MCP251XFD_REG_CON_RTXAT |
554 FIELD_PREP(MCP251XFD_REG_CON_WFT_MASK,
555 MCP251XFD_REG_CON_WFT_T11FILTER) |
556 MCP251XFD_REG_CON_WAKFIL |
557 MCP251XFD_REG_CON_PXEDIS;
558
559 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))
560 val |= MCP251XFD_REG_CON_ISOCRCEN;
561
562 err = regmap_write(priv->map_reg, MCP251XFD_REG_CON, val);
563 if (err)
564 return err;
565
566 /* Nominal Bit Time */
567 val = FIELD_PREP(MCP251XFD_REG_NBTCFG_BRP_MASK, bt->brp - 1) |
568 FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG1_MASK,
569 bt->prop_seg + bt->phase_seg1 - 1) |
570 FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG2_MASK,
571 bt->phase_seg2 - 1) |
572 FIELD_PREP(MCP251XFD_REG_NBTCFG_SJW_MASK, bt->sjw - 1);
573
574 err = regmap_write(priv->map_reg, MCP251XFD_REG_NBTCFG, val);
575 if (err)
576 return err;
577
578 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD))
579 return 0;
580
581 /* Data Bit Time */
582 val = FIELD_PREP(MCP251XFD_REG_DBTCFG_BRP_MASK, dbt->brp - 1) |
583 FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG1_MASK,
584 dbt->prop_seg + dbt->phase_seg1 - 1) |
585 FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG2_MASK,
586 dbt->phase_seg2 - 1) |
587 FIELD_PREP(MCP251XFD_REG_DBTCFG_SJW_MASK, dbt->sjw - 1);
588
589 err = regmap_write(priv->map_reg, MCP251XFD_REG_DBTCFG, val);
590 if (err)
591 return err;
592
593 /* Transmitter Delay Compensation */
594 if (priv->can.ctrlmode & CAN_CTRLMODE_TDC_AUTO)
595 tdcmod = MCP251XFD_REG_TDC_TDCMOD_AUTO;
596 else if (priv->can.ctrlmode & CAN_CTRLMODE_TDC_MANUAL)
597 tdcmod = MCP251XFD_REG_TDC_TDCMOD_MANUAL;
598 else
599 tdcmod = MCP251XFD_REG_TDC_TDCMOD_DISABLED;
600
601 val = FIELD_PREP(MCP251XFD_REG_TDC_TDCMOD_MASK, tdcmod) |
602 FIELD_PREP(MCP251XFD_REG_TDC_TDCV_MASK, priv->can.fd.tdc.tdcv) |
603 FIELD_PREP(MCP251XFD_REG_TDC_TDCO_MASK, priv->can.fd.tdc.tdco);
604
605 return regmap_write(priv->map_reg, MCP251XFD_REG_TDC, val);
606 }
607
mcp251xfd_chip_rx_int_enable(const struct mcp251xfd_priv * priv)608 static int mcp251xfd_chip_rx_int_enable(const struct mcp251xfd_priv *priv)
609 {
610 u32 val, mask;
611
612 if (!priv->rx_int)
613 return 0;
614
615 /* Configure PIN1 as RX Interrupt:
616 *
617 * PIN1 must be Input, otherwise there is a glitch on the
618 * rx-INT line. It happens between setting the PIN as output
619 * (in the first byte of the SPI transfer) and configuring the
620 * PIN as interrupt (in the last byte of the SPI transfer).
621 */
622 val = MCP251XFD_REG_IOCON_TRIS(1);
623 mask = MCP251XFD_REG_IOCON_TRIS(1) | MCP251XFD_REG_IOCON_PM(1);
624 return regmap_update_bits(priv->map_reg, MCP251XFD_REG_IOCON, mask, val);
625 }
626
mcp251xfd_chip_rx_int_disable(const struct mcp251xfd_priv * priv)627 static int mcp251xfd_chip_rx_int_disable(const struct mcp251xfd_priv *priv)
628 {
629 u32 val;
630
631 if (!priv->rx_int)
632 return 0;
633
634 /* Configure PIN1 as GPIO Input */
635 val = MCP251XFD_REG_IOCON_PM(1) | MCP251XFD_REG_IOCON_TRIS(1);
636 return regmap_update_bits(priv->map_reg, MCP251XFD_REG_IOCON, val, val);
637 }
638
mcp251xfd_chip_ecc_init(struct mcp251xfd_priv * priv)639 static int mcp251xfd_chip_ecc_init(struct mcp251xfd_priv *priv)
640 {
641 struct mcp251xfd_ecc *ecc = &priv->ecc;
642 void *ram;
643 u32 val = 0;
644 int err;
645
646 ecc->ecc_stat = 0;
647
648 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_ECC)
649 val = MCP251XFD_REG_ECCCON_ECCEN;
650
651 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON,
652 MCP251XFD_REG_ECCCON_ECCEN, val);
653 if (err)
654 return err;
655
656 ram = kzalloc(MCP251XFD_RAM_SIZE, GFP_KERNEL);
657 if (!ram)
658 return -ENOMEM;
659
660 err = regmap_raw_write(priv->map_reg, MCP251XFD_RAM_START, ram,
661 MCP251XFD_RAM_SIZE);
662 kfree(ram);
663
664 return err;
665 }
666
mcp251xfd_get_normal_mode(const struct mcp251xfd_priv * priv)667 static u8 mcp251xfd_get_normal_mode(const struct mcp251xfd_priv *priv)
668 {
669 u8 mode;
670
671 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
672 mode = MCP251XFD_REG_CON_MODE_INT_LOOPBACK;
673 else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
674 mode = MCP251XFD_REG_CON_MODE_LISTENONLY;
675 else if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
676 mode = MCP251XFD_REG_CON_MODE_MIXED;
677 else
678 mode = MCP251XFD_REG_CON_MODE_CAN2_0;
679
680 return mode;
681 }
682
683 static int
__mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv * priv,bool nowait)684 __mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv,
685 bool nowait)
686 {
687 u8 mode;
688
689 mode = mcp251xfd_get_normal_mode(priv);
690
691 return __mcp251xfd_chip_set_mode(priv, mode, nowait);
692 }
693
694 static inline int
mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv * priv)695 mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv)
696 {
697 return __mcp251xfd_chip_set_normal_mode(priv, false);
698 }
699
700 static inline int
mcp251xfd_chip_set_normal_mode_nowait(const struct mcp251xfd_priv * priv)701 mcp251xfd_chip_set_normal_mode_nowait(const struct mcp251xfd_priv *priv)
702 {
703 return __mcp251xfd_chip_set_normal_mode(priv, true);
704 }
705
mcp251xfd_chip_interrupts_enable(const struct mcp251xfd_priv * priv)706 static int mcp251xfd_chip_interrupts_enable(const struct mcp251xfd_priv *priv)
707 {
708 u32 val;
709 int err;
710
711 val = MCP251XFD_REG_CRC_FERRIE | MCP251XFD_REG_CRC_CRCERRIE;
712 err = regmap_write(priv->map_reg, MCP251XFD_REG_CRC, val);
713 if (err)
714 return err;
715
716 val = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE;
717 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON, val, val);
718 if (err)
719 return err;
720
721 val = MCP251XFD_REG_INT_CERRIE |
722 MCP251XFD_REG_INT_SERRIE |
723 MCP251XFD_REG_INT_RXOVIE |
724 MCP251XFD_REG_INT_TXATIE |
725 MCP251XFD_REG_INT_SPICRCIE |
726 MCP251XFD_REG_INT_ECCIE |
727 MCP251XFD_REG_INT_TEFIE |
728 MCP251XFD_REG_INT_MODIE |
729 MCP251XFD_REG_INT_RXIE;
730
731 if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
732 val |= MCP251XFD_REG_INT_IVMIE;
733
734 return regmap_write(priv->map_reg, MCP251XFD_REG_INT, val);
735 }
736
mcp251xfd_chip_interrupts_disable(const struct mcp251xfd_priv * priv)737 static int mcp251xfd_chip_interrupts_disable(const struct mcp251xfd_priv *priv)
738 {
739 int err;
740 u32 mask;
741
742 err = regmap_write(priv->map_reg, MCP251XFD_REG_INT, 0);
743 if (err)
744 return err;
745
746 mask = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE;
747 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON,
748 mask, 0x0);
749 if (err)
750 return err;
751
752 return regmap_write(priv->map_reg, MCP251XFD_REG_CRC, 0);
753 }
754
mcp251xfd_chip_stop(struct mcp251xfd_priv * priv,const enum can_state state)755 static void mcp251xfd_chip_stop(struct mcp251xfd_priv *priv,
756 const enum can_state state)
757 {
758 priv->can.state = state;
759
760 mcp251xfd_chip_interrupts_disable(priv);
761 mcp251xfd_chip_rx_int_disable(priv);
762 mcp251xfd_timestamp_stop(priv);
763 mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_CONFIG);
764 }
765
mcp251xfd_chip_xstbyen_enable(const struct mcp251xfd_priv * priv)766 static int mcp251xfd_chip_xstbyen_enable(const struct mcp251xfd_priv *priv)
767 {
768 /* Configure the INT0/GPIO0/XSTBY pin as transceiver standby control:
769 *
770 * - XSTBYEN=1: route the pin to the transceiver standby function
771 * - TRIS0=0: set output direction; the reset default is 1 (input),
772 * which leaves the pin floating HIGH and keeps the
773 * transceiver in standby regardless of XSTBYEN
774 * - LAT0=0: drive pin LOW => transceiver active (not in standby)
775 *
776 * All three bits are included in the mask; only XSTBYEN is set in
777 * val, so TRIS0 and LAT0 are cleared to 0 atomically.
778 *
779 * Pin behaviour by mode:
780 * - Config mode: controlled by LAT0 (LAT0=0 => LOW => active)
781 * - Normal mode: hardware drives pin LOW (active)
782 * - Sleep mode: hardware drives pin HIGH (standby)
783 */
784 return regmap_update_bits(priv->map_reg, MCP251XFD_REG_IOCON,
785 MCP251XFD_REG_IOCON_XSTBYEN |
786 MCP251XFD_REG_IOCON_TRIS0 |
787 MCP251XFD_REG_IOCON_LAT0,
788 MCP251XFD_REG_IOCON_XSTBYEN);
789 }
790
mcp251xfd_chip_start(struct mcp251xfd_priv * priv)791 static int mcp251xfd_chip_start(struct mcp251xfd_priv *priv)
792 {
793 int err;
794
795 err = mcp251xfd_chip_timestamp_init(priv);
796 if (err)
797 goto out_chip_stop;
798
799 mcp251xfd_timestamp_start(priv);
800
801 err = mcp251xfd_set_bittiming(priv);
802 if (err)
803 goto out_chip_stop;
804
805 err = mcp251xfd_chip_rx_int_enable(priv);
806 if (err)
807 goto out_chip_stop;
808
809 err = mcp251xfd_chip_ecc_init(priv);
810 if (err)
811 goto out_chip_stop;
812
813 err = mcp251xfd_ring_init(priv);
814 if (err)
815 goto out_chip_stop;
816
817 err = mcp251xfd_chip_fifo_init(priv);
818 if (err)
819 goto out_chip_stop;
820
821 priv->can.state = CAN_STATE_ERROR_ACTIVE;
822
823 if (priv->xstbyen) {
824 err = mcp251xfd_chip_xstbyen_enable(priv);
825 if (err)
826 goto out_chip_stop;
827 }
828
829 err = mcp251xfd_chip_set_normal_mode(priv);
830 if (err)
831 goto out_chip_stop;
832
833 return 0;
834
835 out_chip_stop:
836 mcp251xfd_dump(priv);
837 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
838
839 return err;
840 }
841
mcp251xfd_set_mode(struct net_device * ndev,enum can_mode mode)842 static int mcp251xfd_set_mode(struct net_device *ndev, enum can_mode mode)
843 {
844 struct mcp251xfd_priv *priv = netdev_priv(ndev);
845 int err;
846
847 switch (mode) {
848 case CAN_MODE_START:
849 err = mcp251xfd_chip_start(priv);
850 if (err)
851 return err;
852
853 err = mcp251xfd_chip_interrupts_enable(priv);
854 if (err) {
855 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
856 return err;
857 }
858
859 netif_wake_queue(ndev);
860 break;
861
862 default:
863 return -EOPNOTSUPP;
864 }
865
866 return 0;
867 }
868
__mcp251xfd_get_berr_counter(const struct net_device * ndev,struct can_berr_counter * bec)869 static int __mcp251xfd_get_berr_counter(const struct net_device *ndev,
870 struct can_berr_counter *bec)
871 {
872 const struct mcp251xfd_priv *priv = netdev_priv(ndev);
873 u32 trec;
874 int err;
875
876 err = regmap_read(priv->map_reg, MCP251XFD_REG_TREC, &trec);
877 if (err)
878 return err;
879
880 if (trec & MCP251XFD_REG_TREC_TXBO)
881 bec->txerr = CAN_BUS_OFF_THRESHOLD;
882 else
883 bec->txerr = FIELD_GET(MCP251XFD_REG_TREC_TEC_MASK, trec);
884 bec->rxerr = FIELD_GET(MCP251XFD_REG_TREC_REC_MASK, trec);
885
886 return 0;
887 }
888
mcp251xfd_get_berr_counter(const struct net_device * ndev,struct can_berr_counter * bec)889 static int mcp251xfd_get_berr_counter(const struct net_device *ndev,
890 struct can_berr_counter *bec)
891 {
892 const struct mcp251xfd_priv *priv = netdev_priv(ndev);
893
894 /* Avoid waking up the controller if the interface is down */
895 if (!(ndev->flags & IFF_UP))
896 return 0;
897
898 /* The controller is powered down during Bus Off, use saved
899 * bec values.
900 */
901 if (priv->can.state == CAN_STATE_BUS_OFF) {
902 *bec = priv->bec;
903 return 0;
904 }
905
906 return __mcp251xfd_get_berr_counter(ndev, bec);
907 }
908
909 static struct sk_buff *
mcp251xfd_alloc_can_err_skb(struct mcp251xfd_priv * priv,struct can_frame ** cf,u32 * ts_raw)910 mcp251xfd_alloc_can_err_skb(struct mcp251xfd_priv *priv,
911 struct can_frame **cf, u32 *ts_raw)
912 {
913 struct sk_buff *skb;
914 int err;
915
916 err = mcp251xfd_get_timestamp_raw(priv, ts_raw);
917 if (err)
918 return NULL;
919
920 skb = alloc_can_err_skb(priv->ndev, cf);
921 if (skb)
922 mcp251xfd_skb_set_timestamp_raw(priv, skb, *ts_raw);
923
924 return skb;
925 }
926
mcp251xfd_handle_rxovif(struct mcp251xfd_priv * priv)927 static int mcp251xfd_handle_rxovif(struct mcp251xfd_priv *priv)
928 {
929 struct net_device_stats *stats = &priv->ndev->stats;
930 struct mcp251xfd_rx_ring *ring;
931 struct sk_buff *skb;
932 struct can_frame *cf;
933 u32 ts_raw, rxovif;
934 int err, i;
935
936 stats->rx_over_errors++;
937 stats->rx_errors++;
938
939 err = regmap_read(priv->map_reg, MCP251XFD_REG_RXOVIF, &rxovif);
940 if (err)
941 return err;
942
943 mcp251xfd_for_each_rx_ring(priv, ring, i) {
944 if (!(rxovif & BIT(ring->fifo_nr)))
945 continue;
946
947 /* If SERRIF is active, there was a RX MAB overflow. */
948 if (priv->regs_status.intf & MCP251XFD_REG_INT_SERRIF) {
949 if (net_ratelimit())
950 netdev_dbg(priv->ndev,
951 "RX-%d: MAB overflow detected.\n",
952 ring->nr);
953 } else {
954 if (net_ratelimit())
955 netdev_dbg(priv->ndev,
956 "RX-%d: FIFO overflow.\n",
957 ring->nr);
958 }
959
960 err = regmap_update_bits(priv->map_reg,
961 MCP251XFD_REG_FIFOSTA(ring->fifo_nr),
962 MCP251XFD_REG_FIFOSTA_RXOVIF,
963 0x0);
964 if (err)
965 return err;
966 }
967
968 skb = mcp251xfd_alloc_can_err_skb(priv, &cf, &ts_raw);
969 if (!skb)
970 return 0;
971
972 cf->can_id |= CAN_ERR_CRTL;
973 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
974
975 err = can_rx_offload_queue_timestamp(&priv->offload, skb, ts_raw);
976 if (err)
977 stats->rx_fifo_errors++;
978
979 return 0;
980 }
981
mcp251xfd_handle_txatif(struct mcp251xfd_priv * priv)982 static int mcp251xfd_handle_txatif(struct mcp251xfd_priv *priv)
983 {
984 netdev_info(priv->ndev, "%s\n", __func__);
985
986 return 0;
987 }
988
mcp251xfd_handle_ivmif(struct mcp251xfd_priv * priv)989 static int mcp251xfd_handle_ivmif(struct mcp251xfd_priv *priv)
990 {
991 struct net_device_stats *stats = &priv->ndev->stats;
992 u32 bdiag1, ts_raw;
993 struct sk_buff *skb;
994 struct can_frame *cf = NULL;
995 int err;
996
997 err = mcp251xfd_get_timestamp_raw(priv, &ts_raw);
998 if (err)
999 return err;
1000
1001 err = regmap_read(priv->map_reg, MCP251XFD_REG_BDIAG1, &bdiag1);
1002 if (err)
1003 return err;
1004
1005 /* Write 0s to clear error bits, don't write 1s to non active
1006 * bits, as they will be set.
1007 */
1008 err = regmap_write(priv->map_reg, MCP251XFD_REG_BDIAG1, 0x0);
1009 if (err)
1010 return err;
1011
1012 priv->can.can_stats.bus_error++;
1013
1014 skb = alloc_can_err_skb(priv->ndev, &cf);
1015 if (cf)
1016 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
1017
1018 /* Controller misconfiguration */
1019 if (WARN_ON(bdiag1 & MCP251XFD_REG_BDIAG1_DLCMM))
1020 netdev_err(priv->ndev,
1021 "recv'd DLC is larger than PLSIZE of FIFO element.");
1022
1023 /* RX errors */
1024 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DCRCERR |
1025 MCP251XFD_REG_BDIAG1_NCRCERR)) {
1026 netdev_dbg(priv->ndev, "CRC error\n");
1027
1028 stats->rx_errors++;
1029 if (cf)
1030 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
1031 }
1032 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DSTUFERR |
1033 MCP251XFD_REG_BDIAG1_NSTUFERR)) {
1034 netdev_dbg(priv->ndev, "Stuff error\n");
1035
1036 stats->rx_errors++;
1037 if (cf)
1038 cf->data[2] |= CAN_ERR_PROT_STUFF;
1039 }
1040 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DFORMERR |
1041 MCP251XFD_REG_BDIAG1_NFORMERR)) {
1042 netdev_dbg(priv->ndev, "Format error\n");
1043
1044 stats->rx_errors++;
1045 if (cf)
1046 cf->data[2] |= CAN_ERR_PROT_FORM;
1047 }
1048
1049 /* TX errors */
1050 if (bdiag1 & MCP251XFD_REG_BDIAG1_NACKERR) {
1051 netdev_dbg(priv->ndev, "NACK error\n");
1052
1053 stats->tx_errors++;
1054 if (cf) {
1055 cf->can_id |= CAN_ERR_ACK;
1056 cf->data[2] |= CAN_ERR_PROT_TX;
1057 }
1058 }
1059 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT1ERR |
1060 MCP251XFD_REG_BDIAG1_NBIT1ERR)) {
1061 netdev_dbg(priv->ndev, "Bit1 error\n");
1062
1063 stats->tx_errors++;
1064 if (cf)
1065 cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT1;
1066 }
1067 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT0ERR |
1068 MCP251XFD_REG_BDIAG1_NBIT0ERR)) {
1069 netdev_dbg(priv->ndev, "Bit0 error\n");
1070
1071 stats->tx_errors++;
1072 if (cf)
1073 cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT0;
1074 }
1075
1076 if (!cf)
1077 return 0;
1078
1079 mcp251xfd_skb_set_timestamp_raw(priv, skb, ts_raw);
1080 err = can_rx_offload_queue_timestamp(&priv->offload, skb, ts_raw);
1081 if (err)
1082 stats->rx_fifo_errors++;
1083
1084 return 0;
1085 }
1086
mcp251xfd_handle_cerrif(struct mcp251xfd_priv * priv)1087 static int mcp251xfd_handle_cerrif(struct mcp251xfd_priv *priv)
1088 {
1089 struct net_device_stats *stats = &priv->ndev->stats;
1090 struct sk_buff *skb;
1091 struct can_frame *cf = NULL;
1092 enum can_state new_state, rx_state, tx_state;
1093 u32 trec, ts_raw;
1094 int err;
1095
1096 err = regmap_read(priv->map_reg, MCP251XFD_REG_TREC, &trec);
1097 if (err)
1098 return err;
1099
1100 if (trec & MCP251XFD_REG_TREC_TXBO)
1101 tx_state = CAN_STATE_BUS_OFF;
1102 else if (trec & MCP251XFD_REG_TREC_TXBP)
1103 tx_state = CAN_STATE_ERROR_PASSIVE;
1104 else if (trec & MCP251XFD_REG_TREC_TXWARN)
1105 tx_state = CAN_STATE_ERROR_WARNING;
1106 else
1107 tx_state = CAN_STATE_ERROR_ACTIVE;
1108
1109 if (trec & MCP251XFD_REG_TREC_RXBP)
1110 rx_state = CAN_STATE_ERROR_PASSIVE;
1111 else if (trec & MCP251XFD_REG_TREC_RXWARN)
1112 rx_state = CAN_STATE_ERROR_WARNING;
1113 else
1114 rx_state = CAN_STATE_ERROR_ACTIVE;
1115
1116 new_state = max(tx_state, rx_state);
1117 if (new_state == priv->can.state)
1118 return 0;
1119
1120 /* The skb allocation might fail, but can_change_state()
1121 * handles cf == NULL.
1122 */
1123 skb = mcp251xfd_alloc_can_err_skb(priv, &cf, &ts_raw);
1124 can_change_state(priv->ndev, cf, tx_state, rx_state);
1125
1126 if (new_state == CAN_STATE_BUS_OFF) {
1127 /* As we're going to switch off the chip now, let's
1128 * save the error counters and return them to
1129 * userspace, if do_get_berr_counter() is called while
1130 * the chip is in Bus Off.
1131 */
1132 err = __mcp251xfd_get_berr_counter(priv->ndev, &priv->bec);
1133 if (err)
1134 return err;
1135
1136 mcp251xfd_chip_stop(priv, CAN_STATE_BUS_OFF);
1137 can_bus_off(priv->ndev);
1138 }
1139
1140 if (!skb)
1141 return 0;
1142
1143 if (new_state != CAN_STATE_BUS_OFF) {
1144 struct can_berr_counter bec;
1145
1146 err = mcp251xfd_get_berr_counter(priv->ndev, &bec);
1147 if (err)
1148 return err;
1149 cf->can_id |= CAN_ERR_CNT;
1150 cf->data[6] = bec.txerr;
1151 cf->data[7] = bec.rxerr;
1152 }
1153
1154 err = can_rx_offload_queue_timestamp(&priv->offload, skb, ts_raw);
1155 if (err)
1156 stats->rx_fifo_errors++;
1157
1158 return 0;
1159 }
1160
1161 static int
mcp251xfd_handle_modif(const struct mcp251xfd_priv * priv,bool * set_normal_mode)1162 mcp251xfd_handle_modif(const struct mcp251xfd_priv *priv, bool *set_normal_mode)
1163 {
1164 const u8 mode_reference = mcp251xfd_get_normal_mode(priv);
1165 u8 mode;
1166 int err;
1167
1168 err = mcp251xfd_chip_get_mode(priv, &mode);
1169 if (err)
1170 return err;
1171
1172 if (mode == mode_reference) {
1173 netdev_dbg(priv->ndev,
1174 "Controller changed into %s Mode (%u).\n",
1175 mcp251xfd_get_mode_str(mode), mode);
1176 return 0;
1177 }
1178
1179 /* According to MCP2517FD errata DS80000792C 1., during a TX
1180 * MAB underflow, the controller will transition to Restricted
1181 * Operation Mode or Listen Only Mode (depending on SERR2LOM).
1182 *
1183 * However this is not always the case. If SERR2LOM is
1184 * configured for Restricted Operation Mode (SERR2LOM not set)
1185 * the MCP2517FD will sometimes transition to Listen Only Mode
1186 * first. When polling this bit we see that it will transition
1187 * to Restricted Operation Mode shortly after.
1188 */
1189 if ((priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN) &&
1190 (mode == MCP251XFD_REG_CON_MODE_RESTRICTED ||
1191 mode == MCP251XFD_REG_CON_MODE_LISTENONLY))
1192 netdev_dbg(priv->ndev,
1193 "Controller changed into %s Mode (%u).\n",
1194 mcp251xfd_get_mode_str(mode), mode);
1195 else
1196 netdev_err(priv->ndev,
1197 "Controller changed into %s Mode (%u).\n",
1198 mcp251xfd_get_mode_str(mode), mode);
1199
1200 /* After the application requests Normal mode, the controller
1201 * will automatically attempt to retransmit the message that
1202 * caused the TX MAB underflow.
1203 *
1204 * However, if there is an ECC error in the TX-RAM, we first
1205 * have to reload the tx-object before requesting Normal
1206 * mode. This is done later in mcp251xfd_handle_eccif().
1207 */
1208 if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF) {
1209 *set_normal_mode = true;
1210 return 0;
1211 }
1212
1213 return mcp251xfd_chip_set_normal_mode_nowait(priv);
1214 }
1215
mcp251xfd_handle_serrif(struct mcp251xfd_priv * priv)1216 static int mcp251xfd_handle_serrif(struct mcp251xfd_priv *priv)
1217 {
1218 struct mcp251xfd_ecc *ecc = &priv->ecc;
1219 struct net_device_stats *stats = &priv->ndev->stats;
1220 bool handled = false;
1221
1222 /* TX MAB underflow
1223 *
1224 * According to MCP2517FD Errata DS80000792C 1. a TX MAB
1225 * underflow is indicated by SERRIF and MODIF.
1226 *
1227 * In addition to the effects mentioned in the Errata, there
1228 * are Bus Errors due to the aborted CAN frame, so a IVMIF
1229 * will be seen as well.
1230 *
1231 * Sometimes there is an ECC error in the TX-RAM, which leads
1232 * to a TX MAB underflow.
1233 *
1234 * However, probably due to a race condition, there is no
1235 * associated MODIF pending.
1236 *
1237 * Further, there are situations, where the SERRIF is caused
1238 * by an ECC error in the TX-RAM, but not even the ECCIF is
1239 * set. This only seems to happen _after_ the first occurrence
1240 * of a ECCIF (which is tracked in ecc->cnt).
1241 *
1242 * Treat all as a known system errors..
1243 */
1244 if ((priv->regs_status.intf & MCP251XFD_REG_INT_MODIF &&
1245 priv->regs_status.intf & MCP251XFD_REG_INT_IVMIF) ||
1246 priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF ||
1247 ecc->cnt) {
1248 const char *msg;
1249
1250 if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF ||
1251 ecc->cnt)
1252 msg = "TX MAB underflow due to ECC error detected.";
1253 else
1254 msg = "TX MAB underflow detected.";
1255
1256 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN)
1257 netdev_dbg(priv->ndev, "%s\n", msg);
1258 else
1259 netdev_info(priv->ndev, "%s\n", msg);
1260
1261 stats->tx_aborted_errors++;
1262 stats->tx_errors++;
1263 handled = true;
1264 }
1265
1266 /* RX MAB overflow
1267 *
1268 * According to MCP2517FD Errata DS80000792C 1. a RX MAB
1269 * overflow is indicated by SERRIF.
1270 *
1271 * In addition to the effects mentioned in the Errata, (most
1272 * of the times) a RXOVIF is raised, if the FIFO that is being
1273 * received into has the RXOVIE activated (and we have enabled
1274 * RXOVIE on all FIFOs).
1275 *
1276 * Sometimes there is no RXOVIF just a RXIF is pending.
1277 *
1278 * Treat all as a known system errors..
1279 */
1280 if (priv->regs_status.intf & MCP251XFD_REG_INT_RXOVIF ||
1281 priv->regs_status.intf & MCP251XFD_REG_INT_RXIF) {
1282 stats->rx_dropped++;
1283 handled = true;
1284 }
1285
1286 if (!handled)
1287 netdev_err(priv->ndev,
1288 "Unhandled System Error Interrupt (intf=0x%08x)!\n",
1289 priv->regs_status.intf);
1290
1291 return 0;
1292 }
1293
1294 static int
mcp251xfd_handle_eccif_recover(struct mcp251xfd_priv * priv,u8 nr)1295 mcp251xfd_handle_eccif_recover(struct mcp251xfd_priv *priv, u8 nr)
1296 {
1297 struct mcp251xfd_tx_ring *tx_ring = priv->tx;
1298 struct mcp251xfd_ecc *ecc = &priv->ecc;
1299 struct mcp251xfd_tx_obj *tx_obj;
1300 u8 chip_tx_tail, tx_tail, offset;
1301 u16 addr;
1302 int err;
1303
1304 addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc->ecc_stat);
1305
1306 err = mcp251xfd_tx_tail_get_from_chip(priv, &chip_tx_tail);
1307 if (err)
1308 return err;
1309
1310 tx_tail = mcp251xfd_get_tx_tail(tx_ring);
1311 offset = (nr - chip_tx_tail) & (tx_ring->obj_num - 1);
1312
1313 /* Bail out if one of the following is met:
1314 * - tx_tail information is inconsistent
1315 * - for mcp2517fd: offset not 0
1316 * - for mcp2518fd: offset not 0 or 1
1317 */
1318 if (chip_tx_tail != tx_tail ||
1319 !(offset == 0 || (offset == 1 && (mcp251xfd_is_2518FD(priv) ||
1320 mcp251xfd_is_251863(priv))))) {
1321 netdev_err(priv->ndev,
1322 "ECC Error information inconsistent (addr=0x%04x, nr=%d, tx_tail=0x%08x(%d), chip_tx_tail=%d, offset=%d).\n",
1323 addr, nr, tx_ring->tail, tx_tail, chip_tx_tail,
1324 offset);
1325 return -EINVAL;
1326 }
1327
1328 netdev_info(priv->ndev,
1329 "Recovering %s ECC Error at address 0x%04x (in TX-RAM, tx_obj=%d, tx_tail=0x%08x(%d), offset=%d).\n",
1330 ecc->ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF ?
1331 "Single" : "Double",
1332 addr, nr, tx_ring->tail, tx_tail, offset);
1333
1334 /* reload tx_obj into controller RAM ... */
1335 tx_obj = &tx_ring->obj[nr];
1336 err = spi_sync_transfer(priv->spi, tx_obj->xfer, 1);
1337 if (err)
1338 return err;
1339
1340 /* ... and trigger retransmit */
1341 return mcp251xfd_chip_set_normal_mode(priv);
1342 }
1343
1344 static int
mcp251xfd_handle_eccif(struct mcp251xfd_priv * priv,bool set_normal_mode)1345 mcp251xfd_handle_eccif(struct mcp251xfd_priv *priv, bool set_normal_mode)
1346 {
1347 struct mcp251xfd_ecc *ecc = &priv->ecc;
1348 const char *msg;
1349 bool in_tx_ram;
1350 u32 ecc_stat;
1351 u16 addr;
1352 u8 nr;
1353 int err;
1354
1355 err = regmap_read(priv->map_reg, MCP251XFD_REG_ECCSTAT, &ecc_stat);
1356 if (err)
1357 return err;
1358
1359 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCSTAT,
1360 MCP251XFD_REG_ECCSTAT_IF_MASK, ~ecc_stat);
1361 if (err)
1362 return err;
1363
1364 /* Check if ECC error occurred in TX-RAM */
1365 addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc_stat);
1366 err = mcp251xfd_get_tx_nr_by_addr(priv->tx, &nr, addr);
1367 if (!err)
1368 in_tx_ram = true;
1369 else if (err == -ENOENT)
1370 in_tx_ram = false;
1371 else
1372 return err;
1373
1374 /* Errata Reference:
1375 * mcp2517fd: DS80000789C 3., mcp2518fd: DS80000792E 2.,
1376 * mcp251863: DS80000984A 2.
1377 *
1378 * ECC single error correction does not work in all cases:
1379 *
1380 * Fix/Work Around:
1381 * Enable single error correction and double error detection
1382 * interrupts by setting SECIE and DEDIE. Handle SECIF as a
1383 * detection interrupt and do not rely on the error
1384 * correction. Instead, handle both interrupts as a
1385 * notification that the RAM word at ERRADDR was corrupted.
1386 */
1387 if (ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF)
1388 msg = "Single ECC Error detected at address";
1389 else if (ecc_stat & MCP251XFD_REG_ECCSTAT_DEDIF)
1390 msg = "Double ECC Error detected at address";
1391 else
1392 return -EINVAL;
1393
1394 if (!in_tx_ram) {
1395 ecc->ecc_stat = 0;
1396
1397 netdev_notice(priv->ndev, "%s 0x%04x.\n", msg, addr);
1398 } else {
1399 /* Re-occurring error? */
1400 if (ecc->ecc_stat == ecc_stat) {
1401 ecc->cnt++;
1402 } else {
1403 ecc->ecc_stat = ecc_stat;
1404 ecc->cnt = 1;
1405 }
1406
1407 netdev_info(priv->ndev,
1408 "%s 0x%04x (in TX-RAM, tx_obj=%d), occurred %d time%s.\n",
1409 msg, addr, nr, ecc->cnt, ecc->cnt > 1 ? "s" : "");
1410
1411 if (ecc->cnt >= MCP251XFD_ECC_CNT_MAX)
1412 return mcp251xfd_handle_eccif_recover(priv, nr);
1413 }
1414
1415 if (set_normal_mode)
1416 return mcp251xfd_chip_set_normal_mode_nowait(priv);
1417
1418 return 0;
1419 }
1420
mcp251xfd_handle_spicrcif(struct mcp251xfd_priv * priv)1421 static int mcp251xfd_handle_spicrcif(struct mcp251xfd_priv *priv)
1422 {
1423 int err;
1424 u32 crc;
1425
1426 err = regmap_read(priv->map_reg, MCP251XFD_REG_CRC, &crc);
1427 if (err)
1428 return err;
1429
1430 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_CRC,
1431 MCP251XFD_REG_CRC_IF_MASK,
1432 ~crc);
1433 if (err)
1434 return err;
1435
1436 if (crc & MCP251XFD_REG_CRC_FERRIF)
1437 netdev_notice(priv->ndev, "CRC write command format error.\n");
1438 else if (crc & MCP251XFD_REG_CRC_CRCERRIF)
1439 netdev_notice(priv->ndev,
1440 "CRC write error detected. CRC=0x%04lx.\n",
1441 FIELD_GET(MCP251XFD_REG_CRC_MASK, crc));
1442
1443 return 0;
1444 }
1445
mcp251xfd_read_regs_status(struct mcp251xfd_priv * priv)1446 static int mcp251xfd_read_regs_status(struct mcp251xfd_priv *priv)
1447 {
1448 const int val_bytes = regmap_get_val_bytes(priv->map_reg);
1449 size_t len;
1450
1451 if (priv->rx_ring_num == 1)
1452 len = sizeof(priv->regs_status.intf);
1453 else
1454 len = sizeof(priv->regs_status);
1455
1456 return regmap_bulk_read(priv->map_reg, MCP251XFD_REG_INT,
1457 &priv->regs_status, len / val_bytes);
1458 }
1459
1460 #define mcp251xfd_handle(priv, irq, ...) \
1461 ({ \
1462 struct mcp251xfd_priv *_priv = (priv); \
1463 int err; \
1464 \
1465 err = mcp251xfd_handle_##irq(_priv, ## __VA_ARGS__); \
1466 if (err) \
1467 netdev_err(_priv->ndev, \
1468 "IRQ handler mcp251xfd_handle_%s() returned %d.\n", \
1469 __stringify(irq), err); \
1470 err; \
1471 })
1472
mcp251xfd_irq(int irq,void * dev_id)1473 static irqreturn_t mcp251xfd_irq(int irq, void *dev_id)
1474 {
1475 struct mcp251xfd_priv *priv = dev_id;
1476 irqreturn_t handled = IRQ_NONE;
1477 int err;
1478
1479 if (priv->rx_int)
1480 do {
1481 int rx_pending;
1482
1483 rx_pending = gpiod_get_value_cansleep(priv->rx_int);
1484 if (!rx_pending)
1485 break;
1486
1487 /* Assume 1st RX-FIFO pending, if other FIFOs
1488 * are pending the main IRQ handler will take
1489 * care.
1490 */
1491 priv->regs_status.rxif = BIT(priv->rx[0]->fifo_nr);
1492 err = mcp251xfd_handle(priv, rxif);
1493 if (err)
1494 goto out_fail;
1495
1496 handled = IRQ_HANDLED;
1497
1498 /* We don't know which RX-FIFO is pending, but only
1499 * handle the 1st RX-FIFO. Leave loop here if we have
1500 * more than 1 RX-FIFO to avoid starvation.
1501 */
1502 } while (priv->rx_ring_num == 1);
1503
1504 do {
1505 u32 intf_pending, intf_pending_clearable;
1506 bool set_normal_mode = false;
1507
1508 err = mcp251xfd_read_regs_status(priv);
1509 if (err)
1510 goto out_fail;
1511
1512 intf_pending = FIELD_GET(MCP251XFD_REG_INT_IF_MASK,
1513 priv->regs_status.intf) &
1514 FIELD_GET(MCP251XFD_REG_INT_IE_MASK,
1515 priv->regs_status.intf);
1516
1517 if (!(intf_pending)) {
1518 can_rx_offload_threaded_irq_finish(&priv->offload);
1519 return handled;
1520 }
1521
1522 /* Some interrupts must be ACKed in the
1523 * MCP251XFD_REG_INT register.
1524 * - First ACK then handle, to avoid lost-IRQ race
1525 * condition on fast re-occurring interrupts.
1526 * - Write "0" to clear active IRQs, "1" to all other,
1527 * to avoid r/m/w race condition on the
1528 * MCP251XFD_REG_INT register.
1529 */
1530 intf_pending_clearable = intf_pending &
1531 MCP251XFD_REG_INT_IF_CLEARABLE_MASK;
1532 if (intf_pending_clearable) {
1533 err = regmap_update_bits(priv->map_reg,
1534 MCP251XFD_REG_INT,
1535 MCP251XFD_REG_INT_IF_MASK,
1536 ~intf_pending_clearable);
1537 if (err)
1538 goto out_fail;
1539 }
1540
1541 if (intf_pending & MCP251XFD_REG_INT_MODIF) {
1542 err = mcp251xfd_handle(priv, modif, &set_normal_mode);
1543 if (err)
1544 goto out_fail;
1545 }
1546
1547 if (intf_pending & MCP251XFD_REG_INT_RXIF) {
1548 err = mcp251xfd_handle(priv, rxif);
1549 if (err)
1550 goto out_fail;
1551 }
1552
1553 if (intf_pending & MCP251XFD_REG_INT_TEFIF) {
1554 err = mcp251xfd_handle(priv, tefif);
1555 if (err)
1556 goto out_fail;
1557 }
1558
1559 if (intf_pending & MCP251XFD_REG_INT_RXOVIF) {
1560 err = mcp251xfd_handle(priv, rxovif);
1561 if (err)
1562 goto out_fail;
1563 }
1564
1565 if (intf_pending & MCP251XFD_REG_INT_TXATIF) {
1566 err = mcp251xfd_handle(priv, txatif);
1567 if (err)
1568 goto out_fail;
1569 }
1570
1571 if (intf_pending & MCP251XFD_REG_INT_IVMIF) {
1572 err = mcp251xfd_handle(priv, ivmif);
1573 if (err)
1574 goto out_fail;
1575 }
1576
1577 if (intf_pending & MCP251XFD_REG_INT_SERRIF) {
1578 err = mcp251xfd_handle(priv, serrif);
1579 if (err)
1580 goto out_fail;
1581 }
1582
1583 if (intf_pending & MCP251XFD_REG_INT_ECCIF) {
1584 err = mcp251xfd_handle(priv, eccif, set_normal_mode);
1585 if (err)
1586 goto out_fail;
1587 }
1588
1589 if (intf_pending & MCP251XFD_REG_INT_SPICRCIF) {
1590 err = mcp251xfd_handle(priv, spicrcif);
1591 if (err)
1592 goto out_fail;
1593 }
1594
1595 /* On the MCP2527FD and MCP2518FD, we don't get a
1596 * CERRIF IRQ on the transition TX ERROR_WARNING -> TX
1597 * ERROR_ACTIVE.
1598 */
1599 if (intf_pending & MCP251XFD_REG_INT_CERRIF ||
1600 priv->can.state > CAN_STATE_ERROR_ACTIVE) {
1601 err = mcp251xfd_handle(priv, cerrif);
1602 if (err)
1603 goto out_fail;
1604
1605 /* In Bus Off we completely shut down the
1606 * controller. Every subsequent register read
1607 * will read bogus data, and if
1608 * MCP251XFD_QUIRK_CRC_REG is enabled the CRC
1609 * check will fail, too. So leave IRQ handler
1610 * directly.
1611 */
1612 if (priv->can.state == CAN_STATE_BUS_OFF) {
1613 can_rx_offload_threaded_irq_finish(&priv->offload);
1614 return IRQ_HANDLED;
1615 }
1616 }
1617
1618 handled = IRQ_HANDLED;
1619 } while (1);
1620
1621 out_fail:
1622 can_rx_offload_threaded_irq_finish(&priv->offload);
1623
1624 netdev_err(priv->ndev, "IRQ handler returned %d (intf=0x%08x).\n",
1625 err, priv->regs_status.intf);
1626 mcp251xfd_dump(priv);
1627 mcp251xfd_chip_interrupts_disable(priv);
1628 mcp251xfd_timestamp_stop(priv);
1629
1630 return handled;
1631 }
1632
mcp251xfd_open(struct net_device * ndev)1633 static int mcp251xfd_open(struct net_device *ndev)
1634 {
1635 struct mcp251xfd_priv *priv = netdev_priv(ndev);
1636 const struct spi_device *spi = priv->spi;
1637 int err;
1638
1639 err = open_candev(ndev);
1640 if (err)
1641 return err;
1642
1643 err = pm_runtime_resume_and_get(ndev->dev.parent);
1644 if (err) {
1645 if (err == -ETIMEDOUT || err == -ENODEV)
1646 pm_runtime_set_suspended(ndev->dev.parent);
1647 goto out_close_candev;
1648 }
1649
1650 err = mcp251xfd_ring_alloc(priv);
1651 if (err)
1652 goto out_pm_runtime_put;
1653
1654 err = mcp251xfd_transceiver_enable(priv);
1655 if (err)
1656 goto out_mcp251xfd_ring_free;
1657
1658 mcp251xfd_timestamp_init(priv);
1659
1660 err = mcp251xfd_chip_start(priv);
1661 if (err)
1662 goto out_transceiver_disable;
1663
1664 clear_bit(MCP251XFD_FLAGS_DOWN, priv->flags);
1665 can_rx_offload_enable(&priv->offload);
1666
1667 priv->wq = alloc_ordered_workqueue("%s-mcp251xfd_wq",
1668 WQ_FREEZABLE | WQ_MEM_RECLAIM,
1669 dev_name(&spi->dev));
1670 if (!priv->wq) {
1671 err = -ENOMEM;
1672 goto out_can_rx_offload_disable;
1673 }
1674 INIT_WORK(&priv->tx_work, mcp251xfd_tx_obj_write_sync);
1675
1676 err = request_threaded_irq(spi->irq, NULL, mcp251xfd_irq,
1677 IRQF_SHARED | IRQF_ONESHOT,
1678 dev_name(&spi->dev), priv);
1679 if (err)
1680 goto out_destroy_workqueue;
1681
1682 err = mcp251xfd_chip_interrupts_enable(priv);
1683 if (err)
1684 goto out_free_irq;
1685
1686 netif_start_queue(ndev);
1687
1688 return 0;
1689
1690 out_free_irq:
1691 free_irq(spi->irq, priv);
1692 out_destroy_workqueue:
1693 destroy_workqueue(priv->wq);
1694 out_can_rx_offload_disable:
1695 can_rx_offload_disable(&priv->offload);
1696 set_bit(MCP251XFD_FLAGS_DOWN, priv->flags);
1697 out_transceiver_disable:
1698 mcp251xfd_transceiver_disable(priv);
1699 out_mcp251xfd_ring_free:
1700 mcp251xfd_ring_free(priv);
1701 out_pm_runtime_put:
1702 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
1703 pm_runtime_put(ndev->dev.parent);
1704 out_close_candev:
1705 close_candev(ndev);
1706
1707 return err;
1708 }
1709
mcp251xfd_stop(struct net_device * ndev)1710 static int mcp251xfd_stop(struct net_device *ndev)
1711 {
1712 struct mcp251xfd_priv *priv = netdev_priv(ndev);
1713
1714 netif_stop_queue(ndev);
1715 set_bit(MCP251XFD_FLAGS_DOWN, priv->flags);
1716 hrtimer_cancel(&priv->rx_irq_timer);
1717 hrtimer_cancel(&priv->tx_irq_timer);
1718 mcp251xfd_chip_interrupts_disable(priv);
1719 free_irq(ndev->irq, priv);
1720 destroy_workqueue(priv->wq);
1721 can_rx_offload_disable(&priv->offload);
1722 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
1723 mcp251xfd_transceiver_disable(priv);
1724 mcp251xfd_ring_free(priv);
1725 close_candev(ndev);
1726
1727 pm_runtime_put(ndev->dev.parent);
1728
1729 return 0;
1730 }
1731
1732 static const struct net_device_ops mcp251xfd_netdev_ops = {
1733 .ndo_open = mcp251xfd_open,
1734 .ndo_stop = mcp251xfd_stop,
1735 .ndo_start_xmit = mcp251xfd_start_xmit,
1736 .ndo_hwtstamp_get = can_hwtstamp_get,
1737 .ndo_hwtstamp_set = can_hwtstamp_set,
1738 };
1739
1740 static void
mcp251xfd_register_quirks(struct mcp251xfd_priv * priv)1741 mcp251xfd_register_quirks(struct mcp251xfd_priv *priv)
1742 {
1743 const struct spi_device *spi = priv->spi;
1744 const struct spi_controller *ctlr = spi->controller;
1745
1746 if (ctlr->flags & SPI_CONTROLLER_HALF_DUPLEX)
1747 priv->devtype_data.quirks |= MCP251XFD_QUIRK_HALF_DUPLEX;
1748 }
1749
mcp251xfd_register_chip_detect(struct mcp251xfd_priv * priv)1750 static int mcp251xfd_register_chip_detect(struct mcp251xfd_priv *priv)
1751 {
1752 const struct net_device *ndev = priv->ndev;
1753 const struct mcp251xfd_devtype_data *devtype_data;
1754 u32 osc;
1755 int err;
1756
1757 /* The OSC_LPMEN is only supported on MCP2518FD and MCP251863,
1758 * so use it to autodetect the model.
1759 */
1760 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_OSC,
1761 MCP251XFD_REG_OSC_LPMEN,
1762 MCP251XFD_REG_OSC_LPMEN);
1763 if (err)
1764 return err;
1765
1766 err = regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc);
1767 if (err)
1768 return err;
1769
1770 if (osc & MCP251XFD_REG_OSC_LPMEN) {
1771 /* We cannot distinguish between MCP2518FD and
1772 * MCP251863. If firmware specifies MCP251863, keep
1773 * it, otherwise set to MCP2518FD.
1774 */
1775 if (mcp251xfd_is_251863(priv))
1776 devtype_data = &mcp251xfd_devtype_data_mcp251863;
1777 else
1778 devtype_data = &mcp251xfd_devtype_data_mcp2518fd;
1779 } else {
1780 devtype_data = &mcp251xfd_devtype_data_mcp2517fd;
1781 }
1782
1783 if (!mcp251xfd_is_251XFD(priv) &&
1784 priv->devtype_data.model != devtype_data->model) {
1785 netdev_info(ndev,
1786 "Detected %s, but firmware specifies a %s. Fixing up.\n",
1787 __mcp251xfd_get_model_str(devtype_data->model),
1788 mcp251xfd_get_model_str(priv));
1789 }
1790 priv->devtype_data = *devtype_data;
1791
1792 /* We need to preserve the Half Duplex Quirk. */
1793 mcp251xfd_register_quirks(priv);
1794
1795 /* Re-init regmap with quirks of detected model. */
1796 return mcp251xfd_regmap_init(priv);
1797 }
1798
mcp251xfd_register_check_rx_int(struct mcp251xfd_priv * priv)1799 static int mcp251xfd_register_check_rx_int(struct mcp251xfd_priv *priv)
1800 {
1801 int err, rx_pending;
1802
1803 if (!priv->rx_int)
1804 return 0;
1805
1806 err = mcp251xfd_chip_rx_int_enable(priv);
1807 if (err)
1808 return err;
1809
1810 /* Check if RX_INT is properly working. The RX_INT should not
1811 * be active after a softreset.
1812 */
1813 rx_pending = gpiod_get_value_cansleep(priv->rx_int);
1814
1815 err = mcp251xfd_chip_rx_int_disable(priv);
1816 if (err)
1817 return err;
1818
1819 if (!rx_pending)
1820 return 0;
1821
1822 netdev_info(priv->ndev,
1823 "RX_INT active after softreset, disabling RX_INT support.\n");
1824 devm_gpiod_put(&priv->spi->dev, priv->rx_int);
1825 priv->rx_int = NULL;
1826
1827 return 0;
1828 }
1829
1830 static const char * const mcp251xfd_gpio_names[] = { "GPIO0", "GPIO1" };
1831
mcp251xfd_gpio_request(struct gpio_chip * chip,unsigned int offset)1832 static int mcp251xfd_gpio_request(struct gpio_chip *chip, unsigned int offset)
1833 {
1834 struct mcp251xfd_priv *priv = gpiochip_get_data(chip);
1835 u32 pin_mask = MCP251XFD_REG_IOCON_PM(offset);
1836 int ret;
1837
1838 if (priv->xstbyen && offset == 0) {
1839 netdev_err(priv->ndev, "Can't use GPIO 0 with XSTBYEN!\n");
1840 return -EINVAL;
1841 }
1842
1843 if (priv->rx_int && offset == 1) {
1844 netdev_err(priv->ndev, "Can't use GPIO 1 with RX-INT!\n");
1845 return -EINVAL;
1846 }
1847
1848 ret = pm_runtime_resume_and_get(priv->ndev->dev.parent);
1849 if (ret)
1850 return ret;
1851
1852 return regmap_update_bits(priv->map_reg, MCP251XFD_REG_IOCON, pin_mask, pin_mask);
1853 }
1854
mcp251xfd_gpio_free(struct gpio_chip * chip,unsigned int offset)1855 static void mcp251xfd_gpio_free(struct gpio_chip *chip, unsigned int offset)
1856 {
1857 struct mcp251xfd_priv *priv = gpiochip_get_data(chip);
1858
1859 pm_runtime_put(priv->ndev->dev.parent);
1860 }
1861
mcp251xfd_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)1862 static int mcp251xfd_gpio_get_direction(struct gpio_chip *chip,
1863 unsigned int offset)
1864 {
1865 struct mcp251xfd_priv *priv = gpiochip_get_data(chip);
1866 u32 mask = MCP251XFD_REG_IOCON_TRIS(offset);
1867 u32 val;
1868 int ret;
1869
1870 ret = regmap_read(priv->map_reg, MCP251XFD_REG_IOCON, &val);
1871 if (ret)
1872 return ret;
1873
1874 if (mask & val)
1875 return GPIO_LINE_DIRECTION_IN;
1876
1877 return GPIO_LINE_DIRECTION_OUT;
1878 }
1879
mcp251xfd_gpio_get(struct gpio_chip * chip,unsigned int offset)1880 static int mcp251xfd_gpio_get(struct gpio_chip *chip, unsigned int offset)
1881 {
1882 struct mcp251xfd_priv *priv = gpiochip_get_data(chip);
1883 u32 mask = MCP251XFD_REG_IOCON_GPIO(offset);
1884 u32 val;
1885 int ret;
1886
1887 ret = regmap_read(priv->map_reg, MCP251XFD_REG_IOCON, &val);
1888 if (ret)
1889 return ret;
1890
1891 return !!(mask & val);
1892 }
1893
mcp251xfd_gpio_get_multiple(struct gpio_chip * chip,unsigned long * mask,unsigned long * bit)1894 static int mcp251xfd_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
1895 unsigned long *bit)
1896 {
1897 struct mcp251xfd_priv *priv = gpiochip_get_data(chip);
1898 u32 val;
1899 int ret;
1900
1901 ret = regmap_read(priv->map_reg, MCP251XFD_REG_IOCON, &val);
1902 if (ret)
1903 return ret;
1904
1905 *bit = FIELD_GET(MCP251XFD_REG_IOCON_GPIO_MASK, val) & *mask;
1906
1907 return 0;
1908 }
1909
mcp251xfd_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)1910 static int mcp251xfd_gpio_direction_output(struct gpio_chip *chip,
1911 unsigned int offset, int value)
1912 {
1913 struct mcp251xfd_priv *priv = gpiochip_get_data(chip);
1914 u32 dir_mask = MCP251XFD_REG_IOCON_TRIS(offset);
1915 u32 val_mask = MCP251XFD_REG_IOCON_LAT(offset);
1916 u32 val;
1917
1918 if (value)
1919 val = val_mask;
1920 else
1921 val = 0;
1922
1923 return regmap_update_bits(priv->map_reg, MCP251XFD_REG_IOCON,
1924 dir_mask | val_mask, val);
1925 }
1926
mcp251xfd_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)1927 static int mcp251xfd_gpio_direction_input(struct gpio_chip *chip,
1928 unsigned int offset)
1929 {
1930 struct mcp251xfd_priv *priv = gpiochip_get_data(chip);
1931 u32 dir_mask = MCP251XFD_REG_IOCON_TRIS(offset);
1932
1933 return regmap_update_bits(priv->map_reg, MCP251XFD_REG_IOCON, dir_mask, dir_mask);
1934 }
1935
mcp251xfd_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)1936 static int mcp251xfd_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1937 {
1938 struct mcp251xfd_priv *priv = gpiochip_get_data(chip);
1939 u32 val_mask = MCP251XFD_REG_IOCON_LAT(offset);
1940 u32 val;
1941
1942 if (value)
1943 val = val_mask;
1944 else
1945 val = 0;
1946
1947 return regmap_update_bits(priv->map_reg, MCP251XFD_REG_IOCON, val_mask, val);
1948 }
1949
mcp251xfd_gpio_set_multiple(struct gpio_chip * chip,unsigned long * mask,unsigned long * bits)1950 static int mcp251xfd_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
1951 unsigned long *bits)
1952 {
1953 struct mcp251xfd_priv *priv = gpiochip_get_data(chip);
1954 u32 val;
1955
1956 val = FIELD_PREP(MCP251XFD_REG_IOCON_LAT_MASK, *bits);
1957
1958 return regmap_update_bits(priv->map_reg, MCP251XFD_REG_IOCON,
1959 MCP251XFD_REG_IOCON_LAT_MASK, val);
1960 }
1961
mcp251fdx_gpio_setup(struct mcp251xfd_priv * priv)1962 static int mcp251fdx_gpio_setup(struct mcp251xfd_priv *priv)
1963 {
1964 struct gpio_chip *gc = &priv->gc;
1965
1966 if (!device_property_present(&priv->spi->dev, "gpio-controller"))
1967 return 0;
1968
1969 gc->label = dev_name(&priv->spi->dev);
1970 gc->parent = &priv->spi->dev;
1971 gc->owner = THIS_MODULE;
1972 gc->request = mcp251xfd_gpio_request;
1973 gc->free = mcp251xfd_gpio_free;
1974 gc->get_direction = mcp251xfd_gpio_get_direction;
1975 gc->direction_output = mcp251xfd_gpio_direction_output;
1976 gc->direction_input = mcp251xfd_gpio_direction_input;
1977 gc->get = mcp251xfd_gpio_get;
1978 gc->get_multiple = mcp251xfd_gpio_get_multiple;
1979 gc->set = mcp251xfd_gpio_set;
1980 gc->set_multiple = mcp251xfd_gpio_set_multiple;
1981 gc->base = -1;
1982 gc->can_sleep = true;
1983 gc->ngpio = ARRAY_SIZE(mcp251xfd_gpio_names);
1984 gc->names = mcp251xfd_gpio_names;
1985
1986 return devm_gpiochip_add_data(&priv->spi->dev, gc, priv);
1987 }
1988
1989 static int
mcp251xfd_register_get_dev_id(const struct mcp251xfd_priv * priv,u32 * dev_id,u32 * effective_speed_hz_slow,u32 * effective_speed_hz_fast)1990 mcp251xfd_register_get_dev_id(const struct mcp251xfd_priv *priv, u32 *dev_id,
1991 u32 *effective_speed_hz_slow,
1992 u32 *effective_speed_hz_fast)
1993 {
1994 struct mcp251xfd_map_buf_nocrc *buf_rx;
1995 struct mcp251xfd_map_buf_nocrc *buf_tx;
1996 struct spi_transfer xfer[2] = { };
1997 int err;
1998
1999 buf_rx = kzalloc_obj(*buf_rx);
2000 if (!buf_rx)
2001 return -ENOMEM;
2002
2003 buf_tx = kzalloc_obj(*buf_tx);
2004 if (!buf_tx) {
2005 err = -ENOMEM;
2006 goto out_kfree_buf_rx;
2007 }
2008
2009 xfer[0].tx_buf = buf_tx;
2010 xfer[0].len = sizeof(buf_tx->cmd);
2011 xfer[0].speed_hz = priv->spi_max_speed_hz_slow;
2012 xfer[1].rx_buf = buf_rx->data;
2013 xfer[1].len = sizeof(*dev_id);
2014 xfer[1].speed_hz = priv->spi_max_speed_hz_fast;
2015
2016 mcp251xfd_spi_cmd_read_nocrc(&buf_tx->cmd, MCP251XFD_REG_DEVID);
2017
2018 err = spi_sync_transfer(priv->spi, xfer, ARRAY_SIZE(xfer));
2019 if (err)
2020 goto out_kfree_buf_tx;
2021
2022 *dev_id = get_unaligned_le32(buf_rx->data);
2023 *effective_speed_hz_slow = xfer[0].effective_speed_hz;
2024 *effective_speed_hz_fast = xfer[1].effective_speed_hz;
2025
2026 out_kfree_buf_tx:
2027 kfree(buf_tx);
2028 out_kfree_buf_rx:
2029 kfree(buf_rx);
2030
2031 return err;
2032 }
2033
2034 #define MCP251XFD_QUIRK_ACTIVE(quirk) \
2035 (priv->devtype_data.quirks & MCP251XFD_QUIRK_##quirk ? '+' : '-')
2036
2037 static int
mcp251xfd_register_done(const struct mcp251xfd_priv * priv)2038 mcp251xfd_register_done(const struct mcp251xfd_priv *priv)
2039 {
2040 u32 dev_id, effective_speed_hz_slow, effective_speed_hz_fast;
2041 unsigned long clk_rate;
2042 int err;
2043
2044 err = mcp251xfd_register_get_dev_id(priv, &dev_id,
2045 &effective_speed_hz_slow,
2046 &effective_speed_hz_fast);
2047 if (err)
2048 return err;
2049
2050 clk_rate = clk_get_rate(priv->clk);
2051
2052 netdev_info(priv->ndev,
2053 "%s rev%lu.%lu (%cRX_INT %cPLL %cMAB_NO_WARN %cCRC_REG %cCRC_RX %cCRC_TX %cECC %cHD o:%lu.%02luMHz c:%u.%02uMHz m:%u.%02uMHz rs:%u.%02uMHz es:%u.%02uMHz rf:%u.%02uMHz ef:%u.%02uMHz) successfully initialized.\n",
2054 mcp251xfd_get_model_str(priv),
2055 FIELD_GET(MCP251XFD_REG_DEVID_ID_MASK, dev_id),
2056 FIELD_GET(MCP251XFD_REG_DEVID_REV_MASK, dev_id),
2057 priv->rx_int ? '+' : '-',
2058 priv->pll_enable ? '+' : '-',
2059 MCP251XFD_QUIRK_ACTIVE(MAB_NO_WARN),
2060 MCP251XFD_QUIRK_ACTIVE(CRC_REG),
2061 MCP251XFD_QUIRK_ACTIVE(CRC_RX),
2062 MCP251XFD_QUIRK_ACTIVE(CRC_TX),
2063 MCP251XFD_QUIRK_ACTIVE(ECC),
2064 MCP251XFD_QUIRK_ACTIVE(HALF_DUPLEX),
2065 clk_rate / 1000000,
2066 clk_rate % 1000000 / 1000 / 10,
2067 priv->can.clock.freq / 1000000,
2068 priv->can.clock.freq % 1000000 / 1000 / 10,
2069 priv->spi_max_speed_hz_orig / 1000000,
2070 priv->spi_max_speed_hz_orig % 1000000 / 1000 / 10,
2071 priv->spi_max_speed_hz_slow / 1000000,
2072 priv->spi_max_speed_hz_slow % 1000000 / 1000 / 10,
2073 effective_speed_hz_slow / 1000000,
2074 effective_speed_hz_slow % 1000000 / 1000 / 10,
2075 priv->spi_max_speed_hz_fast / 1000000,
2076 priv->spi_max_speed_hz_fast % 1000000 / 1000 / 10,
2077 effective_speed_hz_fast / 1000000,
2078 effective_speed_hz_fast % 1000000 / 1000 / 10);
2079
2080 return 0;
2081 }
2082
mcp251xfd_register(struct mcp251xfd_priv * priv)2083 static int mcp251xfd_register(struct mcp251xfd_priv *priv)
2084 {
2085 struct net_device *ndev = priv->ndev;
2086 int err;
2087
2088 mcp251xfd_register_quirks(priv);
2089
2090 err = mcp251xfd_clks_and_vdd_enable(priv);
2091 if (err)
2092 return err;
2093
2094 err = mcp251xfd_chip_softreset(priv);
2095 if (err == -ENODEV)
2096 goto out_clks_and_vdd_disable;
2097 if (err)
2098 goto out_chip_sleep;
2099
2100 err = mcp251xfd_chip_clock_init(priv);
2101 if (err == -ENODEV)
2102 goto out_clks_and_vdd_disable;
2103 if (err)
2104 goto out_chip_sleep;
2105
2106 pm_runtime_get_noresume(ndev->dev.parent);
2107 err = pm_runtime_set_active(ndev->dev.parent);
2108 if (err)
2109 goto out_runtime_put_noidle;
2110 pm_runtime_enable(ndev->dev.parent);
2111
2112 err = mcp251xfd_register_chip_detect(priv);
2113 if (err)
2114 goto out_runtime_disable;
2115
2116 err = mcp251xfd_register_check_rx_int(priv);
2117 if (err)
2118 goto out_runtime_disable;
2119
2120 mcp251xfd_ethtool_init(priv);
2121
2122 err = mcp251fdx_gpio_setup(priv);
2123 if (err) {
2124 dev_err_probe(&priv->spi->dev, err, "Failed to register gpio-controller.\n");
2125 goto out_runtime_disable;
2126 }
2127
2128 err = register_candev(ndev);
2129 if (err)
2130 goto out_runtime_disable;
2131
2132 err = mcp251xfd_register_done(priv);
2133 if (err)
2134 goto out_unregister_candev;
2135
2136 /* Put controller into Config mode and let pm_runtime_put()
2137 * put in sleep mode, disable the clocks and vdd. If CONFIG_PM
2138 * is not enabled, the clocks and vdd will stay powered.
2139 */
2140 err = mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_CONFIG);
2141 if (err)
2142 goto out_unregister_candev;
2143
2144 pm_runtime_put(ndev->dev.parent);
2145
2146 return 0;
2147
2148 out_unregister_candev:
2149 unregister_candev(ndev);
2150 out_runtime_disable:
2151 pm_runtime_disable(ndev->dev.parent);
2152 out_runtime_put_noidle:
2153 pm_runtime_put_noidle(ndev->dev.parent);
2154 out_chip_sleep:
2155 mcp251xfd_chip_sleep(priv);
2156 out_clks_and_vdd_disable:
2157 mcp251xfd_clks_and_vdd_disable(priv);
2158
2159 return err;
2160 }
2161
mcp251xfd_unregister(struct mcp251xfd_priv * priv)2162 static inline void mcp251xfd_unregister(struct mcp251xfd_priv *priv)
2163 {
2164 struct net_device *ndev = priv->ndev;
2165
2166 unregister_candev(ndev);
2167
2168 if (pm_runtime_enabled(ndev->dev.parent)) {
2169 pm_runtime_disable(ndev->dev.parent);
2170 } else {
2171 mcp251xfd_chip_sleep(priv);
2172 mcp251xfd_clks_and_vdd_disable(priv);
2173 }
2174 }
2175
2176 static const struct of_device_id mcp251xfd_of_match[] = {
2177 {
2178 .compatible = "microchip,mcp2517fd",
2179 .data = &mcp251xfd_devtype_data_mcp2517fd,
2180 }, {
2181 .compatible = "microchip,mcp2518fd",
2182 .data = &mcp251xfd_devtype_data_mcp2518fd,
2183 }, {
2184 .compatible = "microchip,mcp251863",
2185 .data = &mcp251xfd_devtype_data_mcp251863,
2186 }, {
2187 .compatible = "microchip,mcp251xfd",
2188 .data = &mcp251xfd_devtype_data_mcp251xfd,
2189 }, {
2190 /* sentinel */
2191 },
2192 };
2193 MODULE_DEVICE_TABLE(of, mcp251xfd_of_match);
2194
2195 static const struct spi_device_id mcp251xfd_id_table[] = {
2196 {
2197 .name = "mcp2517fd",
2198 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2517fd,
2199 }, {
2200 .name = "mcp2518fd",
2201 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2518fd,
2202 }, {
2203 .name = "mcp251863",
2204 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp251863,
2205 }, {
2206 .name = "mcp251xfd",
2207 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp251xfd,
2208 }, {
2209 /* sentinel */
2210 },
2211 };
2212 MODULE_DEVICE_TABLE(spi, mcp251xfd_id_table);
2213
mcp251xfd_probe(struct spi_device * spi)2214 static int mcp251xfd_probe(struct spi_device *spi)
2215 {
2216 struct net_device *ndev;
2217 struct mcp251xfd_priv *priv;
2218 struct gpio_desc *rx_int;
2219 struct regulator *reg_vdd, *reg_xceiver;
2220 struct clk *clk;
2221 bool pll_enable = false;
2222 u32 freq = 0;
2223 int err;
2224
2225 if (!spi->irq)
2226 return dev_err_probe(&spi->dev, -ENXIO,
2227 "No IRQ specified (maybe node \"interrupts-extended\" in DT missing)!\n");
2228
2229 rx_int = devm_gpiod_get_optional(&spi->dev, "microchip,rx-int",
2230 GPIOD_IN);
2231 if (IS_ERR(rx_int))
2232 return dev_err_probe(&spi->dev, PTR_ERR(rx_int),
2233 "Failed to get RX-INT!\n");
2234
2235 reg_vdd = devm_regulator_get_optional(&spi->dev, "vdd");
2236 if (PTR_ERR(reg_vdd) == -ENODEV)
2237 reg_vdd = NULL;
2238 else if (IS_ERR(reg_vdd))
2239 return dev_err_probe(&spi->dev, PTR_ERR(reg_vdd),
2240 "Failed to get VDD regulator!\n");
2241
2242 reg_xceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
2243 if (PTR_ERR(reg_xceiver) == -ENODEV)
2244 reg_xceiver = NULL;
2245 else if (IS_ERR(reg_xceiver))
2246 return dev_err_probe(&spi->dev, PTR_ERR(reg_xceiver),
2247 "Failed to get Transceiver regulator!\n");
2248
2249 clk = devm_clk_get_optional(&spi->dev, NULL);
2250 if (IS_ERR(clk))
2251 return dev_err_probe(&spi->dev, PTR_ERR(clk),
2252 "Failed to get Oscillator (clock)!\n");
2253 if (clk) {
2254 freq = clk_get_rate(clk);
2255 } else {
2256 err = device_property_read_u32(&spi->dev, "clock-frequency",
2257 &freq);
2258 if (err)
2259 return dev_err_probe(&spi->dev, err,
2260 "Failed to get clock-frequency!\n");
2261 }
2262
2263 /* Sanity check */
2264 if (freq < MCP251XFD_SYSCLOCK_HZ_MIN ||
2265 freq > MCP251XFD_SYSCLOCK_HZ_MAX) {
2266 dev_err(&spi->dev,
2267 "Oscillator frequency (%u Hz) is too low or high.\n",
2268 freq);
2269 return -ERANGE;
2270 }
2271
2272 if (freq <= MCP251XFD_SYSCLOCK_HZ_MAX / MCP251XFD_OSC_PLL_MULTIPLIER)
2273 pll_enable = true;
2274
2275 ndev = alloc_candev(sizeof(struct mcp251xfd_priv),
2276 MCP251XFD_TX_OBJ_NUM_MAX);
2277 if (!ndev)
2278 return -ENOMEM;
2279
2280 SET_NETDEV_DEV(ndev, &spi->dev);
2281
2282 ndev->netdev_ops = &mcp251xfd_netdev_ops;
2283 ndev->irq = spi->irq;
2284 ndev->flags |= IFF_ECHO;
2285
2286 priv = netdev_priv(ndev);
2287 spi_set_drvdata(spi, priv);
2288 priv->can.clock.freq = freq;
2289 if (pll_enable)
2290 priv->can.clock.freq *= MCP251XFD_OSC_PLL_MULTIPLIER;
2291 priv->can.do_set_mode = mcp251xfd_set_mode;
2292 priv->can.do_get_berr_counter = mcp251xfd_get_berr_counter;
2293 priv->can.bittiming_const = &mcp251xfd_bittiming_const;
2294 priv->can.fd.data_bittiming_const = &mcp251xfd_data_bittiming_const;
2295 priv->can.fd.tdc_const = &mcp251xfd_tdc_const;
2296 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
2297 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_BERR_REPORTING |
2298 CAN_CTRLMODE_FD | CAN_CTRLMODE_FD_NON_ISO |
2299 CAN_CTRLMODE_CC_LEN8_DLC | CAN_CTRLMODE_TDC_AUTO |
2300 CAN_CTRLMODE_TDC_MANUAL;
2301 set_bit(MCP251XFD_FLAGS_DOWN, priv->flags);
2302 priv->ndev = ndev;
2303 priv->spi = spi;
2304 priv->rx_int = rx_int;
2305 priv->clk = clk;
2306 priv->pll_enable = pll_enable;
2307 priv->reg_vdd = reg_vdd;
2308 priv->reg_xceiver = reg_xceiver;
2309 priv->xstbyen = device_property_present(&spi->dev, "microchip,xstbyen");
2310 priv->devtype_data = *(struct mcp251xfd_devtype_data *)spi_get_device_match_data(spi);
2311
2312 /* Errata Reference:
2313 * mcp2517fd: DS80000792C 5., mcp2518fd: DS80000789E 4.,
2314 * mcp251863: DS80000984A 4.
2315 *
2316 * The SPI can write corrupted data to the RAM at fast SPI
2317 * speeds:
2318 *
2319 * Simultaneous activity on the CAN bus while writing data to
2320 * RAM via the SPI interface, with high SCK frequency, can
2321 * lead to corrupted data being written to RAM.
2322 *
2323 * Fix/Work Around:
2324 * Ensure that FSCK is less than or equal to 0.85 *
2325 * (FSYSCLK/2).
2326 *
2327 * Known good combinations are:
2328 *
2329 * MCP ext-clk SoC SPI SPI-clk max-clk parent-clk config
2330 *
2331 * 2518 20 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 8333333 Hz 83.33% 600000000 Hz assigned-clocks = <&ccu CLK_SPIx>
2332 * 2518 40 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 16666667 Hz 83.33% 600000000 Hz assigned-clocks = <&ccu CLK_SPIx>
2333 * 2517 40 MHz atmel,sama5d27 atmel,at91rm9200-spi 16400000 Hz 82.00% 82000000 Hz default
2334 * 2518 40 MHz atmel,sama5d27 atmel,at91rm9200-spi 16400000 Hz 82.00% 82000000 Hz default
2335 * 2518 40 MHz fsl,imx6dl fsl,imx51-ecspi 15000000 Hz 75.00% 30000000 Hz default
2336 * 2517 20 MHz fsl,imx8mm fsl,imx51-ecspi 8333333 Hz 83.33% 16666667 Hz assigned-clocks = <&clk IMX8MM_CLK_ECSPIx_ROOT>
2337 *
2338 */
2339 priv->spi_max_speed_hz_orig = spi->max_speed_hz;
2340 priv->spi_max_speed_hz_slow = min(spi->max_speed_hz,
2341 freq / 2 / 1000 * 850);
2342 if (priv->pll_enable)
2343 priv->spi_max_speed_hz_fast = min(spi->max_speed_hz,
2344 freq *
2345 MCP251XFD_OSC_PLL_MULTIPLIER /
2346 2 / 1000 * 850);
2347 else
2348 priv->spi_max_speed_hz_fast = priv->spi_max_speed_hz_slow;
2349 spi->max_speed_hz = priv->spi_max_speed_hz_slow;
2350 spi->bits_per_word = 8;
2351 spi->rt = true;
2352 err = spi_setup(spi);
2353 if (err)
2354 goto out_free_candev;
2355
2356 err = mcp251xfd_regmap_init(priv);
2357 if (err)
2358 goto out_free_candev;
2359
2360 err = can_rx_offload_add_manual(ndev, &priv->offload,
2361 MCP251XFD_NAPI_WEIGHT);
2362 if (err)
2363 goto out_free_candev;
2364
2365 err = mcp251xfd_register(priv);
2366 if (err) {
2367 dev_err_probe(&spi->dev, err, "Failed to detect %s.\n",
2368 mcp251xfd_get_model_str(priv));
2369 goto out_can_rx_offload_del;
2370 }
2371
2372 return 0;
2373
2374 out_can_rx_offload_del:
2375 can_rx_offload_del(&priv->offload);
2376 out_free_candev:
2377 spi->max_speed_hz = priv->spi_max_speed_hz_orig;
2378
2379 free_candev(ndev);
2380
2381 return err;
2382 }
2383
mcp251xfd_remove(struct spi_device * spi)2384 static void mcp251xfd_remove(struct spi_device *spi)
2385 {
2386 struct mcp251xfd_priv *priv = spi_get_drvdata(spi);
2387 struct net_device *ndev = priv->ndev;
2388
2389 mcp251xfd_unregister(priv);
2390 can_rx_offload_del(&priv->offload);
2391 spi->max_speed_hz = priv->spi_max_speed_hz_orig;
2392 free_candev(ndev);
2393 }
2394
mcp251xfd_runtime_suspend(struct device * device)2395 static int __maybe_unused mcp251xfd_runtime_suspend(struct device *device)
2396 {
2397 struct mcp251xfd_priv *priv = dev_get_drvdata(device);
2398
2399 mcp251xfd_chip_sleep(priv);
2400 return mcp251xfd_clks_and_vdd_disable(priv);
2401 }
2402
mcp251xfd_runtime_resume(struct device * device)2403 static int __maybe_unused mcp251xfd_runtime_resume(struct device *device)
2404 {
2405 struct mcp251xfd_priv *priv = dev_get_drvdata(device);
2406 int err;
2407
2408 err = mcp251xfd_clks_and_vdd_enable(priv);
2409 if (err)
2410 return err;
2411
2412 err = mcp251xfd_chip_softreset(priv);
2413 if (err == -ENODEV)
2414 goto out_clks_and_vdd_disable;
2415 if (err)
2416 goto out_chip_sleep;
2417
2418 err = mcp251xfd_chip_clock_init(priv);
2419 if (err == -ENODEV)
2420 goto out_clks_and_vdd_disable;
2421 if (err)
2422 goto out_chip_sleep;
2423
2424 return 0;
2425
2426 out_chip_sleep:
2427 mcp251xfd_chip_sleep(priv);
2428 out_clks_and_vdd_disable:
2429 mcp251xfd_clks_and_vdd_disable(priv);
2430
2431 return err;
2432 }
2433
2434 static const struct dev_pm_ops mcp251xfd_pm_ops = {
2435 SET_RUNTIME_PM_OPS(mcp251xfd_runtime_suspend,
2436 mcp251xfd_runtime_resume, NULL)
2437 };
2438
2439 static struct spi_driver mcp251xfd_driver = {
2440 .driver = {
2441 .name = DEVICE_NAME,
2442 .pm = &mcp251xfd_pm_ops,
2443 .of_match_table = mcp251xfd_of_match,
2444 },
2445 .probe = mcp251xfd_probe,
2446 .remove = mcp251xfd_remove,
2447 .id_table = mcp251xfd_id_table,
2448 };
2449 module_spi_driver(mcp251xfd_driver);
2450
2451 MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>");
2452 MODULE_DESCRIPTION("Microchip MCP251xFD Family CAN controller driver");
2453 MODULE_LICENSE("GPL v2");
2454