1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /*
3 * MTK ECC controller driver.
4 * Copyright (C) 2016 MediaTek Inc.
5 * Authors: Xiaolei Li <xiaolei.li@mediatek.com>
6 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
7 */
8
9 #include <linux/platform_device.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/interrupt.h>
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/iopoll.h>
15 #include <linux/of.h>
16 #include <linux/of_platform.h>
17 #include <linux/mutex.h>
18 #include <linux/mtd/nand-ecc-mtk.h>
19
20 #define ECC_IDLE_MASK BIT(0)
21 #define ECC_IRQ_EN BIT(0)
22 #define ECC_PG_IRQ_SEL BIT(1)
23 #define ECC_OP_ENABLE (1)
24 #define ECC_OP_DISABLE (0)
25
26 #define ECC_ENCCON (0x00)
27 #define ECC_ENCCNFG (0x04)
28 #define ECC_MS_SHIFT (16)
29 #define ECC_ENCDIADDR (0x08)
30 #define ECC_ENCIDLE (0x0C)
31 #define ECC_DECCON (0x100)
32 #define ECC_DECCNFG (0x104)
33 #define DEC_EMPTY_EN BIT(31)
34 #define DEC_CNFG_CORRECT (0x3 << 12)
35 #define ECC_DECIDLE (0x10C)
36 #define ECC_DECENUM0 (0x114)
37
38 #define ECC_TIMEOUT (500000)
39
40 #define ECC_IDLE_REG(op) ((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE)
41 #define ECC_CTL_REG(op) ((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON)
42
43 #define ECC_ERRMASK_MT7622 GENMASK(4, 0)
44 #define ECC_ERRMASK_MT2701 GENMASK(5, 0)
45 #define ECC_ERRMASK_MT2712 GENMASK(6, 0)
46
47 struct mtk_ecc_caps {
48 u32 err_mask;
49 u32 err_shift;
50 const u8 *ecc_strength;
51 const u32 *ecc_regs;
52 u8 num_ecc_strength;
53 u8 ecc_mode_shift;
54 u32 parity_bits;
55 int pg_irq_sel;
56 };
57
58 struct mtk_ecc {
59 struct device *dev;
60 const struct mtk_ecc_caps *caps;
61 void __iomem *regs;
62 struct clk *clk;
63
64 struct completion done;
65 struct mutex lock;
66 u32 sectors;
67
68 u8 *eccdata;
69 };
70
71 /* ecc strength that each IP supports */
72 static const u8 ecc_strength_mt2701[] = {
73 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
74 40, 44, 48, 52, 56, 60
75 };
76
77 static const u8 ecc_strength_mt2712[] = {
78 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
79 40, 44, 48, 52, 56, 60, 68, 72, 80
80 };
81
82 static const u8 ecc_strength_mt7622[] = {
83 4, 6, 8, 10, 12
84 };
85
86 static const u8 ecc_strength_mt7986[] = {
87 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24
88 };
89
90 enum mtk_ecc_regs {
91 ECC_ENCPAR00,
92 ECC_ENCIRQ_EN,
93 ECC_ENCIRQ_STA,
94 ECC_DECDONE,
95 ECC_DECIRQ_EN,
96 ECC_DECIRQ_STA,
97 };
98
99 static int mt2701_ecc_regs[] = {
100 [ECC_ENCPAR00] = 0x10,
101 [ECC_ENCIRQ_EN] = 0x80,
102 [ECC_ENCIRQ_STA] = 0x84,
103 [ECC_DECDONE] = 0x124,
104 [ECC_DECIRQ_EN] = 0x200,
105 [ECC_DECIRQ_STA] = 0x204,
106 };
107
108 static int mt2712_ecc_regs[] = {
109 [ECC_ENCPAR00] = 0x300,
110 [ECC_ENCIRQ_EN] = 0x80,
111 [ECC_ENCIRQ_STA] = 0x84,
112 [ECC_DECDONE] = 0x124,
113 [ECC_DECIRQ_EN] = 0x200,
114 [ECC_DECIRQ_STA] = 0x204,
115 };
116
117 static int mt7622_ecc_regs[] = {
118 [ECC_ENCPAR00] = 0x10,
119 [ECC_ENCIRQ_EN] = 0x30,
120 [ECC_ENCIRQ_STA] = 0x34,
121 [ECC_DECDONE] = 0x11c,
122 [ECC_DECIRQ_EN] = 0x140,
123 [ECC_DECIRQ_STA] = 0x144,
124 };
125
mtk_ecc_wait_idle(struct mtk_ecc * ecc,enum mtk_ecc_operation op)126 static inline int mtk_ecc_wait_idle(struct mtk_ecc *ecc,
127 enum mtk_ecc_operation op)
128 {
129 struct device *dev = ecc->dev;
130 u32 val;
131 int ret;
132
133 ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val,
134 val & ECC_IDLE_MASK,
135 10, ECC_TIMEOUT);
136 if (ret)
137 dev_warn(dev, "%s NOT idle\n",
138 op == ECC_ENCODE ? "encoder" : "decoder");
139
140 return ret;
141 }
142
mtk_ecc_irq(int irq,void * id)143 static irqreturn_t mtk_ecc_irq(int irq, void *id)
144 {
145 struct mtk_ecc *ecc = id;
146 u32 dec, enc;
147
148 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA])
149 & ECC_IRQ_EN;
150 if (dec) {
151 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
152 if (dec & ecc->sectors) {
153 /*
154 * Clear decode IRQ status once again to ensure that
155 * there will be no extra IRQ.
156 */
157 readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]);
158 ecc->sectors = 0;
159 complete(&ecc->done);
160 } else {
161 return IRQ_HANDLED;
162 }
163 } else {
164 enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA])
165 & ECC_IRQ_EN;
166 if (enc)
167 complete(&ecc->done);
168 else
169 return IRQ_NONE;
170 }
171
172 return IRQ_HANDLED;
173 }
174
mtk_ecc_config(struct mtk_ecc * ecc,struct mtk_ecc_config * config)175 static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
176 {
177 u32 ecc_bit, dec_sz, enc_sz;
178 u32 reg, i;
179
180 for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
181 if (ecc->caps->ecc_strength[i] == config->strength)
182 break;
183 }
184
185 if (i == ecc->caps->num_ecc_strength) {
186 dev_err(ecc->dev, "invalid ecc strength %d\n",
187 config->strength);
188 return -EINVAL;
189 }
190
191 ecc_bit = i;
192
193 if (config->op == ECC_ENCODE) {
194 /* configure ECC encoder (in bits) */
195 enc_sz = config->len << 3;
196
197 reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
198 reg |= (enc_sz << ECC_MS_SHIFT);
199 writel(reg, ecc->regs + ECC_ENCCNFG);
200
201 if (config->mode != ECC_NFI_MODE)
202 writel(lower_32_bits(config->addr),
203 ecc->regs + ECC_ENCDIADDR);
204
205 } else {
206 /* configure ECC decoder (in bits) */
207 dec_sz = (config->len << 3) +
208 config->strength * ecc->caps->parity_bits;
209
210 reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
211 reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT;
212 reg |= DEC_EMPTY_EN;
213 writel(reg, ecc->regs + ECC_DECCNFG);
214
215 if (config->sectors)
216 ecc->sectors = 1 << (config->sectors - 1);
217 }
218
219 return 0;
220 }
221
mtk_ecc_get_stats(struct mtk_ecc * ecc,struct mtk_ecc_stats * stats,int sectors)222 void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats,
223 int sectors)
224 {
225 u32 offset, i, err;
226 u32 bitflips = 0;
227
228 stats->corrected = 0;
229 stats->failed = 0;
230
231 for (i = 0; i < sectors; i++) {
232 offset = (i >> 2) << 2;
233 err = readl(ecc->regs + ECC_DECENUM0 + offset);
234 err = err >> ((i % 4) * ecc->caps->err_shift);
235 err &= ecc->caps->err_mask;
236 if (err == ecc->caps->err_mask) {
237 /* uncorrectable errors */
238 stats->failed++;
239 continue;
240 }
241
242 stats->corrected += err;
243 bitflips = max_t(u32, bitflips, err);
244 }
245
246 stats->bitflips = bitflips;
247 }
248 EXPORT_SYMBOL(mtk_ecc_get_stats);
249
mtk_ecc_release(struct mtk_ecc * ecc)250 void mtk_ecc_release(struct mtk_ecc *ecc)
251 {
252 clk_disable_unprepare(ecc->clk);
253 put_device(ecc->dev);
254 }
255 EXPORT_SYMBOL(mtk_ecc_release);
256
mtk_ecc_hw_init(struct mtk_ecc * ecc)257 static void mtk_ecc_hw_init(struct mtk_ecc *ecc)
258 {
259 mtk_ecc_wait_idle(ecc, ECC_ENCODE);
260 writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON);
261
262 mtk_ecc_wait_idle(ecc, ECC_DECODE);
263 writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON);
264 }
265
mtk_ecc_get(struct device_node * np)266 static struct mtk_ecc *mtk_ecc_get(struct device_node *np)
267 {
268 struct platform_device *pdev;
269 struct mtk_ecc *ecc;
270 int ret;
271
272 pdev = of_find_device_by_node(np);
273 if (!pdev)
274 return ERR_PTR(-EPROBE_DEFER);
275
276 ecc = platform_get_drvdata(pdev);
277 if (!ecc) {
278 put_device(&pdev->dev);
279 return ERR_PTR(-EPROBE_DEFER);
280 }
281
282 ret = clk_prepare_enable(ecc->clk);
283 if (ret) {
284 put_device(&pdev->dev);
285 return ERR_PTR(ret);
286 }
287
288 mtk_ecc_hw_init(ecc);
289
290 return ecc;
291 }
292
of_mtk_ecc_get(struct device_node * of_node)293 struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node)
294 {
295 struct mtk_ecc *ecc = NULL;
296 struct device_node *np;
297
298 np = of_parse_phandle(of_node, "nand-ecc-engine", 0);
299 /* for backward compatibility */
300 if (!np)
301 np = of_parse_phandle(of_node, "ecc-engine", 0);
302 if (np) {
303 ecc = mtk_ecc_get(np);
304 of_node_put(np);
305 }
306
307 return ecc;
308 }
309 EXPORT_SYMBOL(of_mtk_ecc_get);
310
mtk_ecc_enable(struct mtk_ecc * ecc,struct mtk_ecc_config * config)311 int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
312 {
313 enum mtk_ecc_operation op = config->op;
314 u16 reg_val;
315 int ret;
316
317 ret = mutex_lock_interruptible(&ecc->lock);
318 if (ret) {
319 dev_err(ecc->dev, "interrupted when attempting to lock\n");
320 return ret;
321 }
322
323 ret = mtk_ecc_wait_idle(ecc, op);
324 if (ret) {
325 mutex_unlock(&ecc->lock);
326 return ret;
327 }
328
329 ret = mtk_ecc_config(ecc, config);
330 if (ret) {
331 mutex_unlock(&ecc->lock);
332 return ret;
333 }
334
335 if (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) {
336 init_completion(&ecc->done);
337 reg_val = ECC_IRQ_EN;
338 /*
339 * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it
340 * means this chip can only generate one ecc irq during page
341 * read / write. If is 0, generate one ecc irq each ecc step.
342 */
343 if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE)
344 reg_val |= ECC_PG_IRQ_SEL;
345 if (op == ECC_ENCODE)
346 writew(reg_val, ecc->regs +
347 ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
348 else
349 writew(reg_val, ecc->regs +
350 ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
351 }
352
353 writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));
354
355 return 0;
356 }
357 EXPORT_SYMBOL(mtk_ecc_enable);
358
mtk_ecc_disable(struct mtk_ecc * ecc)359 void mtk_ecc_disable(struct mtk_ecc *ecc)
360 {
361 enum mtk_ecc_operation op = ECC_ENCODE;
362
363 /* find out the running operation */
364 if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE)
365 op = ECC_DECODE;
366
367 /* disable it */
368 mtk_ecc_wait_idle(ecc, op);
369 if (op == ECC_DECODE) {
370 /*
371 * Clear decode IRQ status in case there is a timeout to wait
372 * decode IRQ.
373 */
374 readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
375 writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
376 } else {
377 writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
378 }
379
380 writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op));
381
382 mutex_unlock(&ecc->lock);
383 }
384 EXPORT_SYMBOL(mtk_ecc_disable);
385
mtk_ecc_wait_done(struct mtk_ecc * ecc,enum mtk_ecc_operation op)386 int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op)
387 {
388 int ret;
389
390 ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500));
391 if (!ret) {
392 dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n",
393 (op == ECC_ENCODE) ? "encoder" : "decoder");
394 return -ETIMEDOUT;
395 }
396
397 return 0;
398 }
399 EXPORT_SYMBOL(mtk_ecc_wait_done);
400
mtk_ecc_encode(struct mtk_ecc * ecc,struct mtk_ecc_config * config,u8 * data,u32 bytes)401 int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config,
402 u8 *data, u32 bytes)
403 {
404 dma_addr_t addr;
405 u32 len;
406 int ret;
407
408 addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE);
409 ret = dma_mapping_error(ecc->dev, addr);
410 if (ret) {
411 dev_err(ecc->dev, "dma mapping error\n");
412 return -EINVAL;
413 }
414
415 config->op = ECC_ENCODE;
416 config->addr = addr;
417 ret = mtk_ecc_enable(ecc, config);
418 if (ret) {
419 dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
420 return ret;
421 }
422
423 ret = mtk_ecc_wait_done(ecc, ECC_ENCODE);
424 if (ret)
425 goto timeout;
426
427 ret = mtk_ecc_wait_idle(ecc, ECC_ENCODE);
428 if (ret)
429 goto timeout;
430
431 /* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */
432 len = (config->strength * ecc->caps->parity_bits + 7) >> 3;
433
434 /* write the parity bytes generated by the ECC back to temp buffer */
435 __ioread32_copy(ecc->eccdata,
436 ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00],
437 round_up(len, 4));
438
439 /* copy into possibly unaligned OOB region with actual length */
440 memcpy(data + bytes, ecc->eccdata, len);
441 timeout:
442
443 dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
444 mtk_ecc_disable(ecc);
445
446 return ret;
447 }
448 EXPORT_SYMBOL(mtk_ecc_encode);
449
mtk_ecc_adjust_strength(struct mtk_ecc * ecc,u32 * p)450 void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p)
451 {
452 const u8 *ecc_strength = ecc->caps->ecc_strength;
453 int i;
454
455 for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
456 if (*p <= ecc_strength[i]) {
457 if (!i)
458 *p = ecc_strength[i];
459 else if (*p != ecc_strength[i])
460 *p = ecc_strength[i - 1];
461 return;
462 }
463 }
464
465 *p = ecc_strength[ecc->caps->num_ecc_strength - 1];
466 }
467 EXPORT_SYMBOL(mtk_ecc_adjust_strength);
468
mtk_ecc_get_parity_bits(struct mtk_ecc * ecc)469 unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc)
470 {
471 return ecc->caps->parity_bits;
472 }
473 EXPORT_SYMBOL(mtk_ecc_get_parity_bits);
474
475 static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = {
476 .err_mask = ECC_ERRMASK_MT2701,
477 .err_shift = 8,
478 .ecc_strength = ecc_strength_mt2701,
479 .ecc_regs = mt2701_ecc_regs,
480 .num_ecc_strength = 20,
481 .ecc_mode_shift = 5,
482 .parity_bits = 14,
483 .pg_irq_sel = 0,
484 };
485
486 static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = {
487 .err_mask = ECC_ERRMASK_MT2712,
488 .err_shift = 8,
489 .ecc_strength = ecc_strength_mt2712,
490 .ecc_regs = mt2712_ecc_regs,
491 .num_ecc_strength = 23,
492 .ecc_mode_shift = 5,
493 .parity_bits = 14,
494 .pg_irq_sel = 1,
495 };
496
497 static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = {
498 .err_mask = ECC_ERRMASK_MT7622,
499 .err_shift = 5,
500 .ecc_strength = ecc_strength_mt7622,
501 .ecc_regs = mt7622_ecc_regs,
502 .num_ecc_strength = 5,
503 .ecc_mode_shift = 4,
504 .parity_bits = 13,
505 .pg_irq_sel = 0,
506 };
507
508 static const struct mtk_ecc_caps mtk_ecc_caps_mt7986 = {
509 .err_mask = ECC_ERRMASK_MT7622,
510 .err_shift = 8,
511 .ecc_strength = ecc_strength_mt7986,
512 .ecc_regs = mt2712_ecc_regs,
513 .num_ecc_strength = 11,
514 .ecc_mode_shift = 5,
515 .parity_bits = 14,
516 .pg_irq_sel = 1,
517 };
518
519 static const struct of_device_id mtk_ecc_dt_match[] = {
520 {
521 .compatible = "mediatek,mt2701-ecc",
522 .data = &mtk_ecc_caps_mt2701,
523 }, {
524 .compatible = "mediatek,mt2712-ecc",
525 .data = &mtk_ecc_caps_mt2712,
526 }, {
527 .compatible = "mediatek,mt7622-ecc",
528 .data = &mtk_ecc_caps_mt7622,
529 }, {
530 .compatible = "mediatek,mt7986-ecc",
531 .data = &mtk_ecc_caps_mt7986,
532 },
533 {},
534 };
535
mtk_ecc_probe(struct platform_device * pdev)536 static int mtk_ecc_probe(struct platform_device *pdev)
537 {
538 struct device *dev = &pdev->dev;
539 struct mtk_ecc *ecc;
540 u32 max_eccdata_size;
541 int irq, ret;
542
543 ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
544 if (!ecc)
545 return -ENOMEM;
546
547 ecc->caps = of_device_get_match_data(dev);
548
549 max_eccdata_size = ecc->caps->num_ecc_strength - 1;
550 max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size];
551 max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3;
552 max_eccdata_size = round_up(max_eccdata_size, 4);
553 ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL);
554 if (!ecc->eccdata)
555 return -ENOMEM;
556
557 ecc->regs = devm_platform_ioremap_resource(pdev, 0);
558 if (IS_ERR(ecc->regs))
559 return PTR_ERR(ecc->regs);
560
561 ecc->clk = devm_clk_get(dev, NULL);
562 if (IS_ERR(ecc->clk)) {
563 dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk));
564 return PTR_ERR(ecc->clk);
565 }
566
567 irq = platform_get_irq(pdev, 0);
568 if (irq < 0)
569 return irq;
570
571 ret = dma_set_mask(dev, DMA_BIT_MASK(32));
572 if (ret) {
573 dev_err(dev, "failed to set DMA mask\n");
574 return ret;
575 }
576
577 ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc);
578 if (ret) {
579 dev_err(dev, "failed to request irq\n");
580 return -EINVAL;
581 }
582
583 ecc->dev = dev;
584 mutex_init(&ecc->lock);
585 platform_set_drvdata(pdev, ecc);
586 dev_info(dev, "probed\n");
587
588 return 0;
589 }
590
591 #ifdef CONFIG_PM_SLEEP
mtk_ecc_suspend(struct device * dev)592 static int mtk_ecc_suspend(struct device *dev)
593 {
594 struct mtk_ecc *ecc = dev_get_drvdata(dev);
595
596 clk_disable_unprepare(ecc->clk);
597
598 return 0;
599 }
600
mtk_ecc_resume(struct device * dev)601 static int mtk_ecc_resume(struct device *dev)
602 {
603 struct mtk_ecc *ecc = dev_get_drvdata(dev);
604 int ret;
605
606 ret = clk_prepare_enable(ecc->clk);
607 if (ret) {
608 dev_err(dev, "failed to enable clk\n");
609 return ret;
610 }
611
612 return 0;
613 }
614
615 static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume);
616 #endif
617
618 MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match);
619
620 static struct platform_driver mtk_ecc_driver = {
621 .probe = mtk_ecc_probe,
622 .driver = {
623 .name = "mtk-ecc",
624 .of_match_table = mtk_ecc_dt_match,
625 #ifdef CONFIG_PM_SLEEP
626 .pm = &mtk_ecc_pm_ops,
627 #endif
628 },
629 };
630
631 module_platform_driver(mtk_ecc_driver);
632
633 MODULE_AUTHOR("Xiaolei Li <xiaolei.li@mediatek.com>");
634 MODULE_DESCRIPTION("MTK Nand ECC Driver");
635 MODULE_LICENSE("Dual MIT/GPL");
636