1 /*
2 * Copyright 2018-2024 Advanced Micro Devices, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <linux/kernfs.h>
26
27 #include "amdgpu.h"
28 #include "amdgpu_discovery.h"
29 #include "soc15_hw_ip.h"
30 #include "discovery.h"
31 #include "amdgpu_ras.h"
32
33 #include "soc15.h"
34 #include "gfx_v9_0.h"
35 #include "gfx_v9_4_3.h"
36 #include "gmc_v9_0.h"
37 #include "df_v1_7.h"
38 #include "df_v3_6.h"
39 #include "df_v4_3.h"
40 #include "df_v4_6_2.h"
41 #include "df_v4_15.h"
42 #include "nbio_v6_1.h"
43 #include "nbio_v7_0.h"
44 #include "nbio_v7_4.h"
45 #include "nbio_v7_9.h"
46 #include "nbio_v7_11.h"
47 #include "hdp_v4_0.h"
48 #include "vega10_ih.h"
49 #include "vega20_ih.h"
50 #include "sdma_v4_0.h"
51 #include "sdma_v4_4_2.h"
52 #include "uvd_v7_0.h"
53 #include "vce_v4_0.h"
54 #include "vcn_v1_0.h"
55 #include "vcn_v2_5.h"
56 #include "jpeg_v2_5.h"
57 #include "smuio_v9_0.h"
58 #include "gmc_v10_0.h"
59 #include "gmc_v11_0.h"
60 #include "gmc_v12_0.h"
61 #include "gfxhub_v2_0.h"
62 #include "mmhub_v2_0.h"
63 #include "nbio_v2_3.h"
64 #include "nbio_v4_3.h"
65 #include "nbio_v7_2.h"
66 #include "nbio_v7_7.h"
67 #include "nbif_v6_3_1.h"
68 #include "nbio_v6_3_2.h"
69 #include "hdp_v5_0.h"
70 #include "hdp_v5_2.h"
71 #include "hdp_v6_0.h"
72 #include "hdp_v7_0.h"
73 #include "nv.h"
74 #include "soc21.h"
75 #include "soc24.h"
76 #include "soc_v1_0.h"
77 #include "navi10_ih.h"
78 #include "ih_v6_0.h"
79 #include "ih_v6_1.h"
80 #include "ih_v7_0.h"
81 #include "gfx_v10_0.h"
82 #include "gfx_v11_0.h"
83 #include "gfx_v12_0.h"
84 #include "gfx_v12_1.h"
85 #include "sdma_v5_0.h"
86 #include "sdma_v5_2.h"
87 #include "sdma_v6_0.h"
88 #include "sdma_v7_0.h"
89 #include "sdma_v7_1.h"
90 #include "lsdma_v6_0.h"
91 #include "lsdma_v7_0.h"
92 #include "lsdma_v7_1.h"
93 #include "vcn_v2_0.h"
94 #include "jpeg_v2_0.h"
95 #include "vcn_v3_0.h"
96 #include "jpeg_v3_0.h"
97 #include "vcn_v4_0.h"
98 #include "jpeg_v4_0.h"
99 #include "vcn_v4_0_3.h"
100 #include "jpeg_v4_0_3.h"
101 #include "vcn_v4_0_5.h"
102 #include "jpeg_v4_0_5.h"
103 #include "amdgpu_vkms.h"
104 #include "mes_v11_0.h"
105 #include "mes_v12_0.h"
106 #include "mes_v12_1.h"
107 #include "smuio_v11_0.h"
108 #include "smuio_v11_0_6.h"
109 #include "smuio_v13_0.h"
110 #include "smuio_v13_0_3.h"
111 #include "smuio_v13_0_6.h"
112 #include "smuio_v14_0_2.h"
113 #include "smuio_v15_0_0.h"
114 #include "smuio_v15_0_8.h"
115 #include "vcn_v5_0_0.h"
116 #include "vcn_v5_0_1.h"
117 #include "vcn_v5_0_2.h"
118 #include "jpeg_v5_0_0.h"
119 #include "jpeg_v5_0_1.h"
120 #include "jpeg_v5_0_2.h"
121 #include "jpeg_v5_3_0.h"
122
123 #include "amdgpu_ras_mgr.h"
124
125 #include "amdgpu_vpe.h"
126 #if defined(CONFIG_DRM_AMD_ISP)
127 #include "amdgpu_isp.h"
128 #endif
129
130 MODULE_FIRMWARE("amdgpu/ip_discovery.bin");
131 MODULE_FIRMWARE("amdgpu/vega10_ip_discovery.bin");
132 MODULE_FIRMWARE("amdgpu/vega12_ip_discovery.bin");
133 MODULE_FIRMWARE("amdgpu/vega20_ip_discovery.bin");
134 MODULE_FIRMWARE("amdgpu/raven_ip_discovery.bin");
135 MODULE_FIRMWARE("amdgpu/raven2_ip_discovery.bin");
136 MODULE_FIRMWARE("amdgpu/picasso_ip_discovery.bin");
137 MODULE_FIRMWARE("amdgpu/arcturus_ip_discovery.bin");
138 MODULE_FIRMWARE("amdgpu/aldebaran_ip_discovery.bin");
139
140 /* Note: These registers are consistent across all the SOCs */
141 #define mmIP_DISCOVERY_VERSION 0x16A00
142 #define mmRCC_CONFIG_MEMSIZE 0xde3
143 #define mmMP0_SMN_C2PMSG_33 0x16061
144 #define mmMM_INDEX 0x0
145 #define mmMM_INDEX_HI 0x6
146 #define mmMM_DATA 0x1
147
148 #define mmDRIVER_SCRATCH_0 0x94
149 #define mmDRIVER_SCRATCH_1 0x95
150 #define mmDRIVER_SCRATCH_2 0x96
151
152 struct ip_discovery_top {
153 struct kobject kobj;
154 struct kset die_kset;
155 struct pci_dev *pdev;
156 struct amdgpu_device *adev;
157 uint8_t *discovery_bin;
158 uint32_t bin_size;
159 bool standalone_mode;
160 };
161
162 /* List to track early-initialized ip_discovery_top entries */
163 struct early_ip_discovery {
164 struct list_head list;
165 struct pci_dev *pdev;
166 struct ip_discovery_top *ip_top;
167 };
168
169 static LIST_HEAD(early_ip_discovery_list);
170 static DEFINE_MUTEX(early_ip_discovery_mutex);
171
172 static const char *hw_id_names[HW_ID_MAX] = {
173 [MP1_HWID] = "MP1",
174 [MP2_HWID] = "MP2",
175 [THM_HWID] = "THM",
176 [SMUIO_HWID] = "SMUIO",
177 [FUSE_HWID] = "FUSE",
178 [CLKA_HWID] = "CLKA",
179 [PWR_HWID] = "PWR",
180 [GC_HWID] = "GC",
181 [UVD_HWID] = "UVD",
182 [AUDIO_AZ_HWID] = "AUDIO_AZ",
183 [ACP_HWID] = "ACP",
184 [DCI_HWID] = "DCI",
185 [DMU_HWID] = "DMU",
186 [DCO_HWID] = "DCO",
187 [DIO_HWID] = "DIO",
188 [XDMA_HWID] = "XDMA",
189 [DCEAZ_HWID] = "DCEAZ",
190 [DAZ_HWID] = "DAZ",
191 [SDPMUX_HWID] = "SDPMUX",
192 [NTB_HWID] = "NTB",
193 [IOHC_HWID] = "IOHC",
194 [L2IMU_HWID] = "L2IMU",
195 [VCE_HWID] = "VCE",
196 [MMHUB_HWID] = "MMHUB",
197 [ATHUB_HWID] = "ATHUB",
198 [DBGU_NBIO_HWID] = "DBGU_NBIO",
199 [DFX_HWID] = "DFX",
200 [DBGU0_HWID] = "DBGU0",
201 [DBGU1_HWID] = "DBGU1",
202 [OSSSYS_HWID] = "OSSSYS",
203 [HDP_HWID] = "HDP",
204 [SDMA0_HWID] = "SDMA0",
205 [SDMA1_HWID] = "SDMA1",
206 [SDMA2_HWID] = "SDMA2",
207 [SDMA3_HWID] = "SDMA3",
208 [LSDMA_HWID] = "LSDMA",
209 [ISP_HWID] = "ISP",
210 [DBGU_IO_HWID] = "DBGU_IO",
211 [DF_HWID] = "DF",
212 [CLKB_HWID] = "CLKB",
213 [FCH_HWID] = "FCH",
214 [DFX_DAP_HWID] = "DFX_DAP",
215 [L1IMU_PCIE_HWID] = "L1IMU_PCIE",
216 [L1IMU_NBIF_HWID] = "L1IMU_NBIF",
217 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR",
218 [L1IMU3_HWID] = "L1IMU3",
219 [L1IMU4_HWID] = "L1IMU4",
220 [L1IMU5_HWID] = "L1IMU5",
221 [L1IMU6_HWID] = "L1IMU6",
222 [L1IMU7_HWID] = "L1IMU7",
223 [L1IMU8_HWID] = "L1IMU8",
224 [L1IMU9_HWID] = "L1IMU9",
225 [L1IMU10_HWID] = "L1IMU10",
226 [L1IMU11_HWID] = "L1IMU11",
227 [L1IMU12_HWID] = "L1IMU12",
228 [L1IMU13_HWID] = "L1IMU13",
229 [L1IMU14_HWID] = "L1IMU14",
230 [L1IMU15_HWID] = "L1IMU15",
231 [WAFLC_HWID] = "WAFLC",
232 [FCH_USB_PD_HWID] = "FCH_USB_PD",
233 [PCIE_HWID] = "PCIE",
234 [PCS_HWID] = "PCS",
235 [DDCL_HWID] = "DDCL",
236 [SST_HWID] = "SST",
237 [IOAGR_HWID] = "IOAGR",
238 [NBIF_HWID] = "NBIF",
239 [IOAPIC_HWID] = "IOAPIC",
240 [SYSTEMHUB_HWID] = "SYSTEMHUB",
241 [NTBCCP_HWID] = "NTBCCP",
242 [UMC_HWID] = "UMC",
243 [SATA_HWID] = "SATA",
244 [USB_HWID] = "USB",
245 [CCXSEC_HWID] = "CCXSEC",
246 [XGMI_HWID] = "XGMI",
247 [XGBE_HWID] = "XGBE",
248 [MP0_HWID] = "MP0",
249 [VPE_HWID] = "VPE",
250 [UMSCH_HWID] = "UMSCH",
251 [ATU_HWID] = "ATU",
252 [AIGC_HWID] = "AIGC",
253 };
254
255 static int hw_id_map[MAX_HWIP] = {
256 [GC_HWIP] = GC_HWID,
257 [HDP_HWIP] = HDP_HWID,
258 [SDMA0_HWIP] = SDMA0_HWID,
259 [SDMA1_HWIP] = SDMA1_HWID,
260 [SDMA2_HWIP] = SDMA2_HWID,
261 [SDMA3_HWIP] = SDMA3_HWID,
262 [LSDMA_HWIP] = LSDMA_HWID,
263 [MMHUB_HWIP] = MMHUB_HWID,
264 [ATHUB_HWIP] = ATHUB_HWID,
265 [NBIO_HWIP] = NBIF_HWID,
266 [MP0_HWIP] = MP0_HWID,
267 [MP1_HWIP] = MP1_HWID,
268 [UVD_HWIP] = UVD_HWID,
269 [VCE_HWIP] = VCE_HWID,
270 [DF_HWIP] = DF_HWID,
271 [DCE_HWIP] = DMU_HWID,
272 [OSSSYS_HWIP] = OSSSYS_HWID,
273 [SMUIO_HWIP] = SMUIO_HWID,
274 [PWR_HWIP] = PWR_HWID,
275 [NBIF_HWIP] = NBIF_HWID,
276 [THM_HWIP] = THM_HWID,
277 [CLK_HWIP] = CLKA_HWID,
278 [UMC_HWIP] = UMC_HWID,
279 [XGMI_HWIP] = XGMI_HWID,
280 [DCI_HWIP] = DCI_HWID,
281 [PCIE_HWIP] = PCIE_HWID,
282 [VPE_HWIP] = VPE_HWID,
283 [UMSCH_HWIP] = UMSCH_HWID,
284 [ISP_HWIP] = ISP_HWID,
285 [ATU_HWIP] = ATU_HWID,
286 };
287
amdgpu_discovery_get_tmr_info(struct amdgpu_device * adev,bool * is_tmr_in_sysmem)288 static int amdgpu_discovery_get_tmr_info(struct amdgpu_device *adev,
289 bool *is_tmr_in_sysmem)
290 {
291 u64 vram_size, tmr_offset, tmr_size;
292 u32 msg, tmr_offset_lo, tmr_offset_hi;
293 int i, ret;
294
295 if (!amdgpu_sriov_vf(adev)) {
296 /* It can take up to two second for IFWI init to complete on some dGPUs,
297 * but generally it should be in the 60-100ms range. Normally this starts
298 * as soon as the device gets power so by the time the OS loads this has long
299 * completed. However, when a card is hotplugged via e.g., USB4, we need to
300 * wait for this to complete. Once the C2PMSG is updated, we can
301 * continue.
302 */
303
304 for (i = 0; i < 2000; i++) {
305 msg = RREG32(mmMP0_SMN_C2PMSG_33);
306 if (msg & 0x80000000)
307 break;
308 msleep(1);
309 }
310 }
311
312 vram_size = RREG32(mmRCC_CONFIG_MEMSIZE);
313 if (vram_size == U32_MAX)
314 return -ENXIO;
315 else if (!vram_size)
316 *is_tmr_in_sysmem = true;
317 else
318 *is_tmr_in_sysmem = false;
319
320 /* init the default tmr size and offset */
321 adev->discovery.size = DISCOVERY_TMR_SIZE;
322 if (vram_size)
323 adev->discovery.offset = (vram_size << 20) - DISCOVERY_TMR_OFFSET;
324
325 if (amdgpu_sriov_vf(adev)) {
326 if (adev->virt.is_dynamic_crit_regn_enabled) {
327 adev->discovery.offset =
328 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].offset;
329 adev->discovery.size =
330 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].size_kb << 10;
331 if (!adev->discovery.size)
332 return -EINVAL;
333 } else {
334 goto out;
335 }
336 } else {
337 if (adev->discovery.offset) {
338 u32 signature;
339
340 /* If VRAM holds a valid discovery signature at the default
341 * discovery offset, use it as-is.
342 */
343 amdgpu_device_vram_access(adev, adev->discovery.offset,
344 &signature, sizeof(signature),
345 false);
346 if (le32_to_cpu(signature) == BINARY_SIGNATURE)
347 goto out;
348 }
349
350 tmr_size = RREG32(mmDRIVER_SCRATCH_2);
351 if (tmr_size) {
352 /* It's preferred to transition to PSP mailbox reg interface
353 * for both bare-metal and passthrough if available */
354 adev->discovery.size = (u32)tmr_size;
355 tmr_offset_lo = RREG32(mmDRIVER_SCRATCH_0);
356 tmr_offset_hi = RREG32(mmDRIVER_SCRATCH_1);
357 adev->discovery.offset = ((u64)le32_to_cpu(tmr_offset_hi) << 32 |
358 le32_to_cpu(tmr_offset_lo));
359 } else if (!vram_size) {
360 /* fall back to apci approach to query tmr offset if vram_size is 0 */
361 ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size);
362 if (ret)
363 return ret;
364 adev->discovery.size = DISCOVERY_TMR_SIZE;
365 adev->discovery.offset = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET;
366 }
367 }
368 out:
369 adev->discovery.bin = kzalloc(adev->discovery.size, GFP_KERNEL);
370 if (!adev->discovery.bin)
371 return -ENOMEM;
372 adev->discovery.debugfs_blob.data = adev->discovery.bin;
373 adev->discovery.debugfs_blob.size = adev->discovery.size;
374
375 return 0;
376 }
377
amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device * adev,uint8_t * binary)378 static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary)
379 {
380 void *discv_regn;
381
382 /* This region is read-only and reserved from system use */
383 discv_regn = memremap(adev->discovery.offset, adev->discovery.size, MEMREMAP_WC);
384 if (discv_regn) {
385 memcpy(binary, discv_regn, adev->discovery.size);
386 memunmap(discv_regn);
387 return 0;
388 }
389
390 return -ENOENT;
391 }
392
393 #define IP_DISCOVERY_V2 2
394 #define IP_DISCOVERY_V4 4
395
amdgpu_discovery_read_binary_from_mem(struct amdgpu_device * adev,uint8_t * binary,bool is_tmr_in_sysmem)396 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev,
397 uint8_t *binary,
398 bool is_tmr_in_sysmem)
399 {
400 int ret = 0;
401
402 if (!is_tmr_in_sysmem) {
403 if (amdgpu_sriov_vf(adev) &&
404 amdgpu_sriov_xgmi_connected_to_cpu(adev)) {
405 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary);
406 } else {
407 amdgpu_device_vram_access(adev, adev->discovery.offset,
408 (uint32_t *)binary,
409 adev->discovery.size, false);
410 adev->discovery.reserve_tmr = true;
411 }
412 } else {
413 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary);
414 }
415
416 return ret;
417 }
418
amdgpu_discovery_read_binary_from_file(struct amdgpu_device * adev,uint8_t * binary,const char * fw_name)419 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev,
420 uint8_t *binary,
421 const char *fw_name)
422 {
423 const struct firmware *fw;
424 int r;
425
426 r = firmware_request_nowarn(&fw, fw_name, adev->dev);
427 if (r) {
428 if (amdgpu_discovery == 2)
429 dev_err(adev->dev, "can't load firmware \"%s\"\n", fw_name);
430 else
431 drm_info(&adev->ddev, "Optional firmware \"%s\" was not found\n", fw_name);
432 return r;
433 }
434
435 if (fw->size > adev->discovery.size) {
436 dev_err(adev->dev,
437 "ip discovery firmware \"%s\" too large (%zu > %u)\n",
438 fw_name, fw->size, adev->discovery.size);
439 release_firmware(fw);
440 return -EINVAL;
441 }
442
443 /* Ensure the firmware is at least large enough to contain the
444 * binary header fields.
445 */
446 if (fw->size < offsetof(struct binary_header, binary_size) +
447 sizeof(((struct binary_header *)0)->binary_size)) {
448 dev_err(adev->dev,
449 "ip discovery firmware \"%s\" too small (%zu)\n",
450 fw_name, fw->size);
451 release_firmware(fw);
452 return -EINVAL;
453 }
454
455 memcpy((u8 *)binary, (u8 *)fw->data, fw->size);
456 release_firmware(fw);
457
458 return 0;
459 }
460
amdgpu_discovery_calculate_checksum(uint8_t * data,uint32_t size)461 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size)
462 {
463 uint16_t checksum = 0;
464 int i;
465
466 for (i = 0; i < size; i++)
467 checksum += data[i];
468
469 return checksum;
470 }
471
amdgpu_discovery_verify_checksum(struct amdgpu_device * adev,uint8_t * data,uint32_t size,uint16_t expected)472 static inline bool amdgpu_discovery_verify_checksum(struct amdgpu_device *adev,
473 uint8_t *data, uint32_t size,
474 uint16_t expected)
475 {
476 uint16_t calculated;
477
478 calculated = amdgpu_discovery_calculate_checksum(data, size);
479
480 if (calculated != expected) {
481 dev_err(adev->dev, "Discovery checksum failed: calc 0x%04x != exp 0x%04x, size %u.\n",
482 calculated, expected, size);
483 return false;
484 }
485
486 return true;
487 }
488
amdgpu_discovery_verify_binary_signature(uint8_t * binary)489 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary)
490 {
491 struct binary_header *bhdr;
492 bhdr = (struct binary_header *)binary;
493
494 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE);
495 }
496
amdgpu_discovery_harvest_config_quirk(struct amdgpu_device * adev)497 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev)
498 {
499 /*
500 * So far, apply this quirk only on those Navy Flounder boards which
501 * have a bad harvest table of VCN config.
502 */
503 if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) &&
504 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 2))) {
505 switch (adev->pdev->revision) {
506 case 0xC1:
507 case 0xC2:
508 case 0xC3:
509 case 0xC5:
510 case 0xC7:
511 case 0xCF:
512 case 0xDF:
513 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
514 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1;
515 break;
516 default:
517 break;
518 }
519 }
520 }
521
amdgpu_discovery_verify_npsinfo(struct amdgpu_device * adev,struct table_info * info)522 static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev,
523 struct table_info *info)
524 {
525 uint8_t *discovery_bin = adev->discovery.bin;
526 uint16_t checksum;
527 uint16_t offset;
528
529 offset = le16_to_cpu(info->offset);
530 checksum = le16_to_cpu(info->checksum);
531
532 struct nps_info_header *nhdr =
533 (struct nps_info_header *)(discovery_bin + offset);
534
535 if (le32_to_cpu(nhdr->table_id) != NPS_INFO_TABLE_ID) {
536 dev_dbg(adev->dev, "invalid ip discovery nps info table id\n");
537 return -EINVAL;
538 }
539
540 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset,
541 le32_to_cpu(nhdr->size_bytes),
542 checksum)) {
543 dev_dbg(adev->dev, "invalid nps info data table checksum\n");
544 return -EINVAL;
545 }
546
547 return 0;
548 }
549
amdgpu_discovery_get_fw_name(struct amdgpu_device * adev)550 static const char *amdgpu_discovery_get_fw_name(struct amdgpu_device *adev)
551 {
552 if (amdgpu_discovery == 2) {
553 /* Assume there is valid discovery TMR in VRAM even if binary is sideloaded */
554 adev->discovery.reserve_tmr = true;
555 return "amdgpu/ip_discovery.bin";
556 }
557
558 switch (adev->asic_type) {
559 case CHIP_VEGA10:
560 return "amdgpu/vega10_ip_discovery.bin";
561 case CHIP_VEGA12:
562 return "amdgpu/vega12_ip_discovery.bin";
563 case CHIP_RAVEN:
564 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
565 return "amdgpu/raven2_ip_discovery.bin";
566 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
567 return "amdgpu/picasso_ip_discovery.bin";
568 else
569 return "amdgpu/raven_ip_discovery.bin";
570 case CHIP_VEGA20:
571 return "amdgpu/vega20_ip_discovery.bin";
572 case CHIP_ARCTURUS:
573 return "amdgpu/arcturus_ip_discovery.bin";
574 case CHIP_ALDEBARAN:
575 return "amdgpu/aldebaran_ip_discovery.bin";
576 default:
577 return NULL;
578 }
579 }
580
581 static struct table_info *
amdgpu_discovery_get_table_info_from_bin(uint8_t * discovery_bin,uint16_t table_id)582 amdgpu_discovery_get_table_info_from_bin(uint8_t *discovery_bin,
583 uint16_t table_id)
584 {
585 struct binary_header *bhdr = (struct binary_header *)discovery_bin;
586 struct binary_header_v2 *bhdrv2;
587
588 switch (bhdr->version_major) {
589 case 2:
590 bhdrv2 = (struct binary_header_v2 *)discovery_bin;
591 return &bhdrv2->table_list[table_id];
592 case 1:
593 case 0:
594 return &bhdr->table_list[table_id];
595 default:
596 return NULL;
597 }
598 }
599
amdgpu_discovery_get_table_info(struct amdgpu_device * adev,struct table_info ** info,uint16_t table_id)600 static int amdgpu_discovery_get_table_info(struct amdgpu_device *adev,
601 struct table_info **info,
602 uint16_t table_id)
603 {
604 struct binary_header *bhdr =
605 (struct binary_header *)adev->discovery.bin;
606
607 *info = amdgpu_discovery_get_table_info_from_bin(adev->discovery.bin,
608 table_id);
609 if (!*info) {
610 dev_err(adev->dev, "Invalid ip discovery table version %d\n",
611 bhdr->version_major);
612 return -EINVAL;
613 }
614
615 return 0;
616 }
617
amdgpu_discovery_table_check(struct amdgpu_device * adev,uint8_t * discovery_bin,uint16_t table_id)618 static int amdgpu_discovery_table_check(struct amdgpu_device *adev,
619 uint8_t *discovery_bin,
620 uint16_t table_id)
621 {
622 int r, act_val, exp_val, table_size;
623 uint16_t offset, checksum;
624 struct table_info *info;
625 bool check_table = true;
626 char *table_name;
627
628 r = amdgpu_discovery_get_table_info(adev, &info, table_id);
629 if (r)
630 return r;
631 offset = le16_to_cpu(info->offset);
632 checksum = le16_to_cpu(info->checksum);
633
634 switch (table_id) {
635 case IP_DISCOVERY: {
636 struct ip_discovery_header *ihdr =
637 (struct ip_discovery_header *)(discovery_bin + offset);
638 act_val = le32_to_cpu(ihdr->signature);
639 exp_val = DISCOVERY_TABLE_SIGNATURE;
640 table_size = le16_to_cpu(ihdr->size);
641 table_name = "data table";
642 break;
643 }
644 case GC: {
645 struct gpu_info_header *ghdr =
646 (struct gpu_info_header *)(discovery_bin + offset);
647 act_val = le32_to_cpu(ghdr->table_id);
648 exp_val = GC_TABLE_ID;
649 table_size = le16_to_cpu(ghdr->size);
650 table_name = "gc table";
651 break;
652 }
653 case HARVEST_INFO: {
654 struct harvest_info_header *hhdr =
655 (struct harvest_info_header *)(discovery_bin + offset);
656 act_val = le32_to_cpu(hhdr->signature);
657 exp_val = HARVEST_TABLE_SIGNATURE;
658 table_size = sizeof(struct harvest_table);
659 table_name = "harvest table";
660 break;
661 }
662 case VCN_INFO: {
663 struct vcn_info_header *vhdr =
664 (struct vcn_info_header *)(discovery_bin + offset);
665 act_val = le32_to_cpu(vhdr->table_id);
666 exp_val = VCN_INFO_TABLE_ID;
667 table_size = le32_to_cpu(vhdr->size_bytes);
668 table_name = "vcn table";
669 break;
670 }
671 case MALL_INFO: {
672 struct mall_info_header *mhdr =
673 (struct mall_info_header *)(discovery_bin + offset);
674 act_val = le32_to_cpu(mhdr->table_id);
675 exp_val = MALL_INFO_TABLE_ID;
676 table_size = le32_to_cpu(mhdr->size_bytes);
677 table_name = "mall table";
678 check_table = false;
679 break;
680 }
681 default:
682 dev_err(adev->dev, "invalid ip discovery table id %d specified\n", table_id);
683 check_table = false;
684 break;
685 }
686
687 if (check_table && offset) {
688 if (act_val != exp_val) {
689 dev_err(adev->dev, "invalid ip discovery %s signature\n", table_name);
690 return -EINVAL;
691 }
692
693 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset,
694 table_size, checksum)) {
695 dev_err(adev->dev, "invalid ip discovery %s checksum\n", table_name);
696 return -EINVAL;
697 }
698 }
699
700 return 0;
701 }
702
amdgpu_discovery_init(struct amdgpu_device * adev)703 static int amdgpu_discovery_init(struct amdgpu_device *adev)
704 {
705 struct binary_header *bhdr;
706 uint8_t *discovery_bin;
707 const char *fw_name;
708 uint16_t offset;
709 uint16_t size;
710 uint16_t checksum;
711 uint16_t table_id;
712 bool is_tmr_in_sysmem;
713 int r;
714
715 r = amdgpu_discovery_get_tmr_info(adev, &is_tmr_in_sysmem);
716 if (r)
717 return r;
718
719 discovery_bin = adev->discovery.bin;
720 /* Read from file if it is the preferred option */
721 fw_name = amdgpu_discovery_get_fw_name(adev);
722 if (fw_name != NULL) {
723 drm_dbg(&adev->ddev, "use ip discovery information from file");
724 r = amdgpu_discovery_read_binary_from_file(adev, discovery_bin,
725 fw_name);
726 if (r)
727 goto out;
728 } else {
729 drm_dbg(&adev->ddev, "use ip discovery information from memory");
730 r = amdgpu_discovery_read_binary_from_mem(adev, discovery_bin,
731 is_tmr_in_sysmem);
732 if (r)
733 goto out;
734 }
735
736 /* check the ip discovery binary signature */
737 if (!amdgpu_discovery_verify_binary_signature(discovery_bin)) {
738 dev_err(adev->dev,
739 "get invalid ip discovery binary signature\n");
740 r = -EINVAL;
741 goto out;
742 }
743
744 bhdr = (struct binary_header *)discovery_bin;
745
746 offset = offsetof(struct binary_header, binary_checksum) +
747 sizeof(bhdr->binary_checksum);
748 size = le16_to_cpu(bhdr->binary_size) - offset;
749 checksum = le16_to_cpu(bhdr->binary_checksum);
750
751 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, size,
752 checksum)) {
753 dev_err(adev->dev, "invalid ip discovery binary checksum\n");
754 r = -EINVAL;
755 goto out;
756 }
757
758 for (table_id = 0; table_id <= MALL_INFO; table_id++) {
759 r = amdgpu_discovery_table_check(adev, discovery_bin, table_id);
760 if (r)
761 goto out;
762 }
763
764 return 0;
765
766 out:
767 kfree(adev->discovery.bin);
768 adev->discovery.bin = NULL;
769 if ((amdgpu_discovery != 2) &&
770 (RREG32(mmIP_DISCOVERY_VERSION) == 4))
771 amdgpu_ras_query_boot_status(adev, 4);
772 return r;
773 }
774
amdgpu_discovery_fini(struct amdgpu_device * adev)775 void amdgpu_discovery_fini(struct amdgpu_device *adev)
776 {
777 if (adev->discovery.ip_top && !adev->discovery.ip_top->standalone_mode)
778 amdgpu_discovery_sysfs_fini(adev);
779
780 kfree(adev->discovery.bin);
781 adev->discovery.bin = NULL;
782 }
783
amdgpu_discovery_validate_ip(struct amdgpu_device * adev,uint8_t instance,uint16_t hw_id)784 static int amdgpu_discovery_validate_ip(struct amdgpu_device *adev,
785 uint8_t instance, uint16_t hw_id)
786 {
787 if (instance >= HWIP_MAX_INSTANCE) {
788 if (adev)
789 dev_err(adev->dev,
790 "Unexpected instance_number (%d) from ip discovery blob\n",
791 instance);
792 return -EINVAL;
793 }
794 if (hw_id >= HW_ID_MAX) {
795 if (adev)
796 dev_err(adev->dev,
797 "Unexpected hw_id (%d) from ip discovery blob\n",
798 hw_id);
799 return -EINVAL;
800 }
801
802 return 0;
803 }
804
amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device * adev,uint32_t * vcn_harvest_count)805 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev,
806 uint32_t *vcn_harvest_count)
807 {
808 uint8_t *discovery_bin = adev->discovery.bin;
809 struct binary_header *bhdr;
810 struct ip_discovery_header *ihdr;
811 struct die_header *dhdr;
812 struct ip *ip;
813 uint16_t die_offset, ip_offset, num_dies, num_ips;
814 uint16_t hw_id;
815 uint8_t inst;
816 int i, j;
817
818 bhdr = (struct binary_header *)discovery_bin;
819 ihdr = (struct ip_discovery_header
820 *)(discovery_bin +
821 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
822 num_dies = le16_to_cpu(ihdr->num_dies);
823
824 /* scan harvest bit of all IP data structures */
825 for (i = 0; i < num_dies; i++) {
826 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
827 dhdr = (struct die_header *)(discovery_bin + die_offset);
828 num_ips = le16_to_cpu(dhdr->num_ips);
829 ip_offset = die_offset + sizeof(*dhdr);
830
831 for (j = 0; j < num_ips; j++) {
832 ip = (struct ip *)(discovery_bin + ip_offset);
833 inst = ip->number_instance;
834 hw_id = le16_to_cpu(ip->hw_id);
835 if (amdgpu_discovery_validate_ip(adev, inst, hw_id))
836 goto next_ip;
837
838 if (ip->harvest == 1) {
839 switch (hw_id) {
840 case VCN_HWID:
841 (*vcn_harvest_count)++;
842 if (inst == 0) {
843 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
844 adev->vcn.inst_mask &=
845 ~AMDGPU_VCN_HARVEST_VCN0;
846 adev->jpeg.inst_mask &=
847 ~AMDGPU_VCN_HARVEST_VCN0;
848 } else {
849 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
850 adev->vcn.inst_mask &=
851 ~AMDGPU_VCN_HARVEST_VCN1;
852 adev->jpeg.inst_mask &=
853 ~AMDGPU_VCN_HARVEST_VCN1;
854 }
855 break;
856 case DMU_HWID:
857 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
858 break;
859 default:
860 break;
861 }
862 }
863 next_ip:
864 ip_offset += struct_size(ip, base_address,
865 ip->num_base_address);
866 }
867 }
868 }
869
amdgpu_discovery_read_from_harvest_table(struct amdgpu_device * adev,uint32_t * vcn_harvest_count,uint32_t * umc_harvest_count)870 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev,
871 uint32_t *vcn_harvest_count,
872 uint32_t *umc_harvest_count)
873 {
874 uint8_t *discovery_bin = adev->discovery.bin;
875 struct table_info *info;
876 struct harvest_table *harvest_info;
877 u16 offset;
878 int i;
879 u64 umc_harvest_config = 0;
880
881 if (amdgpu_discovery_get_table_info(adev, &info, HARVEST_INFO))
882 return;
883 offset = le16_to_cpu(info->offset);
884
885 if (!offset) {
886 dev_err(adev->dev, "invalid harvest table offset\n");
887 return;
888 }
889
890 harvest_info = (struct harvest_table *)(discovery_bin + offset);
891
892 for (i = 0; i < 32; i++) {
893 u16 hw_id = le16_to_cpu(harvest_info->list[i].hw_id);
894 u8 inst = harvest_info->list[i].number_instance;
895
896 if (hw_id == 0)
897 break;
898
899 if (inst >= 32) {
900 dev_warn(adev->dev,
901 "bogus harvest instance %u for hw_id %u\n",
902 inst, hw_id);
903 continue;
904 }
905
906 switch (hw_id) {
907 case VCN_HWID:
908 (*vcn_harvest_count)++;
909 adev->vcn.harvest_config |= BIT(inst);
910 adev->jpeg.harvest_config |= BIT(inst);
911
912 adev->vcn.inst_mask &= ~BIT(inst);
913 adev->jpeg.inst_mask &= ~BIT(inst);
914 break;
915 case DMU_HWID:
916 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
917 break;
918 case UMC_HWID:
919 umc_harvest_config |= BIT_ULL(inst);
920 (*umc_harvest_count)++;
921 break;
922 case GC_HWID:
923 adev->gfx.xcc_mask &= ~BIT(inst);
924 break;
925 case SDMA0_HWID:
926 adev->sdma.sdma_mask &= ~BIT(inst);
927 break;
928 #if defined(CONFIG_DRM_AMD_ISP)
929 case ISP_HWID:
930 adev->isp.harvest_config |= ~BIT(inst);
931 break;
932 #endif
933 default:
934 break;
935 }
936 }
937
938 adev->umc.active_mask = ((1ULL << adev->umc.node_inst_num) - 1ULL) &
939 ~umc_harvest_config;
940 }
941
942 /* ================================================== */
943
944 struct ip_hw_instance {
945 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */
946
947 int hw_id;
948 u8 num_instance;
949 u8 major, minor, revision;
950 u8 harvest;
951
952 int num_base_addresses;
953 u32 base_addr[] __counted_by(num_base_addresses);
954 };
955
956 struct ip_hw_id {
957 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */
958 int hw_id;
959 };
960
961 struct ip_die_entry {
962 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */
963 u16 num_ips;
964 };
965
966 /* -------------------------------------------------- */
967
968 struct ip_hw_instance_attr {
969 struct attribute attr;
970 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf);
971 };
972
hw_id_show(struct ip_hw_instance * ip_hw_instance,char * buf)973 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf)
974 {
975 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id);
976 }
977
num_instance_show(struct ip_hw_instance * ip_hw_instance,char * buf)978 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf)
979 {
980 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance);
981 }
982
major_show(struct ip_hw_instance * ip_hw_instance,char * buf)983 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf)
984 {
985 return sysfs_emit(buf, "%d\n", ip_hw_instance->major);
986 }
987
minor_show(struct ip_hw_instance * ip_hw_instance,char * buf)988 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf)
989 {
990 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor);
991 }
992
revision_show(struct ip_hw_instance * ip_hw_instance,char * buf)993 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf)
994 {
995 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision);
996 }
997
harvest_show(struct ip_hw_instance * ip_hw_instance,char * buf)998 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf)
999 {
1000 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest);
1001 }
1002
num_base_addresses_show(struct ip_hw_instance * ip_hw_instance,char * buf)1003 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf)
1004 {
1005 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses);
1006 }
1007
base_addr_show(struct ip_hw_instance * ip_hw_instance,char * buf)1008 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf)
1009 {
1010 ssize_t at;
1011 int ii;
1012
1013 for (at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) {
1014 /* Here we satisfy the condition that, at + size <= PAGE_SIZE.
1015 */
1016 if (at + 12 > PAGE_SIZE)
1017 break;
1018 at += sysfs_emit_at(buf, at, "0x%08X\n",
1019 ip_hw_instance->base_addr[ii]);
1020 }
1021
1022 return at;
1023 }
1024
1025 static struct ip_hw_instance_attr ip_hw_attr[] = {
1026 __ATTR_RO(hw_id),
1027 __ATTR_RO(num_instance),
1028 __ATTR_RO(major),
1029 __ATTR_RO(minor),
1030 __ATTR_RO(revision),
1031 __ATTR_RO(harvest),
1032 __ATTR_RO(num_base_addresses),
1033 __ATTR_RO(base_addr),
1034 };
1035
1036 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1];
1037 ATTRIBUTE_GROUPS(ip_hw_instance);
1038
1039 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj)
1040 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr)
1041
ip_hw_instance_attr_show(struct kobject * kobj,struct attribute * attr,char * buf)1042 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj,
1043 struct attribute *attr,
1044 char *buf)
1045 {
1046 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
1047 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr);
1048
1049 if (!ip_hw_attr->show)
1050 return -EIO;
1051
1052 return ip_hw_attr->show(ip_hw_instance, buf);
1053 }
1054
1055 static const struct sysfs_ops ip_hw_instance_sysfs_ops = {
1056 .show = ip_hw_instance_attr_show,
1057 };
1058
ip_hw_instance_release(struct kobject * kobj)1059 static void ip_hw_instance_release(struct kobject *kobj)
1060 {
1061 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
1062
1063 kfree(ip_hw_instance);
1064 }
1065
1066 static const struct kobj_type ip_hw_instance_ktype = {
1067 .release = ip_hw_instance_release,
1068 .sysfs_ops = &ip_hw_instance_sysfs_ops,
1069 .default_groups = ip_hw_instance_groups,
1070 };
1071
1072 /* -------------------------------------------------- */
1073
1074 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset)
1075
ip_hw_id_release(struct kobject * kobj)1076 static void ip_hw_id_release(struct kobject *kobj)
1077 {
1078 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj);
1079
1080 if (!list_empty(&ip_hw_id->hw_id_kset.list))
1081 DRM_ERROR("ip_hw_id->hw_id_kset is not empty");
1082 kfree(ip_hw_id);
1083 }
1084
1085 static const struct kobj_type ip_hw_id_ktype = {
1086 .release = ip_hw_id_release,
1087 .sysfs_ops = &kobj_sysfs_ops,
1088 };
1089
1090 /* -------------------------------------------------- */
1091
1092 static void die_kobj_release(struct kobject *kobj);
1093 static void ip_disc_release(struct kobject *kobj);
1094
1095 struct ip_die_entry_attribute {
1096 struct attribute attr;
1097 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf);
1098 };
1099
1100 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr)
1101
num_ips_show(struct ip_die_entry * ip_die_entry,char * buf)1102 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf)
1103 {
1104 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips);
1105 }
1106
1107 /* If there are more ip_die_entry attrs, other than the number of IPs,
1108 * we can make this intro an array of attrs, and then initialize
1109 * ip_die_entry_attrs in a loop.
1110 */
1111 static struct ip_die_entry_attribute num_ips_attr =
1112 __ATTR_RO(num_ips);
1113
1114 static struct attribute *ip_die_entry_attrs[] = {
1115 &num_ips_attr.attr,
1116 NULL,
1117 };
1118 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */
1119
1120 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset)
1121
ip_die_entry_attr_show(struct kobject * kobj,struct attribute * attr,char * buf)1122 static ssize_t ip_die_entry_attr_show(struct kobject *kobj,
1123 struct attribute *attr,
1124 char *buf)
1125 {
1126 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr);
1127 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
1128
1129 if (!ip_die_entry_attr->show)
1130 return -EIO;
1131
1132 return ip_die_entry_attr->show(ip_die_entry, buf);
1133 }
1134
ip_die_entry_release(struct kobject * kobj)1135 static void ip_die_entry_release(struct kobject *kobj)
1136 {
1137 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
1138
1139 if (!list_empty(&ip_die_entry->ip_kset.list))
1140 DRM_ERROR("ip_die_entry->ip_kset is not empty");
1141 kfree(ip_die_entry);
1142 }
1143
1144 static const struct sysfs_ops ip_die_entry_sysfs_ops = {
1145 .show = ip_die_entry_attr_show,
1146 };
1147
1148 static const struct kobj_type ip_die_entry_ktype = {
1149 .release = ip_die_entry_release,
1150 .sysfs_ops = &ip_die_entry_sysfs_ops,
1151 .default_groups = ip_die_entry_groups,
1152 };
1153
1154 static const struct kobj_type die_kobj_ktype = {
1155 .release = die_kobj_release,
1156 .sysfs_ops = &kobj_sysfs_ops,
1157 };
1158
1159 static const struct kobj_type ip_discovery_ktype = {
1160 .release = ip_disc_release,
1161 .sysfs_ops = &kobj_sysfs_ops,
1162 };
1163
die_kobj_release(struct kobject * kobj)1164 static void die_kobj_release(struct kobject *kobj)
1165 {
1166 struct ip_discovery_top *ip_top = container_of(to_kset(kobj),
1167 struct ip_discovery_top,
1168 die_kset);
1169 if (!list_empty(&ip_top->die_kset.list))
1170 DRM_ERROR("ip_top->die_kset is not empty");
1171 }
1172
ip_disc_release(struct kobject * kobj)1173 static void ip_disc_release(struct kobject *kobj)
1174 {
1175 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top,
1176 kobj);
1177 struct amdgpu_device *adev = ip_top->adev;
1178
1179 /* In standalone mode, discovery_bin is managed by devm and will be
1180 * freed automatically when the PCI device is removed. Do not manually
1181 * free it here to avoid double-free.
1182 */
1183
1184 kfree(ip_top);
1185 if (adev)
1186 adev->discovery.ip_top = NULL;
1187 }
1188
amdgpu_discovery_get_harvest_info(struct amdgpu_device * adev,uint16_t hw_id,uint8_t inst)1189 static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev,
1190 uint16_t hw_id, uint8_t inst)
1191 {
1192 uint8_t harvest = 0;
1193
1194 /* In early init mode (adev == NULL), harvest info is not available */
1195 if (!adev)
1196 return 0;
1197
1198 /* Until a uniform way is figured, get mask based on hwid */
1199 switch (hw_id) {
1200 case VCN_HWID:
1201 /* VCN vs UVD+VCE */
1202 if (!amdgpu_ip_version(adev, VCE_HWIP, 0))
1203 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0;
1204 break;
1205 case DMU_HWID:
1206 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK)
1207 harvest = 0x1;
1208 break;
1209 case UMC_HWID:
1210 /* TODO: It needs another parsing; for now, ignore.*/
1211 break;
1212 case GC_HWID:
1213 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0;
1214 break;
1215 case SDMA0_HWID:
1216 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0;
1217 break;
1218 default:
1219 break;
1220 }
1221
1222 return harvest;
1223 }
1224
amdgpu_discovery_sysfs_ips(struct amdgpu_device * adev,struct ip_discovery_top * ip_top,struct ip_die_entry * ip_die_entry,const size_t _ip_offset,const int num_ips,bool reg_base_64)1225 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev,
1226 struct ip_discovery_top *ip_top,
1227 struct ip_die_entry *ip_die_entry,
1228 const size_t _ip_offset, const int num_ips,
1229 bool reg_base_64)
1230 {
1231 uint8_t *discovery_bin = ip_top->standalone_mode ?
1232 ip_top->discovery_bin :
1233 adev->discovery.bin;
1234 int ii, jj, kk, res;
1235 uint16_t hw_id;
1236 uint8_t inst;
1237
1238 DRM_DEBUG("num_ips:%d", num_ips);
1239
1240 /* Find all IPs of a given HW ID, and add their instance to
1241 * #die/#hw_id/#instance/<attributes>
1242 */
1243 for (ii = 0; ii < HW_ID_MAX; ii++) {
1244 struct ip_hw_id *ip_hw_id = NULL;
1245 size_t ip_offset = _ip_offset;
1246
1247 for (jj = 0; jj < num_ips; jj++) {
1248 struct ip_v4 *ip;
1249 struct ip_hw_instance *ip_hw_instance;
1250
1251 ip = (struct ip_v4 *)(discovery_bin + ip_offset);
1252 inst = ip->instance_number;
1253 hw_id = le16_to_cpu(ip->hw_id);
1254 if (amdgpu_discovery_validate_ip(adev, inst, hw_id) ||
1255 hw_id != ii)
1256 goto next_ip;
1257
1258 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset);
1259
1260 /* We have a hw_id match; register the hw
1261 * block if not yet registered.
1262 */
1263 if (!ip_hw_id) {
1264 ip_hw_id = kzalloc_obj(*ip_hw_id);
1265 if (!ip_hw_id)
1266 return -ENOMEM;
1267 ip_hw_id->hw_id = ii;
1268
1269 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii);
1270 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset;
1271 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype;
1272 res = kset_register(&ip_hw_id->hw_id_kset);
1273 if (res) {
1274 DRM_ERROR("Couldn't register ip_hw_id kset");
1275 kfree(ip_hw_id);
1276 return res;
1277 }
1278 if (hw_id_names[ii]) {
1279 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj,
1280 &ip_hw_id->hw_id_kset.kobj,
1281 hw_id_names[ii]);
1282 if (res) {
1283 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n",
1284 hw_id_names[ii],
1285 kobject_name(&ip_die_entry->ip_kset.kobj));
1286 }
1287 }
1288 }
1289
1290 /* Now register its instance.
1291 */
1292 ip_hw_instance = kzalloc_flex(*ip_hw_instance,
1293 base_addr,
1294 ip->num_base_address);
1295 if (!ip_hw_instance) {
1296 DRM_ERROR("no memory for ip_hw_instance");
1297 return -ENOMEM;
1298 }
1299 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */
1300 ip_hw_instance->num_instance = ip->instance_number;
1301 ip_hw_instance->major = ip->major;
1302 ip_hw_instance->minor = ip->minor;
1303 ip_hw_instance->revision = ip->revision;
1304 ip_hw_instance->harvest =
1305 amdgpu_discovery_get_harvest_info(
1306 adev, ip_hw_instance->hw_id,
1307 ip_hw_instance->num_instance);
1308 ip_hw_instance->num_base_addresses = ip->num_base_address;
1309
1310 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++)
1311 ip_hw_instance->base_addr[kk] = ip->base_address[kk];
1312
1313 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype);
1314 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset;
1315 res = kobject_add(&ip_hw_instance->kobj, NULL,
1316 "%d", ip_hw_instance->num_instance);
1317 next_ip:
1318 if (reg_base_64)
1319 ip_offset += struct_size(ip, base_address_64,
1320 ip->num_base_address);
1321 else
1322 ip_offset += struct_size(ip, base_address,
1323 ip->num_base_address);
1324 }
1325 }
1326
1327 return 0;
1328 }
1329
amdgpu_discovery_sysfs_recurse(struct amdgpu_device * adev,struct ip_discovery_top * ip_top)1330 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev,
1331 struct ip_discovery_top *ip_top)
1332 {
1333 uint8_t *discovery_bin = ip_top->standalone_mode ?
1334 ip_top->discovery_bin :
1335 adev->discovery.bin;
1336 struct table_info *info;
1337 struct ip_discovery_header *ihdr;
1338 struct die_header *dhdr;
1339 struct kset *die_kset = &ip_top->die_kset;
1340 u16 num_dies, die_offset, num_ips;
1341 size_t ip_offset;
1342 int ii, res;
1343
1344 info = amdgpu_discovery_get_table_info_from_bin(discovery_bin,
1345 IP_DISCOVERY);
1346 if (!info)
1347 return -EINVAL;
1348 ihdr = (struct ip_discovery_header
1349 *)(discovery_bin +
1350 le16_to_cpu(info->offset));
1351 num_dies = le16_to_cpu(ihdr->num_dies);
1352
1353 DRM_DEBUG("number of dies: %d\n", num_dies);
1354
1355 for (ii = 0; ii < num_dies; ii++) {
1356 struct ip_die_entry *ip_die_entry;
1357
1358 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset);
1359 dhdr = (struct die_header *)(discovery_bin + die_offset);
1360 num_ips = le16_to_cpu(dhdr->num_ips);
1361 ip_offset = die_offset + sizeof(*dhdr);
1362
1363 /* Add the die to the kset.
1364 *
1365 * dhdr->die_id == ii, which was checked in
1366 * amdgpu_discovery_reg_base_init().
1367 */
1368
1369 ip_die_entry = kzalloc_obj(*ip_die_entry);
1370 if (!ip_die_entry)
1371 return -ENOMEM;
1372
1373 ip_die_entry->num_ips = num_ips;
1374
1375 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id));
1376 ip_die_entry->ip_kset.kobj.kset = die_kset;
1377 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype;
1378 res = kset_register(&ip_die_entry->ip_kset);
1379 if (res) {
1380 DRM_ERROR("Couldn't register ip_die_entry kset");
1381 kfree(ip_die_entry);
1382 return res;
1383 }
1384
1385 amdgpu_discovery_sysfs_ips(adev, ip_top, ip_die_entry, ip_offset,
1386 num_ips, !!ihdr->base_addr_64_bit);
1387 }
1388
1389 return 0;
1390 }
1391
amdgpu_discovery_sysfs_init(struct amdgpu_device * adev)1392 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev)
1393 {
1394 uint8_t *discovery_bin = adev->discovery.bin;
1395 struct ip_discovery_top *ip_top;
1396 struct kset *die_kset;
1397 int res, ii;
1398
1399 if (!discovery_bin)
1400 return -EINVAL;
1401
1402 /* If early init already created sysfs in standalone mode, skip normal init */
1403 if (adev->discovery.ip_top && adev->discovery.ip_top->standalone_mode)
1404 return 0;
1405
1406 ip_top = kzalloc_obj(*ip_top);
1407 if (!ip_top)
1408 return -ENOMEM;
1409
1410 ip_top->adev = adev;
1411
1412 /* Check if ip_discovery already exists before creating.
1413 * This shouldn't normally happen but handle it gracefully.
1414 */
1415 if (adev->dev->kobj.sd) {
1416 struct kernfs_node *existing;
1417
1418 existing = kernfs_find_and_get(adev->dev->kobj.sd, "ip_discovery");
1419 if (existing) {
1420 kernfs_put(existing);
1421 kfree(ip_top);
1422 return 0;
1423 }
1424 }
1425
1426 res = kobject_init_and_add(&ip_top->kobj, &ip_discovery_ktype,
1427 &adev->dev->kobj, "ip_discovery");
1428 if (res) {
1429 DRM_ERROR("Couldn't init and add ip_discovery/");
1430 goto Err;
1431 }
1432
1433 adev->discovery.ip_top = ip_top;
1434
1435 die_kset = &ip_top->die_kset;
1436 kobject_set_name(&die_kset->kobj, "%s", "die");
1437 die_kset->kobj.parent = &ip_top->kobj;
1438 die_kset->kobj.ktype = &die_kobj_ktype;
1439 res = kset_register(&ip_top->die_kset);
1440 if (res) {
1441 DRM_ERROR("Couldn't register die_kset");
1442 goto Err;
1443 }
1444
1445 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++)
1446 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr;
1447 ip_hw_instance_attrs[ii] = NULL;
1448
1449 res = amdgpu_discovery_sysfs_recurse(adev, ip_top);
1450
1451 return res;
1452 Err:
1453 kobject_put(&ip_top->kobj);
1454 return res;
1455 }
1456
1457 /* -------------------------------------------------- */
1458
1459 #define list_to_kobj(el) container_of(el, struct kobject, entry)
1460
amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id * ip_hw_id)1461 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id)
1462 {
1463 struct list_head *el, *tmp;
1464 struct kset *hw_id_kset;
1465
1466 hw_id_kset = &ip_hw_id->hw_id_kset;
1467 spin_lock(&hw_id_kset->list_lock);
1468 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) {
1469 list_del_init(el);
1470 spin_unlock(&hw_id_kset->list_lock);
1471 /* kobject is embedded in ip_hw_instance */
1472 kobject_put(list_to_kobj(el));
1473 spin_lock(&hw_id_kset->list_lock);
1474 }
1475 spin_unlock(&hw_id_kset->list_lock);
1476 kobject_put(&ip_hw_id->hw_id_kset.kobj);
1477 }
1478
amdgpu_discovery_sysfs_die_free(struct ip_die_entry * ip_die_entry)1479 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry)
1480 {
1481 struct list_head *el, *tmp;
1482 struct kset *ip_kset;
1483
1484 ip_kset = &ip_die_entry->ip_kset;
1485 spin_lock(&ip_kset->list_lock);
1486 list_for_each_prev_safe(el, tmp, &ip_kset->list) {
1487 list_del_init(el);
1488 spin_unlock(&ip_kset->list_lock);
1489 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el)));
1490 spin_lock(&ip_kset->list_lock);
1491 }
1492 spin_unlock(&ip_kset->list_lock);
1493 kobject_put(&ip_die_entry->ip_kset.kobj);
1494 }
1495
amdgpu_discovery_sysfs_fini(struct amdgpu_device * adev)1496 void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev)
1497 {
1498 struct ip_discovery_top *ip_top = adev->discovery.ip_top;
1499 struct list_head *el, *tmp;
1500 struct kset *die_kset;
1501
1502 if (!ip_top)
1503 return;
1504
1505 /*
1506 * In standalone mode the sysfs hierarchy is tied to the PCI device
1507 * lifetime and is torn down by amdgpu_discovery_sysfs_early_fini().
1508 * Freeing it here would leave a dangling pointer in the early
1509 * discovery list, causing a use-after-free on driver unbind.
1510 */
1511 if (ip_top->standalone_mode)
1512 return;
1513
1514 adev->discovery.ip_top = NULL;
1515 die_kset = &ip_top->die_kset;
1516 spin_lock(&die_kset->list_lock);
1517 list_for_each_prev_safe(el, tmp, &die_kset->list) {
1518 list_del_init(el);
1519 spin_unlock(&die_kset->list_lock);
1520 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el)));
1521 spin_lock(&die_kset->list_lock);
1522 }
1523 spin_unlock(&die_kset->list_lock);
1524 kobject_put(&ip_top->die_kset.kobj);
1525 kobject_put(&ip_top->kobj);
1526 }
1527
1528 /* devcoredump support */
amdgpu_discovery_dump(struct amdgpu_device * adev,struct drm_printer * p)1529 void amdgpu_discovery_dump(struct amdgpu_device *adev, struct drm_printer *p)
1530 {
1531 struct ip_discovery_top *ip_top = adev->discovery.ip_top;
1532 struct ip_die_entry *ip_die_entry;
1533 struct list_head *el_die, *el_hw_id, *el_hw_inst;
1534 struct ip_hw_id *hw_id;
1535 struct kset *die_kset;
1536 struct ip_hw_instance *ip_inst;
1537 int i = 0, j;
1538
1539 if (!ip_top)
1540 return;
1541
1542 die_kset = &ip_top->die_kset;
1543
1544 drm_printf(p, "\nHW IP Discovery\n");
1545
1546 spin_lock(&die_kset->list_lock);
1547 list_for_each(el_die, &die_kset->list) {
1548 drm_printf(p, "die %d\n", i++);
1549 ip_die_entry = to_ip_die_entry(list_to_kobj(el_die));
1550
1551 list_for_each(el_hw_id, &ip_die_entry->ip_kset.list) {
1552 hw_id = to_ip_hw_id(list_to_kobj(el_hw_id));
1553 drm_printf(p, "hw_id %d %s\n", hw_id->hw_id, hw_id_names[hw_id->hw_id]);
1554
1555 list_for_each(el_hw_inst, &hw_id->hw_id_kset.list) {
1556 ip_inst = to_ip_hw_instance(list_to_kobj(el_hw_inst));
1557 drm_printf(p, "\tinstance %d\n", ip_inst->num_instance);
1558 drm_printf(p, "\tmajor %d\n", ip_inst->major);
1559 drm_printf(p, "\tminor %d\n", ip_inst->minor);
1560 drm_printf(p, "\trevision %d\n", ip_inst->revision);
1561 drm_printf(p, "\tharvest 0x%01X\n", ip_inst->harvest);
1562 drm_printf(p, "\tnum_base_addresses %d\n",
1563 ip_inst->num_base_addresses);
1564 for (j = 0; j < ip_inst->num_base_addresses; j++)
1565 drm_printf(p, "\tbase_addr[%d] 0x%08X\n",
1566 j, ip_inst->base_addr[j]);
1567 }
1568 }
1569 }
1570 spin_unlock(&die_kset->list_lock);
1571 }
1572
amdgpu_discovery_sysfs_early_init(struct amdgpu_device * adev,struct pci_dev * pdev)1573 int amdgpu_discovery_sysfs_early_init(struct amdgpu_device *adev, struct pci_dev *pdev)
1574 {
1575 struct ip_discovery_top *ip_top;
1576 struct early_ip_discovery *early_entry, *tmp;
1577 struct kset *die_kset;
1578 uint8_t *discovery_bin;
1579 int res, ii;
1580
1581 if (!adev || !adev->discovery.bin)
1582 return -EINVAL;
1583
1584 if (adev->discovery.ip_top)
1585 return 0;
1586
1587 mutex_lock(&early_ip_discovery_mutex);
1588 list_for_each_entry_safe(early_entry, tmp, &early_ip_discovery_list, list) {
1589 if (early_entry->pdev == pdev) {
1590 adev->discovery.ip_top = early_entry->ip_top;
1591 early_entry->ip_top->adev = adev;
1592 mutex_unlock(&early_ip_discovery_mutex);
1593 return 0;
1594 }
1595 }
1596 mutex_unlock(&early_ip_discovery_mutex);
1597
1598 discovery_bin = adev->discovery.bin;
1599
1600 early_entry = kzalloc(sizeof(*early_entry), GFP_KERNEL);
1601 if (!early_entry)
1602 return -ENOMEM;
1603
1604 ip_top = kzalloc(sizeof(*ip_top), GFP_KERNEL);
1605 if (!ip_top) {
1606 kfree(early_entry);
1607 return -ENOMEM;
1608 }
1609
1610 ip_top->discovery_bin = devm_kmemdup(&pdev->dev, discovery_bin,
1611 DISCOVERY_TMR_SIZE, GFP_KERNEL);
1612 if (!ip_top->discovery_bin) {
1613 kfree(ip_top);
1614 kfree(early_entry);
1615 return -ENOMEM;
1616 }
1617
1618 ip_top->bin_size = DISCOVERY_TMR_SIZE;
1619 ip_top->pdev = pdev;
1620 ip_top->adev = adev;
1621 ip_top->standalone_mode = true;
1622
1623 /* Check if ip_discovery already exists (from previous probe attempt).
1624 * This can happen if the module was unloaded and reloaded but the
1625 * sysfs persisted (tied to PCI device lifetime).
1626 */
1627 if (pdev->dev.kobj.sd) {
1628 struct kernfs_node *existing;
1629
1630 existing = kernfs_find_and_get(pdev->dev.kobj.sd, "ip_discovery");
1631 if (existing) {
1632 kernfs_put(existing);
1633 kfree(ip_top);
1634 kfree(early_entry);
1635 return 0;
1636 }
1637 }
1638
1639 res = kobject_init_and_add(&ip_top->kobj, &ip_discovery_ktype,
1640 &pdev->dev.kobj, "ip_discovery");
1641 if (res)
1642 goto err_put_kobj;
1643
1644 adev->discovery.ip_top = ip_top;
1645
1646 die_kset = &ip_top->die_kset;
1647 kobject_set_name(&die_kset->kobj, "%s", "die");
1648 die_kset->kobj.parent = &ip_top->kobj;
1649 die_kset->kobj.ktype = &die_kobj_ktype;
1650 res = kset_register(&ip_top->die_kset);
1651 if (res)
1652 goto err_put_die_kset;
1653
1654 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++)
1655 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr;
1656 ip_hw_instance_attrs[ii] = NULL;
1657
1658 res = amdgpu_discovery_sysfs_recurse(NULL, ip_top);
1659 if (res)
1660 goto err_put_die_kset;
1661
1662 early_entry->pdev = pdev;
1663 early_entry->ip_top = ip_top;
1664 mutex_lock(&early_ip_discovery_mutex);
1665 list_add(&early_entry->list, &early_ip_discovery_list);
1666 mutex_unlock(&early_ip_discovery_mutex);
1667
1668 return 0;
1669
1670 err_put_die_kset:
1671 kobject_put(&ip_top->die_kset.kobj);
1672 err_put_kobj:
1673 kobject_put(&ip_top->kobj);
1674 kfree(early_entry);
1675 adev->discovery.ip_top = NULL;
1676 return res;
1677 }
1678
amdgpu_discovery_sysfs_early_fini(struct pci_dev * pdev)1679 void amdgpu_discovery_sysfs_early_fini(struct pci_dev *pdev)
1680 {
1681 struct early_ip_discovery *entry, *tmp_entry;
1682 struct ip_discovery_top *ip_top = NULL;
1683 struct list_head *el, *tmp;
1684 struct kset *die_kset;
1685
1686 /* Find the entry in our tracking list */
1687 mutex_lock(&early_ip_discovery_mutex);
1688 list_for_each_entry_safe(entry, tmp_entry, &early_ip_discovery_list, list) {
1689 if (entry->pdev == pdev) {
1690 ip_top = entry->ip_top;
1691 list_del(&entry->list);
1692 kfree(entry);
1693 break;
1694 }
1695 }
1696 mutex_unlock(&early_ip_discovery_mutex);
1697
1698 if (!ip_top)
1699 return;
1700
1701 /* Clean up sysfs hierarchy */
1702 die_kset = &ip_top->die_kset;
1703
1704 spin_lock(&die_kset->list_lock);
1705 list_for_each_prev_safe(el, tmp, &die_kset->list) {
1706 list_del_init(el);
1707 spin_unlock(&die_kset->list_lock);
1708 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el)));
1709 spin_lock(&die_kset->list_lock);
1710 }
1711 spin_unlock(&die_kset->list_lock);
1712
1713 kobject_put(&ip_top->die_kset.kobj);
1714 kobject_put(&ip_top->kobj);
1715 /* ip_top itself will be freed by kobject_put via ip_disc_release */
1716 }
1717
1718 /* ================================================== */
1719
amdgpu_discovery_reg_base_init(struct amdgpu_device * adev)1720 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
1721 {
1722 uint8_t num_base_address, subrev, variant;
1723 struct table_info *info;
1724 struct ip_discovery_header *ihdr;
1725 struct die_header *dhdr;
1726 uint8_t *discovery_bin;
1727 struct ip_v4 *ip;
1728 uint16_t die_offset;
1729 uint16_t ip_offset;
1730 uint16_t num_dies;
1731 uint32_t wafl_ver;
1732 uint16_t num_ips;
1733 uint16_t hw_id;
1734 uint8_t inst;
1735 int hw_ip;
1736 int i, j, k;
1737 int r;
1738
1739 r = amdgpu_discovery_init(adev);
1740 if (r)
1741 return r;
1742
1743 amdgpu_discovery_sysfs_early_init(adev, adev->pdev);
1744
1745 discovery_bin = adev->discovery.bin;
1746 wafl_ver = 0;
1747 adev->gfx.xcc_mask = 0;
1748 adev->sdma.sdma_mask = 0;
1749 adev->vcn.inst_mask = 0;
1750 adev->jpeg.inst_mask = 0;
1751 r = amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY);
1752 if (r)
1753 return r;
1754 ihdr = (struct ip_discovery_header
1755 *)(discovery_bin +
1756 le16_to_cpu(info->offset));
1757 num_dies = le16_to_cpu(ihdr->num_dies);
1758
1759 DRM_DEBUG("number of dies: %d\n", num_dies);
1760
1761 for (i = 0; i < num_dies; i++) {
1762 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
1763 dhdr = (struct die_header *)(discovery_bin + die_offset);
1764 num_ips = le16_to_cpu(dhdr->num_ips);
1765 ip_offset = die_offset + sizeof(*dhdr);
1766
1767 if (le16_to_cpu(dhdr->die_id) != i) {
1768 DRM_ERROR("invalid die id %d, expected %d\n",
1769 le16_to_cpu(dhdr->die_id), i);
1770 return -EINVAL;
1771 }
1772
1773 DRM_DEBUG("number of hardware IPs on die%d: %d\n",
1774 le16_to_cpu(dhdr->die_id), num_ips);
1775
1776 for (j = 0; j < num_ips; j++) {
1777 ip = (struct ip_v4 *)(discovery_bin + ip_offset);
1778
1779 inst = ip->instance_number;
1780 hw_id = le16_to_cpu(ip->hw_id);
1781 if (amdgpu_discovery_validate_ip(adev, inst, hw_id))
1782 goto next_ip;
1783
1784 num_base_address = ip->num_base_address;
1785
1786 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n",
1787 hw_id_names[le16_to_cpu(ip->hw_id)],
1788 le16_to_cpu(ip->hw_id),
1789 ip->instance_number,
1790 ip->major, ip->minor,
1791 ip->revision);
1792
1793 if (le16_to_cpu(ip->hw_id) == VCN_HWID) {
1794 /* Bit [5:0]: original revision value
1795 * Bit [7:6]: en/decode capability:
1796 * 0b00 : VCN function normally
1797 * 0b10 : encode is disabled
1798 * 0b01 : decode is disabled
1799 */
1800 if (adev->vcn.num_vcn_inst <
1801 AMDGPU_MAX_VCN_INSTANCES) {
1802 adev->vcn.inst[adev->vcn.num_vcn_inst].vcn_config =
1803 ip->revision & 0xc0;
1804 adev->vcn.num_vcn_inst++;
1805 adev->vcn.inst_mask |=
1806 (1U << ip->instance_number);
1807 adev->jpeg.inst_mask |=
1808 (1U << ip->instance_number);
1809 } else {
1810 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n",
1811 adev->vcn.num_vcn_inst + 1,
1812 AMDGPU_MAX_VCN_INSTANCES);
1813 }
1814 ip->revision &= ~0xc0;
1815 }
1816 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID ||
1817 le16_to_cpu(ip->hw_id) == SDMA1_HWID ||
1818 le16_to_cpu(ip->hw_id) == SDMA2_HWID ||
1819 le16_to_cpu(ip->hw_id) == SDMA3_HWID) {
1820 if (adev->sdma.num_instances <
1821 AMDGPU_MAX_SDMA_INSTANCES) {
1822 adev->sdma.num_instances++;
1823 adev->sdma.sdma_mask |=
1824 (1U << ip->instance_number);
1825 } else {
1826 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n",
1827 adev->sdma.num_instances + 1,
1828 AMDGPU_MAX_SDMA_INSTANCES);
1829 }
1830 }
1831
1832 if (le16_to_cpu(ip->hw_id) == VPE_HWID) {
1833 if (adev->vpe.num_instances < AMDGPU_MAX_VPE_INSTANCES)
1834 adev->vpe.num_instances++;
1835 else
1836 dev_err(adev->dev, "Too many VPE instances: %d vs %d\n",
1837 adev->vpe.num_instances + 1,
1838 AMDGPU_MAX_VPE_INSTANCES);
1839 }
1840
1841 if (le16_to_cpu(ip->hw_id) == UMC_HWID) {
1842 adev->gmc.num_umc++;
1843 adev->umc.node_inst_num++;
1844 }
1845
1846 if (le16_to_cpu(ip->hw_id) == GC_HWID)
1847 adev->gfx.xcc_mask |=
1848 (1U << ip->instance_number);
1849
1850 if (!wafl_ver && le16_to_cpu(ip->hw_id) == WAFLC_HWID)
1851 wafl_ver = IP_VERSION_FULL(ip->major, ip->minor,
1852 ip->revision, 0, 0);
1853
1854 for (k = 0; k < num_base_address; k++) {
1855 /*
1856 * convert the endianness of base addresses in place,
1857 * so that we don't need to convert them when accessing adev->reg_offset.
1858 */
1859 if (ihdr->base_addr_64_bit)
1860 /* Truncate the 64bit base address from ip discovery
1861 * and only store lower 32bit ip base in reg_offset[].
1862 * Bits > 32 follows ASIC specific format, thus just
1863 * discard them and handle it within specific ASIC.
1864 * By this way reg_offset[] and related helpers can
1865 * stay unchanged.
1866 * The base address is in dwords, thus clear the
1867 * highest 2 bits to store.
1868 */
1869 ip->base_address[k] =
1870 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF;
1871 else
1872 ip->base_address[k] = le32_to_cpu(ip->base_address[k]);
1873 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]);
1874 }
1875
1876 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) {
1877 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) &&
1878 hw_id_map[hw_ip] != 0) {
1879 DRM_DEBUG("set register base offset for %s\n",
1880 hw_id_names[le16_to_cpu(ip->hw_id)]);
1881 adev->reg_offset[hw_ip][ip->instance_number] =
1882 ip->base_address;
1883 /* Instance support is somewhat inconsistent.
1884 * SDMA is a good example. Sienna cichlid has 4 total
1885 * SDMA instances, each enumerated separately (HWIDs
1886 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances,
1887 * but they are enumerated as multiple instances of the
1888 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another
1889 * example. On most chips there are multiple instances
1890 * with the same HWID.
1891 */
1892
1893 if (ihdr->version < 3) {
1894 subrev = 0;
1895 variant = 0;
1896 } else {
1897 subrev = ip->sub_revision;
1898 variant = ip->variant;
1899 }
1900
1901 adev->ip_versions[hw_ip]
1902 [ip->instance_number] =
1903 IP_VERSION_FULL(ip->major,
1904 ip->minor,
1905 ip->revision,
1906 variant,
1907 subrev);
1908 }
1909 }
1910
1911 next_ip:
1912 if (ihdr->base_addr_64_bit)
1913 ip_offset += struct_size(ip, base_address_64, ip->num_base_address);
1914 else
1915 ip_offset += struct_size(ip, base_address, ip->num_base_address);
1916 }
1917 }
1918
1919 if (wafl_ver && !adev->ip_versions[XGMI_HWIP][0])
1920 adev->ip_versions[XGMI_HWIP][0] = wafl_ver;
1921
1922 return 0;
1923 }
1924
amdgpu_discovery_harvest_ip(struct amdgpu_device * adev)1925 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
1926 {
1927 uint8_t *discovery_bin = adev->discovery.bin;
1928 struct ip_discovery_header *ihdr;
1929 struct table_info *info;
1930 int vcn_harvest_count = 0;
1931 int umc_harvest_count = 0;
1932 uint16_t ihdr_ver;
1933
1934 if (amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY))
1935 return;
1936 ihdr = (struct ip_discovery_header *)(discovery_bin +
1937 le16_to_cpu(info->offset));
1938 ihdr_ver = le16_to_cpu(ihdr->version);
1939 /*
1940 * Harvest table does not fit Navi1x and legacy GPUs,
1941 * so read harvest bit per IP data structure to set
1942 * harvest configuration.
1943 */
1944 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 2, 0) &&
1945 ihdr_ver <= 2) {
1946 if ((adev->pdev->device == 0x731E &&
1947 (adev->pdev->revision == 0xC6 ||
1948 adev->pdev->revision == 0xC7)) ||
1949 (adev->pdev->device == 0x7340 &&
1950 adev->pdev->revision == 0xC9) ||
1951 (adev->pdev->device == 0x7360 &&
1952 adev->pdev->revision == 0xC7))
1953 amdgpu_discovery_read_harvest_bit_per_ip(adev,
1954 &vcn_harvest_count);
1955 } else {
1956 amdgpu_discovery_read_from_harvest_table(adev,
1957 &vcn_harvest_count,
1958 &umc_harvest_count);
1959 }
1960
1961 amdgpu_discovery_harvest_config_quirk(adev);
1962
1963 if (vcn_harvest_count == adev->vcn.num_vcn_inst) {
1964 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
1965 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
1966 }
1967
1968 if (umc_harvest_count < adev->gmc.num_umc) {
1969 adev->gmc.num_umc -= umc_harvest_count;
1970 }
1971 }
1972
1973 union gc_info {
1974 struct gc_info_v1_0 v1;
1975 struct gc_info_v1_1 v1_1;
1976 struct gc_info_v1_2 v1_2;
1977 struct gc_info_v1_3 v1_3;
1978 struct gc_info_v2_0 v2;
1979 struct gc_info_v2_1 v2_1;
1980 };
1981
amdgpu_discovery_get_gfx_info(struct amdgpu_device * adev)1982 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
1983 {
1984 uint8_t *discovery_bin = adev->discovery.bin;
1985 struct table_info *info;
1986 union gc_info *gc_info;
1987 u16 offset;
1988
1989 if (!discovery_bin) {
1990 DRM_ERROR("ip discovery uninitialized\n");
1991 return -EINVAL;
1992 }
1993
1994 if (amdgpu_discovery_get_table_info(adev, &info, GC))
1995 return -EINVAL;
1996 offset = le16_to_cpu(info->offset);
1997
1998 if (!offset)
1999 return 0;
2000
2001 gc_info = (union gc_info *)(discovery_bin + offset);
2002
2003 switch (le16_to_cpu(gc_info->v1.header.version_major)) {
2004 case 1:
2005 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se);
2006 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) +
2007 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa));
2008 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
2009 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se);
2010 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c);
2011 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs);
2012 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds);
2013 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth);
2014 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth);
2015 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer);
2016 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size);
2017 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd);
2018 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu);
2019 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size);
2020 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) /
2021 le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
2022 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc);
2023 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 1) {
2024 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa);
2025 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface);
2026 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps);
2027 }
2028 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 2) {
2029 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg);
2030 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size);
2031 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp);
2032 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc);
2033 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc);
2034 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa);
2035 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance);
2036 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu);
2037 }
2038 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 3) {
2039 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v1_3.gc_tcp_size_per_cu);
2040 adev->gfx.config.gc_tcp_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcp_cache_line_size);
2041 adev->gfx.config.gc_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_size_per_sqc);
2042 adev->gfx.config.gc_instruction_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_line_size);
2043 adev->gfx.config.gc_scalar_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_size_per_sqc);
2044 adev->gfx.config.gc_scalar_data_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_line_size);
2045 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size);
2046 adev->gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcc_cache_line_size);
2047 }
2048 break;
2049 case 2:
2050 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se);
2051 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh);
2052 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
2053 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se);
2054 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs);
2055 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs);
2056 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds);
2057 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth);
2058 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth);
2059 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer);
2060 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size);
2061 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd);
2062 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu);
2063 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size);
2064 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) /
2065 le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
2066 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc);
2067 if (le16_to_cpu(gc_info->v2.header.version_minor) == 1) {
2068 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh);
2069 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu);
2070 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XCD */
2071 adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc);
2072 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_cache_size_per_sqc);
2073 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_size_per_sqc);
2074 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */
2075 }
2076 break;
2077 default:
2078 dev_err(adev->dev,
2079 "Unhandled GC info table %d.%d\n",
2080 le16_to_cpu(gc_info->v1.header.version_major),
2081 le16_to_cpu(gc_info->v1.header.version_minor));
2082 return -EINVAL;
2083 }
2084 return 0;
2085 }
2086
2087 union mall_info {
2088 struct mall_info_v1_0 v1;
2089 struct mall_info_v2_0 v2;
2090 };
2091
amdgpu_discovery_get_mall_info(struct amdgpu_device * adev)2092 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev)
2093 {
2094 uint8_t *discovery_bin = adev->discovery.bin;
2095 struct table_info *info;
2096 union mall_info *mall_info;
2097 u32 u, mall_size_per_umc, m_s_present, half_use;
2098 u64 mall_size;
2099 u16 offset;
2100
2101 if (!discovery_bin) {
2102 DRM_ERROR("ip discovery uninitialized\n");
2103 return -EINVAL;
2104 }
2105
2106 if (amdgpu_discovery_get_table_info(adev, &info, MALL_INFO))
2107 return -EINVAL;
2108 offset = le16_to_cpu(info->offset);
2109
2110 if (!offset)
2111 return 0;
2112
2113 mall_info = (union mall_info *)(discovery_bin + offset);
2114
2115 switch (le16_to_cpu(mall_info->v1.header.version_major)) {
2116 case 1:
2117 mall_size = 0;
2118 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m);
2119 m_s_present = le32_to_cpu(mall_info->v1.m_s_present);
2120 half_use = le32_to_cpu(mall_info->v1.m_half_use);
2121 for (u = 0; u < adev->gmc.num_umc; u++) {
2122 if (m_s_present & (1 << u))
2123 mall_size += mall_size_per_umc * 2;
2124 else if (half_use & (1 << u))
2125 mall_size += mall_size_per_umc / 2;
2126 else
2127 mall_size += mall_size_per_umc;
2128 }
2129 adev->gmc.mall_size = mall_size;
2130 adev->gmc.m_half_use = half_use;
2131 break;
2132 case 2:
2133 mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc);
2134 adev->gmc.mall_size = (uint64_t)mall_size_per_umc * adev->gmc.num_umc;
2135 break;
2136 default:
2137 dev_err(adev->dev,
2138 "Unhandled MALL info table %d.%d\n",
2139 le16_to_cpu(mall_info->v1.header.version_major),
2140 le16_to_cpu(mall_info->v1.header.version_minor));
2141 return -EINVAL;
2142 }
2143 return 0;
2144 }
2145
2146 union vcn_info {
2147 struct vcn_info_v1_0 v1;
2148 };
2149
amdgpu_discovery_get_vcn_info(struct amdgpu_device * adev)2150 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev)
2151 {
2152 uint8_t *discovery_bin = adev->discovery.bin;
2153 struct table_info *info;
2154 union vcn_info *vcn_info;
2155 u16 offset;
2156 int v;
2157
2158 if (!discovery_bin) {
2159 DRM_ERROR("ip discovery uninitialized\n");
2160 return -EINVAL;
2161 }
2162
2163 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES
2164 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES
2165 * but that may change in the future with new GPUs so keep this
2166 * check for defensive purposes.
2167 */
2168 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) {
2169 dev_err(adev->dev, "invalid vcn instances\n");
2170 return -EINVAL;
2171 }
2172
2173 if (amdgpu_discovery_get_table_info(adev, &info, VCN_INFO))
2174 return -EINVAL;
2175 offset = le16_to_cpu(info->offset);
2176
2177 if (!offset)
2178 return 0;
2179
2180 vcn_info = (union vcn_info *)(discovery_bin + offset);
2181
2182 switch (le16_to_cpu(vcn_info->v1.header.version_major)) {
2183 case 1:
2184 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES
2185 * so this won't overflow.
2186 */
2187 for (v = 0; v < adev->vcn.num_vcn_inst; v++) {
2188 adev->vcn.inst[v].vcn_codec_disable_mask =
2189 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits);
2190 }
2191 break;
2192 default:
2193 dev_err(adev->dev,
2194 "Unhandled VCN info table %d.%d\n",
2195 le16_to_cpu(vcn_info->v1.header.version_major),
2196 le16_to_cpu(vcn_info->v1.header.version_minor));
2197 return -EINVAL;
2198 }
2199 return 0;
2200 }
2201
2202 union nps_info {
2203 struct nps_info_v1_0 v1;
2204 };
2205
amdgpu_discovery_refresh_nps_info(struct amdgpu_device * adev,union nps_info * nps_data)2206 static int amdgpu_discovery_refresh_nps_info(struct amdgpu_device *adev,
2207 union nps_info *nps_data)
2208 {
2209 uint64_t vram_size, pos, offset;
2210 struct nps_info_header *nhdr;
2211 struct binary_header bhdr;
2212 struct binary_header_v2 bhdrv2;
2213 uint16_t checksum;
2214
2215 vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
2216 pos = vram_size - DISCOVERY_TMR_OFFSET;
2217 amdgpu_device_vram_access(adev, pos, &bhdr, sizeof(bhdr), false);
2218
2219 switch (bhdr.version_major) {
2220 case 2:
2221 amdgpu_device_vram_access(adev, pos, &bhdrv2, sizeof(bhdrv2), false);
2222 offset = le16_to_cpu(bhdrv2.table_list[NPS_INFO].offset);
2223 checksum = le16_to_cpu(bhdrv2.table_list[NPS_INFO].checksum);
2224 break;
2225 case 1:
2226 offset = le16_to_cpu(bhdr.table_list[NPS_INFO].offset);
2227 checksum = le16_to_cpu(bhdr.table_list[NPS_INFO].checksum);
2228 break;
2229 default:
2230 return -EINVAL;
2231 }
2232
2233 amdgpu_device_vram_access(adev, (pos + offset), nps_data,
2234 sizeof(*nps_data), false);
2235
2236 nhdr = (struct nps_info_header *)(nps_data);
2237 if (!amdgpu_discovery_verify_checksum(adev, (uint8_t *)nps_data,
2238 le32_to_cpu(nhdr->size_bytes),
2239 checksum)) {
2240 dev_err(adev->dev, "nps data refresh, checksum mismatch\n");
2241 return -EINVAL;
2242 }
2243
2244 return 0;
2245 }
2246
amdgpu_discovery_get_nps_info(struct amdgpu_device * adev,uint32_t * nps_type,struct amdgpu_gmc_memrange * ranges,int * range_cnt,bool refresh)2247 int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev,
2248 uint32_t *nps_type,
2249 struct amdgpu_gmc_memrange *ranges,
2250 int *range_cnt, bool refresh)
2251 {
2252 uint8_t *discovery_bin = adev->discovery.bin;
2253 struct table_info *info;
2254 union nps_info *nps_info;
2255 union nps_info nps_data;
2256 u16 offset;
2257 int i, r;
2258
2259 if (!nps_type || !range_cnt || !ranges)
2260 return -EINVAL;
2261
2262 if (refresh) {
2263 r = amdgpu_discovery_refresh_nps_info(adev, &nps_data);
2264 if (r)
2265 return r;
2266 nps_info = &nps_data;
2267 } else {
2268 if (!discovery_bin) {
2269 dev_err(adev->dev,
2270 "fetch mem range failed, ip discovery uninitialized\n");
2271 return -EINVAL;
2272 }
2273
2274 if (amdgpu_discovery_get_table_info(adev, &info, NPS_INFO))
2275 return -EINVAL;
2276 offset = le16_to_cpu(info->offset);
2277
2278 if (!offset)
2279 return -ENOENT;
2280
2281 /* If verification fails, return as if NPS table doesn't exist */
2282 if (amdgpu_discovery_verify_npsinfo(adev, info))
2283 return -ENOENT;
2284
2285 nps_info = (union nps_info *)(discovery_bin + offset);
2286 }
2287
2288 switch (le16_to_cpu(nps_info->v1.header.version_major)) {
2289 case 1:
2290 *nps_type = nps_info->v1.nps_type;
2291 if (*range_cnt < nps_info->v1.count) {
2292 dev_dbg(adev->dev,
2293 "not enough space for nps ranges: %d < %d\n",
2294 *range_cnt, nps_info->v1.count);
2295 return -ENOSPC;
2296 }
2297 *range_cnt = nps_info->v1.count;
2298 for (i = 0; i < *range_cnt; i++) {
2299 ranges[i].base_address =
2300 nps_info->v1.instance_info[i].base_address;
2301 ranges[i].limit_address =
2302 nps_info->v1.instance_info[i].limit_address;
2303 ranges[i].nid_mask = -1;
2304 ranges[i].flags = 0;
2305 }
2306 break;
2307 default:
2308 dev_err(adev->dev, "Unhandled NPS info table %d.%d\n",
2309 le16_to_cpu(nps_info->v1.header.version_major),
2310 le16_to_cpu(nps_info->v1.header.version_minor));
2311 return -EINVAL;
2312 }
2313
2314 return 0;
2315 }
2316
amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device * adev)2317 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
2318 {
2319 /* what IP to use for this? */
2320 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2321 case IP_VERSION(9, 0, 1):
2322 case IP_VERSION(9, 1, 0):
2323 case IP_VERSION(9, 2, 1):
2324 case IP_VERSION(9, 2, 2):
2325 case IP_VERSION(9, 3, 0):
2326 case IP_VERSION(9, 4, 0):
2327 case IP_VERSION(9, 4, 1):
2328 case IP_VERSION(9, 4, 2):
2329 case IP_VERSION(9, 4, 3):
2330 case IP_VERSION(9, 4, 4):
2331 case IP_VERSION(9, 5, 0):
2332 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
2333 break;
2334 case IP_VERSION(10, 1, 10):
2335 case IP_VERSION(10, 1, 1):
2336 case IP_VERSION(10, 1, 2):
2337 case IP_VERSION(10, 1, 3):
2338 case IP_VERSION(10, 1, 4):
2339 case IP_VERSION(10, 3, 0):
2340 case IP_VERSION(10, 3, 1):
2341 case IP_VERSION(10, 3, 2):
2342 case IP_VERSION(10, 3, 3):
2343 case IP_VERSION(10, 3, 4):
2344 case IP_VERSION(10, 3, 5):
2345 case IP_VERSION(10, 3, 6):
2346 case IP_VERSION(10, 3, 7):
2347 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
2348 break;
2349 case IP_VERSION(11, 0, 0):
2350 case IP_VERSION(11, 0, 1):
2351 case IP_VERSION(11, 0, 2):
2352 case IP_VERSION(11, 0, 3):
2353 case IP_VERSION(11, 0, 4):
2354 case IP_VERSION(11, 5, 0):
2355 case IP_VERSION(11, 5, 1):
2356 case IP_VERSION(11, 5, 2):
2357 case IP_VERSION(11, 5, 3):
2358 case IP_VERSION(11, 5, 4):
2359 case IP_VERSION(11, 5, 6):
2360 case IP_VERSION(11, 7, 0):
2361 case IP_VERSION(11, 7, 1):
2362 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block);
2363 break;
2364 case IP_VERSION(12, 0, 0):
2365 case IP_VERSION(12, 0, 1):
2366 amdgpu_device_ip_block_add(adev, &soc24_common_ip_block);
2367 break;
2368 case IP_VERSION(12, 1, 0):
2369 amdgpu_device_ip_block_add(adev, &soc_v1_0_common_ip_block);
2370 break;
2371 default:
2372 dev_err(adev->dev,
2373 "Failed to add common ip block(GC_HWIP:0x%x)\n",
2374 amdgpu_ip_version(adev, GC_HWIP, 0));
2375 return -EINVAL;
2376 }
2377 return 0;
2378 }
2379
amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device * adev)2380 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev)
2381 {
2382 /* use GC or MMHUB IP version */
2383 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2384 case IP_VERSION(9, 0, 1):
2385 case IP_VERSION(9, 1, 0):
2386 case IP_VERSION(9, 2, 1):
2387 case IP_VERSION(9, 2, 2):
2388 case IP_VERSION(9, 3, 0):
2389 case IP_VERSION(9, 4, 0):
2390 case IP_VERSION(9, 4, 1):
2391 case IP_VERSION(9, 4, 2):
2392 case IP_VERSION(9, 4, 3):
2393 case IP_VERSION(9, 4, 4):
2394 case IP_VERSION(9, 5, 0):
2395 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
2396 break;
2397 case IP_VERSION(10, 1, 10):
2398 case IP_VERSION(10, 1, 1):
2399 case IP_VERSION(10, 1, 2):
2400 case IP_VERSION(10, 1, 3):
2401 case IP_VERSION(10, 1, 4):
2402 case IP_VERSION(10, 3, 0):
2403 case IP_VERSION(10, 3, 1):
2404 case IP_VERSION(10, 3, 2):
2405 case IP_VERSION(10, 3, 3):
2406 case IP_VERSION(10, 3, 4):
2407 case IP_VERSION(10, 3, 5):
2408 case IP_VERSION(10, 3, 6):
2409 case IP_VERSION(10, 3, 7):
2410 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
2411 break;
2412 case IP_VERSION(11, 0, 0):
2413 case IP_VERSION(11, 0, 1):
2414 case IP_VERSION(11, 0, 2):
2415 case IP_VERSION(11, 0, 3):
2416 case IP_VERSION(11, 0, 4):
2417 case IP_VERSION(11, 5, 0):
2418 case IP_VERSION(11, 5, 1):
2419 case IP_VERSION(11, 5, 2):
2420 case IP_VERSION(11, 5, 3):
2421 case IP_VERSION(11, 5, 4):
2422 case IP_VERSION(11, 5, 6):
2423 case IP_VERSION(11, 7, 0):
2424 case IP_VERSION(11, 7, 1):
2425 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block);
2426 break;
2427 case IP_VERSION(12, 0, 0):
2428 case IP_VERSION(12, 0, 1):
2429 case IP_VERSION(12, 1, 0):
2430 amdgpu_device_ip_block_add(adev, &gmc_v12_0_ip_block);
2431 break;
2432 default:
2433 dev_err(adev->dev, "Failed to add gmc ip block(GC_HWIP:0x%x)\n",
2434 amdgpu_ip_version(adev, GC_HWIP, 0));
2435 return -EINVAL;
2436 }
2437 return 0;
2438 }
2439
amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device * adev)2440 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev)
2441 {
2442 switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) {
2443 case IP_VERSION(4, 0, 0):
2444 case IP_VERSION(4, 0, 1):
2445 case IP_VERSION(4, 1, 0):
2446 case IP_VERSION(4, 1, 1):
2447 case IP_VERSION(4, 3, 0):
2448 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
2449 break;
2450 case IP_VERSION(4, 2, 0):
2451 case IP_VERSION(4, 2, 1):
2452 case IP_VERSION(4, 4, 0):
2453 case IP_VERSION(4, 4, 2):
2454 case IP_VERSION(4, 4, 5):
2455 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
2456 break;
2457 case IP_VERSION(5, 0, 0):
2458 case IP_VERSION(5, 0, 1):
2459 case IP_VERSION(5, 0, 2):
2460 case IP_VERSION(5, 0, 3):
2461 case IP_VERSION(5, 2, 0):
2462 case IP_VERSION(5, 2, 1):
2463 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
2464 break;
2465 case IP_VERSION(6, 0, 0):
2466 case IP_VERSION(6, 0, 1):
2467 case IP_VERSION(6, 0, 2):
2468 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block);
2469 break;
2470 case IP_VERSION(6, 1, 0):
2471 case IP_VERSION(6, 1, 1):
2472 case IP_VERSION(6, 4, 0):
2473 amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block);
2474 break;
2475 case IP_VERSION(7, 0, 0):
2476 case IP_VERSION(7, 1, 0):
2477 amdgpu_device_ip_block_add(adev, &ih_v7_0_ip_block);
2478 break;
2479 default:
2480 dev_err(adev->dev,
2481 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n",
2482 amdgpu_ip_version(adev, OSSSYS_HWIP, 0));
2483 return -EINVAL;
2484 }
2485 return 0;
2486 }
2487
amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device * adev)2488 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)
2489 {
2490 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
2491 case IP_VERSION(9, 0, 0):
2492 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
2493 break;
2494 case IP_VERSION(10, 0, 0):
2495 case IP_VERSION(10, 0, 1):
2496 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
2497 break;
2498 case IP_VERSION(11, 0, 0):
2499 case IP_VERSION(11, 0, 2):
2500 case IP_VERSION(11, 0, 4):
2501 case IP_VERSION(11, 0, 5):
2502 case IP_VERSION(11, 0, 9):
2503 case IP_VERSION(11, 0, 7):
2504 case IP_VERSION(11, 0, 11):
2505 case IP_VERSION(11, 0, 12):
2506 case IP_VERSION(11, 0, 13):
2507 case IP_VERSION(11, 5, 0):
2508 case IP_VERSION(11, 5, 2):
2509 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
2510 break;
2511 case IP_VERSION(11, 0, 8):
2512 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
2513 break;
2514 case IP_VERSION(11, 0, 3):
2515 case IP_VERSION(12, 0, 1):
2516 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
2517 break;
2518 case IP_VERSION(13, 0, 0):
2519 case IP_VERSION(13, 0, 1):
2520 case IP_VERSION(13, 0, 2):
2521 case IP_VERSION(13, 0, 3):
2522 case IP_VERSION(13, 0, 5):
2523 case IP_VERSION(13, 0, 6):
2524 case IP_VERSION(13, 0, 7):
2525 case IP_VERSION(13, 0, 8):
2526 case IP_VERSION(13, 0, 10):
2527 case IP_VERSION(13, 0, 11):
2528 case IP_VERSION(13, 0, 12):
2529 case IP_VERSION(13, 0, 14):
2530 case IP_VERSION(13, 0, 15):
2531 case IP_VERSION(14, 0, 0):
2532 case IP_VERSION(14, 0, 1):
2533 case IP_VERSION(14, 0, 4):
2534 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
2535 break;
2536 case IP_VERSION(13, 0, 4):
2537 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block);
2538 break;
2539 case IP_VERSION(14, 0, 2):
2540 case IP_VERSION(14, 0, 3):
2541 case IP_VERSION(14, 0, 5):
2542 amdgpu_device_ip_block_add(adev, &psp_v14_0_ip_block);
2543 break;
2544 case IP_VERSION(15, 0, 0):
2545 case IP_VERSION(15, 0, 5):
2546 case IP_VERSION(15, 0, 9):
2547 amdgpu_device_ip_block_add(adev, &psp_v15_0_ip_block);
2548 break;
2549 case IP_VERSION(15, 0, 8):
2550 amdgpu_device_ip_block_add(adev, &psp_v15_0_8_ip_block);
2551 break;
2552 default:
2553 dev_err(adev->dev,
2554 "Failed to add psp ip block(MP0_HWIP:0x%x)\n",
2555 amdgpu_ip_version(adev, MP0_HWIP, 0));
2556 return -EINVAL;
2557 }
2558 return 0;
2559 }
2560
amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device * adev)2561 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)
2562 {
2563 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
2564 case IP_VERSION(9, 0, 0):
2565 case IP_VERSION(10, 0, 0):
2566 case IP_VERSION(10, 0, 1):
2567 case IP_VERSION(11, 0, 2):
2568 if (adev->asic_type == CHIP_ARCTURUS)
2569 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
2570 else
2571 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
2572 break;
2573 case IP_VERSION(11, 0, 0):
2574 case IP_VERSION(11, 0, 5):
2575 case IP_VERSION(11, 0, 9):
2576 case IP_VERSION(11, 0, 7):
2577 case IP_VERSION(11, 0, 11):
2578 case IP_VERSION(11, 0, 12):
2579 case IP_VERSION(11, 0, 13):
2580 case IP_VERSION(11, 5, 0):
2581 case IP_VERSION(11, 5, 2):
2582 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
2583 break;
2584 case IP_VERSION(11, 0, 8):
2585 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2)
2586 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
2587 break;
2588 case IP_VERSION(12, 0, 0):
2589 case IP_VERSION(12, 0, 1):
2590 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
2591 break;
2592 case IP_VERSION(13, 0, 0):
2593 case IP_VERSION(13, 0, 1):
2594 case IP_VERSION(13, 0, 2):
2595 case IP_VERSION(13, 0, 3):
2596 case IP_VERSION(13, 0, 4):
2597 case IP_VERSION(13, 0, 5):
2598 case IP_VERSION(13, 0, 6):
2599 case IP_VERSION(13, 0, 7):
2600 case IP_VERSION(13, 0, 8):
2601 case IP_VERSION(13, 0, 10):
2602 case IP_VERSION(13, 0, 11):
2603 case IP_VERSION(13, 0, 14):
2604 case IP_VERSION(13, 0, 12):
2605 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
2606 break;
2607 case IP_VERSION(14, 0, 0):
2608 case IP_VERSION(14, 0, 1):
2609 case IP_VERSION(14, 0, 2):
2610 case IP_VERSION(14, 0, 3):
2611 case IP_VERSION(14, 0, 4):
2612 case IP_VERSION(14, 0, 5):
2613 amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block);
2614 break;
2615 case IP_VERSION(15, 0, 0):
2616 case IP_VERSION(15, 0, 5):
2617 case IP_VERSION(15, 0, 8):
2618 case IP_VERSION(15, 0, 9):
2619 amdgpu_device_ip_block_add(adev, &smu_v15_0_ip_block);
2620 break;
2621 default:
2622 dev_err(adev->dev,
2623 "Failed to add smu ip block(MP1_HWIP:0x%x)\n",
2624 amdgpu_ip_version(adev, MP1_HWIP, 0));
2625 return -EINVAL;
2626 }
2627 return 0;
2628 }
2629
2630 #if defined(CONFIG_DRM_AMD_DC)
amdgpu_discovery_set_sriov_display(struct amdgpu_device * adev)2631 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev)
2632 {
2633 amdgpu_device_set_sriov_virtual_display(adev);
2634 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2635 }
2636 #endif
2637
amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device * adev)2638 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev)
2639 {
2640 if (adev->enable_virtual_display) {
2641 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2642 return 0;
2643 }
2644
2645 if (!amdgpu_device_has_dc_support(adev))
2646 return 0;
2647
2648 #if defined(CONFIG_DRM_AMD_DC)
2649 if (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2650 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2651 case IP_VERSION(1, 0, 0):
2652 case IP_VERSION(1, 0, 1):
2653 case IP_VERSION(2, 0, 2):
2654 case IP_VERSION(2, 0, 0):
2655 case IP_VERSION(2, 0, 3):
2656 case IP_VERSION(2, 1, 0):
2657 case IP_VERSION(3, 0, 0):
2658 case IP_VERSION(3, 0, 2):
2659 case IP_VERSION(3, 0, 3):
2660 case IP_VERSION(3, 0, 1):
2661 case IP_VERSION(3, 1, 2):
2662 case IP_VERSION(3, 1, 3):
2663 case IP_VERSION(3, 1, 4):
2664 case IP_VERSION(3, 1, 5):
2665 case IP_VERSION(3, 1, 6):
2666 case IP_VERSION(3, 2, 0):
2667 case IP_VERSION(3, 2, 1):
2668 case IP_VERSION(3, 5, 0):
2669 case IP_VERSION(3, 5, 1):
2670 case IP_VERSION(3, 6, 0):
2671 case IP_VERSION(4, 1, 0):
2672 case IP_VERSION(4, 2, 0):
2673 case IP_VERSION(4, 2, 1):
2674 case IP_VERSION(6, 0, 0):
2675 /* TODO: Fix IP version. DC code expects version 4.0.1 */
2676 if (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(4, 1, 0))
2677 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(4, 0, 1);
2678
2679 if (amdgpu_sriov_vf(adev))
2680 amdgpu_discovery_set_sriov_display(adev);
2681 else
2682 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2683 break;
2684 default:
2685 dev_err(adev->dev,
2686 "Failed to add dm ip block(DCE_HWIP:0x%x)\n",
2687 amdgpu_ip_version(adev, DCE_HWIP, 0));
2688 return -EINVAL;
2689 }
2690 } else if (amdgpu_ip_version(adev, DCI_HWIP, 0)) {
2691 switch (amdgpu_ip_version(adev, DCI_HWIP, 0)) {
2692 case IP_VERSION(12, 0, 0):
2693 case IP_VERSION(12, 0, 1):
2694 case IP_VERSION(12, 1, 0):
2695 if (amdgpu_sriov_vf(adev))
2696 amdgpu_discovery_set_sriov_display(adev);
2697 else
2698 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2699 break;
2700 default:
2701 dev_err(adev->dev,
2702 "Failed to add dm ip block(DCI_HWIP:0x%x)\n",
2703 amdgpu_ip_version(adev, DCI_HWIP, 0));
2704 return -EINVAL;
2705 }
2706 }
2707 #endif
2708 return 0;
2709 }
2710
amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device * adev)2711 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)
2712 {
2713 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2714 case IP_VERSION(9, 0, 1):
2715 case IP_VERSION(9, 1, 0):
2716 case IP_VERSION(9, 2, 1):
2717 case IP_VERSION(9, 2, 2):
2718 case IP_VERSION(9, 3, 0):
2719 case IP_VERSION(9, 4, 0):
2720 case IP_VERSION(9, 4, 1):
2721 case IP_VERSION(9, 4, 2):
2722 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
2723 break;
2724 case IP_VERSION(9, 4, 3):
2725 case IP_VERSION(9, 4, 4):
2726 case IP_VERSION(9, 5, 0):
2727 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block);
2728 break;
2729 case IP_VERSION(10, 1, 10):
2730 case IP_VERSION(10, 1, 2):
2731 case IP_VERSION(10, 1, 1):
2732 case IP_VERSION(10, 1, 3):
2733 case IP_VERSION(10, 1, 4):
2734 case IP_VERSION(10, 3, 0):
2735 case IP_VERSION(10, 3, 2):
2736 case IP_VERSION(10, 3, 1):
2737 case IP_VERSION(10, 3, 4):
2738 case IP_VERSION(10, 3, 5):
2739 case IP_VERSION(10, 3, 6):
2740 case IP_VERSION(10, 3, 3):
2741 case IP_VERSION(10, 3, 7):
2742 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
2743 break;
2744 case IP_VERSION(11, 0, 0):
2745 case IP_VERSION(11, 0, 1):
2746 case IP_VERSION(11, 0, 2):
2747 case IP_VERSION(11, 0, 3):
2748 case IP_VERSION(11, 0, 4):
2749 case IP_VERSION(11, 5, 0):
2750 case IP_VERSION(11, 5, 1):
2751 case IP_VERSION(11, 5, 2):
2752 case IP_VERSION(11, 5, 3):
2753 case IP_VERSION(11, 5, 4):
2754 case IP_VERSION(11, 5, 6):
2755 case IP_VERSION(11, 7, 0):
2756 case IP_VERSION(11, 7, 1):
2757 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block);
2758 break;
2759 case IP_VERSION(12, 0, 0):
2760 case IP_VERSION(12, 0, 1):
2761 amdgpu_device_ip_block_add(adev, &gfx_v12_0_ip_block);
2762 break;
2763 case IP_VERSION(12, 1, 0):
2764 amdgpu_device_ip_block_add(adev, &gfx_v12_1_ip_block);
2765 break;
2766 default:
2767 dev_err(adev->dev, "Failed to add gfx ip block(GC_HWIP:0x%x)\n",
2768 amdgpu_ip_version(adev, GC_HWIP, 0));
2769 return -EINVAL;
2770 }
2771 return 0;
2772 }
2773
amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device * adev)2774 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)
2775 {
2776 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
2777 case IP_VERSION(4, 0, 0):
2778 case IP_VERSION(4, 0, 1):
2779 case IP_VERSION(4, 1, 0):
2780 case IP_VERSION(4, 1, 1):
2781 case IP_VERSION(4, 1, 2):
2782 case IP_VERSION(4, 2, 0):
2783 case IP_VERSION(4, 2, 2):
2784 case IP_VERSION(4, 4, 0):
2785 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
2786 break;
2787 case IP_VERSION(4, 4, 2):
2788 case IP_VERSION(4, 4, 5):
2789 case IP_VERSION(4, 4, 4):
2790 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block);
2791 break;
2792 case IP_VERSION(5, 0, 0):
2793 case IP_VERSION(5, 0, 1):
2794 case IP_VERSION(5, 0, 2):
2795 case IP_VERSION(5, 0, 5):
2796 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
2797 break;
2798 case IP_VERSION(5, 2, 0):
2799 case IP_VERSION(5, 2, 2):
2800 case IP_VERSION(5, 2, 4):
2801 case IP_VERSION(5, 2, 5):
2802 case IP_VERSION(5, 2, 6):
2803 case IP_VERSION(5, 2, 3):
2804 case IP_VERSION(5, 2, 1):
2805 case IP_VERSION(5, 2, 7):
2806 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
2807 break;
2808 case IP_VERSION(6, 0, 0):
2809 case IP_VERSION(6, 0, 1):
2810 case IP_VERSION(6, 0, 2):
2811 case IP_VERSION(6, 0, 3):
2812 case IP_VERSION(6, 1, 0):
2813 case IP_VERSION(6, 1, 1):
2814 case IP_VERSION(6, 1, 2):
2815 case IP_VERSION(6, 1, 3):
2816 case IP_VERSION(6, 1, 4):
2817 case IP_VERSION(6, 4, 0):
2818 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block);
2819 break;
2820 case IP_VERSION(7, 0, 0):
2821 case IP_VERSION(7, 0, 1):
2822 amdgpu_device_ip_block_add(adev, &sdma_v7_0_ip_block);
2823 break;
2824 case IP_VERSION(7, 1, 0):
2825 amdgpu_device_ip_block_add(adev, &sdma_v7_1_ip_block);
2826 break;
2827 default:
2828 dev_err(adev->dev,
2829 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n",
2830 amdgpu_ip_version(adev, SDMA0_HWIP, 0));
2831 return -EINVAL;
2832 }
2833
2834 return 0;
2835 }
2836
amdgpu_discovery_set_ras_ip_blocks(struct amdgpu_device * adev)2837 static int amdgpu_discovery_set_ras_ip_blocks(struct amdgpu_device *adev)
2838 {
2839 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
2840 case IP_VERSION(13, 0, 6):
2841 case IP_VERSION(13, 0, 12):
2842 case IP_VERSION(13, 0, 14):
2843 amdgpu_device_ip_block_add(adev, &ras_v1_0_ip_block);
2844 break;
2845 default:
2846 break;
2847 }
2848 return 0;
2849 }
2850
amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device * adev)2851 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
2852 {
2853 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) {
2854 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
2855 case IP_VERSION(7, 0, 0):
2856 case IP_VERSION(7, 2, 0):
2857 /* UVD is not supported on vega20 SR-IOV */
2858 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
2859 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
2860 break;
2861 default:
2862 dev_err(adev->dev,
2863 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n",
2864 amdgpu_ip_version(adev, UVD_HWIP, 0));
2865 return -EINVAL;
2866 }
2867 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) {
2868 case IP_VERSION(4, 0, 0):
2869 case IP_VERSION(4, 1, 0):
2870 /* VCE is not supported on vega20 SR-IOV */
2871 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
2872 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
2873 break;
2874 default:
2875 dev_err(adev->dev,
2876 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n",
2877 amdgpu_ip_version(adev, VCE_HWIP, 0));
2878 return -EINVAL;
2879 }
2880 } else {
2881 uint32_t vcn_version = amdgpu_ip_version(adev, UVD_HWIP, 0);
2882
2883 /* no VCN discovered; nothing to add */
2884 if (!vcn_version)
2885 return 0;
2886 switch (vcn_version) {
2887 case IP_VERSION(1, 0, 0):
2888 case IP_VERSION(1, 0, 1):
2889 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
2890 break;
2891 case IP_VERSION(2, 0, 0):
2892 case IP_VERSION(2, 0, 2):
2893 case IP_VERSION(2, 2, 0):
2894 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
2895 if (!amdgpu_sriov_vf(adev))
2896 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
2897 break;
2898 case IP_VERSION(2, 0, 3):
2899 break;
2900 case IP_VERSION(2, 5, 0):
2901 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
2902 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
2903 break;
2904 case IP_VERSION(2, 6, 0):
2905 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
2906 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
2907 break;
2908 case IP_VERSION(3, 0, 0):
2909 case IP_VERSION(3, 0, 16):
2910 case IP_VERSION(3, 1, 1):
2911 case IP_VERSION(3, 1, 2):
2912 case IP_VERSION(3, 0, 2):
2913 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
2914 if (!amdgpu_sriov_vf(adev))
2915 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
2916 break;
2917 case IP_VERSION(3, 0, 33):
2918 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
2919 break;
2920 case IP_VERSION(4, 0, 0):
2921 case IP_VERSION(4, 0, 2):
2922 case IP_VERSION(4, 0, 4):
2923 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block);
2924 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block);
2925 break;
2926 case IP_VERSION(4, 0, 3):
2927 amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block);
2928 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block);
2929 break;
2930 case IP_VERSION(4, 0, 5):
2931 case IP_VERSION(4, 0, 6):
2932 amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block);
2933 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block);
2934 break;
2935 case IP_VERSION(5, 0, 0):
2936 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block);
2937 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block);
2938 break;
2939 case IP_VERSION(5, 3, 0):
2940 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block);
2941 amdgpu_device_ip_block_add(adev, &jpeg_v5_3_0_ip_block);
2942 break;
2943 case IP_VERSION(5, 0, 1):
2944 amdgpu_device_ip_block_add(adev, &vcn_v5_0_1_ip_block);
2945 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_1_ip_block);
2946 break;
2947 case IP_VERSION(5, 0, 2):
2948 amdgpu_device_ip_block_add(adev, &vcn_v5_0_2_ip_block);
2949 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_2_ip_block);
2950 break;
2951 default:
2952 dev_err(adev->dev,
2953 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n",
2954 vcn_version);
2955 return -EINVAL;
2956 }
2957 }
2958 return 0;
2959 }
2960
amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device * adev)2961 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
2962 {
2963 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2964 case IP_VERSION(11, 0, 0):
2965 case IP_VERSION(11, 0, 1):
2966 case IP_VERSION(11, 0, 2):
2967 case IP_VERSION(11, 0, 3):
2968 case IP_VERSION(11, 0, 4):
2969 case IP_VERSION(11, 5, 0):
2970 case IP_VERSION(11, 5, 1):
2971 case IP_VERSION(11, 5, 2):
2972 case IP_VERSION(11, 5, 3):
2973 case IP_VERSION(11, 5, 4):
2974 case IP_VERSION(11, 5, 6):
2975 case IP_VERSION(11, 7, 0):
2976 case IP_VERSION(11, 7, 1):
2977 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block);
2978 adev->enable_mes = true;
2979 adev->enable_mes_kiq = true;
2980 break;
2981 case IP_VERSION(12, 0, 0):
2982 case IP_VERSION(12, 0, 1):
2983 amdgpu_device_ip_block_add(adev, &mes_v12_0_ip_block);
2984 adev->enable_mes = true;
2985 adev->enable_mes_kiq = true;
2986 if (amdgpu_uni_mes)
2987 adev->enable_uni_mes = true;
2988 break;
2989 case IP_VERSION(12, 1, 0):
2990 amdgpu_device_ip_block_add(adev, &mes_v12_1_ip_block);
2991 adev->enable_mes = true;
2992 adev->enable_mes_kiq = true;
2993 if (amdgpu_uni_mes)
2994 adev->enable_uni_mes = true;
2995 break;
2996 default:
2997 break;
2998 }
2999 return 0;
3000 }
3001
amdgpu_discovery_init_soc_config(struct amdgpu_device * adev)3002 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev)
3003 {
3004 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3005 case IP_VERSION(9, 4, 3):
3006 case IP_VERSION(9, 4, 4):
3007 case IP_VERSION(9, 5, 0):
3008 aqua_vanjaram_init_soc_config(adev);
3009 break;
3010 case IP_VERSION(12, 1, 0):
3011 soc_v1_0_init_soc_config(adev);
3012 break;
3013 default:
3014 break;
3015 }
3016 }
3017
amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device * adev)3018 static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev)
3019 {
3020 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) {
3021 case IP_VERSION(6, 1, 0):
3022 case IP_VERSION(6, 1, 1):
3023 case IP_VERSION(6, 1, 3):
3024 amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block);
3025 break;
3026 case IP_VERSION(2, 0, 0):
3027 case IP_VERSION(2, 2, 0):
3028 amdgpu_device_ip_block_add(adev, &vpe_v2_0_ip_block);
3029 break;
3030 default:
3031 break;
3032 }
3033
3034 return 0;
3035 }
3036
amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device * adev)3037 static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev)
3038 {
3039 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) {
3040 case IP_VERSION(4, 0, 5):
3041 case IP_VERSION(4, 0, 6):
3042 if (amdgpu_umsch_mm & 0x1) {
3043 amdgpu_device_ip_block_add(adev, &umsch_mm_v4_0_ip_block);
3044 adev->enable_umsch_mm = true;
3045 }
3046 break;
3047 default:
3048 break;
3049 }
3050
3051 return 0;
3052 }
3053
amdgpu_discovery_set_isp_ip_blocks(struct amdgpu_device * adev)3054 static int amdgpu_discovery_set_isp_ip_blocks(struct amdgpu_device *adev)
3055 {
3056 #if defined(CONFIG_DRM_AMD_ISP)
3057 switch (amdgpu_ip_version(adev, ISP_HWIP, 0)) {
3058 case IP_VERSION(4, 1, 0):
3059 amdgpu_device_ip_block_add(adev, &isp_v4_1_0_ip_block);
3060 break;
3061 case IP_VERSION(4, 1, 1):
3062 amdgpu_device_ip_block_add(adev, &isp_v4_1_1_ip_block);
3063 break;
3064 default:
3065 break;
3066 }
3067 #endif
3068
3069 return 0;
3070 }
3071
amdgpu_discovery_set_ip_blocks(struct amdgpu_device * adev)3072 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
3073 {
3074 int r;
3075
3076 switch (adev->asic_type) {
3077 case CHIP_VEGA10:
3078 /* This is not fatal. We only need the discovery
3079 * binary for sysfs. We don't need it for a
3080 * functional system.
3081 */
3082 amdgpu_discovery_init(adev);
3083 vega10_reg_base_init(adev);
3084 adev->sdma.num_instances = 2;
3085 adev->sdma.sdma_mask = 3;
3086 adev->gmc.num_umc = 4;
3087 adev->gfx.xcc_mask = 1;
3088 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
3089 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
3090 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
3091 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);
3092 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);
3093 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0);
3094 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
3095 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
3096 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);
3097 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
3098 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
3099 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
3100 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);
3101 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);
3102 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
3103 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
3104 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
3105 break;
3106 case CHIP_VEGA12:
3107 /* This is not fatal. We only need the discovery
3108 * binary for sysfs. We don't need it for a
3109 * functional system.
3110 */
3111 amdgpu_discovery_init(adev);
3112 vega10_reg_base_init(adev);
3113 adev->sdma.num_instances = 2;
3114 adev->sdma.sdma_mask = 3;
3115 adev->gmc.num_umc = 4;
3116 adev->gfx.xcc_mask = 1;
3117 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
3118 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
3119 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
3120 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);
3121 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);
3122 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1);
3123 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);
3124 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
3125 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);
3126 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
3127 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
3128 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
3129 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);
3130 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);
3131 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
3132 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
3133 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
3134 break;
3135 case CHIP_RAVEN:
3136 /* This is not fatal. We only need the discovery
3137 * binary for sysfs. We don't need it for a
3138 * functional system.
3139 */
3140 amdgpu_discovery_init(adev);
3141 vega10_reg_base_init(adev);
3142 adev->sdma.num_instances = 1;
3143 adev->sdma.sdma_mask = 1;
3144 adev->vcn.num_vcn_inst = 1;
3145 adev->gmc.num_umc = 2;
3146 adev->gfx.xcc_mask = 1;
3147 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
3148 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
3149 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
3150 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);
3151 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);
3152 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);
3153 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);
3154 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
3155 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);
3156 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);
3157 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);
3158 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);
3159 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);
3160 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);
3161 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
3162 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);
3163 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0);
3164 } else {
3165 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);
3166 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);
3167 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);
3168 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);
3169 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);
3170 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
3171 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
3172 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);
3173 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);
3174 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);
3175 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);
3176 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);
3177 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);
3178 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
3179 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
3180 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0);
3181 }
3182 break;
3183 case CHIP_VEGA20:
3184 /* This is not fatal. We only need the discovery
3185 * binary for sysfs. We don't need it for a
3186 * functional system.
3187 */
3188 amdgpu_discovery_init(adev);
3189 vega20_reg_base_init(adev);
3190 adev->sdma.num_instances = 2;
3191 adev->sdma.sdma_mask = 3;
3192 adev->gmc.num_umc = 8;
3193 adev->gfx.xcc_mask = 1;
3194 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
3195 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
3196 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
3197 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);
3198 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);
3199 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0);
3200 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);
3201 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
3202 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);
3203 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);
3204 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
3205 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);
3206 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);
3207 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);
3208 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
3209 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0);
3210 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);
3211 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
3212 break;
3213 case CHIP_ARCTURUS:
3214 /* This is not fatal. We only need the discovery
3215 * binary for sysfs. We don't need it for a
3216 * functional system.
3217 */
3218 amdgpu_discovery_init(adev);
3219 arct_reg_base_init(adev);
3220 adev->sdma.num_instances = 8;
3221 adev->sdma.sdma_mask = 0xff;
3222 adev->vcn.num_vcn_inst = 2;
3223 adev->gmc.num_umc = 8;
3224 adev->gfx.xcc_mask = 1;
3225 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
3226 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
3227 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
3228 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);
3229 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);
3230 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2);
3231 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2);
3232 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2);
3233 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2);
3234 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2);
3235 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2);
3236 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2);
3237 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);
3238 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
3239 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);
3240 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);
3241 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
3242 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);
3243 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);
3244 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);
3245 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
3246 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0);
3247 break;
3248 case CHIP_ALDEBARAN:
3249 /* This is not fatal. We only need the discovery
3250 * binary for sysfs. We don't need it for a
3251 * functional system.
3252 */
3253 amdgpu_discovery_init(adev);
3254 aldebaran_reg_base_init(adev);
3255 adev->sdma.num_instances = 5;
3256 adev->sdma.sdma_mask = 0x1f;
3257 adev->vcn.num_vcn_inst = 2;
3258 adev->gmc.num_umc = 4;
3259 adev->gfx.xcc_mask = 1;
3260 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
3261 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
3262 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
3263 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);
3264 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);
3265 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0);
3266 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0);
3267 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0);
3268 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0);
3269 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);
3270 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
3271 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);
3272 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);
3273 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);
3274 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);
3275 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);
3276 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);
3277 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
3278 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0);
3279 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
3280 break;
3281 case CHIP_CYAN_SKILLFISH:
3282 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
3283 r = amdgpu_discovery_reg_base_init(adev);
3284 if (r)
3285 return -EINVAL;
3286
3287 amdgpu_discovery_harvest_ip(adev);
3288 amdgpu_discovery_get_gfx_info(adev);
3289 amdgpu_discovery_get_mall_info(adev);
3290 amdgpu_discovery_get_vcn_info(adev);
3291 } else {
3292 cyan_skillfish_reg_base_init(adev);
3293 adev->sdma.num_instances = 2;
3294 adev->sdma.sdma_mask = 3;
3295 adev->gfx.xcc_mask = 1;
3296 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(2, 0, 3);
3297 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(2, 0, 3);
3298 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(5, 0, 1);
3299 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(5, 0, 1);
3300 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(5, 0, 1);
3301 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(5, 0, 1);
3302 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 5, 0);
3303 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(2, 1, 1);
3304 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(8, 1, 1);
3305 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 8);
3306 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 8);
3307 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 1);
3308 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 8);
3309 adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 1, 3);
3310 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 0, 3);
3311 }
3312 break;
3313 default:
3314 r = amdgpu_discovery_reg_base_init(adev);
3315 if (r) {
3316 drm_err(&adev->ddev, "discovery failed: %d\n", r);
3317 return r;
3318 }
3319
3320 amdgpu_discovery_harvest_ip(adev);
3321 amdgpu_discovery_get_gfx_info(adev);
3322 amdgpu_discovery_get_mall_info(adev);
3323 amdgpu_discovery_get_vcn_info(adev);
3324 break;
3325 }
3326
3327 amdgpu_discovery_init_soc_config(adev);
3328 amdgpu_discovery_sysfs_init(adev);
3329
3330 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3331 case IP_VERSION(9, 0, 1):
3332 case IP_VERSION(9, 2, 1):
3333 case IP_VERSION(9, 4, 0):
3334 case IP_VERSION(9, 4, 1):
3335 case IP_VERSION(9, 4, 2):
3336 case IP_VERSION(9, 4, 3):
3337 case IP_VERSION(9, 4, 4):
3338 case IP_VERSION(9, 5, 0):
3339 adev->family = AMDGPU_FAMILY_AI;
3340 break;
3341 case IP_VERSION(9, 1, 0):
3342 case IP_VERSION(9, 2, 2):
3343 case IP_VERSION(9, 3, 0):
3344 adev->family = AMDGPU_FAMILY_RV;
3345 break;
3346 case IP_VERSION(10, 1, 10):
3347 case IP_VERSION(10, 1, 1):
3348 case IP_VERSION(10, 1, 2):
3349 case IP_VERSION(10, 1, 3):
3350 case IP_VERSION(10, 1, 4):
3351 case IP_VERSION(10, 3, 0):
3352 case IP_VERSION(10, 3, 2):
3353 case IP_VERSION(10, 3, 4):
3354 case IP_VERSION(10, 3, 5):
3355 adev->family = AMDGPU_FAMILY_NV;
3356 break;
3357 case IP_VERSION(10, 3, 1):
3358 adev->family = AMDGPU_FAMILY_VGH;
3359 adev->apu_flags |= AMD_APU_IS_VANGOGH;
3360 break;
3361 case IP_VERSION(10, 3, 3):
3362 adev->family = AMDGPU_FAMILY_YC;
3363 break;
3364 case IP_VERSION(10, 3, 6):
3365 adev->family = AMDGPU_FAMILY_GC_10_3_6;
3366 break;
3367 case IP_VERSION(10, 3, 7):
3368 adev->family = AMDGPU_FAMILY_GC_10_3_7;
3369 break;
3370 case IP_VERSION(11, 0, 0):
3371 case IP_VERSION(11, 0, 2):
3372 case IP_VERSION(11, 0, 3):
3373 adev->family = AMDGPU_FAMILY_GC_11_0_0;
3374 break;
3375 case IP_VERSION(11, 0, 1):
3376 case IP_VERSION(11, 0, 4):
3377 adev->family = AMDGPU_FAMILY_GC_11_0_1;
3378 break;
3379 case IP_VERSION(11, 5, 0):
3380 case IP_VERSION(11, 5, 1):
3381 case IP_VERSION(11, 5, 2):
3382 case IP_VERSION(11, 5, 3):
3383 case IP_VERSION(11, 5, 4):
3384 case IP_VERSION(11, 5, 6):
3385 adev->family = AMDGPU_FAMILY_GC_11_5_0;
3386 break;
3387 case IP_VERSION(11, 7, 0):
3388 case IP_VERSION(11, 7, 1):
3389 adev->family = AMDGPU_FAMILY_GC_11_5_4;
3390 break;
3391 case IP_VERSION(12, 0, 0):
3392 case IP_VERSION(12, 0, 1):
3393 case IP_VERSION(12, 1, 0):
3394 adev->family = AMDGPU_FAMILY_GC_12_0_0;
3395 break;
3396 default:
3397 return -EINVAL;
3398 }
3399
3400 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3401 case IP_VERSION(9, 1, 0):
3402 case IP_VERSION(9, 2, 2):
3403 case IP_VERSION(9, 3, 0):
3404 case IP_VERSION(10, 1, 3):
3405 case IP_VERSION(10, 1, 4):
3406 case IP_VERSION(10, 3, 1):
3407 case IP_VERSION(10, 3, 3):
3408 case IP_VERSION(10, 3, 6):
3409 case IP_VERSION(10, 3, 7):
3410 case IP_VERSION(11, 0, 1):
3411 case IP_VERSION(11, 0, 4):
3412 case IP_VERSION(11, 5, 0):
3413 case IP_VERSION(11, 5, 1):
3414 case IP_VERSION(11, 5, 2):
3415 case IP_VERSION(11, 5, 3):
3416 case IP_VERSION(11, 5, 4):
3417 case IP_VERSION(11, 5, 6):
3418 case IP_VERSION(11, 7, 0):
3419 case IP_VERSION(11, 7, 1):
3420 adev->flags |= AMD_IS_APU;
3421 break;
3422 default:
3423 break;
3424 }
3425
3426 /* set NBIO version */
3427 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
3428 case IP_VERSION(6, 1, 0):
3429 case IP_VERSION(6, 2, 0):
3430 adev->nbio.funcs = &nbio_v6_1_funcs;
3431 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
3432 break;
3433 case IP_VERSION(7, 0, 0):
3434 case IP_VERSION(7, 0, 1):
3435 case IP_VERSION(2, 5, 0):
3436 adev->nbio.funcs = &nbio_v7_0_funcs;
3437 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
3438 break;
3439 case IP_VERSION(7, 4, 0):
3440 case IP_VERSION(7, 4, 1):
3441 case IP_VERSION(7, 4, 4):
3442 adev->nbio.funcs = &nbio_v7_4_funcs;
3443 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
3444 break;
3445 case IP_VERSION(7, 9, 0):
3446 case IP_VERSION(7, 9, 1):
3447 adev->nbio.funcs = &nbio_v7_9_funcs;
3448 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg;
3449 break;
3450 case IP_VERSION(7, 11, 0):
3451 case IP_VERSION(7, 11, 1):
3452 case IP_VERSION(7, 11, 2):
3453 case IP_VERSION(7, 11, 3):
3454 adev->nbio.funcs = &nbio_v7_11_funcs;
3455 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg;
3456 break;
3457 case IP_VERSION(7, 2, 0):
3458 case IP_VERSION(7, 2, 1):
3459 case IP_VERSION(7, 3, 0):
3460 case IP_VERSION(7, 5, 0):
3461 case IP_VERSION(7, 5, 1):
3462 adev->nbio.funcs = &nbio_v7_2_funcs;
3463 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
3464 break;
3465 case IP_VERSION(2, 1, 1):
3466 case IP_VERSION(2, 3, 0):
3467 case IP_VERSION(2, 3, 1):
3468 case IP_VERSION(2, 3, 2):
3469 case IP_VERSION(3, 3, 0):
3470 case IP_VERSION(3, 3, 1):
3471 case IP_VERSION(3, 3, 2):
3472 case IP_VERSION(3, 3, 3):
3473 adev->nbio.funcs = &nbio_v2_3_funcs;
3474 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
3475 break;
3476 case IP_VERSION(4, 3, 0):
3477 case IP_VERSION(4, 3, 1):
3478 if (amdgpu_sriov_vf(adev))
3479 adev->nbio.funcs = &nbio_v4_3_sriov_funcs;
3480 else
3481 adev->nbio.funcs = &nbio_v4_3_funcs;
3482 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg;
3483 break;
3484 case IP_VERSION(7, 7, 0):
3485 case IP_VERSION(7, 7, 1):
3486 adev->nbio.funcs = &nbio_v7_7_funcs;
3487 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg;
3488 break;
3489 case IP_VERSION(6, 3, 1):
3490 case IP_VERSION(7, 11, 4):
3491 case IP_VERSION(7, 11, 5):
3492 adev->nbio.funcs = &nbif_v6_3_1_funcs;
3493 adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg;
3494 break;
3495 case IP_VERSION(6, 3, 2):
3496 adev->nbio.funcs = &nbio_v6_3_2_funcs;
3497 break;
3498 default:
3499 break;
3500 }
3501
3502 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) {
3503 case IP_VERSION(4, 0, 0):
3504 case IP_VERSION(4, 0, 1):
3505 case IP_VERSION(4, 1, 0):
3506 case IP_VERSION(4, 1, 1):
3507 case IP_VERSION(4, 1, 2):
3508 case IP_VERSION(4, 2, 0):
3509 case IP_VERSION(4, 2, 1):
3510 case IP_VERSION(4, 4, 0):
3511 case IP_VERSION(4, 4, 2):
3512 case IP_VERSION(4, 4, 5):
3513 adev->hdp.funcs = &hdp_v4_0_funcs;
3514 break;
3515 case IP_VERSION(5, 0, 0):
3516 case IP_VERSION(5, 0, 1):
3517 case IP_VERSION(5, 0, 2):
3518 case IP_VERSION(5, 0, 3):
3519 case IP_VERSION(5, 0, 4):
3520 case IP_VERSION(5, 2, 0):
3521 adev->hdp.funcs = &hdp_v5_0_funcs;
3522 break;
3523 case IP_VERSION(5, 2, 1):
3524 adev->hdp.funcs = &hdp_v5_2_funcs;
3525 break;
3526 case IP_VERSION(6, 0, 0):
3527 case IP_VERSION(6, 0, 1):
3528 case IP_VERSION(6, 1, 0):
3529 case IP_VERSION(6, 1, 1):
3530 case IP_VERSION(6, 4, 0):
3531 adev->hdp.funcs = &hdp_v6_0_funcs;
3532 break;
3533 case IP_VERSION(7, 0, 0):
3534 adev->hdp.funcs = &hdp_v7_0_funcs;
3535 break;
3536 default:
3537 break;
3538 }
3539
3540 switch (amdgpu_ip_version(adev, DF_HWIP, 0)) {
3541 case IP_VERSION(3, 6, 0):
3542 case IP_VERSION(3, 6, 1):
3543 case IP_VERSION(3, 6, 2):
3544 adev->df.funcs = &df_v3_6_funcs;
3545 break;
3546 case IP_VERSION(2, 1, 0):
3547 case IP_VERSION(2, 1, 1):
3548 case IP_VERSION(2, 5, 0):
3549 case IP_VERSION(3, 5, 1):
3550 case IP_VERSION(3, 5, 2):
3551 adev->df.funcs = &df_v1_7_funcs;
3552 break;
3553 case IP_VERSION(4, 3, 0):
3554 adev->df.funcs = &df_v4_3_funcs;
3555 break;
3556 case IP_VERSION(4, 6, 2):
3557 adev->df.funcs = &df_v4_6_2_funcs;
3558 break;
3559 case IP_VERSION(4, 15, 0):
3560 case IP_VERSION(4, 15, 1):
3561 adev->df.funcs = &df_v4_15_funcs;
3562 break;
3563 default:
3564 break;
3565 }
3566
3567 switch (amdgpu_ip_version(adev, SMUIO_HWIP, 0)) {
3568 case IP_VERSION(9, 0, 0):
3569 case IP_VERSION(9, 0, 1):
3570 case IP_VERSION(10, 0, 0):
3571 case IP_VERSION(10, 0, 1):
3572 case IP_VERSION(10, 0, 2):
3573 adev->smuio.funcs = &smuio_v9_0_funcs;
3574 break;
3575 case IP_VERSION(11, 0, 0):
3576 case IP_VERSION(11, 0, 2):
3577 case IP_VERSION(11, 0, 3):
3578 case IP_VERSION(11, 0, 4):
3579 case IP_VERSION(11, 0, 7):
3580 case IP_VERSION(11, 0, 8):
3581 adev->smuio.funcs = &smuio_v11_0_funcs;
3582 break;
3583 case IP_VERSION(11, 0, 6):
3584 case IP_VERSION(11, 0, 10):
3585 case IP_VERSION(11, 0, 11):
3586 case IP_VERSION(11, 5, 0):
3587 case IP_VERSION(11, 5, 2):
3588 case IP_VERSION(13, 0, 1):
3589 case IP_VERSION(13, 0, 9):
3590 case IP_VERSION(13, 0, 10):
3591 adev->smuio.funcs = &smuio_v11_0_6_funcs;
3592 break;
3593 case IP_VERSION(13, 0, 2):
3594 adev->smuio.funcs = &smuio_v13_0_funcs;
3595 break;
3596 case IP_VERSION(13, 0, 3):
3597 case IP_VERSION(13, 0, 11):
3598 adev->smuio.funcs = &smuio_v13_0_3_funcs;
3599 if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) {
3600 adev->flags |= AMD_IS_APU;
3601 }
3602 break;
3603 case IP_VERSION(13, 0, 6):
3604 case IP_VERSION(13, 0, 8):
3605 case IP_VERSION(14, 0, 0):
3606 case IP_VERSION(14, 0, 1):
3607 adev->smuio.funcs = &smuio_v13_0_6_funcs;
3608 break;
3609 case IP_VERSION(14, 0, 2):
3610 adev->smuio.funcs = &smuio_v14_0_2_funcs;
3611 break;
3612 case IP_VERSION(15, 0, 0):
3613 case IP_VERSION(15, 0, 5):
3614 adev->smuio.funcs = &smuio_v15_0_0_funcs;
3615 break;
3616 case IP_VERSION(15, 0, 8):
3617 adev->smuio.funcs = &smuio_v15_0_8_funcs;
3618 break;
3619 default:
3620 break;
3621 }
3622
3623 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {
3624 case IP_VERSION(6, 0, 0):
3625 case IP_VERSION(6, 0, 1):
3626 case IP_VERSION(6, 0, 2):
3627 case IP_VERSION(6, 0, 3):
3628 adev->lsdma.funcs = &lsdma_v6_0_funcs;
3629 break;
3630 case IP_VERSION(7, 0, 0):
3631 case IP_VERSION(7, 0, 1):
3632 adev->lsdma.funcs = &lsdma_v7_0_funcs;
3633 break;
3634 case IP_VERSION(7, 1, 0):
3635 adev->lsdma.funcs = &lsdma_v7_1_funcs;
3636 break;
3637 default:
3638 break;
3639 }
3640
3641 r = amdgpu_discovery_set_common_ip_blocks(adev);
3642 if (r)
3643 return r;
3644
3645 r = amdgpu_discovery_set_gmc_ip_blocks(adev);
3646 if (r)
3647 return r;
3648
3649 /* For SR-IOV, PSP needs to be initialized before IH */
3650 if (amdgpu_sriov_vf(adev)) {
3651 r = amdgpu_discovery_set_psp_ip_blocks(adev);
3652 if (r)
3653 return r;
3654 r = amdgpu_discovery_set_ih_ip_blocks(adev);
3655 if (r)
3656 return r;
3657 } else {
3658 r = amdgpu_discovery_set_ih_ip_blocks(adev);
3659 if (r)
3660 return r;
3661
3662 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
3663 r = amdgpu_discovery_set_psp_ip_blocks(adev);
3664 if (r)
3665 return r;
3666 }
3667 }
3668
3669 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
3670 r = amdgpu_discovery_set_smu_ip_blocks(adev);
3671 if (r)
3672 return r;
3673 }
3674
3675 r = amdgpu_discovery_set_display_ip_blocks(adev);
3676 if (r)
3677 return r;
3678
3679 r = amdgpu_discovery_set_gc_ip_blocks(adev);
3680 if (r)
3681 return r;
3682
3683 r = amdgpu_discovery_set_sdma_ip_blocks(adev);
3684 if (r)
3685 return r;
3686
3687 r = amdgpu_discovery_set_ras_ip_blocks(adev);
3688 if (r)
3689 return r;
3690
3691 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
3692 !amdgpu_sriov_vf(adev) &&
3693 amdgpu_dpm == 1) ||
3694 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO &&
3695 amdgpu_dpm == 1)) {
3696 r = amdgpu_discovery_set_smu_ip_blocks(adev);
3697 if (r)
3698 return r;
3699 }
3700
3701 r = amdgpu_discovery_set_mm_ip_blocks(adev);
3702 if (r)
3703 return r;
3704
3705 r = amdgpu_discovery_set_mes_ip_blocks(adev);
3706 if (r)
3707 return r;
3708
3709 r = amdgpu_discovery_set_vpe_ip_blocks(adev);
3710 if (r)
3711 return r;
3712
3713 r = amdgpu_discovery_set_umsch_mm_ip_blocks(adev);
3714 if (r)
3715 return r;
3716
3717 r = amdgpu_discovery_set_isp_ip_blocks(adev);
3718 if (r)
3719 return r;
3720 return 0;
3721 }
3722
amdgpu_discovery_get_gc_major_minor_version(struct amdgpu_device * adev,uint16_t * major,uint16_t * minor)3723 int amdgpu_discovery_get_gc_major_minor_version(struct amdgpu_device *adev,
3724 uint16_t *major, uint16_t *minor)
3725 {
3726 uint8_t *discovery_bin = adev->discovery.bin;
3727 struct table_info *info;
3728 union gc_info *gc_info;
3729 u16 offset;
3730
3731 if (!discovery_bin)
3732 return -EINVAL;
3733 if (amdgpu_discovery_get_table_info(adev, &info, GC))
3734 return -EINVAL;
3735
3736 offset = le16_to_cpu(info->offset);
3737 if (!offset)
3738 return -EINVAL;
3739
3740 gc_info = (union gc_info *)(discovery_bin + offset);
3741
3742 if (major)
3743 *major = le16_to_cpu(gc_info->v1.header.version_major);
3744 if (minor)
3745 *minor = le16_to_cpu(gc_info->v1.header.version_minor);
3746 return 0;
3747 }
3748