1 /* QLogic qedr NIC Driver
2 * Copyright (c) 2015-2016 QLogic Corporation
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #include <linux/module.h>
33 #include <rdma/ib_verbs.h>
34 #include <rdma/ib_addr.h>
35 #include <rdma/ib_user_verbs.h>
36 #include <rdma/iw_cm.h>
37 #include <rdma/ib_mad.h>
38 #include <linux/netdevice.h>
39 #include <linux/iommu.h>
40 #include <linux/pci.h>
41 #include <net/addrconf.h>
42
43 #include <linux/qed/qed_chain.h>
44 #include <linux/qed/qed_if.h>
45 #include "qedr.h"
46 #include "verbs.h"
47 #include <rdma/qedr-abi.h>
48 #include "qedr_iw_cm.h"
49
50 MODULE_DESCRIPTION("QLogic 40G/100G ROCE Driver");
51 MODULE_AUTHOR("QLogic Corporation");
52 MODULE_LICENSE("Dual BSD/GPL");
53
54 #define QEDR_WQ_MULTIPLIER_DFT (3)
55
qedr_ib_dispatch_event(struct qedr_dev * dev,u32 port_num,enum ib_event_type type)56 static void qedr_ib_dispatch_event(struct qedr_dev *dev, u32 port_num,
57 enum ib_event_type type)
58 {
59 struct ib_event ibev;
60
61 ibev.device = &dev->ibdev;
62 ibev.element.port_num = port_num;
63 ibev.event = type;
64
65 ib_dispatch_event(&ibev);
66 }
67
qedr_link_layer(struct ib_device * device,u32 port_num)68 static enum rdma_link_layer qedr_link_layer(struct ib_device *device,
69 u32 port_num)
70 {
71 return IB_LINK_LAYER_ETHERNET;
72 }
73
qedr_get_dev_fw_str(struct ib_device * ibdev,char * str)74 static void qedr_get_dev_fw_str(struct ib_device *ibdev, char *str)
75 {
76 struct qedr_dev *qedr = get_qedr_dev(ibdev);
77 u32 fw_ver = (u32)qedr->attr.fw_ver;
78
79 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d",
80 (fw_ver >> 24) & 0xFF, (fw_ver >> 16) & 0xFF,
81 (fw_ver >> 8) & 0xFF, fw_ver & 0xFF);
82 }
83
qedr_roce_port_immutable(struct ib_device * ibdev,u32 port_num,struct ib_port_immutable * immutable)84 static int qedr_roce_port_immutable(struct ib_device *ibdev, u32 port_num,
85 struct ib_port_immutable *immutable)
86 {
87 struct ib_port_attr attr;
88 int err;
89
90 err = qedr_query_port(ibdev, port_num, &attr);
91 if (err)
92 return err;
93
94 immutable->pkey_tbl_len = attr.pkey_tbl_len;
95 immutable->gid_tbl_len = attr.gid_tbl_len;
96 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE |
97 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
98 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
99
100 return 0;
101 }
102
qedr_iw_port_immutable(struct ib_device * ibdev,u32 port_num,struct ib_port_immutable * immutable)103 static int qedr_iw_port_immutable(struct ib_device *ibdev, u32 port_num,
104 struct ib_port_immutable *immutable)
105 {
106 struct ib_port_attr attr;
107 int err;
108
109 err = qedr_query_port(ibdev, port_num, &attr);
110 if (err)
111 return err;
112
113 immutable->gid_tbl_len = 1;
114 immutable->core_cap_flags = RDMA_CORE_PORT_IWARP;
115 immutable->max_mad_size = 0;
116
117 return 0;
118 }
119
120 /* QEDR sysfs interface */
hw_rev_show(struct device * device,struct device_attribute * attr,char * buf)121 static ssize_t hw_rev_show(struct device *device, struct device_attribute *attr,
122 char *buf)
123 {
124 struct qedr_dev *dev =
125 rdma_device_to_drv_device(device, struct qedr_dev, ibdev);
126
127 return sysfs_emit(buf, "0x%x\n", dev->attr.hw_ver);
128 }
129 static DEVICE_ATTR_RO(hw_rev);
130
hca_type_show(struct device * device,struct device_attribute * attr,char * buf)131 static ssize_t hca_type_show(struct device *device,
132 struct device_attribute *attr, char *buf)
133 {
134 struct qedr_dev *dev =
135 rdma_device_to_drv_device(device, struct qedr_dev, ibdev);
136
137 return sysfs_emit(buf, "FastLinQ QL%x %s\n", dev->pdev->device,
138 rdma_protocol_iwarp(&dev->ibdev, 1) ? "iWARP" :
139 "RoCE");
140 }
141 static DEVICE_ATTR_RO(hca_type);
142
143 static struct attribute *qedr_attributes[] = {
144 &dev_attr_hw_rev.attr,
145 &dev_attr_hca_type.attr,
146 NULL
147 };
148
149 static const struct attribute_group qedr_attr_group = {
150 .attrs = qedr_attributes,
151 };
152
153 static const struct ib_device_ops qedr_iw_dev_ops = {
154 .get_port_immutable = qedr_iw_port_immutable,
155 .iw_accept = qedr_iw_accept,
156 .iw_add_ref = qedr_iw_qp_add_ref,
157 .iw_connect = qedr_iw_connect,
158 .iw_create_listen = qedr_iw_create_listen,
159 .iw_destroy_listen = qedr_iw_destroy_listen,
160 .iw_get_qp = qedr_iw_get_qp,
161 .iw_reject = qedr_iw_reject,
162 .iw_rem_ref = qedr_iw_qp_rem_ref,
163 .query_gid = qedr_iw_query_gid,
164 };
165
qedr_iw_register_device(struct qedr_dev * dev)166 static int qedr_iw_register_device(struct qedr_dev *dev)
167 {
168 dev->ibdev.node_type = RDMA_NODE_RNIC;
169
170 ib_set_device_ops(&dev->ibdev, &qedr_iw_dev_ops);
171
172 memcpy(dev->ibdev.iw_ifname,
173 dev->ndev->name, sizeof(dev->ibdev.iw_ifname));
174
175 return 0;
176 }
177
178 static const struct ib_device_ops qedr_roce_dev_ops = {
179 .alloc_xrcd = qedr_alloc_xrcd,
180 .dealloc_xrcd = qedr_dealloc_xrcd,
181 .get_port_immutable = qedr_roce_port_immutable,
182 .query_pkey = qedr_query_pkey,
183 };
184
qedr_roce_register_device(struct qedr_dev * dev)185 static void qedr_roce_register_device(struct qedr_dev *dev)
186 {
187 dev->ibdev.node_type = RDMA_NODE_IB_CA;
188
189 ib_set_device_ops(&dev->ibdev, &qedr_roce_dev_ops);
190 }
191
192 static const struct ib_device_ops qedr_dev_ops = {
193 .owner = THIS_MODULE,
194 .driver_id = RDMA_DRIVER_QEDR,
195 .uverbs_abi_ver = QEDR_ABI_VERSION,
196
197 .alloc_mr = qedr_alloc_mr,
198 .alloc_pd = qedr_alloc_pd,
199 .alloc_ucontext = qedr_alloc_ucontext,
200 .create_ah = qedr_create_ah,
201 .create_cq = qedr_create_cq,
202 .create_qp = qedr_create_qp,
203 .create_srq = qedr_create_srq,
204 .dealloc_pd = qedr_dealloc_pd,
205 .dealloc_ucontext = qedr_dealloc_ucontext,
206 .dereg_mr = qedr_dereg_mr,
207 .destroy_ah = qedr_destroy_ah,
208 .destroy_cq = qedr_destroy_cq,
209 .destroy_qp = qedr_destroy_qp,
210 .destroy_srq = qedr_destroy_srq,
211 .device_group = &qedr_attr_group,
212 .get_dev_fw_str = qedr_get_dev_fw_str,
213 .get_dma_mr = qedr_get_dma_mr,
214 .get_link_layer = qedr_link_layer,
215 .map_mr_sg = qedr_map_mr_sg,
216 .mmap = qedr_mmap,
217 .mmap_free = qedr_mmap_free,
218 .modify_qp = qedr_modify_qp,
219 .modify_srq = qedr_modify_srq,
220 .poll_cq = qedr_poll_cq,
221 .post_recv = qedr_post_recv,
222 .post_send = qedr_post_send,
223 .post_srq_recv = qedr_post_srq_recv,
224 .process_mad = qedr_process_mad,
225 .query_device = qedr_query_device,
226 .query_port = qedr_query_port,
227 .query_qp = qedr_query_qp,
228 .query_srq = qedr_query_srq,
229 .reg_user_mr = qedr_reg_user_mr,
230 .req_notify_cq = qedr_arm_cq,
231
232 INIT_RDMA_OBJ_SIZE(ib_ah, qedr_ah, ibah),
233 INIT_RDMA_OBJ_SIZE(ib_cq, qedr_cq, ibcq),
234 INIT_RDMA_OBJ_SIZE(ib_pd, qedr_pd, ibpd),
235 INIT_RDMA_OBJ_SIZE(ib_qp, qedr_qp, ibqp),
236 INIT_RDMA_OBJ_SIZE(ib_srq, qedr_srq, ibsrq),
237 INIT_RDMA_OBJ_SIZE(ib_xrcd, qedr_xrcd, ibxrcd),
238 INIT_RDMA_OBJ_SIZE(ib_ucontext, qedr_ucontext, ibucontext),
239 };
240
qedr_register_device(struct qedr_dev * dev)241 static int qedr_register_device(struct qedr_dev *dev)
242 {
243 int rc;
244
245 dev->ibdev.node_guid = dev->attr.node_guid;
246 memcpy(dev->ibdev.node_desc, QEDR_NODE_DESC, sizeof(QEDR_NODE_DESC));
247
248 if (IS_IWARP(dev)) {
249 rc = qedr_iw_register_device(dev);
250 if (rc)
251 return rc;
252 } else {
253 qedr_roce_register_device(dev);
254 }
255
256 dev->ibdev.phys_port_cnt = 1;
257 dev->ibdev.num_comp_vectors = dev->num_cnq;
258 dev->ibdev.dev.parent = &dev->pdev->dev;
259
260 ib_set_device_ops(&dev->ibdev, &qedr_dev_ops);
261
262 rc = ib_device_set_netdev(&dev->ibdev, dev->ndev, 1);
263 if (rc)
264 return rc;
265
266 dma_set_max_seg_size(&dev->pdev->dev, UINT_MAX);
267 return ib_register_device(&dev->ibdev, "qedr%d", &dev->pdev->dev);
268 }
269
270 /* This function allocates fast-path status block memory */
qedr_alloc_mem_sb(struct qedr_dev * dev,struct qed_sb_info * sb_info,u16 sb_id)271 static int qedr_alloc_mem_sb(struct qedr_dev *dev,
272 struct qed_sb_info *sb_info, u16 sb_id)
273 {
274 struct status_block *sb_virt;
275 dma_addr_t sb_phys;
276 int rc;
277
278 sb_virt = dma_alloc_coherent(&dev->pdev->dev,
279 sizeof(*sb_virt), &sb_phys, GFP_KERNEL);
280 if (!sb_virt)
281 return -ENOMEM;
282
283 rc = dev->ops->common->sb_init(dev->cdev, sb_info,
284 sb_virt, sb_phys, sb_id,
285 QED_SB_TYPE_CNQ);
286 if (rc) {
287 pr_err("Status block initialization failed\n");
288 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_virt),
289 sb_virt, sb_phys);
290 return rc;
291 }
292
293 return 0;
294 }
295
qedr_free_mem_sb(struct qedr_dev * dev,struct qed_sb_info * sb_info,int sb_id)296 static void qedr_free_mem_sb(struct qedr_dev *dev,
297 struct qed_sb_info *sb_info, int sb_id)
298 {
299 if (sb_info->sb_virt) {
300 dev->ops->common->sb_release(dev->cdev, sb_info, sb_id,
301 QED_SB_TYPE_CNQ);
302 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_info->sb_virt),
303 (void *)sb_info->sb_virt, sb_info->sb_phys);
304 }
305 }
306
qedr_free_resources(struct qedr_dev * dev)307 static void qedr_free_resources(struct qedr_dev *dev)
308 {
309 int i;
310
311 if (IS_IWARP(dev))
312 destroy_workqueue(dev->iwarp_wq);
313
314 for (i = 0; i < dev->num_cnq; i++) {
315 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
316 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
317 }
318
319 kfree(dev->cnq_array);
320 kfree(dev->sb_array);
321 kfree(dev->sgid_tbl);
322 }
323
qedr_alloc_resources(struct qedr_dev * dev)324 static int qedr_alloc_resources(struct qedr_dev *dev)
325 {
326 struct qed_chain_init_params params = {
327 .mode = QED_CHAIN_MODE_PBL,
328 .intended_use = QED_CHAIN_USE_TO_CONSUME,
329 .cnt_type = QED_CHAIN_CNT_TYPE_U16,
330 .elem_size = sizeof(struct regpair *),
331 };
332 struct qedr_cnq *cnq;
333 __le16 *cons_pi;
334 int i, rc;
335
336 dev->sgid_tbl = kzalloc_objs(union ib_gid, QEDR_MAX_SGID);
337 if (!dev->sgid_tbl)
338 return -ENOMEM;
339
340 spin_lock_init(&dev->sgid_lock);
341 xa_init_flags(&dev->srqs, XA_FLAGS_LOCK_IRQ);
342
343 if (IS_IWARP(dev)) {
344 xa_init(&dev->qps);
345 dev->iwarp_wq = create_singlethread_workqueue("qedr_iwarpq");
346 if (!dev->iwarp_wq) {
347 rc = -ENOMEM;
348 goto err1;
349 }
350 }
351
352 /* Allocate Status blocks for CNQ */
353 dev->sb_array = kzalloc_objs(*dev->sb_array, dev->num_cnq);
354 if (!dev->sb_array) {
355 rc = -ENOMEM;
356 goto err_destroy_wq;
357 }
358
359 dev->cnq_array = kzalloc_objs(*dev->cnq_array, dev->num_cnq);
360 if (!dev->cnq_array) {
361 rc = -ENOMEM;
362 goto err2;
363 }
364
365 dev->sb_start = dev->ops->rdma_get_start_sb(dev->cdev);
366
367 /* Allocate CNQ PBLs */
368 params.num_elems = min_t(u32, QED_RDMA_MAX_CNQ_SIZE,
369 QEDR_ROCE_MAX_CNQ_SIZE);
370
371 for (i = 0; i < dev->num_cnq; i++) {
372 cnq = &dev->cnq_array[i];
373
374 rc = qedr_alloc_mem_sb(dev, &dev->sb_array[i],
375 dev->sb_start + i);
376 if (rc)
377 goto err3;
378
379 rc = dev->ops->common->chain_alloc(dev->cdev, &cnq->pbl,
380 ¶ms);
381 if (rc)
382 goto err4;
383
384 cnq->dev = dev;
385 cnq->sb = &dev->sb_array[i];
386 cons_pi = dev->sb_array[i].sb_virt->pi_array;
387 cnq->hw_cons_ptr = &cons_pi[QED_ROCE_PROTOCOL_INDEX];
388 cnq->index = i;
389 sprintf(cnq->name, "qedr%d@pci:%s", i, pci_name(dev->pdev));
390
391 DP_DEBUG(dev, QEDR_MSG_INIT, "cnq[%d].cons=%d\n",
392 i, qed_chain_get_cons_idx(&cnq->pbl));
393 }
394
395 return 0;
396 err4:
397 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
398 err3:
399 for (--i; i >= 0; i--) {
400 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
401 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
402 }
403 kfree(dev->cnq_array);
404 err2:
405 kfree(dev->sb_array);
406 err_destroy_wq:
407 if (IS_IWARP(dev))
408 destroy_workqueue(dev->iwarp_wq);
409 err1:
410 kfree(dev->sgid_tbl);
411 return rc;
412 }
413
qedr_pci_set_atomic(struct qedr_dev * dev,struct pci_dev * pdev)414 static void qedr_pci_set_atomic(struct qedr_dev *dev, struct pci_dev *pdev)
415 {
416 int rc = pci_enable_atomic_ops_to_root(pdev,
417 PCI_EXP_DEVCAP2_ATOMIC_COMP64);
418
419 if (rc) {
420 dev->atomic_cap = IB_ATOMIC_NONE;
421 DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability disabled\n");
422 } else {
423 dev->atomic_cap = IB_ATOMIC_GLOB;
424 DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability enabled\n");
425 }
426 }
427
428 static const struct qed_rdma_ops *qed_ops;
429
430 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
431
qedr_irq_handler(int irq,void * handle)432 static irqreturn_t qedr_irq_handler(int irq, void *handle)
433 {
434 u16 hw_comp_cons, sw_comp_cons;
435 struct qedr_cnq *cnq = handle;
436 struct regpair *cq_handle;
437 struct qedr_cq *cq;
438
439 qed_sb_ack(cnq->sb, IGU_INT_DISABLE, 0);
440
441 qed_sb_update_sb_idx(cnq->sb);
442
443 hw_comp_cons = le16_to_cpu(*cnq->hw_cons_ptr);
444 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
445
446 /* Align protocol-index and chain reads */
447 rmb();
448
449 while (sw_comp_cons != hw_comp_cons) {
450 cq_handle = (struct regpair *)qed_chain_consume(&cnq->pbl);
451 cq = (struct qedr_cq *)(uintptr_t)HILO_U64(cq_handle->hi,
452 cq_handle->lo);
453
454 if (cq == NULL) {
455 DP_ERR(cnq->dev,
456 "Received NULL CQ cq_handle->hi=%d cq_handle->lo=%d sw_comp_cons=%d hw_comp_cons=%d\n",
457 cq_handle->hi, cq_handle->lo, sw_comp_cons,
458 hw_comp_cons);
459
460 break;
461 }
462
463 if (cq->sig != QEDR_CQ_MAGIC_NUMBER) {
464 DP_ERR(cnq->dev,
465 "Problem with cq signature, cq_handle->hi=%d ch_handle->lo=%d cq=%p\n",
466 cq_handle->hi, cq_handle->lo, cq);
467 break;
468 }
469
470 cq->arm_flags = 0;
471
472 if (!cq->destroyed && cq->ibcq.comp_handler)
473 (*cq->ibcq.comp_handler)
474 (&cq->ibcq, cq->ibcq.cq_context);
475
476 /* The CQ's CNQ notification counter is checked before
477 * destroying the CQ in a busy-wait loop that waits for all of
478 * the CQ's CNQ interrupts to be processed. It is increased
479 * here, only after the completion handler, to ensure that
480 * the handler is not running when the CQ is destroyed.
481 */
482 cq->cnq_notif++;
483
484 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
485
486 cnq->n_comp++;
487 }
488
489 qed_ops->rdma_cnq_prod_update(cnq->dev->rdma_ctx, cnq->index,
490 sw_comp_cons);
491
492 qed_sb_ack(cnq->sb, IGU_INT_ENABLE, 1);
493
494 return IRQ_HANDLED;
495 }
496
qedr_sync_free_irqs(struct qedr_dev * dev)497 static void qedr_sync_free_irqs(struct qedr_dev *dev)
498 {
499 u32 vector;
500 u16 idx;
501 int i;
502
503 for (i = 0; i < dev->int_info.used_cnt; i++) {
504 if (dev->int_info.msix_cnt) {
505 idx = i * dev->num_hwfns + dev->affin_hwfn_idx;
506 vector = dev->int_info.msix[idx].vector;
507 free_irq(vector, &dev->cnq_array[i]);
508 }
509 }
510
511 dev->int_info.used_cnt = 0;
512 }
513
qedr_req_msix_irqs(struct qedr_dev * dev)514 static int qedr_req_msix_irqs(struct qedr_dev *dev)
515 {
516 int i, rc = 0;
517 u16 idx;
518
519 if (dev->num_cnq > dev->int_info.msix_cnt) {
520 DP_ERR(dev,
521 "Interrupt mismatch: %d CNQ queues > %d MSI-x vectors\n",
522 dev->num_cnq, dev->int_info.msix_cnt);
523 return -EINVAL;
524 }
525
526 for (i = 0; i < dev->num_cnq; i++) {
527 idx = i * dev->num_hwfns + dev->affin_hwfn_idx;
528 rc = request_irq(dev->int_info.msix[idx].vector,
529 qedr_irq_handler, 0, dev->cnq_array[i].name,
530 &dev->cnq_array[i]);
531 if (rc) {
532 DP_ERR(dev, "Request cnq %d irq failed\n", i);
533 qedr_sync_free_irqs(dev);
534 } else {
535 DP_DEBUG(dev, QEDR_MSG_INIT,
536 "Requested cnq irq for %s [entry %d]. Cookie is at %p\n",
537 dev->cnq_array[i].name, i,
538 &dev->cnq_array[i]);
539 dev->int_info.used_cnt++;
540 }
541 }
542
543 return rc;
544 }
545
qedr_setup_irqs(struct qedr_dev * dev)546 static int qedr_setup_irqs(struct qedr_dev *dev)
547 {
548 int rc;
549
550 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs\n");
551
552 /* Learn Interrupt configuration */
553 rc = dev->ops->rdma_set_rdma_int(dev->cdev, dev->num_cnq);
554 if (rc < 0)
555 return rc;
556
557 rc = dev->ops->rdma_get_rdma_int(dev->cdev, &dev->int_info);
558 if (rc) {
559 DP_DEBUG(dev, QEDR_MSG_INIT, "get_rdma_int failed\n");
560 return rc;
561 }
562
563 if (dev->int_info.msix_cnt) {
564 DP_DEBUG(dev, QEDR_MSG_INIT, "rdma msix_cnt = %d\n",
565 dev->int_info.msix_cnt);
566 rc = qedr_req_msix_irqs(dev);
567 if (rc)
568 return rc;
569 }
570
571 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs succeeded\n");
572
573 return 0;
574 }
575
qedr_set_device_attr(struct qedr_dev * dev)576 static int qedr_set_device_attr(struct qedr_dev *dev)
577 {
578 struct qed_rdma_device *qed_attr;
579 struct qedr_device_attr *attr;
580 u32 page_size;
581
582 /* Part 1 - query core capabilities */
583 qed_attr = dev->ops->rdma_query_device(dev->rdma_ctx);
584
585 /* Part 2 - check capabilities */
586 page_size = ~qed_attr->page_size_caps + 1;
587 if (page_size > PAGE_SIZE) {
588 DP_ERR(dev,
589 "Kernel PAGE_SIZE is %ld which is smaller than minimum page size (%d) required by qedr\n",
590 PAGE_SIZE, page_size);
591 return -ENODEV;
592 }
593
594 /* Part 3 - copy and update capabilities */
595 attr = &dev->attr;
596 attr->vendor_id = qed_attr->vendor_id;
597 attr->vendor_part_id = qed_attr->vendor_part_id;
598 attr->hw_ver = qed_attr->hw_ver;
599 attr->fw_ver = qed_attr->fw_ver;
600 attr->node_guid = qed_attr->node_guid;
601 attr->sys_image_guid = qed_attr->sys_image_guid;
602 attr->max_cnq = qed_attr->max_cnq;
603 attr->max_sge = qed_attr->max_sge;
604 attr->max_inline = qed_attr->max_inline;
605 attr->max_sqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_SQE);
606 attr->max_rqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_RQE);
607 attr->max_qp_resp_rd_atomic_resc = qed_attr->max_qp_resp_rd_atomic_resc;
608 attr->max_qp_req_rd_atomic_resc = qed_attr->max_qp_req_rd_atomic_resc;
609 attr->max_dev_resp_rd_atomic_resc =
610 qed_attr->max_dev_resp_rd_atomic_resc;
611 attr->max_cq = qed_attr->max_cq;
612 attr->max_qp = qed_attr->max_qp;
613 attr->max_mr = qed_attr->max_mr;
614 attr->max_mr_size = qed_attr->max_mr_size;
615 attr->max_cqe = min_t(u64, qed_attr->max_cqe, QEDR_MAX_CQES);
616 attr->max_mw = qed_attr->max_mw;
617 attr->max_mr_mw_fmr_pbl = qed_attr->max_mr_mw_fmr_pbl;
618 attr->max_mr_mw_fmr_size = qed_attr->max_mr_mw_fmr_size;
619 attr->max_pd = qed_attr->max_pd;
620 attr->max_ah = qed_attr->max_ah;
621 attr->max_pkey = qed_attr->max_pkey;
622 attr->max_srq = qed_attr->max_srq;
623 attr->max_srq_wr = qed_attr->max_srq_wr;
624 attr->dev_caps = qed_attr->dev_caps;
625 attr->page_size_caps = qed_attr->page_size_caps;
626 attr->dev_ack_delay = qed_attr->dev_ack_delay;
627 attr->reserved_lkey = qed_attr->reserved_lkey;
628 attr->bad_pkey_counter = qed_attr->bad_pkey_counter;
629 attr->max_stats_queues = qed_attr->max_stats_queues;
630
631 return 0;
632 }
633
qedr_unaffiliated_event(void * context,u8 event_code)634 static void qedr_unaffiliated_event(void *context, u8 event_code)
635 {
636 pr_err("unaffiliated event not implemented yet\n");
637 }
638
qedr_affiliated_event(void * context,u8 e_code,void * fw_handle)639 static void qedr_affiliated_event(void *context, u8 e_code, void *fw_handle)
640 {
641 #define EVENT_TYPE_NOT_DEFINED 0
642 #define EVENT_TYPE_CQ 1
643 #define EVENT_TYPE_QP 2
644 #define EVENT_TYPE_SRQ 3
645 struct qedr_dev *dev = (struct qedr_dev *)context;
646 struct regpair *async_handle = (struct regpair *)fw_handle;
647 u64 roce_handle64 = ((u64) async_handle->hi << 32) + async_handle->lo;
648 u8 event_type = EVENT_TYPE_NOT_DEFINED;
649 struct ib_event event;
650 struct ib_srq *ibsrq;
651 struct qedr_srq *srq;
652 unsigned long flags;
653 struct ib_cq *ibcq;
654 struct ib_qp *ibqp;
655 struct qedr_cq *cq;
656 struct qedr_qp *qp;
657 u16 srq_id;
658
659 if (IS_ROCE(dev)) {
660 switch (e_code) {
661 case ROCE_ASYNC_EVENT_CQ_OVERFLOW_ERR:
662 event.event = IB_EVENT_CQ_ERR;
663 event_type = EVENT_TYPE_CQ;
664 break;
665 case ROCE_ASYNC_EVENT_SQ_DRAINED:
666 event.event = IB_EVENT_SQ_DRAINED;
667 event_type = EVENT_TYPE_QP;
668 break;
669 case ROCE_ASYNC_EVENT_QP_CATASTROPHIC_ERR:
670 event.event = IB_EVENT_QP_FATAL;
671 event_type = EVENT_TYPE_QP;
672 break;
673 case ROCE_ASYNC_EVENT_LOCAL_INVALID_REQUEST_ERR:
674 event.event = IB_EVENT_QP_REQ_ERR;
675 event_type = EVENT_TYPE_QP;
676 break;
677 case ROCE_ASYNC_EVENT_LOCAL_ACCESS_ERR:
678 event.event = IB_EVENT_QP_ACCESS_ERR;
679 event_type = EVENT_TYPE_QP;
680 break;
681 case ROCE_ASYNC_EVENT_SRQ_LIMIT:
682 event.event = IB_EVENT_SRQ_LIMIT_REACHED;
683 event_type = EVENT_TYPE_SRQ;
684 break;
685 case ROCE_ASYNC_EVENT_SRQ_EMPTY:
686 event.event = IB_EVENT_SRQ_ERR;
687 event_type = EVENT_TYPE_SRQ;
688 break;
689 case ROCE_ASYNC_EVENT_XRC_DOMAIN_ERR:
690 event.event = IB_EVENT_QP_ACCESS_ERR;
691 event_type = EVENT_TYPE_QP;
692 break;
693 case ROCE_ASYNC_EVENT_INVALID_XRCETH_ERR:
694 event.event = IB_EVENT_QP_ACCESS_ERR;
695 event_type = EVENT_TYPE_QP;
696 break;
697 case ROCE_ASYNC_EVENT_XRC_SRQ_CATASTROPHIC_ERR:
698 event.event = IB_EVENT_CQ_ERR;
699 event_type = EVENT_TYPE_CQ;
700 break;
701 default:
702 DP_ERR(dev, "unsupported event %d on handle=%llx\n",
703 e_code, roce_handle64);
704 }
705 } else {
706 switch (e_code) {
707 case QED_IWARP_EVENT_SRQ_LIMIT:
708 event.event = IB_EVENT_SRQ_LIMIT_REACHED;
709 event_type = EVENT_TYPE_SRQ;
710 break;
711 case QED_IWARP_EVENT_SRQ_EMPTY:
712 event.event = IB_EVENT_SRQ_ERR;
713 event_type = EVENT_TYPE_SRQ;
714 break;
715 default:
716 DP_ERR(dev, "unsupported event %d on handle=%llx\n", e_code,
717 roce_handle64);
718 }
719 }
720 switch (event_type) {
721 case EVENT_TYPE_CQ:
722 cq = (struct qedr_cq *)(uintptr_t)roce_handle64;
723 if (cq) {
724 ibcq = &cq->ibcq;
725 if (ibcq->event_handler) {
726 event.device = ibcq->device;
727 event.element.cq = ibcq;
728 ibcq->event_handler(&event, ibcq->cq_context);
729 }
730 } else {
731 WARN(1,
732 "Error: CQ event with NULL pointer ibcq. Handle=%llx\n",
733 roce_handle64);
734 }
735 DP_ERR(dev, "CQ event %d on handle %p\n", e_code, cq);
736 break;
737 case EVENT_TYPE_QP:
738 qp = (struct qedr_qp *)(uintptr_t)roce_handle64;
739 if (qp) {
740 ibqp = &qp->ibqp;
741 if (ibqp->event_handler) {
742 event.device = ibqp->device;
743 event.element.qp = ibqp;
744 ibqp->event_handler(&event, ibqp->qp_context);
745 }
746 } else {
747 WARN(1,
748 "Error: QP event with NULL pointer ibqp. Handle=%llx\n",
749 roce_handle64);
750 }
751 DP_ERR(dev, "QP event %d on handle %p\n", e_code, qp);
752 break;
753 case EVENT_TYPE_SRQ:
754 srq_id = (u16)roce_handle64;
755 xa_lock_irqsave(&dev->srqs, flags);
756 srq = xa_load(&dev->srqs, srq_id);
757 if (srq) {
758 ibsrq = &srq->ibsrq;
759 if (ibsrq->event_handler) {
760 event.device = ibsrq->device;
761 event.element.srq = ibsrq;
762 ibsrq->event_handler(&event,
763 ibsrq->srq_context);
764 }
765 } else {
766 DP_NOTICE(dev,
767 "SRQ event with NULL pointer ibsrq. Handle=%llx\n",
768 roce_handle64);
769 }
770 xa_unlock_irqrestore(&dev->srqs, flags);
771 DP_NOTICE(dev, "SRQ event %d on handle %p\n", e_code, srq);
772 break;
773 default:
774 break;
775 }
776 }
777
qedr_init_hw(struct qedr_dev * dev)778 static int qedr_init_hw(struct qedr_dev *dev)
779 {
780 struct qed_rdma_add_user_out_params out_params;
781 struct qed_rdma_start_in_params *in_params;
782 struct qed_rdma_cnq_params *cur_pbl;
783 struct qed_rdma_events events;
784 dma_addr_t p_phys_table;
785 u32 page_cnt;
786 int rc = 0;
787 int i;
788
789 in_params = kzalloc_obj(*in_params);
790 if (!in_params) {
791 rc = -ENOMEM;
792 goto out;
793 }
794
795 in_params->desired_cnq = dev->num_cnq;
796 for (i = 0; i < dev->num_cnq; i++) {
797 cur_pbl = &in_params->cnq_pbl_list[i];
798
799 page_cnt = qed_chain_get_page_cnt(&dev->cnq_array[i].pbl);
800 cur_pbl->num_pbl_pages = page_cnt;
801
802 p_phys_table = qed_chain_get_pbl_phys(&dev->cnq_array[i].pbl);
803 cur_pbl->pbl_ptr = (u64)p_phys_table;
804 }
805
806 events.affiliated_event = qedr_affiliated_event;
807 events.unaffiliated_event = qedr_unaffiliated_event;
808 events.context = dev;
809
810 in_params->events = &events;
811 in_params->cq_mode = QED_RDMA_CQ_MODE_32_BITS;
812 in_params->max_mtu = dev->ndev->mtu;
813 dev->iwarp_max_mtu = dev->ndev->mtu;
814 ether_addr_copy(&in_params->mac_addr[0], dev->ndev->dev_addr);
815
816 rc = dev->ops->rdma_init(dev->cdev, in_params);
817 if (rc)
818 goto out;
819
820 rc = dev->ops->rdma_add_user(dev->rdma_ctx, &out_params);
821 if (rc)
822 goto out;
823
824 dev->db_addr = out_params.dpi_addr;
825 dev->db_phys_addr = out_params.dpi_phys_addr;
826 dev->db_size = out_params.dpi_size;
827 dev->dpi = out_params.dpi;
828
829 rc = qedr_set_device_attr(dev);
830 out:
831 kfree(in_params);
832 if (rc)
833 DP_ERR(dev, "Init HW Failed rc = %d\n", rc);
834
835 return rc;
836 }
837
qedr_stop_hw(struct qedr_dev * dev)838 static void qedr_stop_hw(struct qedr_dev *dev)
839 {
840 dev->ops->rdma_remove_user(dev->rdma_ctx, dev->dpi);
841 dev->ops->rdma_stop(dev->rdma_ctx);
842 }
843
qedr_add(struct qed_dev * cdev,struct pci_dev * pdev,struct net_device * ndev)844 static struct qedr_dev *qedr_add(struct qed_dev *cdev, struct pci_dev *pdev,
845 struct net_device *ndev)
846 {
847 struct qed_dev_rdma_info dev_info;
848 struct qedr_dev *dev;
849 int rc = 0;
850
851 dev = ib_alloc_device(qedr_dev, ibdev);
852 if (!dev) {
853 pr_err("Unable to allocate ib device\n");
854 return NULL;
855 }
856
857 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr add device called\n");
858
859 dev->pdev = pdev;
860 dev->ndev = ndev;
861 dev->cdev = cdev;
862
863 qed_ops = qed_get_rdma_ops();
864 if (!qed_ops) {
865 DP_ERR(dev, "Failed to get qed roce operations\n");
866 goto init_err;
867 }
868
869 dev->ops = qed_ops;
870 rc = qed_ops->fill_dev_info(cdev, &dev_info);
871 if (rc)
872 goto init_err;
873
874 dev->user_dpm_enabled = dev_info.user_dpm_enabled;
875 dev->rdma_type = dev_info.rdma_type;
876 dev->num_hwfns = dev_info.common.num_hwfns;
877
878 if (IS_IWARP(dev) && QEDR_IS_CMT(dev)) {
879 rc = dev->ops->iwarp_set_engine_affin(cdev, false);
880 if (rc) {
881 DP_ERR(dev, "iWARP is disabled over a 100g device Enabling it may impact L2 performance. To enable it run devlink dev param set <dev> name iwarp_cmt value true cmode runtime\n");
882 goto init_err;
883 }
884 }
885 dev->affin_hwfn_idx = dev->ops->common->get_affin_hwfn_idx(cdev);
886
887 dev->rdma_ctx = dev->ops->rdma_get_rdma_ctx(cdev);
888
889 dev->num_cnq = dev->ops->rdma_get_min_cnq_msix(cdev);
890 if (!dev->num_cnq) {
891 DP_ERR(dev, "Failed. At least one CNQ is required.\n");
892 rc = -ENOMEM;
893 goto init_err;
894 }
895
896 dev->wq_multiplier = QEDR_WQ_MULTIPLIER_DFT;
897
898 qedr_pci_set_atomic(dev, pdev);
899
900 rc = qedr_alloc_resources(dev);
901 if (rc)
902 goto init_err;
903
904 rc = qedr_init_hw(dev);
905 if (rc)
906 goto alloc_err;
907
908 rc = qedr_setup_irqs(dev);
909 if (rc)
910 goto irq_err;
911
912 rc = qedr_register_device(dev);
913 if (rc) {
914 DP_ERR(dev, "Unable to allocate register device\n");
915 goto reg_err;
916 }
917
918 if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
919 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE);
920
921 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr driver loaded successfully\n");
922 return dev;
923
924 reg_err:
925 qedr_sync_free_irqs(dev);
926 irq_err:
927 qedr_stop_hw(dev);
928 alloc_err:
929 qedr_free_resources(dev);
930 init_err:
931 ib_dealloc_device(&dev->ibdev);
932 DP_ERR(dev, "qedr driver load failed rc=%d\n", rc);
933
934 return NULL;
935 }
936
qedr_remove(struct qedr_dev * dev)937 static void qedr_remove(struct qedr_dev *dev)
938 {
939 /* First unregister with stack to stop all the active traffic
940 * of the registered clients.
941 */
942 ib_unregister_device(&dev->ibdev);
943
944 qedr_stop_hw(dev);
945 qedr_sync_free_irqs(dev);
946 qedr_free_resources(dev);
947
948 if (IS_IWARP(dev) && QEDR_IS_CMT(dev))
949 dev->ops->iwarp_set_engine_affin(dev->cdev, true);
950
951 ib_dealloc_device(&dev->ibdev);
952 }
953
qedr_close(struct qedr_dev * dev)954 static void qedr_close(struct qedr_dev *dev)
955 {
956 if (test_and_clear_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
957 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ERR);
958 }
959
qedr_shutdown(struct qedr_dev * dev)960 static void qedr_shutdown(struct qedr_dev *dev)
961 {
962 qedr_close(dev);
963 qedr_remove(dev);
964 }
965
qedr_open(struct qedr_dev * dev)966 static void qedr_open(struct qedr_dev *dev)
967 {
968 if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
969 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE);
970 }
971
qedr_mac_address_change(struct qedr_dev * dev)972 static void qedr_mac_address_change(struct qedr_dev *dev)
973 {
974 union ib_gid *sgid = &dev->sgid_tbl[0];
975 u8 guid[8], mac_addr[6];
976 int rc;
977
978 /* Update SGID */
979 ether_addr_copy(&mac_addr[0], dev->ndev->dev_addr);
980 guid[0] = mac_addr[0] ^ 2;
981 guid[1] = mac_addr[1];
982 guid[2] = mac_addr[2];
983 guid[3] = 0xff;
984 guid[4] = 0xfe;
985 guid[5] = mac_addr[3];
986 guid[6] = mac_addr[4];
987 guid[7] = mac_addr[5];
988 sgid->global.subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
989 memcpy(&sgid->raw[8], guid, sizeof(guid));
990
991 /* Update LL2 */
992 rc = dev->ops->ll2_set_mac_filter(dev->cdev,
993 dev->gsi_ll2_mac_address,
994 dev->ndev->dev_addr);
995
996 ether_addr_copy(dev->gsi_ll2_mac_address, dev->ndev->dev_addr);
997
998 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_GID_CHANGE);
999
1000 if (rc)
1001 DP_ERR(dev, "Error updating mac filter\n");
1002 }
1003
1004 /* event handling via NIC driver ensures that all the NIC specific
1005 * initialization done before RoCE driver notifies
1006 * event to stack.
1007 */
qedr_notify(struct qedr_dev * dev,enum qede_rdma_event event)1008 static void qedr_notify(struct qedr_dev *dev, enum qede_rdma_event event)
1009 {
1010 switch (event) {
1011 case QEDE_UP:
1012 qedr_open(dev);
1013 break;
1014 case QEDE_DOWN:
1015 qedr_close(dev);
1016 break;
1017 case QEDE_CLOSE:
1018 qedr_shutdown(dev);
1019 break;
1020 case QEDE_CHANGE_ADDR:
1021 qedr_mac_address_change(dev);
1022 break;
1023 case QEDE_CHANGE_MTU:
1024 if (rdma_protocol_iwarp(&dev->ibdev, 1))
1025 if (dev->ndev->mtu != dev->iwarp_max_mtu)
1026 DP_NOTICE(dev,
1027 "Mtu was changed from %d to %d. This will not take affect for iWARP until qedr is reloaded\n",
1028 dev->iwarp_max_mtu, dev->ndev->mtu);
1029 break;
1030 default:
1031 pr_err("Event not supported\n");
1032 }
1033 }
1034
1035 static struct qedr_driver qedr_drv = {
1036 .name = "qedr_driver",
1037 .add = qedr_add,
1038 .remove = qedr_remove,
1039 .notify = qedr_notify,
1040 };
1041
qedr_init_module(void)1042 static int __init qedr_init_module(void)
1043 {
1044 return qede_rdma_register_driver(&qedr_drv);
1045 }
1046
qedr_exit_module(void)1047 static void __exit qedr_exit_module(void)
1048 {
1049 qede_rdma_unregister_driver(&qedr_drv);
1050 }
1051
1052 module_init(qedr_init_module);
1053 module_exit(qedr_exit_module);
1054