1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * HiSilicon SoC MN uncore Hardware event counters support
4 *
5 * Copyright (c) 2025 HiSilicon Technologies Co., Ltd.
6 */
7 #include <linux/cpuhotplug.h>
8 #include <linux/interrupt.h>
9 #include <linux/iopoll.h>
10 #include <linux/irq.h>
11 #include <linux/list.h>
12 #include <linux/property.h>
13
14 #include "hisi_uncore_pmu.h"
15
16 /* MN register definition */
17 #define HISI_MN_DYNAMIC_CTRL_REG 0x400
18 #define HISI_MN_DYNAMIC_CTRL_EN BIT(0)
19 #define HISI_MN_PERF_CTRL_REG 0x408
20 #define HISI_MN_PERF_CTRL_EN BIT(6)
21 #define HISI_MN_INT_MASK_REG 0x800
22 #define HISI_MN_INT_STATUS_REG 0x808
23 #define HISI_MN_INT_CLEAR_REG 0x80C
24 #define HISI_MN_EVENT_CTRL_REG 0x1C00
25 #define HISI_MN_VERSION_REG 0x1C04
26 #define HISI_MN_EVTYPE0_REG 0x1d00
27 #define HISI_MN_EVTYPE_MASK GENMASK(7, 0)
28 #define HISI_MN_CNTR0_REG 0x1e00
29 #define HISI_MN_EVTYPE_REGn(evtype0, n) ((evtype0) + (n) * 4)
30 #define HISI_MN_CNTR_REGn(cntr0, n) ((cntr0) + (n) * 8)
31
32 #define HISI_MN_NR_COUNTERS 4
33 #define HISI_MN_TIMEOUT_US 500U
34
35 struct hisi_mn_pmu_regs {
36 u32 version;
37 u32 dyn_ctrl;
38 u32 perf_ctrl;
39 u32 int_mask;
40 u32 int_clear;
41 u32 int_status;
42 u32 event_ctrl;
43 u32 event_type0;
44 u32 event_cntr0;
45 };
46
47 /*
48 * Each event request takes a certain amount of time to complete. If
49 * we counting the latency related event, we need to wait for the all
50 * requests complete. Otherwise, the value of counter is slightly larger.
51 */
hisi_mn_pmu_counter_flush(struct hisi_pmu * mn_pmu)52 static void hisi_mn_pmu_counter_flush(struct hisi_pmu *mn_pmu)
53 {
54 struct hisi_mn_pmu_regs *reg_info = mn_pmu->dev_info->private;
55 int ret;
56 u32 val;
57
58 val = readl(mn_pmu->base + reg_info->dyn_ctrl);
59 val |= HISI_MN_DYNAMIC_CTRL_EN;
60 writel(val, mn_pmu->base + reg_info->dyn_ctrl);
61
62 ret = readl_poll_timeout_atomic(mn_pmu->base + reg_info->dyn_ctrl,
63 val, !(val & HISI_MN_DYNAMIC_CTRL_EN),
64 1, HISI_MN_TIMEOUT_US);
65 if (ret)
66 dev_warn(mn_pmu->dev, "Counter flush timeout\n");
67 }
68
hisi_mn_pmu_read_counter(struct hisi_pmu * mn_pmu,struct hw_perf_event * hwc)69 static u64 hisi_mn_pmu_read_counter(struct hisi_pmu *mn_pmu,
70 struct hw_perf_event *hwc)
71 {
72 struct hisi_mn_pmu_regs *reg_info = mn_pmu->dev_info->private;
73
74 return readq(mn_pmu->base + HISI_MN_CNTR_REGn(reg_info->event_cntr0, hwc->idx));
75 }
76
hisi_mn_pmu_write_counter(struct hisi_pmu * mn_pmu,struct hw_perf_event * hwc,u64 val)77 static void hisi_mn_pmu_write_counter(struct hisi_pmu *mn_pmu,
78 struct hw_perf_event *hwc, u64 val)
79 {
80 struct hisi_mn_pmu_regs *reg_info = mn_pmu->dev_info->private;
81
82 writeq(val, mn_pmu->base + HISI_MN_CNTR_REGn(reg_info->event_cntr0, hwc->idx));
83 }
84
hisi_mn_pmu_write_evtype(struct hisi_pmu * mn_pmu,int idx,u32 type)85 static void hisi_mn_pmu_write_evtype(struct hisi_pmu *mn_pmu, int idx, u32 type)
86 {
87 struct hisi_mn_pmu_regs *reg_info = mn_pmu->dev_info->private;
88 u32 val;
89
90 /*
91 * Select the appropriate event select register.
92 * There are 2 32-bit event select registers for the
93 * 8 hardware counters, each event code is 8-bit wide.
94 */
95 val = readl(mn_pmu->base + HISI_MN_EVTYPE_REGn(reg_info->event_type0, idx / 4));
96 val &= ~(HISI_MN_EVTYPE_MASK << HISI_PMU_EVTYPE_SHIFT(idx));
97 val |= (type << HISI_PMU_EVTYPE_SHIFT(idx));
98 writel(val, mn_pmu->base + HISI_MN_EVTYPE_REGn(reg_info->event_type0, idx / 4));
99 }
100
hisi_mn_pmu_start_counters(struct hisi_pmu * mn_pmu)101 static void hisi_mn_pmu_start_counters(struct hisi_pmu *mn_pmu)
102 {
103 struct hisi_mn_pmu_regs *reg_info = mn_pmu->dev_info->private;
104 u32 val;
105
106 val = readl(mn_pmu->base + reg_info->perf_ctrl);
107 val |= HISI_MN_PERF_CTRL_EN;
108 writel(val, mn_pmu->base + reg_info->perf_ctrl);
109 }
110
hisi_mn_pmu_stop_counters(struct hisi_pmu * mn_pmu)111 static void hisi_mn_pmu_stop_counters(struct hisi_pmu *mn_pmu)
112 {
113 struct hisi_mn_pmu_regs *reg_info = mn_pmu->dev_info->private;
114 u32 val;
115
116 val = readl(mn_pmu->base + reg_info->perf_ctrl);
117 val &= ~HISI_MN_PERF_CTRL_EN;
118 writel(val, mn_pmu->base + reg_info->perf_ctrl);
119
120 hisi_mn_pmu_counter_flush(mn_pmu);
121 }
122
hisi_mn_pmu_enable_counter(struct hisi_pmu * mn_pmu,struct hw_perf_event * hwc)123 static void hisi_mn_pmu_enable_counter(struct hisi_pmu *mn_pmu,
124 struct hw_perf_event *hwc)
125 {
126 struct hisi_mn_pmu_regs *reg_info = mn_pmu->dev_info->private;
127 u32 val;
128
129 val = readl(mn_pmu->base + reg_info->event_ctrl);
130 val |= BIT(hwc->idx);
131 writel(val, mn_pmu->base + reg_info->event_ctrl);
132 }
133
hisi_mn_pmu_disable_counter(struct hisi_pmu * mn_pmu,struct hw_perf_event * hwc)134 static void hisi_mn_pmu_disable_counter(struct hisi_pmu *mn_pmu,
135 struct hw_perf_event *hwc)
136 {
137 struct hisi_mn_pmu_regs *reg_info = mn_pmu->dev_info->private;
138 u32 val;
139
140 val = readl(mn_pmu->base + reg_info->event_ctrl);
141 val &= ~BIT(hwc->idx);
142 writel(val, mn_pmu->base + reg_info->event_ctrl);
143 }
144
hisi_mn_pmu_enable_counter_int(struct hisi_pmu * mn_pmu,struct hw_perf_event * hwc)145 static void hisi_mn_pmu_enable_counter_int(struct hisi_pmu *mn_pmu,
146 struct hw_perf_event *hwc)
147 {
148 struct hisi_mn_pmu_regs *reg_info = mn_pmu->dev_info->private;
149 u32 val;
150
151 val = readl(mn_pmu->base + reg_info->int_mask);
152 val &= ~BIT(hwc->idx);
153 writel(val, mn_pmu->base + reg_info->int_mask);
154 }
155
hisi_mn_pmu_disable_counter_int(struct hisi_pmu * mn_pmu,struct hw_perf_event * hwc)156 static void hisi_mn_pmu_disable_counter_int(struct hisi_pmu *mn_pmu,
157 struct hw_perf_event *hwc)
158 {
159 struct hisi_mn_pmu_regs *reg_info = mn_pmu->dev_info->private;
160 u32 val;
161
162 val = readl(mn_pmu->base + reg_info->int_mask);
163 val |= BIT(hwc->idx);
164 writel(val, mn_pmu->base + reg_info->int_mask);
165 }
166
hisi_mn_pmu_get_int_status(struct hisi_pmu * mn_pmu)167 static u32 hisi_mn_pmu_get_int_status(struct hisi_pmu *mn_pmu)
168 {
169 struct hisi_mn_pmu_regs *reg_info = mn_pmu->dev_info->private;
170
171 return readl(mn_pmu->base + reg_info->int_status);
172 }
173
hisi_mn_pmu_clear_int_status(struct hisi_pmu * mn_pmu,int idx)174 static void hisi_mn_pmu_clear_int_status(struct hisi_pmu *mn_pmu, int idx)
175 {
176 struct hisi_mn_pmu_regs *reg_info = mn_pmu->dev_info->private;
177
178 writel(BIT(idx), mn_pmu->base + reg_info->int_clear);
179 }
180
181 static struct attribute *hisi_mn_pmu_format_attr[] = {
182 HISI_PMU_FORMAT_ATTR(event, "config:0-7"),
183 NULL
184 };
185
186 static const struct attribute_group hisi_mn_pmu_format_group = {
187 .name = "format",
188 .attrs = hisi_mn_pmu_format_attr,
189 };
190
191 static struct attribute *hisi_mn_pmu_events_attr_v1[] = {
192 HISI_PMU_EVENT_ATTR(req_eobarrier_num, 0x00),
193 HISI_PMU_EVENT_ATTR(req_ecbarrier_num, 0x01),
194 HISI_PMU_EVENT_ATTR(req_dvmop_num, 0x02),
195 HISI_PMU_EVENT_ATTR(req_dvmsync_num, 0x03),
196 HISI_PMU_EVENT_ATTR(req_retry_num, 0x04),
197 HISI_PMU_EVENT_ATTR(req_writenosnp_num, 0x05),
198 HISI_PMU_EVENT_ATTR(req_readnosnp_num, 0x06),
199 HISI_PMU_EVENT_ATTR(snp_dvm_num, 0x07),
200 HISI_PMU_EVENT_ATTR(snp_dvmsync_num, 0x08),
201 HISI_PMU_EVENT_ATTR(l3t_req_dvm_num, 0x09),
202 HISI_PMU_EVENT_ATTR(l3t_req_dvmsync_num, 0x0A),
203 HISI_PMU_EVENT_ATTR(mn_req_dvm_num, 0x0B),
204 HISI_PMU_EVENT_ATTR(mn_req_dvmsync_num, 0x0C),
205 HISI_PMU_EVENT_ATTR(pa_req_dvm_num, 0x0D),
206 HISI_PMU_EVENT_ATTR(pa_req_dvmsync_num, 0x0E),
207 HISI_PMU_EVENT_ATTR(snp_dvm_latency, 0x80),
208 HISI_PMU_EVENT_ATTR(snp_dvmsync_latency, 0x81),
209 HISI_PMU_EVENT_ATTR(l3t_req_dvm_latency, 0x82),
210 HISI_PMU_EVENT_ATTR(l3t_req_dvmsync_latency, 0x83),
211 HISI_PMU_EVENT_ATTR(mn_req_dvm_latency, 0x84),
212 HISI_PMU_EVENT_ATTR(mn_req_dvmsync_latency, 0x85),
213 HISI_PMU_EVENT_ATTR(pa_req_dvm_latency, 0x86),
214 HISI_PMU_EVENT_ATTR(pa_req_dvmsync_latency, 0x87),
215 NULL
216 };
217
218 static const struct attribute_group hisi_mn_pmu_events_group_v1 = {
219 .name = "events",
220 .attrs = hisi_mn_pmu_events_attr_v1,
221 };
222
223 static const struct attribute_group *hisi_mn_pmu_attr_groups_v1[] = {
224 &hisi_mn_pmu_format_group,
225 &hisi_mn_pmu_events_group_v1,
226 &hisi_pmu_cpumask_attr_group,
227 &hisi_pmu_identifier_group,
228 NULL
229 };
230
231 static struct attribute *hisi_mn_pmu_events_attr_v2[] = {
232 HISI_PMU_EVENT_ATTR(req_eobarrier_num, 0x00),
233 HISI_PMU_EVENT_ATTR(req_ecbarrier_num, 0x01),
234 HISI_PMU_EVENT_ATTR(req_dvmop_num, 0x02),
235 HISI_PMU_EVENT_ATTR(req_dvmsync_num, 0x03),
236 HISI_PMU_EVENT_ATTR(req_retry_num, 0x04),
237 HISI_PMU_EVENT_ATTR(req_writenosnp_num, 0x05),
238 HISI_PMU_EVENT_ATTR(req_readnosnp_num, 0x06),
239 HISI_PMU_EVENT_ATTR(snp_dvm_num, 0x07),
240 HISI_PMU_EVENT_ATTR(snp_dvmsync_num, 0x08),
241 HISI_PMU_EVENT_ATTR(l3t_req_dvm_num, 0x09),
242 HISI_PMU_EVENT_ATTR(l3t_req_dvmsync_num, 0x0A),
243 HISI_PMU_EVENT_ATTR(mn_req_dvm_num, 0x0B),
244 HISI_PMU_EVENT_ATTR(mn_req_dvmsync_num, 0x0C),
245 HISI_PMU_EVENT_ATTR(pa_req_dvm_num, 0x0D),
246 HISI_PMU_EVENT_ATTR(pa_req_dvmsync_num, 0x0E),
247 HISI_PMU_EVENT_ATTR(cycles, 0x0F),
248 HISI_PMU_EVENT_ATTR(snp_dvm_latency, 0x80),
249 HISI_PMU_EVENT_ATTR(snp_dvmsync_latency, 0x81),
250 HISI_PMU_EVENT_ATTR(l3t_req_dvm_latency, 0x82),
251 HISI_PMU_EVENT_ATTR(l3t_req_dvmsync_latency, 0x83),
252 HISI_PMU_EVENT_ATTR(mn_req_dvm_latency, 0x84),
253 HISI_PMU_EVENT_ATTR(mn_req_dvmsync_latency, 0x85),
254 HISI_PMU_EVENT_ATTR(pa_req_dvm_latency, 0x86),
255 HISI_PMU_EVENT_ATTR(pa_req_dvmsync_latency, 0x87),
256 NULL
257 };
258
259 static const struct attribute_group hisi_mn_pmu_events_group_v2 = {
260 .name = "events",
261 .attrs = hisi_mn_pmu_events_attr_v2,
262 };
263
264 static const struct attribute_group *hisi_mn_pmu_attr_groups_v2[] = {
265 &hisi_mn_pmu_format_group,
266 &hisi_mn_pmu_events_group_v2,
267 &hisi_pmu_cpumask_attr_group,
268 &hisi_pmu_identifier_group,
269 NULL
270 };
271
272 static const struct hisi_uncore_ops hisi_uncore_mn_ops = {
273 .write_evtype = hisi_mn_pmu_write_evtype,
274 .get_event_idx = hisi_uncore_pmu_get_event_idx,
275 .start_counters = hisi_mn_pmu_start_counters,
276 .stop_counters = hisi_mn_pmu_stop_counters,
277 .enable_counter = hisi_mn_pmu_enable_counter,
278 .disable_counter = hisi_mn_pmu_disable_counter,
279 .enable_counter_int = hisi_mn_pmu_enable_counter_int,
280 .disable_counter_int = hisi_mn_pmu_disable_counter_int,
281 .write_counter = hisi_mn_pmu_write_counter,
282 .read_counter = hisi_mn_pmu_read_counter,
283 .get_int_status = hisi_mn_pmu_get_int_status,
284 .clear_int_status = hisi_mn_pmu_clear_int_status,
285 };
286
hisi_mn_pmu_dev_init(struct platform_device * pdev,struct hisi_pmu * mn_pmu)287 static int hisi_mn_pmu_dev_init(struct platform_device *pdev,
288 struct hisi_pmu *mn_pmu)
289 {
290 struct hisi_mn_pmu_regs *reg_info;
291 int ret;
292
293 hisi_uncore_pmu_init_topology(mn_pmu, &pdev->dev);
294
295 if (mn_pmu->topo.scl_id < 0)
296 return dev_err_probe(&pdev->dev, -EINVAL,
297 "Failed to read MN scl id\n");
298
299 if (mn_pmu->topo.index_id < 0)
300 return dev_err_probe(&pdev->dev, -EINVAL,
301 "Failed to read MN index id\n");
302
303 mn_pmu->base = devm_platform_ioremap_resource(pdev, 0);
304 if (IS_ERR(mn_pmu->base))
305 return dev_err_probe(&pdev->dev, PTR_ERR(mn_pmu->base),
306 "Failed to ioremap resource\n");
307
308 ret = hisi_uncore_pmu_init_irq(mn_pmu, pdev);
309 if (ret)
310 return ret;
311
312 mn_pmu->dev_info = device_get_match_data(&pdev->dev);
313 if (!mn_pmu->dev_info)
314 return -ENODEV;
315
316 mn_pmu->pmu_events.attr_groups = mn_pmu->dev_info->attr_groups;
317 mn_pmu->counter_bits = mn_pmu->dev_info->counter_bits;
318 mn_pmu->check_event = mn_pmu->dev_info->check_event;
319 mn_pmu->num_counters = HISI_MN_NR_COUNTERS;
320 mn_pmu->ops = &hisi_uncore_mn_ops;
321 mn_pmu->dev = &pdev->dev;
322 mn_pmu->on_cpu = -1;
323
324 reg_info = mn_pmu->dev_info->private;
325 mn_pmu->identifier = readl(mn_pmu->base + reg_info->version);
326
327 return 0;
328 }
329
hisi_mn_pmu_remove_cpuhp(void * hotplug_node)330 static void hisi_mn_pmu_remove_cpuhp(void *hotplug_node)
331 {
332 cpuhp_state_remove_instance_nocalls(hisi_uncore_pmu_cpuhp_state, hotplug_node);
333 }
334
hisi_mn_pmu_unregister(void * pmu)335 static void hisi_mn_pmu_unregister(void *pmu)
336 {
337 perf_pmu_unregister(pmu);
338 }
339
hisi_mn_pmu_probe(struct platform_device * pdev)340 static int hisi_mn_pmu_probe(struct platform_device *pdev)
341 {
342 struct hisi_pmu *mn_pmu;
343 char *name;
344 int ret;
345
346 mn_pmu = devm_kzalloc(&pdev->dev, sizeof(*mn_pmu), GFP_KERNEL);
347 if (!mn_pmu)
348 return -ENOMEM;
349
350 platform_set_drvdata(pdev, mn_pmu);
351
352 ret = hisi_mn_pmu_dev_init(pdev, mn_pmu);
353 if (ret)
354 return ret;
355
356 name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "hisi_scl%d_mn%d",
357 mn_pmu->topo.scl_id, mn_pmu->topo.index_id);
358 if (!name)
359 return -ENOMEM;
360
361 ret = cpuhp_state_add_instance(hisi_uncore_pmu_cpuhp_state, &mn_pmu->node);
362 if (ret)
363 return dev_err_probe(&pdev->dev, ret, "Failed to register cpu hotplug\n");
364
365 ret = devm_add_action_or_reset(&pdev->dev, hisi_mn_pmu_remove_cpuhp, &mn_pmu->node);
366 if (ret)
367 return ret;
368
369 hisi_pmu_init(mn_pmu, THIS_MODULE);
370
371 ret = perf_pmu_register(&mn_pmu->pmu, name, -1);
372 if (ret)
373 return dev_err_probe(mn_pmu->dev, ret, "Failed to register MN PMU\n");
374
375 return devm_add_action_or_reset(&pdev->dev, hisi_mn_pmu_unregister, &mn_pmu->pmu);
376 }
377
378 static struct hisi_mn_pmu_regs hisi_mn_v1_pmu_regs = {
379 .version = HISI_MN_VERSION_REG,
380 .dyn_ctrl = HISI_MN_DYNAMIC_CTRL_REG,
381 .perf_ctrl = HISI_MN_PERF_CTRL_REG,
382 .int_mask = HISI_MN_INT_MASK_REG,
383 .int_clear = HISI_MN_INT_CLEAR_REG,
384 .int_status = HISI_MN_INT_STATUS_REG,
385 .event_ctrl = HISI_MN_EVENT_CTRL_REG,
386 .event_type0 = HISI_MN_EVTYPE0_REG,
387 .event_cntr0 = HISI_MN_CNTR0_REG,
388 };
389
390 static const struct hisi_pmu_dev_info hisi_mn_v1 = {
391 .attr_groups = hisi_mn_pmu_attr_groups_v1,
392 .counter_bits = 48,
393 .check_event = HISI_MN_EVTYPE_MASK,
394 .private = &hisi_mn_v1_pmu_regs,
395 };
396
397 static const struct hisi_pmu_dev_info hisi_mn_v2 = {
398 .attr_groups = hisi_mn_pmu_attr_groups_v2,
399 .counter_bits = 48,
400 .check_event = HISI_MN_EVTYPE_MASK,
401 .private = &hisi_mn_v1_pmu_regs,
402 };
403
404 static const struct acpi_device_id hisi_mn_pmu_acpi_match[] = {
405 { "HISI0222", (kernel_ulong_t)&hisi_mn_v1 },
406 { "HISI0224", (kernel_ulong_t)&hisi_mn_v2 },
407 { }
408 };
409 MODULE_DEVICE_TABLE(acpi, hisi_mn_pmu_acpi_match);
410
411 static struct platform_driver hisi_mn_pmu_driver = {
412 .driver = {
413 .name = "hisi_mn_pmu",
414 .acpi_match_table = hisi_mn_pmu_acpi_match,
415 /*
416 * We have not worked out a safe bind/unbind process,
417 * Forcefully unbinding during sampling will lead to a
418 * kernel panic, so this is not supported yet.
419 */
420 .suppress_bind_attrs = true,
421 },
422 .probe = hisi_mn_pmu_probe,
423 };
424
425 module_platform_driver(hisi_mn_pmu_driver);
426
427 MODULE_IMPORT_NS("HISI_PMU");
428 MODULE_DESCRIPTION("HiSilicon SoC MN uncore PMU driver");
429 MODULE_LICENSE("GPL");
430 MODULE_AUTHOR("Junhao He <hejunhao3@huawei.com>");
431