1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
4 * DWC Ether MAC version 4.00 has been used for developing this code.
5 *
6 * This only implements the mac core functions for this chip.
7 *
8 * Copyright (C) 2015 STMicroelectronics Ltd
9 *
10 * Author: Alexandre Torgue <alexandre.torgue@st.com>
11 */
12
13 #include <linux/crc32.h>
14 #include <linux/slab.h>
15 #include <linux/ethtool.h>
16 #include <linux/io.h>
17 #include <linux/iopoll.h>
18 #include "stmmac.h"
19 #include "stmmac_fpe.h"
20 #include "stmmac_pcs.h"
21 #include "stmmac_vlan.h"
22 #include "dwmac4.h"
23 #include "dwmac5.h"
24
25 static const struct stmmac_pcs_info dwmac4_pcs_info = {
26 .pcs_offset = GMAC_PCS_BASE,
27 .rgsmii_offset = GMAC_PHYIF_CONTROL_STATUS,
28 .rgsmii_status_mask = GMAC_PHYIF_CTRLSTATUS_RSGMII_MASK,
29 .int_mask = GMAC_INT_PCS_LINK | GMAC_INT_PCS_ANE,
30 };
31
dwmac4_pcs_init(struct stmmac_priv * priv)32 static int dwmac4_pcs_init(struct stmmac_priv *priv)
33 {
34 if (!priv->dma_cap.pcs)
35 return 0;
36
37 return stmmac_integrated_pcs_init(priv, &dwmac4_pcs_info);
38 }
39
dwmac4_core_init(struct mac_device_info * hw,struct net_device * dev)40 static void dwmac4_core_init(struct mac_device_info *hw,
41 struct net_device *dev)
42 {
43 struct stmmac_priv *priv = netdev_priv(dev);
44 void __iomem *ioaddr = hw->pcsr;
45 unsigned long clk_rate;
46 u32 value;
47
48 value = readl(ioaddr + GMAC_CONFIG);
49 writel(value | GMAC_CORE_INIT, ioaddr + GMAC_CONFIG);
50
51 /* Configure LPI 1us counter to number of CSR clock ticks in 1us - 1 */
52 clk_rate = clk_get_rate(priv->plat->stmmac_clk);
53 writel((clk_rate / 1000000) - 1, ioaddr + GMAC4_MAC_ONEUS_TIC_COUNTER);
54
55 /* Enable GMAC interrupts */
56 writel(GMAC_INT_DEFAULT_ENABLE, ioaddr + GMAC_INT_EN);
57
58 if (GMAC_INT_DEFAULT_ENABLE & GMAC_INT_TSIE)
59 init_waitqueue_head(&priv->tstamp_busy_wait);
60 }
61
dwmac4_irq_modify(struct mac_device_info * hw,u32 disable,u32 enable)62 static void dwmac4_irq_modify(struct mac_device_info *hw, u32 disable,
63 u32 enable)
64 {
65 void __iomem *int_mask = hw->pcsr + GMAC_INT_EN;
66 unsigned long flags;
67 u32 value;
68
69 spin_lock_irqsave(&hw->irq_ctrl_lock, flags);
70 value = readl(int_mask) & ~disable;
71 value |= enable;
72 writel(value, int_mask);
73 spin_unlock_irqrestore(&hw->irq_ctrl_lock, flags);
74 }
75
dwmac4_update_caps(struct stmmac_priv * priv)76 static void dwmac4_update_caps(struct stmmac_priv *priv)
77 {
78 if (priv->plat->tx_queues_to_use > 1)
79 priv->hw->link.caps &= ~(MAC_10HD | MAC_100HD | MAC_1000HD);
80 else
81 priv->hw->link.caps |= (MAC_10HD | MAC_100HD | MAC_1000HD);
82 }
83
dwmac4_rx_queue_enable(struct mac_device_info * hw,u8 mode,u32 queue)84 static void dwmac4_rx_queue_enable(struct mac_device_info *hw,
85 u8 mode, u32 queue)
86 {
87 void __iomem *ioaddr = hw->pcsr;
88 u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
89
90 value &= GMAC_RX_QUEUE_CLEAR(queue);
91 if (mode == MTL_QUEUE_AVB)
92 value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
93 else if (mode == MTL_QUEUE_DCB)
94 value |= GMAC_RX_DCB_QUEUE_ENABLE(queue);
95
96 writel(value, ioaddr + GMAC_RXQ_CTRL0);
97 }
98
dwmac4_rx_queue_priority(struct mac_device_info * hw,u32 prio,u32 queue)99 static void dwmac4_rx_queue_priority(struct mac_device_info *hw,
100 u32 prio, u32 queue)
101 {
102 void __iomem *ioaddr = hw->pcsr;
103 u32 clear_mask = 0;
104 u32 ctrl2, ctrl3;
105 int i;
106
107 ctrl2 = readl(ioaddr + GMAC_RXQ_CTRL2);
108 ctrl3 = readl(ioaddr + GMAC_RXQ_CTRL3);
109
110 /* The software must ensure that the same priority
111 * is not mapped to multiple Rx queues
112 */
113 for (i = 0; i < 4; i++)
114 clear_mask |= ((prio << GMAC_RXQCTRL_PSRQX_SHIFT(i)) &
115 GMAC_RXQCTRL_PSRQX_MASK(i));
116
117 ctrl2 &= ~clear_mask;
118 ctrl3 &= ~clear_mask;
119
120 /* First assign new priorities to a queue, then
121 * clear them from others queues
122 */
123 if (queue < 4) {
124 ctrl2 |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
125 GMAC_RXQCTRL_PSRQX_MASK(queue);
126
127 writel(ctrl2, ioaddr + GMAC_RXQ_CTRL2);
128 writel(ctrl3, ioaddr + GMAC_RXQ_CTRL3);
129 } else {
130 queue -= 4;
131
132 ctrl3 |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
133 GMAC_RXQCTRL_PSRQX_MASK(queue);
134
135 writel(ctrl3, ioaddr + GMAC_RXQ_CTRL3);
136 writel(ctrl2, ioaddr + GMAC_RXQ_CTRL2);
137 }
138 }
139
dwmac4_tx_queue_priority(struct mac_device_info * hw,u32 prio,u32 queue)140 static void dwmac4_tx_queue_priority(struct mac_device_info *hw,
141 u32 prio, u32 queue)
142 {
143 void __iomem *ioaddr = hw->pcsr;
144 u32 base_register;
145 u32 value;
146
147 base_register = (queue < 4) ? GMAC_TXQ_PRTY_MAP0 : GMAC_TXQ_PRTY_MAP1;
148 if (queue >= 4)
149 queue -= 4;
150
151 value = readl(ioaddr + base_register);
152
153 value &= ~GMAC_TXQCTRL_PSTQX_MASK(queue);
154 value |= (prio << GMAC_TXQCTRL_PSTQX_SHIFT(queue)) &
155 GMAC_TXQCTRL_PSTQX_MASK(queue);
156
157 writel(value, ioaddr + base_register);
158 }
159
dwmac4_rx_queue_routing(struct mac_device_info * hw,u8 packet,u32 queue)160 static void dwmac4_rx_queue_routing(struct mac_device_info *hw,
161 u8 packet, u32 queue)
162 {
163 void __iomem *ioaddr = hw->pcsr;
164 u32 value;
165
166 static const struct stmmac_rx_routing route_possibilities[] = {
167 { GMAC_RXQCTRL_AVCPQ_MASK, GMAC_RXQCTRL_AVCPQ_SHIFT },
168 { GMAC_RXQCTRL_PTPQ_MASK, GMAC_RXQCTRL_PTPQ_SHIFT },
169 { GMAC_RXQCTRL_DCBCPQ_MASK, GMAC_RXQCTRL_DCBCPQ_SHIFT },
170 { GMAC_RXQCTRL_UPQ_MASK, GMAC_RXQCTRL_UPQ_SHIFT },
171 { GMAC_RXQCTRL_MCBCQ_MASK, GMAC_RXQCTRL_MCBCQ_SHIFT },
172 };
173
174 value = readl(ioaddr + GMAC_RXQ_CTRL1);
175
176 /* routing configuration */
177 value &= ~route_possibilities[packet - 1].reg_mask;
178 value |= (queue << route_possibilities[packet-1].reg_shift) &
179 route_possibilities[packet - 1].reg_mask;
180
181 /* some packets require extra ops */
182 if (packet == PACKET_AVCPQ) {
183 value &= ~GMAC_RXQCTRL_TACPQE;
184 value |= 0x1 << GMAC_RXQCTRL_TACPQE_SHIFT;
185 } else if (packet == PACKET_MCBCQ) {
186 value &= ~GMAC_RXQCTRL_MCBCQEN;
187 value |= 0x1 << GMAC_RXQCTRL_MCBCQEN_SHIFT;
188 }
189
190 writel(value, ioaddr + GMAC_RXQ_CTRL1);
191 }
192
dwmac4_prog_mtl_rx_algorithms(struct mac_device_info * hw,u32 rx_alg)193 static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw,
194 u32 rx_alg)
195 {
196 void __iomem *ioaddr = hw->pcsr;
197 u32 value = readl(ioaddr + MTL_OPERATION_MODE);
198
199 value &= ~MTL_OPERATION_RAA;
200 switch (rx_alg) {
201 case MTL_RX_ALGORITHM_SP:
202 value |= MTL_OPERATION_RAA_SP;
203 break;
204 case MTL_RX_ALGORITHM_WSP:
205 value |= MTL_OPERATION_RAA_WSP;
206 break;
207 default:
208 break;
209 }
210
211 writel(value, ioaddr + MTL_OPERATION_MODE);
212 }
213
dwmac4_prog_mtl_tx_algorithms(struct mac_device_info * hw,u32 tx_alg)214 static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw,
215 u32 tx_alg)
216 {
217 void __iomem *ioaddr = hw->pcsr;
218 u32 value = readl(ioaddr + MTL_OPERATION_MODE);
219
220 value &= ~MTL_OPERATION_SCHALG_MASK;
221 switch (tx_alg) {
222 case MTL_TX_ALGORITHM_WRR:
223 value |= MTL_OPERATION_SCHALG_WRR;
224 break;
225 case MTL_TX_ALGORITHM_WFQ:
226 value |= MTL_OPERATION_SCHALG_WFQ;
227 break;
228 case MTL_TX_ALGORITHM_DWRR:
229 value |= MTL_OPERATION_SCHALG_DWRR;
230 break;
231 case MTL_TX_ALGORITHM_SP:
232 value |= MTL_OPERATION_SCHALG_SP;
233 break;
234 default:
235 break;
236 }
237
238 writel(value, ioaddr + MTL_OPERATION_MODE);
239 }
240
dwmac4_set_mtl_tx_queue_weight(struct stmmac_priv * priv,struct mac_device_info * hw,u32 weight,u32 queue)241 static void dwmac4_set_mtl_tx_queue_weight(struct stmmac_priv *priv,
242 struct mac_device_info *hw,
243 u32 weight, u32 queue)
244 {
245 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
246 void __iomem *ioaddr = hw->pcsr;
247 u32 value = readl(ioaddr + mtl_txqx_weight_base_addr(dwmac4_addrs,
248 queue));
249
250 value &= ~MTL_TXQ_WEIGHT_ISCQW_MASK;
251 value |= weight & MTL_TXQ_WEIGHT_ISCQW_MASK;
252 writel(value, ioaddr + mtl_txqx_weight_base_addr(dwmac4_addrs, queue));
253 }
254
dwmac4_map_mtl_dma(struct mac_device_info * hw,u32 queue,u32 chan)255 static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan)
256 {
257 void __iomem *ioaddr = hw->pcsr;
258 u32 value;
259
260 if (queue < 4) {
261 value = readl(ioaddr + MTL_RXQ_DMA_MAP0);
262 value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue);
263 value |= MTL_RXQ_DMA_QXMDMACH(chan, queue);
264 writel(value, ioaddr + MTL_RXQ_DMA_MAP0);
265 } else {
266 value = readl(ioaddr + MTL_RXQ_DMA_MAP1);
267 value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue - 4);
268 value |= MTL_RXQ_DMA_QXMDMACH(chan, queue - 4);
269 writel(value, ioaddr + MTL_RXQ_DMA_MAP1);
270 }
271 }
272
dwmac4_config_cbs(struct stmmac_priv * priv,struct mac_device_info * hw,u32 send_slope,u32 idle_slope,u32 high_credit,u32 low_credit,u32 queue)273 static void dwmac4_config_cbs(struct stmmac_priv *priv,
274 struct mac_device_info *hw,
275 u32 send_slope, u32 idle_slope,
276 u32 high_credit, u32 low_credit, u32 queue)
277 {
278 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
279 void __iomem *ioaddr = hw->pcsr;
280 u32 value;
281
282 pr_debug("Queue %d configured as AVB. Parameters:\n", queue);
283 pr_debug("\tsend_slope: 0x%08x\n", send_slope);
284 pr_debug("\tidle_slope: 0x%08x\n", idle_slope);
285 pr_debug("\thigh_credit: 0x%08x\n", high_credit);
286 pr_debug("\tlow_credit: 0x%08x\n", low_credit);
287
288 /* enable AV algorithm */
289 value = readl(ioaddr + mtl_etsx_ctrl_base_addr(dwmac4_addrs, queue));
290 value |= MTL_ETS_CTRL_AVALG;
291 value |= MTL_ETS_CTRL_CC;
292 writel(value, ioaddr + mtl_etsx_ctrl_base_addr(dwmac4_addrs, queue));
293
294 /* configure send slope */
295 value = readl(ioaddr + mtl_send_slp_credx_base_addr(dwmac4_addrs,
296 queue));
297 value &= ~MTL_SEND_SLP_CRED_SSC_MASK;
298 value |= send_slope & MTL_SEND_SLP_CRED_SSC_MASK;
299 writel(value, ioaddr + mtl_send_slp_credx_base_addr(dwmac4_addrs,
300 queue));
301
302 /* configure idle slope (same register as tx weight) */
303 dwmac4_set_mtl_tx_queue_weight(priv, hw, idle_slope, queue);
304
305 /* configure high credit */
306 value = readl(ioaddr + mtl_high_credx_base_addr(dwmac4_addrs, queue));
307 value &= ~MTL_HIGH_CRED_HC_MASK;
308 value |= high_credit & MTL_HIGH_CRED_HC_MASK;
309 writel(value, ioaddr + mtl_high_credx_base_addr(dwmac4_addrs, queue));
310
311 /* configure high credit */
312 value = readl(ioaddr + mtl_low_credx_base_addr(dwmac4_addrs, queue));
313 value &= ~MTL_HIGH_CRED_LC_MASK;
314 value |= low_credit & MTL_HIGH_CRED_LC_MASK;
315 writel(value, ioaddr + mtl_low_credx_base_addr(dwmac4_addrs, queue));
316 }
317
dwmac4_dump_regs(struct mac_device_info * hw,u32 * reg_space)318 static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)
319 {
320 void __iomem *ioaddr = hw->pcsr;
321 int i;
322
323 for (i = 0; i < GMAC_REG_NUM; i++)
324 reg_space[i] = readl(ioaddr + i * 4);
325 }
326
dwmac4_rx_ipc_enable(struct mac_device_info * hw)327 static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
328 {
329 void __iomem *ioaddr = hw->pcsr;
330 u32 value = readl(ioaddr + GMAC_CONFIG);
331
332 if (hw->rx_csum)
333 value |= GMAC_CONFIG_IPC;
334 else
335 value &= ~GMAC_CONFIG_IPC;
336
337 writel(value, ioaddr + GMAC_CONFIG);
338
339 value = readl(ioaddr + GMAC_CONFIG);
340
341 return !!(value & GMAC_CONFIG_IPC);
342 }
343
dwmac4_pmt(struct mac_device_info * hw,unsigned long mode)344 static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
345 {
346 void __iomem *ioaddr = hw->pcsr;
347 unsigned int pmt = 0;
348 u32 config;
349
350 if (mode & WAKE_MAGIC) {
351 pr_debug("GMAC: WOL Magic frame\n");
352 pmt |= power_down | magic_pkt_en;
353 }
354 if (mode & WAKE_UCAST) {
355 pr_debug("GMAC: WOL on global unicast\n");
356 pmt |= power_down | global_unicast | wake_up_frame_en;
357 }
358
359 if (pmt) {
360 /* The receiver must be enabled for WOL before powering down */
361 config = readl(ioaddr + GMAC_CONFIG);
362 config |= GMAC_CONFIG_RE;
363 writel(config, ioaddr + GMAC_CONFIG);
364 }
365 writel(pmt, ioaddr + GMAC_PMT);
366 }
367
dwmac4_set_umac_addr(struct mac_device_info * hw,const unsigned char * addr,unsigned int reg_n)368 static void dwmac4_set_umac_addr(struct mac_device_info *hw,
369 const unsigned char *addr, unsigned int reg_n)
370 {
371 void __iomem *ioaddr = hw->pcsr;
372
373 stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
374 GMAC_ADDR_LOW(reg_n));
375 }
376
dwmac4_get_umac_addr(struct mac_device_info * hw,unsigned char * addr,unsigned int reg_n)377 static void dwmac4_get_umac_addr(struct mac_device_info *hw,
378 unsigned char *addr, unsigned int reg_n)
379 {
380 void __iomem *ioaddr = hw->pcsr;
381
382 stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
383 GMAC_ADDR_LOW(reg_n));
384 }
385
dwmac4_set_lpi_mode(struct mac_device_info * hw,enum stmmac_lpi_mode mode,bool en_tx_lpi_clockgating,u32 et)386 static int dwmac4_set_lpi_mode(struct mac_device_info *hw,
387 enum stmmac_lpi_mode mode,
388 bool en_tx_lpi_clockgating, u32 et)
389 {
390 void __iomem *ioaddr = hw->pcsr;
391 u32 value, mask;
392
393 if (mode == STMMAC_LPI_DISABLE) {
394 value = 0;
395 } else {
396 value = LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;
397
398 if (mode == STMMAC_LPI_TIMER) {
399 /* Return ERANGE if the timer is larger than the
400 * register field.
401 */
402 if (et > STMMAC_ET_MAX)
403 return -ERANGE;
404
405 /* Set the hardware LPI entry timer */
406 writel(et, ioaddr + GMAC4_LPI_ENTRY_TIMER);
407
408 /* Interpret a zero LPI entry timer to mean
409 * immediate entry into LPI mode.
410 */
411 if (et)
412 value |= LPI_CTRL_STATUS_LPIATE;
413 }
414
415 if (en_tx_lpi_clockgating)
416 value |= LPI_CTRL_STATUS_LPITCSE;
417 }
418
419 mask = LPI_CTRL_STATUS_LPIATE | LPI_CTRL_STATUS_LPIEN |
420 LPI_CTRL_STATUS_LPITXA | LPI_CTRL_STATUS_LPITCSE;
421
422 value |= readl(ioaddr + GMAC4_LPI_CTRL_STATUS) & ~mask;
423 writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
424
425 return 0;
426 }
427
dwmac4_set_eee_pls(struct mac_device_info * hw,int link)428 static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
429 {
430 void __iomem *ioaddr = hw->pcsr;
431 u32 value;
432
433 value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
434
435 if (link)
436 value |= LPI_CTRL_STATUS_PLS;
437 else
438 value &= ~LPI_CTRL_STATUS_PLS;
439
440 writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
441 }
442
dwmac4_set_eee_timer(struct mac_device_info * hw,int ls,int tw)443 static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
444 {
445 void __iomem *ioaddr = hw->pcsr;
446 int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16);
447
448 /* Program the timers in the LPI timer control register:
449 * LS: minimum time (ms) for which the link
450 * status from PHY should be ok before transmitting
451 * the LPI pattern.
452 * TW: minimum time (us) for which the core waits
453 * after it has stopped transmitting the LPI pattern.
454 */
455 writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
456 }
457
dwmac4_set_filter(struct mac_device_info * hw,struct net_device * dev)458 static void dwmac4_set_filter(struct mac_device_info *hw,
459 struct net_device *dev)
460 {
461 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
462 int numhashregs = (hw->multicast_filter_bins >> 5);
463 int mcbitslog2 = hw->mcast_bits_log2;
464 unsigned int value;
465 u32 mc_filter[8];
466 int i;
467
468 memset(mc_filter, 0, sizeof(mc_filter));
469
470 value = readl(ioaddr + GMAC_PACKET_FILTER);
471 value &= ~GMAC_PACKET_FILTER_HMC;
472 value &= ~GMAC_PACKET_FILTER_HPF;
473 value &= ~GMAC_PACKET_FILTER_PCF;
474 value &= ~GMAC_PACKET_FILTER_PM;
475 value &= ~GMAC_PACKET_FILTER_PR;
476 value &= ~GMAC_PACKET_FILTER_RA;
477 if (dev->flags & IFF_PROMISC) {
478 /* VLAN Tag Filter Fail Packets Queuing */
479 if (hw->vlan_fail_q_en) {
480 value = readl(ioaddr + GMAC_RXQ_CTRL4);
481 value &= ~GMAC_RXQCTRL_VFFQ_MASK;
482 value |= GMAC_RXQCTRL_VFFQE |
483 (hw->vlan_fail_q << GMAC_RXQCTRL_VFFQ_SHIFT);
484 writel(value, ioaddr + GMAC_RXQ_CTRL4);
485 value = GMAC_PACKET_FILTER_PR | GMAC_PACKET_FILTER_RA;
486 } else {
487 value = GMAC_PACKET_FILTER_PR | GMAC_PACKET_FILTER_PCF;
488 }
489
490 } else if ((dev->flags & IFF_ALLMULTI) ||
491 (netdev_mc_count(dev) > hw->multicast_filter_bins)) {
492 /* Pass all multi */
493 value |= GMAC_PACKET_FILTER_PM;
494 /* Set all the bits of the HASH tab */
495 memset(mc_filter, 0xff, sizeof(mc_filter));
496 } else if (!netdev_mc_empty(dev) && (dev->flags & IFF_MULTICAST)) {
497 struct netdev_hw_addr *ha;
498
499 /* Hash filter for multicast */
500 value |= GMAC_PACKET_FILTER_HMC;
501
502 netdev_for_each_mc_addr(ha, dev) {
503 /* The upper n bits of the calculated CRC are used to
504 * index the contents of the hash table. The number of
505 * bits used depends on the hardware configuration
506 * selected at core configuration time.
507 */
508 u32 bit_nr = bitrev32(~crc32_le(~0, ha->addr,
509 ETH_ALEN)) >> (32 - mcbitslog2);
510 /* The most significant bit determines the register to
511 * use (H/L) while the other 5 bits determine the bit
512 * within the register.
513 */
514 mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1f));
515 }
516 }
517
518 for (i = 0; i < numhashregs; i++)
519 writel(mc_filter[i], ioaddr + GMAC_HASH_TAB(i));
520
521 value |= GMAC_PACKET_FILTER_HPF;
522
523 /* Handle multiple unicast addresses */
524 if (netdev_uc_count(dev) + 1 > hw->unicast_filter_entries) {
525 /* Switch to promiscuous mode if more than 128 addrs
526 * are required
527 */
528 value |= GMAC_PACKET_FILTER_PR;
529 } else {
530 struct netdev_hw_addr *ha;
531 int reg = 1;
532
533 netdev_for_each_uc_addr(ha, dev) {
534 dwmac4_set_umac_addr(hw, ha->addr, reg);
535 reg++;
536 }
537
538 while (reg < GMAC_MAX_PERFECT_ADDRESSES) {
539 writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
540 writel(0, ioaddr + GMAC_ADDR_LOW(reg));
541 reg++;
542 }
543 }
544
545 /* VLAN filtering */
546 if (dev->flags & IFF_PROMISC && !hw->vlan_fail_q_en)
547 value &= ~GMAC_PACKET_FILTER_VTFE;
548 else if (dev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
549 value |= GMAC_PACKET_FILTER_VTFE;
550
551 writel(value, ioaddr + GMAC_PACKET_FILTER);
552 }
553
dwmac4_flow_ctrl(struct mac_device_info * hw,unsigned int duplex,unsigned int fc,unsigned int pause_time,u8 tx_cnt)554 static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
555 unsigned int fc, unsigned int pause_time,
556 u8 tx_cnt)
557 {
558 void __iomem *ioaddr = hw->pcsr;
559 unsigned int flow = 0;
560 u8 queue;
561
562 pr_debug("GMAC Flow-Control:\n");
563 if (fc & FLOW_RX) {
564 pr_debug("\tReceive Flow-Control ON\n");
565 flow |= GMAC_RX_FLOW_CTRL_RFE;
566 } else {
567 pr_debug("\tReceive Flow-Control OFF\n");
568 }
569 writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
570
571 if (fc & FLOW_TX) {
572 pr_debug("\tTransmit Flow-Control ON\n");
573
574 if (duplex)
575 pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
576
577 for (queue = 0; queue < tx_cnt; queue++) {
578 flow = GMAC_TX_FLOW_CTRL_TFE;
579
580 if (duplex)
581 flow |= FIELD_PREP(GMAC_TX_FLOW_CTRL_PT_MASK,
582 pause_time);
583
584 writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
585 }
586 } else {
587 for (queue = 0; queue < tx_cnt; queue++)
588 writel(0, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
589 }
590 }
591
dwmac4_ctrl_ane(struct stmmac_priv * priv,bool ane,bool srgmi_ral)592 static void dwmac4_ctrl_ane(struct stmmac_priv *priv, bool ane, bool srgmi_ral)
593 {
594 dwmac_ctrl_ane(priv->ioaddr, GMAC_PCS_BASE, ane, srgmi_ral);
595 }
596
dwmac4_irq_mtl_status(struct stmmac_priv * priv,struct mac_device_info * hw,u32 chan)597 static int dwmac4_irq_mtl_status(struct stmmac_priv *priv,
598 struct mac_device_info *hw, u32 chan)
599 {
600 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
601 void __iomem *ioaddr = hw->pcsr;
602 u32 mtl_int_qx_status;
603 int ret = 0;
604
605 mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
606
607 /* Check MTL Interrupt */
608 if (mtl_int_qx_status & MTL_INT_QX(chan)) {
609 /* read Queue x Interrupt status */
610 u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(dwmac4_addrs,
611 chan));
612
613 if (status & MTL_RX_OVERFLOW_INT) {
614 /* clear Interrupt */
615 writel(status | MTL_RX_OVERFLOW_INT,
616 ioaddr + MTL_CHAN_INT_CTRL(dwmac4_addrs, chan));
617 ret = CORE_IRQ_MTL_RX_OVERFLOW;
618 }
619 }
620
621 return ret;
622 }
623
dwmac4_irq_status(struct stmmac_priv * priv,struct stmmac_extra_stats * x)624 static int dwmac4_irq_status(struct stmmac_priv *priv,
625 struct stmmac_extra_stats *x)
626 {
627 void __iomem *ioaddr = priv->hw->pcsr;
628 u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
629 u32 intr_enable = readl(ioaddr + GMAC_INT_EN);
630 int ret = 0;
631
632 /* Discard disabled bits */
633 intr_status &= intr_enable;
634
635 /* Not used events (e.g. MMC interrupts) are not handled. */
636 if ((intr_status & mmc_tx_irq))
637 x->mmc_tx_irq_n++;
638 if (unlikely(intr_status & mmc_rx_irq))
639 x->mmc_rx_irq_n++;
640 if (unlikely(intr_status & mmc_rx_csum_offload_irq))
641 x->mmc_rx_csum_offload_irq_n++;
642 /* Clear the PMT bits 5 and 6 by reading the PMT status reg */
643 if (unlikely(intr_status & pmt_irq)) {
644 readl(ioaddr + GMAC_PMT);
645 x->irq_receive_pmt_irq_n++;
646 }
647
648 /* MAC tx/rx EEE LPI entry/exit interrupts */
649 if (intr_status & lpi_irq) {
650 /* Clear LPI interrupt by reading MAC_LPI_Control_Status */
651 u32 status = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
652
653 if (status & LPI_CTRL_STATUS_TLPIEN) {
654 ret |= CORE_IRQ_TX_PATH_IN_LPI_MODE;
655 x->irq_tx_path_in_lpi_mode_n++;
656 }
657 if (status & LPI_CTRL_STATUS_TLPIEX) {
658 ret |= CORE_IRQ_TX_PATH_EXIT_LPI_MODE;
659 x->irq_tx_path_exit_lpi_mode_n++;
660 }
661 if (status & LPI_CTRL_STATUS_RLPIEN)
662 x->irq_rx_path_in_lpi_mode_n++;
663 if (status & LPI_CTRL_STATUS_RLPIEX)
664 x->irq_rx_path_exit_lpi_mode_n++;
665 }
666
667 if (intr_status & (PCS_ANE_IRQ | PCS_LINK_IRQ))
668 stmmac_integrated_pcs_irq(priv, intr_status, x);
669
670 return ret;
671 }
672
dwmac4_debug(struct stmmac_priv * priv,void __iomem * ioaddr,struct stmmac_extra_stats * x,u32 rx_queues,u32 tx_queues)673 static void dwmac4_debug(struct stmmac_priv *priv, void __iomem *ioaddr,
674 struct stmmac_extra_stats *x,
675 u32 rx_queues, u32 tx_queues)
676 {
677 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
678 u32 value;
679 u32 queue;
680
681 for (queue = 0; queue < tx_queues; queue++) {
682 value = readl(ioaddr + MTL_CHAN_TX_DEBUG(dwmac4_addrs, queue));
683
684 if (value & MTL_DEBUG_TXSTSFSTS)
685 x->mtl_tx_status_fifo_full++;
686 if (value & MTL_DEBUG_TXFSTS)
687 x->mtl_tx_fifo_not_empty++;
688 if (value & MTL_DEBUG_TWCSTS)
689 x->mmtl_fifo_ctrl++;
690 if (value & MTL_DEBUG_TRCSTS_MASK) {
691 u32 trcsts = FIELD_GET(MTL_DEBUG_TRCSTS_MASK, value);
692
693 if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
694 x->mtl_tx_fifo_read_ctrl_write++;
695 else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
696 x->mtl_tx_fifo_read_ctrl_wait++;
697 else if (trcsts == MTL_DEBUG_TRCSTS_READ)
698 x->mtl_tx_fifo_read_ctrl_read++;
699 else
700 x->mtl_tx_fifo_read_ctrl_idle++;
701 }
702 if (value & MTL_DEBUG_TXPAUSED)
703 x->mac_tx_in_pause++;
704 }
705
706 for (queue = 0; queue < rx_queues; queue++) {
707 value = readl(ioaddr + MTL_CHAN_RX_DEBUG(dwmac4_addrs, queue));
708
709 if (value & MTL_DEBUG_RXFSTS_MASK) {
710 u32 rxfsts = FIELD_GET(MTL_DEBUG_RXFSTS_MASK, value);
711
712 if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
713 x->mtl_rx_fifo_fill_level_full++;
714 else if (rxfsts == MTL_DEBUG_RXFSTS_AT)
715 x->mtl_rx_fifo_fill_above_thresh++;
716 else if (rxfsts == MTL_DEBUG_RXFSTS_BT)
717 x->mtl_rx_fifo_fill_below_thresh++;
718 else
719 x->mtl_rx_fifo_fill_level_empty++;
720 }
721 if (value & MTL_DEBUG_RRCSTS_MASK) {
722 u32 rrcsts = FIELD_GET(MTL_DEBUG_RRCSTS_MASK, value);
723
724 if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
725 x->mtl_rx_fifo_read_ctrl_flush++;
726 else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT)
727 x->mtl_rx_fifo_read_ctrl_read_data++;
728 else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA)
729 x->mtl_rx_fifo_read_ctrl_status++;
730 else
731 x->mtl_rx_fifo_read_ctrl_idle++;
732 }
733 if (value & MTL_DEBUG_RWCSTS)
734 x->mtl_rx_fifo_ctrl_active++;
735 }
736
737 /* GMAC debug */
738 value = readl(ioaddr + GMAC_DEBUG);
739
740 if (value & GMAC_DEBUG_TFCSTS_MASK) {
741 u32 tfcsts = FIELD_GET(GMAC_DEBUG_TFCSTS_MASK, value);
742
743 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
744 x->mac_tx_frame_ctrl_xfer++;
745 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
746 x->mac_tx_frame_ctrl_pause++;
747 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
748 x->mac_tx_frame_ctrl_wait++;
749 else
750 x->mac_tx_frame_ctrl_idle++;
751 }
752 if (value & GMAC_DEBUG_TPESTS)
753 x->mac_gmii_tx_proto_engine++;
754 if (value & GMAC_DEBUG_RFCFCSTS_MASK)
755 x->mac_rx_frame_ctrl_fifo = FIELD_GET(GMAC_DEBUG_RFCFCSTS_MASK,
756 value);
757 if (value & GMAC_DEBUG_RPESTS)
758 x->mac_gmii_rx_proto_engine++;
759 }
760
dwmac4_set_mac_loopback(void __iomem * ioaddr,bool enable)761 static void dwmac4_set_mac_loopback(void __iomem *ioaddr, bool enable)
762 {
763 u32 value = readl(ioaddr + GMAC_CONFIG);
764
765 if (enable)
766 value |= GMAC_CONFIG_LM;
767 else
768 value &= ~GMAC_CONFIG_LM;
769
770 writel(value, ioaddr + GMAC_CONFIG);
771 }
772
dwmac4_sarc_configure(void __iomem * ioaddr,int val)773 static void dwmac4_sarc_configure(void __iomem *ioaddr, int val)
774 {
775 u32 value = readl(ioaddr + GMAC_CONFIG);
776
777 value = u32_replace_bits(value, val, GMAC_CONFIG_SARC);
778
779 writel(value, ioaddr + GMAC_CONFIG);
780 }
781
dwmac4_set_arp_offload(struct mac_device_info * hw,bool en,u32 addr)782 static void dwmac4_set_arp_offload(struct mac_device_info *hw, bool en,
783 u32 addr)
784 {
785 void __iomem *ioaddr = hw->pcsr;
786 u32 value;
787
788 writel(addr, ioaddr + GMAC_ARP_ADDR);
789
790 value = readl(ioaddr + GMAC_CONFIG);
791 if (en)
792 value |= GMAC_CONFIG_ARPEN;
793 else
794 value &= ~GMAC_CONFIG_ARPEN;
795 writel(value, ioaddr + GMAC_CONFIG);
796 }
797
dwmac4_config_l3_filter(struct mac_device_info * hw,u32 filter_no,bool en,bool ipv6,bool sa,bool inv,u32 match)798 static int dwmac4_config_l3_filter(struct mac_device_info *hw, u32 filter_no,
799 bool en, bool ipv6, bool sa, bool inv,
800 u32 match)
801 {
802 void __iomem *ioaddr = hw->pcsr;
803 u32 value;
804
805 value = readl(ioaddr + GMAC_PACKET_FILTER);
806 value |= GMAC_PACKET_FILTER_IPFE;
807 writel(value, ioaddr + GMAC_PACKET_FILTER);
808
809 value = readl(ioaddr + GMAC_L3L4_CTRL(filter_no));
810
811 /* For IPv6 not both SA/DA filters can be active */
812 if (ipv6) {
813 value |= GMAC_L3PEN0;
814 value &= ~(GMAC_L3SAM0 | GMAC_L3SAIM0);
815 value &= ~(GMAC_L3DAM0 | GMAC_L3DAIM0);
816 if (sa) {
817 value |= GMAC_L3SAM0;
818 if (inv)
819 value |= GMAC_L3SAIM0;
820 } else {
821 value |= GMAC_L3DAM0;
822 if (inv)
823 value |= GMAC_L3DAIM0;
824 }
825 } else {
826 value &= ~GMAC_L3PEN0;
827 if (sa) {
828 value |= GMAC_L3SAM0;
829 if (inv)
830 value |= GMAC_L3SAIM0;
831 } else {
832 value |= GMAC_L3DAM0;
833 if (inv)
834 value |= GMAC_L3DAIM0;
835 }
836 }
837
838 writel(value, ioaddr + GMAC_L3L4_CTRL(filter_no));
839
840 if (sa) {
841 writel(match, ioaddr + GMAC_L3_ADDR0(filter_no));
842 } else {
843 writel(match, ioaddr + GMAC_L3_ADDR1(filter_no));
844 }
845
846 if (!en)
847 writel(0, ioaddr + GMAC_L3L4_CTRL(filter_no));
848
849 return 0;
850 }
851
dwmac4_config_l4_filter(struct mac_device_info * hw,u32 filter_no,bool en,bool udp,bool sa,bool inv,u32 match)852 static int dwmac4_config_l4_filter(struct mac_device_info *hw, u32 filter_no,
853 bool en, bool udp, bool sa, bool inv,
854 u32 match)
855 {
856 void __iomem *ioaddr = hw->pcsr;
857 u32 value;
858
859 value = readl(ioaddr + GMAC_PACKET_FILTER);
860 value |= GMAC_PACKET_FILTER_IPFE;
861 writel(value, ioaddr + GMAC_PACKET_FILTER);
862
863 value = readl(ioaddr + GMAC_L3L4_CTRL(filter_no));
864 if (udp) {
865 value |= GMAC_L4PEN0;
866 } else {
867 value &= ~GMAC_L4PEN0;
868 }
869
870 value &= ~(GMAC_L4SPM0 | GMAC_L4SPIM0);
871 value &= ~(GMAC_L4DPM0 | GMAC_L4DPIM0);
872 if (sa) {
873 value |= GMAC_L4SPM0;
874 if (inv)
875 value |= GMAC_L4SPIM0;
876 } else {
877 value |= GMAC_L4DPM0;
878 if (inv)
879 value |= GMAC_L4DPIM0;
880 }
881
882 writel(value, ioaddr + GMAC_L3L4_CTRL(filter_no));
883
884 if (sa) {
885 value = FIELD_PREP(GMAC_L4SP0, match);
886 } else {
887 value = FIELD_PREP(GMAC_L4DP0, match);
888 }
889
890 writel(value, ioaddr + GMAC_L4_ADDR(filter_no));
891
892 if (!en)
893 writel(0, ioaddr + GMAC_L3L4_CTRL(filter_no));
894
895 return 0;
896 }
897
898 const struct stmmac_ops dwmac4_ops = {
899 .pcs_init = dwmac4_pcs_init,
900 .core_init = dwmac4_core_init,
901 .irq_modify = dwmac4_irq_modify,
902 .update_caps = dwmac4_update_caps,
903 .set_mac = stmmac_set_mac,
904 .rx_ipc = dwmac4_rx_ipc_enable,
905 .rx_queue_enable = dwmac4_rx_queue_enable,
906 .rx_queue_prio = dwmac4_rx_queue_priority,
907 .tx_queue_prio = dwmac4_tx_queue_priority,
908 .rx_queue_routing = dwmac4_rx_queue_routing,
909 .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
910 .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
911 .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
912 .map_mtl_to_dma = dwmac4_map_mtl_dma,
913 .config_cbs = dwmac4_config_cbs,
914 .dump_regs = dwmac4_dump_regs,
915 .host_irq_status = dwmac4_irq_status,
916 .host_mtl_irq_status = dwmac4_irq_mtl_status,
917 .flow_ctrl = dwmac4_flow_ctrl,
918 .pmt = dwmac4_pmt,
919 .set_umac_addr = dwmac4_set_umac_addr,
920 .get_umac_addr = dwmac4_get_umac_addr,
921 .set_lpi_mode = dwmac4_set_lpi_mode,
922 .set_eee_timer = dwmac4_set_eee_timer,
923 .set_eee_pls = dwmac4_set_eee_pls,
924 .pcs_ctrl_ane = dwmac4_ctrl_ane,
925 .debug = dwmac4_debug,
926 .set_filter = dwmac4_set_filter,
927 .set_mac_loopback = dwmac4_set_mac_loopback,
928 .sarc_configure = dwmac4_sarc_configure,
929 .set_arp_offload = dwmac4_set_arp_offload,
930 .config_l3_filter = dwmac4_config_l3_filter,
931 .config_l4_filter = dwmac4_config_l4_filter,
932 };
933
934 const struct stmmac_ops dwmac410_ops = {
935 .pcs_init = dwmac4_pcs_init,
936 .core_init = dwmac4_core_init,
937 .irq_modify = dwmac4_irq_modify,
938 .update_caps = dwmac4_update_caps,
939 .set_mac = stmmac_dwmac4_set_mac,
940 .rx_ipc = dwmac4_rx_ipc_enable,
941 .rx_queue_enable = dwmac4_rx_queue_enable,
942 .rx_queue_prio = dwmac4_rx_queue_priority,
943 .tx_queue_prio = dwmac4_tx_queue_priority,
944 .rx_queue_routing = dwmac4_rx_queue_routing,
945 .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
946 .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
947 .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
948 .map_mtl_to_dma = dwmac4_map_mtl_dma,
949 .config_cbs = dwmac4_config_cbs,
950 .dump_regs = dwmac4_dump_regs,
951 .host_irq_status = dwmac4_irq_status,
952 .host_mtl_irq_status = dwmac4_irq_mtl_status,
953 .flow_ctrl = dwmac4_flow_ctrl,
954 .pmt = dwmac4_pmt,
955 .set_umac_addr = dwmac4_set_umac_addr,
956 .get_umac_addr = dwmac4_get_umac_addr,
957 .set_lpi_mode = dwmac4_set_lpi_mode,
958 .set_eee_timer = dwmac4_set_eee_timer,
959 .set_eee_pls = dwmac4_set_eee_pls,
960 .pcs_ctrl_ane = dwmac4_ctrl_ane,
961 .debug = dwmac4_debug,
962 .set_filter = dwmac4_set_filter,
963 .flex_pps_config = dwmac5_flex_pps_config,
964 .set_mac_loopback = dwmac4_set_mac_loopback,
965 .sarc_configure = dwmac4_sarc_configure,
966 .set_arp_offload = dwmac4_set_arp_offload,
967 .config_l3_filter = dwmac4_config_l3_filter,
968 .config_l4_filter = dwmac4_config_l4_filter,
969 .fpe_map_preemption_class = dwmac5_fpe_map_preemption_class,
970 };
971
972 const struct stmmac_ops dwmac510_ops = {
973 .pcs_init = dwmac4_pcs_init,
974 .core_init = dwmac4_core_init,
975 .irq_modify = dwmac4_irq_modify,
976 .update_caps = dwmac4_update_caps,
977 .set_mac = stmmac_dwmac4_set_mac,
978 .rx_ipc = dwmac4_rx_ipc_enable,
979 .rx_queue_enable = dwmac4_rx_queue_enable,
980 .rx_queue_prio = dwmac4_rx_queue_priority,
981 .tx_queue_prio = dwmac4_tx_queue_priority,
982 .rx_queue_routing = dwmac4_rx_queue_routing,
983 .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
984 .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
985 .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
986 .map_mtl_to_dma = dwmac4_map_mtl_dma,
987 .config_cbs = dwmac4_config_cbs,
988 .dump_regs = dwmac4_dump_regs,
989 .host_irq_status = dwmac4_irq_status,
990 .host_mtl_irq_status = dwmac4_irq_mtl_status,
991 .flow_ctrl = dwmac4_flow_ctrl,
992 .pmt = dwmac4_pmt,
993 .set_umac_addr = dwmac4_set_umac_addr,
994 .get_umac_addr = dwmac4_get_umac_addr,
995 .set_lpi_mode = dwmac4_set_lpi_mode,
996 .set_eee_timer = dwmac4_set_eee_timer,
997 .set_eee_pls = dwmac4_set_eee_pls,
998 .pcs_ctrl_ane = dwmac4_ctrl_ane,
999 .debug = dwmac4_debug,
1000 .set_filter = dwmac4_set_filter,
1001 .safety_feat_config = dwmac5_safety_feat_config,
1002 .safety_feat_irq_status = dwmac5_safety_feat_irq_status,
1003 .safety_feat_dump = dwmac5_safety_feat_dump,
1004 .rxp_config = dwmac5_rxp_config,
1005 .flex_pps_config = dwmac5_flex_pps_config,
1006 .set_mac_loopback = dwmac4_set_mac_loopback,
1007 .sarc_configure = dwmac4_sarc_configure,
1008 .set_arp_offload = dwmac4_set_arp_offload,
1009 .config_l3_filter = dwmac4_config_l3_filter,
1010 .config_l4_filter = dwmac4_config_l4_filter,
1011 .fpe_map_preemption_class = dwmac5_fpe_map_preemption_class,
1012 };
1013
dwmac4_setup(struct stmmac_priv * priv)1014 int dwmac4_setup(struct stmmac_priv *priv)
1015 {
1016 struct mac_device_info *mac = priv->hw;
1017
1018 dev_info(priv->device, "\tDWMAC4/5\n");
1019
1020 priv->dev->priv_flags |= IFF_UNICAST_FLT;
1021 mac->pcsr = priv->ioaddr;
1022 mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
1023 mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
1024 mac->mcast_bits_log2 = 0;
1025
1026 if (mac->multicast_filter_bins)
1027 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
1028
1029 mac->link.caps = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1030 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD;
1031 mac->link.duplex = GMAC_CONFIG_DM;
1032 mac->link.speed10 = GMAC_CONFIG_PS;
1033 mac->link.speed100 = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
1034 mac->link.speed1000 = 0;
1035 mac->link.speed2500 = GMAC_CONFIG_FES;
1036 mac->link.speed_mask = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
1037 mac->mii.addr = GMAC_MDIO_ADDR;
1038 mac->mii.data = GMAC_MDIO_DATA;
1039 mac->mii.addr_mask = GENMASK_U32(25, 21);
1040 mac->mii.reg_mask = GENMASK_U32(20, 16);
1041 mac->mii.clk_csr_mask = GENMASK_U32(11, 8);
1042 mac->num_vlan = stmmac_get_num_vlan(priv->ioaddr);
1043
1044 return 0;
1045 }
1046