1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ALSA SoC Synopsys I2S Audio Layer 4 * 5 * sound/soc/dwc/designware_i2s.c 6 * 7 * Copyright (C) 2010 ST Microelectronics 8 * Rajeev Kumar <rajeevkumar.linux@gmail.com> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/device.h> 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <linux/interrupt.h> 16 #include <linux/mfd/syscon.h> 17 #include <linux/module.h> 18 #include <linux/reset.h> 19 #include <linux/slab.h> 20 #include <linux/pm_runtime.h> 21 #include <sound/designware_i2s.h> 22 #include <sound/pcm.h> 23 #include <sound/pcm_params.h> 24 #include <sound/soc.h> 25 #include <sound/dmaengine_pcm.h> 26 #include "local.h" 27 28 static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val) 29 { 30 writel(val, io_base + reg); 31 } 32 33 static inline u32 i2s_read_reg(void __iomem *io_base, int reg) 34 { 35 return readl(io_base + reg); 36 } 37 38 static inline void i2s_disable_channels(struct dw_i2s_dev *dev, u32 stream) 39 { 40 u32 i = 0; 41 42 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 43 for (i = 0; i < 4; i++) 44 i2s_write_reg(dev->i2s_base, TER(i), 0); 45 } else { 46 for (i = 0; i < 4; i++) 47 i2s_write_reg(dev->i2s_base, RER(i), 0); 48 } 49 } 50 51 static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream) 52 { 53 u32 i = 0; 54 55 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 56 for (i = 0; i < 4; i++) 57 i2s_read_reg(dev->i2s_base, TOR(i)); 58 } else { 59 for (i = 0; i < 4; i++) 60 i2s_read_reg(dev->i2s_base, ROR(i)); 61 } 62 } 63 64 static inline void i2s_disable_irqs(struct dw_i2s_dev *dev, u32 stream, 65 int chan_nr) 66 { 67 u32 i, irq; 68 69 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 70 for (i = 0; i < (chan_nr / 2); i++) { 71 irq = i2s_read_reg(dev->i2s_base, IMR(i)); 72 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30); 73 } 74 } else { 75 for (i = 0; i < (chan_nr / 2); i++) { 76 irq = i2s_read_reg(dev->i2s_base, IMR(i)); 77 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03); 78 } 79 } 80 } 81 82 static inline void i2s_enable_irqs(struct dw_i2s_dev *dev, u32 stream, 83 int chan_nr) 84 { 85 u32 i, irq; 86 87 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 88 for (i = 0; i < (chan_nr / 2); i++) { 89 irq = i2s_read_reg(dev->i2s_base, IMR(i)); 90 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30); 91 } 92 } else { 93 for (i = 0; i < (chan_nr / 2); i++) { 94 irq = i2s_read_reg(dev->i2s_base, IMR(i)); 95 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03); 96 } 97 } 98 } 99 100 static irqreturn_t i2s_irq_handler(int irq, void *dev_id) 101 { 102 struct dw_i2s_dev *dev = dev_id; 103 bool irq_valid = false; 104 u32 isr[4]; 105 int i; 106 107 for (i = 0; i < 4; i++) 108 isr[i] = i2s_read_reg(dev->i2s_base, ISR(i)); 109 110 i2s_clear_irqs(dev, SNDRV_PCM_STREAM_PLAYBACK); 111 i2s_clear_irqs(dev, SNDRV_PCM_STREAM_CAPTURE); 112 113 for (i = 0; i < 4; i++) { 114 /* 115 * Check if TX fifo is empty. If empty fill FIFO with samples 116 * NOTE: Only two channels supported 117 */ 118 if ((isr[i] & ISR_TXFE) && (i == 0) && dev->use_pio) { 119 dw_pcm_push_tx(dev); 120 irq_valid = true; 121 } 122 123 /* 124 * Data available. Retrieve samples from FIFO 125 * NOTE: Only two channels supported 126 */ 127 if ((isr[i] & ISR_RXDA) && (i == 0) && dev->use_pio) { 128 dw_pcm_pop_rx(dev); 129 irq_valid = true; 130 } 131 132 /* Error Handling: TX */ 133 if (isr[i] & ISR_TXFO) { 134 dev_err_ratelimited(dev->dev, "TX overrun (ch_id=%d)\n", i); 135 irq_valid = true; 136 } 137 138 /* Error Handling: TX */ 139 if (isr[i] & ISR_RXFO) { 140 dev_err_ratelimited(dev->dev, "RX overrun (ch_id=%d)\n", i); 141 irq_valid = true; 142 } 143 } 144 145 if (irq_valid) 146 return IRQ_HANDLED; 147 else 148 return IRQ_NONE; 149 } 150 151 static void i2s_enable_dma(struct dw_i2s_dev *dev, u32 stream) 152 { 153 u32 dma_reg = i2s_read_reg(dev->i2s_base, I2S_DMACR); 154 155 /* Enable DMA handshake for stream */ 156 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 157 dma_reg |= I2S_DMAEN_TXBLOCK; 158 else 159 dma_reg |= I2S_DMAEN_RXBLOCK; 160 161 i2s_write_reg(dev->i2s_base, I2S_DMACR, dma_reg); 162 } 163 164 static void i2s_disable_dma(struct dw_i2s_dev *dev, u32 stream) 165 { 166 u32 dma_reg = i2s_read_reg(dev->i2s_base, I2S_DMACR); 167 168 /* Disable DMA handshake for stream */ 169 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 170 dma_reg &= ~I2S_DMAEN_TXBLOCK; 171 i2s_write_reg(dev->i2s_base, I2S_RTXDMA, 1); 172 } else { 173 dma_reg &= ~I2S_DMAEN_RXBLOCK; 174 i2s_write_reg(dev->i2s_base, I2S_RRXDMA, 1); 175 } 176 i2s_write_reg(dev->i2s_base, I2S_DMACR, dma_reg); 177 } 178 179 static void i2s_start(struct dw_i2s_dev *dev, 180 struct snd_pcm_substream *substream) 181 { 182 struct i2s_clk_config_data *config = &dev->config; 183 184 u32 reg = IER_IEN; 185 186 if (dev->tdm_slots) { 187 reg |= (dev->tdm_slots - 1) << IER_TDM_SLOTS_SHIFT; 188 reg |= IER_INTF_TYPE; 189 reg |= dev->frame_offset << IER_FRAME_OFF_SHIFT; 190 } 191 192 i2s_write_reg(dev->i2s_base, IER, reg); 193 194 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 195 i2s_write_reg(dev->i2s_base, ITER, 1); 196 else 197 i2s_write_reg(dev->i2s_base, IRER, 1); 198 199 if (!(dev->use_pio || dev->is_jh7110)) 200 i2s_enable_dma(dev, substream->stream); 201 202 i2s_enable_irqs(dev, substream->stream, config->chan_nr); 203 i2s_write_reg(dev->i2s_base, CER, 1); 204 } 205 206 static void i2s_stop(struct dw_i2s_dev *dev, 207 struct snd_pcm_substream *substream) 208 { 209 210 i2s_clear_irqs(dev, substream->stream); 211 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 212 i2s_write_reg(dev->i2s_base, ITER, 0); 213 else 214 i2s_write_reg(dev->i2s_base, IRER, 0); 215 216 if (!(dev->use_pio || dev->is_jh7110)) 217 i2s_disable_dma(dev, substream->stream); 218 219 i2s_disable_irqs(dev, substream->stream, 8); 220 221 222 if (!dev->active) { 223 i2s_write_reg(dev->i2s_base, CER, 0); 224 i2s_write_reg(dev->i2s_base, IER, 0); 225 } 226 } 227 228 static int dw_i2s_startup(struct snd_pcm_substream *substream, 229 struct snd_soc_dai *cpu_dai) 230 { 231 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); 232 233 if (dev->is_jh7110) { 234 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 235 struct snd_soc_dai_link *dai_link = rtd->dai_link; 236 237 dai_link->trigger_stop = SND_SOC_TRIGGER_ORDER_LDC; 238 } 239 240 return 0; 241 } 242 243 static void dw_i2s_config(struct dw_i2s_dev *dev, int stream) 244 { 245 u32 ch_reg; 246 struct i2s_clk_config_data *config = &dev->config; 247 248 249 i2s_disable_channels(dev, stream); 250 251 for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) { 252 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 253 i2s_write_reg(dev->i2s_base, TCR(ch_reg), 254 dev->xfer_resolution); 255 i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 256 dev->fifo_th - 1); 257 i2s_write_reg(dev->i2s_base, TER(ch_reg), TER_TXCHEN | 258 dev->tdm_mask << TER_TXSLOT_SHIFT); 259 } else { 260 i2s_write_reg(dev->i2s_base, RCR(ch_reg), 261 dev->xfer_resolution); 262 i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 263 dev->fifo_th - 1); 264 i2s_write_reg(dev->i2s_base, RER(ch_reg), RER_RXCHEN | 265 dev->tdm_mask << RER_RXSLOT_SHIFT); 266 } 267 268 } 269 } 270 271 static int dw_i2s_hw_params(struct snd_pcm_substream *substream, 272 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 273 { 274 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 275 struct i2s_clk_config_data *config = &dev->config; 276 int ret; 277 278 switch (params_format(params)) { 279 case SNDRV_PCM_FORMAT_S16_LE: 280 config->data_width = 16; 281 dev->ccr = 0x00; 282 dev->xfer_resolution = 0x02; 283 break; 284 285 case SNDRV_PCM_FORMAT_S24_LE: 286 config->data_width = 24; 287 dev->ccr = 0x08; 288 dev->xfer_resolution = 0x04; 289 break; 290 291 case SNDRV_PCM_FORMAT_S32_LE: 292 config->data_width = 32; 293 dev->ccr = 0x10; 294 dev->xfer_resolution = 0x05; 295 break; 296 297 default: 298 dev_err(dev->dev, "designware-i2s: unsupported PCM fmt"); 299 return -EINVAL; 300 } 301 302 if (dev->tdm_slots) 303 config->data_width = 32; 304 305 config->chan_nr = params_channels(params); 306 307 switch (config->chan_nr) { 308 case EIGHT_CHANNEL_SUPPORT: 309 case SIX_CHANNEL_SUPPORT: 310 case FOUR_CHANNEL_SUPPORT: 311 case TWO_CHANNEL_SUPPORT: 312 break; 313 default: 314 dev_err(dev->dev, "channel not supported\n"); 315 return -EINVAL; 316 } 317 318 dw_i2s_config(dev, substream->stream); 319 320 i2s_write_reg(dev->i2s_base, CCR, dev->ccr); 321 322 config->sample_rate = params_rate(params); 323 324 if (dev->capability & DW_I2S_MASTER) { 325 if (dev->i2s_clk_cfg) { 326 ret = dev->i2s_clk_cfg(config); 327 if (ret < 0) { 328 dev_err(dev->dev, "runtime audio clk config fail\n"); 329 return ret; 330 } 331 } else { 332 u32 bitclk = config->sample_rate * 333 config->data_width * 2; 334 335 ret = clk_set_rate(dev->clk, bitclk); 336 if (ret) { 337 dev_err(dev->dev, "Can't set I2S clock rate: %d\n", 338 ret); 339 return ret; 340 } 341 } 342 } 343 return 0; 344 } 345 346 static int dw_i2s_prepare(struct snd_pcm_substream *substream, 347 struct snd_soc_dai *dai) 348 { 349 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 350 351 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 352 i2s_write_reg(dev->i2s_base, TXFFR, 1); 353 else 354 i2s_write_reg(dev->i2s_base, RXFFR, 1); 355 356 return 0; 357 } 358 359 static int dw_i2s_trigger(struct snd_pcm_substream *substream, 360 int cmd, struct snd_soc_dai *dai) 361 { 362 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 363 int ret = 0; 364 365 switch (cmd) { 366 case SNDRV_PCM_TRIGGER_START: 367 case SNDRV_PCM_TRIGGER_RESUME: 368 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 369 dev->active++; 370 i2s_start(dev, substream); 371 break; 372 373 case SNDRV_PCM_TRIGGER_STOP: 374 case SNDRV_PCM_TRIGGER_SUSPEND: 375 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 376 dev->active--; 377 i2s_stop(dev, substream); 378 break; 379 default: 380 ret = -EINVAL; 381 break; 382 } 383 return ret; 384 } 385 386 static int dw_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 387 { 388 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); 389 int ret = 0; 390 391 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 392 case SND_SOC_DAIFMT_BC_FC: 393 if (dev->capability & DW_I2S_SLAVE) 394 ret = 0; 395 else 396 ret = -EINVAL; 397 break; 398 case SND_SOC_DAIFMT_BP_FP: 399 if (dev->capability & DW_I2S_MASTER) 400 ret = 0; 401 else 402 ret = -EINVAL; 403 break; 404 case SND_SOC_DAIFMT_BC_FP: 405 case SND_SOC_DAIFMT_BP_FC: 406 ret = -EINVAL; 407 break; 408 default: 409 dev_dbg(dev->dev, "dwc : Invalid clock provider format\n"); 410 ret = -EINVAL; 411 break; 412 } 413 414 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 415 case SND_SOC_DAIFMT_I2S: 416 case SND_SOC_DAIFMT_LEFT_J: 417 case SND_SOC_DAIFMT_RIGHT_J: 418 break; 419 case SND_SOC_DAIFMT_DSP_A: 420 dev->frame_offset = 1; 421 break; 422 case SND_SOC_DAIFMT_DSP_B: 423 dev->frame_offset = 0; 424 break; 425 default: 426 dev_err(dev->dev, "DAI format unsupported"); 427 return -EINVAL; 428 } 429 430 return ret; 431 } 432 433 static int dw_i2s_set_tdm_slot(struct snd_soc_dai *cpu_dai, unsigned int tx_mask, 434 unsigned int rx_mask, int slots, int slot_width) 435 { 436 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); 437 438 if (slot_width != 32) 439 return -EINVAL; 440 441 if (slots < 0 || slots > 16) 442 return -EINVAL; 443 444 if (rx_mask != tx_mask) 445 return -EINVAL; 446 447 if (!rx_mask) 448 return -EINVAL; 449 450 dev->tdm_slots = slots; 451 dev->tdm_mask = rx_mask; 452 453 dev->l_reg = RSLOT_TSLOT(ffs(rx_mask) - 1); 454 dev->r_reg = RSLOT_TSLOT(fls(rx_mask) - 1); 455 456 return 0; 457 } 458 459 static int dw_i2s_dai_probe(struct snd_soc_dai *dai) 460 { 461 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 462 463 snd_soc_dai_init_dma_data(dai, &dev->play_dma_data, &dev->capture_dma_data); 464 return 0; 465 } 466 467 static const struct snd_soc_dai_ops dw_i2s_dai_ops = { 468 .probe = dw_i2s_dai_probe, 469 .startup = dw_i2s_startup, 470 .hw_params = dw_i2s_hw_params, 471 .prepare = dw_i2s_prepare, 472 .trigger = dw_i2s_trigger, 473 .set_fmt = dw_i2s_set_fmt, 474 .set_tdm_slot = dw_i2s_set_tdm_slot, 475 }; 476 477 static int dw_i2s_runtime_suspend(struct device *dev) 478 { 479 struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev); 480 481 if (dw_dev->capability & DW_I2S_MASTER) 482 clk_disable(dw_dev->clk); 483 return 0; 484 } 485 486 static int dw_i2s_runtime_resume(struct device *dev) 487 { 488 struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev); 489 int ret; 490 491 if (dw_dev->capability & DW_I2S_MASTER) { 492 ret = clk_enable(dw_dev->clk); 493 if (ret) 494 return ret; 495 } 496 return 0; 497 } 498 499 #ifdef CONFIG_PM 500 static int dw_i2s_suspend(struct snd_soc_component *component) 501 { 502 struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component); 503 504 if (dev->capability & DW_I2S_MASTER) 505 clk_disable(dev->clk); 506 return 0; 507 } 508 509 static int dw_i2s_resume(struct snd_soc_component *component) 510 { 511 struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component); 512 struct snd_soc_dai *dai; 513 int stream, ret; 514 515 if (dev->capability & DW_I2S_MASTER) { 516 ret = clk_enable(dev->clk); 517 if (ret) 518 return ret; 519 } 520 521 for_each_component_dais(component, dai) { 522 for_each_pcm_streams(stream) 523 if (snd_soc_dai_stream_active(dai, stream)) 524 dw_i2s_config(dev, stream); 525 } 526 527 return 0; 528 } 529 530 #else 531 #define dw_i2s_suspend NULL 532 #define dw_i2s_resume NULL 533 #endif 534 535 static const struct snd_soc_component_driver dw_i2s_component = { 536 .name = "dw-i2s", 537 .suspend = dw_i2s_suspend, 538 .resume = dw_i2s_resume, 539 .legacy_dai_naming = 1, 540 }; 541 542 /* 543 * The following tables allow a direct lookup of various parameters 544 * defined in the I2S block's configuration in terms of sound system 545 * parameters. Each table is sized to the number of entries possible 546 * according to the number of configuration bits describing an I2S 547 * block parameter. 548 */ 549 550 /* Maximum bit resolution of a channel - not uniformly spaced */ 551 static const u32 fifo_width[COMP_MAX_WORDSIZE] = { 552 12, 16, 20, 24, 32, 0, 0, 0 553 }; 554 555 /* Width of (DMA) bus */ 556 static const u32 bus_widths[COMP_MAX_DATA_WIDTH] = { 557 DMA_SLAVE_BUSWIDTH_1_BYTE, 558 DMA_SLAVE_BUSWIDTH_2_BYTES, 559 DMA_SLAVE_BUSWIDTH_4_BYTES, 560 DMA_SLAVE_BUSWIDTH_UNDEFINED 561 }; 562 563 /* PCM format to support channel resolution */ 564 static const u32 formats[COMP_MAX_WORDSIZE] = { 565 SNDRV_PCM_FMTBIT_S16_LE, 566 SNDRV_PCM_FMTBIT_S16_LE, 567 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 568 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 569 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 570 0, 571 0, 572 0 573 }; 574 575 static int dw_configure_dai(struct dw_i2s_dev *dev, 576 struct snd_soc_dai_driver *dw_i2s_dai, 577 unsigned int rates) 578 { 579 /* 580 * Read component parameter registers to extract 581 * the I2S block's configuration. 582 */ 583 u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1); 584 u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2); 585 u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1)); 586 u32 idx; 587 588 if (dev->capability & DWC_I2S_RECORD && 589 dev->quirks & DW_I2S_QUIRK_COMP_PARAM1) 590 comp1 = comp1 & ~BIT(5); 591 592 if (dev->capability & DWC_I2S_PLAY && 593 dev->quirks & DW_I2S_QUIRK_COMP_PARAM1) 594 comp1 = comp1 & ~BIT(6); 595 596 if (COMP1_TX_ENABLED(comp1)) { 597 dev_dbg(dev->dev, " designware: play supported\n"); 598 idx = COMP1_TX_WORDSIZE_0(comp1); 599 if (WARN_ON(idx >= ARRAY_SIZE(formats))) 600 return -EINVAL; 601 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE) 602 idx = 1; 603 dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM; 604 dw_i2s_dai->playback.channels_max = 605 1 << (COMP1_TX_CHANNELS(comp1) + 1); 606 dw_i2s_dai->playback.formats = formats[idx]; 607 dw_i2s_dai->playback.rates = rates; 608 } 609 610 if (COMP1_RX_ENABLED(comp1)) { 611 dev_dbg(dev->dev, "designware: record supported\n"); 612 idx = COMP2_RX_WORDSIZE_0(comp2); 613 if (WARN_ON(idx >= ARRAY_SIZE(formats))) 614 return -EINVAL; 615 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE) 616 idx = 1; 617 dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM; 618 dw_i2s_dai->capture.channels_max = 619 1 << (COMP1_RX_CHANNELS(comp1) + 1); 620 dw_i2s_dai->capture.formats = formats[idx]; 621 dw_i2s_dai->capture.rates = rates; 622 } 623 624 if (COMP1_MODE_EN(comp1)) { 625 dev_dbg(dev->dev, "designware: i2s master mode supported\n"); 626 dev->capability |= DW_I2S_MASTER; 627 } else { 628 dev_dbg(dev->dev, "designware: i2s slave mode supported\n"); 629 dev->capability |= DW_I2S_SLAVE; 630 } 631 632 dev->fifo_th = fifo_depth / 2; 633 return 0; 634 } 635 636 static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev, 637 struct snd_soc_dai_driver *dw_i2s_dai, 638 struct resource *res, 639 const struct i2s_platform_data *pdata) 640 { 641 u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1); 642 u32 idx = COMP1_APB_DATA_WIDTH(comp1); 643 int ret; 644 645 if (WARN_ON(idx >= ARRAY_SIZE(bus_widths))) 646 return -EINVAL; 647 648 ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates); 649 if (ret < 0) 650 return ret; 651 652 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE) 653 idx = 1; 654 655 if (dev->is_jh7110) { 656 /* Use platform data and snd_dmaengine_dai_dma_data struct at the same time */ 657 u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2); 658 u32 idx2; 659 660 if (COMP1_TX_ENABLED(comp1)) { 661 idx2 = COMP1_TX_WORDSIZE_0(comp1); 662 dev->play_dma_data.dt.addr = res->start + I2S_TXDMA; 663 dev->play_dma_data.dt.fifo_size = dev->fifo_th * 2 * 664 (fifo_width[idx2]) >> 8; 665 dev->play_dma_data.dt.maxburst = 16; 666 } 667 if (COMP1_RX_ENABLED(comp1)) { 668 idx2 = COMP2_RX_WORDSIZE_0(comp2); 669 dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA; 670 dev->capture_dma_data.dt.fifo_size = dev->fifo_th * 2 * 671 (fifo_width[idx2] >> 8); 672 dev->capture_dma_data.dt.maxburst = 16; 673 } 674 } else { 675 /* Set DMA slaves info */ 676 dev->play_dma_data.pd.data = pdata->play_dma_data; 677 dev->capture_dma_data.pd.data = pdata->capture_dma_data; 678 dev->play_dma_data.pd.addr = res->start + I2S_TXDMA; 679 dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA; 680 dev->play_dma_data.pd.max_burst = 16; 681 dev->capture_dma_data.pd.max_burst = 16; 682 dev->play_dma_data.pd.addr_width = bus_widths[idx]; 683 dev->capture_dma_data.pd.addr_width = bus_widths[idx]; 684 dev->play_dma_data.pd.filter = pdata->filter; 685 dev->capture_dma_data.pd.filter = pdata->filter; 686 } 687 688 return 0; 689 } 690 691 static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev, 692 struct snd_soc_dai_driver *dw_i2s_dai, 693 struct resource *res) 694 { 695 u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1); 696 u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2); 697 u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1)); 698 u32 idx2; 699 int ret; 700 701 ret = dw_configure_dai(dev, dw_i2s_dai, SNDRV_PCM_RATE_8000_192000); 702 if (ret < 0) 703 return ret; 704 705 if (COMP1_TX_ENABLED(comp1)) { 706 idx2 = COMP1_TX_WORDSIZE_0(comp1); 707 708 dev->capability |= DWC_I2S_PLAY; 709 dev->play_dma_data.dt.addr = res->start + I2S_TXDMA; 710 dev->play_dma_data.dt.fifo_size = fifo_depth * 711 (fifo_width[idx2]) >> 8; 712 dev->play_dma_data.dt.maxburst = 16; 713 } 714 if (COMP1_RX_ENABLED(comp1)) { 715 idx2 = COMP2_RX_WORDSIZE_0(comp2); 716 717 dev->capability |= DWC_I2S_RECORD; 718 dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA; 719 dev->capture_dma_data.dt.fifo_size = fifo_depth * 720 (fifo_width[idx2] >> 8); 721 dev->capture_dma_data.dt.maxburst = 16; 722 } 723 724 return 0; 725 726 } 727 728 #ifdef CONFIG_OF 729 /* clocks initialization with master mode on JH7110 SoC */ 730 static int jh7110_i2s_crg_master_init(struct dw_i2s_dev *dev) 731 { 732 static struct clk_bulk_data clks[] = { 733 { .id = "mclk" }, 734 { .id = "mclk_ext" }, 735 { .id = "mclk_inner" }, 736 { .id = "apb" }, 737 { .id = "i2sclk" }, 738 }; 739 struct reset_control *resets = devm_reset_control_array_get_exclusive(dev->dev); 740 int ret; 741 struct clk *pclk; 742 struct clk *bclk_mst; 743 struct clk *mclk; 744 struct clk *mclk_ext; 745 struct clk *mclk_inner; 746 747 if (IS_ERR(resets)) 748 return dev_err_probe(dev->dev, PTR_ERR(resets), "failed to get i2s resets\n"); 749 750 ret = clk_bulk_get(dev->dev, ARRAY_SIZE(clks), clks); 751 if (ret) 752 return dev_err_probe(dev->dev, ret, "failed to get i2s clocks\n"); 753 754 mclk = clks[0].clk; 755 mclk_ext = clks[1].clk; 756 mclk_inner = clks[2].clk; 757 pclk = clks[3].clk; 758 bclk_mst = clks[4].clk; 759 760 ret = clk_prepare_enable(pclk); 761 if (ret) 762 goto exit; 763 764 /* Use inner mclk first and avoid uninitialized gpio for external mclk */ 765 ret = clk_set_parent(mclk, mclk_inner); 766 if (ret) 767 goto err_dis_pclk; 768 769 ret = clk_prepare_enable(bclk_mst); 770 if (ret) 771 goto err_dis_pclk; 772 773 /* deassert resets before set clock parent */ 774 ret = reset_control_deassert(resets); 775 if (ret) 776 goto err_dis_all; 777 778 /* external clock (12.288MHz) for Audio */ 779 ret = clk_set_parent(mclk, mclk_ext); 780 if (ret) 781 goto err_dis_all; 782 783 /* i2sclk will be got and enabled repeatedly later and should be disabled now. */ 784 clk_disable_unprepare(bclk_mst); 785 clk_bulk_put(ARRAY_SIZE(clks), clks); 786 dev->is_jh7110 = true; 787 788 return 0; 789 790 err_dis_all: 791 clk_disable_unprepare(bclk_mst); 792 err_dis_pclk: 793 clk_disable_unprepare(pclk); 794 exit: 795 clk_bulk_put(ARRAY_SIZE(clks), clks); 796 return ret; 797 } 798 799 /* clocks initialization with slave mode on JH7110 SoC */ 800 static int jh7110_i2s_crg_slave_init(struct dw_i2s_dev *dev) 801 { 802 static struct clk_bulk_data clks[] = { 803 { .id = "mclk" }, 804 { .id = "mclk_ext" }, 805 { .id = "apb" }, 806 { .id = "bclk_ext" }, 807 { .id = "lrck_ext" }, 808 { .id = "bclk" }, 809 { .id = "lrck" }, 810 { .id = "mclk_inner" }, 811 { .id = "i2sclk" }, 812 }; 813 struct reset_control *resets = devm_reset_control_array_get_exclusive(dev->dev); 814 int ret; 815 struct clk *pclk; 816 struct clk *bclk_mst; 817 struct clk *bclk_ext; 818 struct clk *lrck_ext; 819 struct clk *bclk; 820 struct clk *lrck; 821 struct clk *mclk; 822 struct clk *mclk_ext; 823 struct clk *mclk_inner; 824 825 if (IS_ERR(resets)) 826 return dev_err_probe(dev->dev, PTR_ERR(resets), "failed to get i2s resets\n"); 827 828 ret = clk_bulk_get(dev->dev, ARRAY_SIZE(clks), clks); 829 if (ret) 830 return dev_err_probe(dev->dev, ret, "failed to get i2s clocks\n"); 831 832 mclk = clks[0].clk; 833 mclk_ext = clks[1].clk; 834 pclk = clks[2].clk; 835 bclk_ext = clks[3].clk; 836 lrck_ext = clks[4].clk; 837 bclk = clks[5].clk; 838 lrck = clks[6].clk; 839 mclk_inner = clks[7].clk; 840 bclk_mst = clks[8].clk; 841 842 ret = clk_prepare_enable(pclk); 843 if (ret) 844 goto exit; 845 846 ret = clk_set_parent(mclk, mclk_inner); 847 if (ret) 848 goto err_dis_pclk; 849 850 ret = clk_prepare_enable(bclk_mst); 851 if (ret) 852 goto err_dis_pclk; 853 854 ret = reset_control_deassert(resets); 855 if (ret) 856 goto err_dis_all; 857 858 /* The sources of BCLK and LRCK are the external codec. */ 859 ret = clk_set_parent(bclk, bclk_ext); 860 if (ret) 861 goto err_dis_all; 862 863 ret = clk_set_parent(lrck, lrck_ext); 864 if (ret) 865 goto err_dis_all; 866 867 ret = clk_set_parent(mclk, mclk_ext); 868 if (ret) 869 goto err_dis_all; 870 871 /* The i2sclk will be got and enabled repeatedly later and should be disabled now. */ 872 clk_disable_unprepare(bclk_mst); 873 clk_bulk_put(ARRAY_SIZE(clks), clks); 874 dev->is_jh7110 = true; 875 876 return 0; 877 878 err_dis_all: 879 clk_disable_unprepare(bclk_mst); 880 err_dis_pclk: 881 clk_disable_unprepare(pclk); 882 exit: 883 clk_bulk_put(ARRAY_SIZE(clks), clks); 884 return ret; 885 } 886 887 /* Special syscon initialization about RX channel with slave mode on JH7110 SoC */ 888 static int jh7110_i2srx_crg_init(struct dw_i2s_dev *dev) 889 { 890 struct regmap *regmap; 891 unsigned int args[2]; 892 893 regmap = syscon_regmap_lookup_by_phandle_args(dev->dev->of_node, 894 "starfive,syscon", 895 2, args); 896 if (IS_ERR(regmap)) 897 return dev_err_probe(dev->dev, PTR_ERR(regmap), "getting the regmap failed\n"); 898 899 /* Enable I2Srx with syscon register, args[0]: offset, args[1]: mask */ 900 regmap_update_bits(regmap, args[0], args[1], args[1]); 901 902 return jh7110_i2s_crg_slave_init(dev); 903 } 904 905 static int jh7110_i2stx0_clk_cfg(struct i2s_clk_config_data *config) 906 { 907 struct dw_i2s_dev *dev = container_of(config, struct dw_i2s_dev, config); 908 u32 bclk_rate = config->sample_rate * 64; 909 910 return clk_set_rate(dev->clk, bclk_rate); 911 } 912 #endif /* CONFIG_OF */ 913 914 static int dw_i2s_probe(struct platform_device *pdev) 915 { 916 const struct i2s_platform_data *pdata = pdev->dev.platform_data; 917 struct dw_i2s_dev *dev; 918 struct resource *res; 919 int ret, irq; 920 struct snd_soc_dai_driver *dw_i2s_dai; 921 const char *clk_id; 922 923 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 924 if (!dev) 925 return -ENOMEM; 926 927 dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL); 928 if (!dw_i2s_dai) 929 return -ENOMEM; 930 931 dw_i2s_dai->ops = &dw_i2s_dai_ops; 932 933 dev->i2s_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 934 if (IS_ERR(dev->i2s_base)) 935 return PTR_ERR(dev->i2s_base); 936 937 dev->dev = &pdev->dev; 938 dev->is_jh7110 = false; 939 if (pdata) { 940 if (pdata->i2s_pd_init) { 941 ret = pdata->i2s_pd_init(dev); 942 if (ret) 943 return ret; 944 } 945 } 946 947 if (!dev->is_jh7110) { 948 dev->reset = devm_reset_control_array_get_optional_shared(&pdev->dev); 949 if (IS_ERR(dev->reset)) 950 return PTR_ERR(dev->reset); 951 952 ret = reset_control_deassert(dev->reset); 953 if (ret) 954 return ret; 955 } 956 957 irq = platform_get_irq_optional(pdev, 0); 958 if (irq >= 0) { 959 ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0, 960 pdev->name, dev); 961 if (ret < 0) { 962 dev_err(&pdev->dev, "failed to request irq\n"); 963 goto err_assert_reset; 964 } 965 } 966 967 dev->i2s_reg_comp1 = I2S_COMP_PARAM_1; 968 dev->i2s_reg_comp2 = I2S_COMP_PARAM_2; 969 if (pdata) { 970 dev->capability = pdata->cap; 971 clk_id = NULL; 972 dev->quirks = pdata->quirks; 973 if (dev->quirks & DW_I2S_QUIRK_COMP_REG_OFFSET) { 974 dev->i2s_reg_comp1 = pdata->i2s_reg_comp1; 975 dev->i2s_reg_comp2 = pdata->i2s_reg_comp2; 976 } 977 ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata); 978 } else { 979 clk_id = "i2sclk"; 980 ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res); 981 } 982 if (ret < 0) 983 goto err_assert_reset; 984 985 if (dev->capability & DW_I2S_MASTER) { 986 if (pdata) { 987 dev->i2s_clk_cfg = pdata->i2s_clk_cfg; 988 if (!dev->i2s_clk_cfg) { 989 dev_err(&pdev->dev, "no clock configure method\n"); 990 ret = -ENODEV; 991 goto err_assert_reset; 992 } 993 } 994 dev->clk = devm_clk_get_enabled(&pdev->dev, clk_id); 995 996 if (IS_ERR(dev->clk)) { 997 ret = PTR_ERR(dev->clk); 998 goto err_assert_reset; 999 } 1000 } 1001 1002 dev_set_drvdata(&pdev->dev, dev); 1003 ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component, 1004 dw_i2s_dai, 1); 1005 if (ret != 0) { 1006 dev_err(&pdev->dev, "not able to register dai\n"); 1007 goto err_assert_reset; 1008 } 1009 1010 if (!pdata || dev->is_jh7110) { 1011 if (irq >= 0) { 1012 ret = dw_pcm_register(pdev); 1013 dev->use_pio = true; 1014 dev->l_reg = LRBR_LTHR(0); 1015 dev->r_reg = RRBR_RTHR(0); 1016 } else { 1017 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 1018 0); 1019 dev->use_pio = false; 1020 } 1021 1022 if (ret) { 1023 dev_err(&pdev->dev, "could not register pcm: %d\n", 1024 ret); 1025 goto err_assert_reset; 1026 } 1027 } 1028 1029 pm_runtime_enable(&pdev->dev); 1030 return 0; 1031 1032 err_assert_reset: 1033 reset_control_assert(dev->reset); 1034 return ret; 1035 } 1036 1037 static void dw_i2s_remove(struct platform_device *pdev) 1038 { 1039 struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev); 1040 1041 reset_control_assert(dev->reset); 1042 pm_runtime_disable(&pdev->dev); 1043 } 1044 1045 #ifdef CONFIG_OF 1046 static const struct i2s_platform_data jh7110_i2stx0_data = { 1047 .cap = DWC_I2S_PLAY | DW_I2S_MASTER, 1048 .channel = TWO_CHANNEL_SUPPORT, 1049 .snd_fmts = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, 1050 .snd_rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000, 1051 .i2s_clk_cfg = jh7110_i2stx0_clk_cfg, 1052 .i2s_pd_init = jh7110_i2s_crg_master_init, 1053 }; 1054 1055 static const struct i2s_platform_data jh7110_i2stx1_data = { 1056 .cap = DWC_I2S_PLAY | DW_I2S_SLAVE, 1057 .channel = TWO_CHANNEL_SUPPORT, 1058 .snd_fmts = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, 1059 .snd_rates = SNDRV_PCM_RATE_8000_192000, 1060 .i2s_pd_init = jh7110_i2s_crg_slave_init, 1061 }; 1062 1063 static const struct i2s_platform_data jh7110_i2srx_data = { 1064 .cap = DWC_I2S_RECORD | DW_I2S_SLAVE, 1065 .channel = TWO_CHANNEL_SUPPORT, 1066 .snd_fmts = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, 1067 .snd_rates = SNDRV_PCM_RATE_8000_192000, 1068 .i2s_pd_init = jh7110_i2srx_crg_init, 1069 }; 1070 1071 static const struct of_device_id dw_i2s_of_match[] = { 1072 { .compatible = "snps,designware-i2s", }, 1073 { .compatible = "starfive,jh7110-i2stx0", .data = &jh7110_i2stx0_data, }, 1074 { .compatible = "starfive,jh7110-i2stx1", .data = &jh7110_i2stx1_data,}, 1075 { .compatible = "starfive,jh7110-i2srx", .data = &jh7110_i2srx_data,}, 1076 {}, 1077 }; 1078 1079 MODULE_DEVICE_TABLE(of, dw_i2s_of_match); 1080 #endif 1081 1082 static const struct dev_pm_ops dwc_pm_ops = { 1083 RUNTIME_PM_OPS(dw_i2s_runtime_suspend, dw_i2s_runtime_resume, NULL) 1084 }; 1085 1086 static struct platform_driver dw_i2s_driver = { 1087 .probe = dw_i2s_probe, 1088 .remove = dw_i2s_remove, 1089 .driver = { 1090 .name = "designware-i2s", 1091 .of_match_table = of_match_ptr(dw_i2s_of_match), 1092 .pm = pm_ptr(&dwc_pm_ops), 1093 }, 1094 }; 1095 1096 module_platform_driver(dw_i2s_driver); 1097 1098 MODULE_AUTHOR("Rajeev Kumar <rajeevkumar.linux@gmail.com>"); 1099 MODULE_DESCRIPTION("DESIGNWARE I2S SoC Interface"); 1100 MODULE_LICENSE("GPL"); 1101 MODULE_ALIAS("platform:designware_i2s"); 1102