1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * core.c - DesignWare USB3 DRD Controller Core file 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/version.h> 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/slab.h> 16 #include <linux/spinlock.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/interrupt.h> 20 #include <linux/ioport.h> 21 #include <linux/io.h> 22 #include <linux/list.h> 23 #include <linux/delay.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/of.h> 26 #include <linux/of_graph.h> 27 #include <linux/acpi.h> 28 #include <linux/pci.h> 29 #include <linux/pinctrl/consumer.h> 30 #include <linux/pinctrl/devinfo.h> 31 #include <linux/reset.h> 32 #include <linux/bitfield.h> 33 34 #include <linux/usb/ch9.h> 35 #include <linux/usb/gadget.h> 36 #include <linux/usb/of.h> 37 #include <linux/usb/otg.h> 38 39 #include "core.h" 40 #include "gadget.h" 41 #include "glue.h" 42 #include "io.h" 43 44 #include "debug.h" 45 #include "../host/xhci-ext-caps.h" 46 47 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 48 49 /** 50 * dwc3_get_dr_mode - Validates and sets dr_mode 51 * @dwc: pointer to our context structure 52 */ 53 static int dwc3_get_dr_mode(struct dwc3 *dwc) 54 { 55 enum usb_dr_mode mode; 56 struct device *dev = dwc->dev; 57 unsigned int hw_mode; 58 59 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 60 dwc->dr_mode = USB_DR_MODE_OTG; 61 62 mode = dwc->dr_mode; 63 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 64 65 switch (hw_mode) { 66 case DWC3_GHWPARAMS0_MODE_GADGET: 67 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 68 dev_err(dev, 69 "Controller does not support host mode.\n"); 70 return -EINVAL; 71 } 72 mode = USB_DR_MODE_PERIPHERAL; 73 break; 74 case DWC3_GHWPARAMS0_MODE_HOST: 75 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 76 dev_err(dev, 77 "Controller does not support device mode.\n"); 78 return -EINVAL; 79 } 80 mode = USB_DR_MODE_HOST; 81 break; 82 default: 83 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 84 mode = USB_DR_MODE_HOST; 85 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 86 mode = USB_DR_MODE_PERIPHERAL; 87 88 /* 89 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG 90 * mode. If the controller supports DRD but the dr_mode is not 91 * specified or set to OTG, then set the mode to peripheral. 92 */ 93 if (mode == USB_DR_MODE_OTG && !dwc->edev && 94 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) || 95 !device_property_read_bool(dwc->dev, "usb-role-switch")) && 96 !DWC3_VER_IS_PRIOR(DWC3, 330A)) 97 mode = USB_DR_MODE_PERIPHERAL; 98 } 99 100 if (mode != dwc->dr_mode) { 101 dev_warn(dev, 102 "Configuration mismatch. dr_mode forced to %s\n", 103 mode == USB_DR_MODE_HOST ? "host" : "gadget"); 104 105 dwc->dr_mode = mode; 106 } 107 108 return 0; 109 } 110 111 void dwc3_enable_susphy(struct dwc3 *dwc, bool enable) 112 { 113 u32 reg; 114 int i; 115 116 for (i = 0; i < dwc->num_usb3_ports; i++) { 117 reg = dwc3_readl(dwc, DWC3_GUSB3PIPECTL(i)); 118 if (enable && !dwc->dis_u3_susphy_quirk) 119 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 120 else 121 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 122 123 dwc3_writel(dwc, DWC3_GUSB3PIPECTL(i), reg); 124 } 125 126 for (i = 0; i < dwc->num_usb2_ports; i++) { 127 reg = dwc3_readl(dwc, DWC3_GUSB2PHYCFG(i)); 128 if (enable && !dwc->dis_u2_susphy_quirk) 129 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 130 else 131 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 132 133 dwc3_writel(dwc, DWC3_GUSB2PHYCFG(i), reg); 134 } 135 } 136 EXPORT_SYMBOL_GPL(dwc3_enable_susphy); 137 138 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode, bool ignore_susphy) 139 { 140 unsigned int hw_mode; 141 u32 reg; 142 143 reg = dwc3_readl(dwc, DWC3_GCTL); 144 145 /* 146 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE and 147 * GUSB2PHYCFG.SUSPHY should be cleared during mode switching, 148 * and they can be set after core initialization. 149 */ 150 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 151 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD && !ignore_susphy) { 152 if (DWC3_GCTL_PRTCAP(reg) != mode) 153 dwc3_enable_susphy(dwc, false); 154 } 155 156 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 157 reg |= DWC3_GCTL_PRTCAPDIR(mode); 158 dwc3_writel(dwc, DWC3_GCTL, reg); 159 160 dwc->current_dr_role = mode; 161 trace_dwc3_set_prtcap(dwc, mode); 162 } 163 EXPORT_SYMBOL_GPL(dwc3_set_prtcap); 164 165 static void __dwc3_set_mode(struct work_struct *work) 166 { 167 struct dwc3 *dwc = work_to_dwc(work); 168 unsigned long flags; 169 int ret; 170 u32 reg; 171 u32 desired_dr_role; 172 int i; 173 174 mutex_lock(&dwc->mutex); 175 spin_lock_irqsave(&dwc->lock, flags); 176 desired_dr_role = dwc->desired_dr_role; 177 spin_unlock_irqrestore(&dwc->lock, flags); 178 179 pm_runtime_get_sync(dwc->dev); 180 181 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) 182 dwc3_otg_update(dwc, 0); 183 184 if (!desired_dr_role) 185 goto out; 186 187 if (desired_dr_role == dwc->current_dr_role) 188 goto out; 189 190 if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) 191 goto out; 192 193 switch (dwc->current_dr_role) { 194 case DWC3_GCTL_PRTCAP_HOST: 195 dwc3_host_exit(dwc); 196 break; 197 case DWC3_GCTL_PRTCAP_DEVICE: 198 dwc3_gadget_exit(dwc); 199 dwc3_event_buffers_cleanup(dwc); 200 break; 201 case DWC3_GCTL_PRTCAP_OTG: 202 dwc3_otg_exit(dwc); 203 spin_lock_irqsave(&dwc->lock, flags); 204 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; 205 spin_unlock_irqrestore(&dwc->lock, flags); 206 dwc3_otg_update(dwc, 1); 207 break; 208 default: 209 break; 210 } 211 212 /* 213 * When current_dr_role is not set, there's no role switching. 214 * Only perform GCTL.CoreSoftReset when there's DRD role switching. 215 */ 216 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) || 217 DWC3_VER_IS_PRIOR(DWC31, 190A)) && 218 desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) { 219 reg = dwc3_readl(dwc, DWC3_GCTL); 220 reg |= DWC3_GCTL_CORESOFTRESET; 221 dwc3_writel(dwc, DWC3_GCTL, reg); 222 223 /* 224 * Wait for internal clocks to synchronized. DWC_usb31 and 225 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To 226 * keep it consistent across different IPs, let's wait up to 227 * 100ms before clearing GCTL.CORESOFTRESET. 228 */ 229 msleep(100); 230 231 reg = dwc3_readl(dwc, DWC3_GCTL); 232 reg &= ~DWC3_GCTL_CORESOFTRESET; 233 dwc3_writel(dwc, DWC3_GCTL, reg); 234 } 235 236 spin_lock_irqsave(&dwc->lock, flags); 237 238 dwc3_set_prtcap(dwc, desired_dr_role, false); 239 240 spin_unlock_irqrestore(&dwc->lock, flags); 241 242 switch (desired_dr_role) { 243 case DWC3_GCTL_PRTCAP_HOST: 244 ret = dwc3_host_init(dwc); 245 if (ret) { 246 dev_err(dwc->dev, "failed to initialize host\n"); 247 } else { 248 if (dwc->usb2_phy) 249 otg_set_vbus(dwc->usb2_phy->otg, true); 250 251 for (i = 0; i < dwc->num_usb2_ports; i++) 252 phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST); 253 for (i = 0; i < dwc->num_usb3_ports; i++) 254 phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST); 255 256 if (dwc->dis_split_quirk) { 257 reg = dwc3_readl(dwc, DWC3_GUCTL3); 258 reg |= DWC3_GUCTL3_SPLITDISABLE; 259 dwc3_writel(dwc, DWC3_GUCTL3, reg); 260 } 261 } 262 break; 263 case DWC3_GCTL_PRTCAP_DEVICE: 264 dwc3_core_soft_reset(dwc); 265 266 dwc3_event_buffers_setup(dwc); 267 268 if (dwc->usb2_phy) 269 otg_set_vbus(dwc->usb2_phy->otg, false); 270 phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE); 271 phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE); 272 273 ret = dwc3_gadget_init(dwc); 274 if (ret) 275 dev_err(dwc->dev, "failed to initialize peripheral\n"); 276 break; 277 case DWC3_GCTL_PRTCAP_OTG: 278 dwc3_otg_init(dwc); 279 dwc3_otg_update(dwc, 0); 280 break; 281 default: 282 break; 283 } 284 285 out: 286 pm_runtime_put_autosuspend(dwc->dev); 287 mutex_unlock(&dwc->mutex); 288 } 289 290 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 291 { 292 unsigned long flags; 293 294 if (dwc->dr_mode != USB_DR_MODE_OTG) 295 return; 296 297 spin_lock_irqsave(&dwc->lock, flags); 298 dwc->desired_dr_role = mode; 299 spin_unlock_irqrestore(&dwc->lock, flags); 300 301 queue_work(system_freezable_wq, &dwc->drd_work); 302 } 303 304 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 305 { 306 struct dwc3 *dwc = dep->dwc; 307 u32 reg; 308 309 dwc3_writel(dwc, DWC3_GDBGFIFOSPACE, 310 DWC3_GDBGFIFOSPACE_NUM(dep->number) | 311 DWC3_GDBGFIFOSPACE_TYPE(type)); 312 313 reg = dwc3_readl(dwc, DWC3_GDBGFIFOSPACE); 314 315 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 316 } 317 318 /** 319 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 320 * @dwc: pointer to our context structure 321 */ 322 int dwc3_core_soft_reset(struct dwc3 *dwc) 323 { 324 u32 reg; 325 int retries = 1000; 326 327 /* 328 * We're resetting only the device side because, if we're in host mode, 329 * XHCI driver will reset the host block. If dwc3 was configured for 330 * host-only mode, then we can return early. 331 */ 332 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) 333 return 0; 334 335 reg = dwc3_readl(dwc, DWC3_DCTL); 336 reg |= DWC3_DCTL_CSFTRST; 337 reg &= ~DWC3_DCTL_RUN_STOP; 338 dwc3_gadget_dctl_write_safe(dwc, reg); 339 340 /* 341 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit 342 * is cleared only after all the clocks are synchronized. This can 343 * take a little more than 50ms. Set the polling rate at 20ms 344 * for 10 times instead. 345 */ 346 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 347 retries = 10; 348 349 do { 350 reg = dwc3_readl(dwc, DWC3_DCTL); 351 if (!(reg & DWC3_DCTL_CSFTRST)) 352 goto done; 353 354 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 355 msleep(20); 356 else 357 udelay(1); 358 } while (--retries); 359 360 dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n"); 361 return -ETIMEDOUT; 362 363 done: 364 /* 365 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit 366 * is cleared, we must wait at least 50ms before accessing the PHY 367 * domain (synchronization delay). 368 */ 369 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A)) 370 msleep(50); 371 372 return 0; 373 } 374 375 /* 376 * dwc3_frame_length_adjustment - Adjusts frame length if required 377 * @dwc3: Pointer to our controller context structure 378 */ 379 static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 380 { 381 u32 reg; 382 u32 dft; 383 384 if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 385 return; 386 387 if (dwc->fladj == 0) 388 return; 389 390 reg = dwc3_readl(dwc, DWC3_GFLADJ); 391 dft = reg & DWC3_GFLADJ_30MHZ_MASK; 392 if (dft != dwc->fladj) { 393 reg &= ~DWC3_GFLADJ_30MHZ_MASK; 394 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 395 dwc3_writel(dwc, DWC3_GFLADJ, reg); 396 } 397 } 398 399 /** 400 * dwc3_ref_clk_period - Reference clock period configuration 401 * Default reference clock period depends on hardware 402 * configuration. For systems with reference clock that differs 403 * from the default, this will set clock period in DWC3_GUCTL 404 * register. 405 * @dwc: Pointer to our controller context structure 406 */ 407 static void dwc3_ref_clk_period(struct dwc3 *dwc) 408 { 409 unsigned long period; 410 unsigned long fladj; 411 unsigned long decr; 412 unsigned long rate; 413 u32 reg; 414 415 if (dwc->ref_clk) { 416 rate = clk_get_rate(dwc->ref_clk); 417 if (!rate) 418 return; 419 period = NSEC_PER_SEC / rate; 420 } else if (dwc->ref_clk_per) { 421 period = dwc->ref_clk_per; 422 rate = NSEC_PER_SEC / period; 423 } else { 424 return; 425 } 426 427 reg = dwc3_readl(dwc, DWC3_GUCTL); 428 reg &= ~DWC3_GUCTL_REFCLKPER_MASK; 429 reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period); 430 dwc3_writel(dwc, DWC3_GUCTL, reg); 431 432 if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 433 return; 434 435 /* 436 * The calculation below is 437 * 438 * 125000 * (NSEC_PER_SEC / (rate * period) - 1) 439 * 440 * but rearranged for fixed-point arithmetic. The division must be 441 * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and 442 * neither does rate * period). 443 * 444 * Note that rate * period ~= NSEC_PER_SECOND, minus the number of 445 * nanoseconds of error caused by the truncation which happened during 446 * the division when calculating rate or period (whichever one was 447 * derived from the other). We first calculate the relative error, then 448 * scale it to units of 8 ppm. 449 */ 450 fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period); 451 fladj -= 125000; 452 453 /* 454 * The documented 240MHz constant is scaled by 2 to get PLS1 as well. 455 */ 456 decr = 480000000 / rate; 457 458 reg = dwc3_readl(dwc, DWC3_GFLADJ); 459 reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK 460 & ~DWC3_GFLADJ_240MHZDECR 461 & ~DWC3_GFLADJ_240MHZDECR_PLS1; 462 reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj) 463 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1) 464 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1); 465 466 if (dwc->gfladj_refclk_lpm_sel) 467 reg |= DWC3_GFLADJ_REFCLK_LPM_SEL; 468 469 dwc3_writel(dwc, DWC3_GFLADJ, reg); 470 } 471 472 /** 473 * dwc3_free_one_event_buffer - Frees one event buffer 474 * @dwc: Pointer to our controller context structure 475 * @evt: Pointer to event buffer to be freed 476 */ 477 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 478 struct dwc3_event_buffer *evt) 479 { 480 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 481 } 482 483 /** 484 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 485 * @dwc: Pointer to our controller context structure 486 * @length: size of the event buffer 487 * 488 * Returns a pointer to the allocated event buffer structure on success 489 * otherwise ERR_PTR(errno). 490 */ 491 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 492 unsigned int length) 493 { 494 struct dwc3_event_buffer *evt; 495 496 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 497 if (!evt) 498 return ERR_PTR(-ENOMEM); 499 500 evt->dwc = dwc; 501 evt->length = length; 502 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 503 if (!evt->cache) 504 return ERR_PTR(-ENOMEM); 505 506 evt->buf = dma_alloc_coherent(dwc->sysdev, length, 507 &evt->dma, GFP_KERNEL); 508 if (!evt->buf) 509 return ERR_PTR(-ENOMEM); 510 511 return evt; 512 } 513 514 /** 515 * dwc3_free_event_buffers - frees all allocated event buffers 516 * @dwc: Pointer to our controller context structure 517 */ 518 static void dwc3_free_event_buffers(struct dwc3 *dwc) 519 { 520 struct dwc3_event_buffer *evt; 521 522 evt = dwc->ev_buf; 523 if (evt) 524 dwc3_free_one_event_buffer(dwc, evt); 525 } 526 527 /** 528 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 529 * @dwc: pointer to our controller context structure 530 * @length: size of event buffer 531 * 532 * Returns 0 on success otherwise negative errno. In the error case, dwc 533 * may contain some buffers allocated but not all which were requested. 534 */ 535 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length) 536 { 537 struct dwc3_event_buffer *evt; 538 unsigned int hw_mode; 539 540 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 541 if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) { 542 dwc->ev_buf = NULL; 543 return 0; 544 } 545 546 evt = dwc3_alloc_one_event_buffer(dwc, length); 547 if (IS_ERR(evt)) { 548 dev_err(dwc->dev, "can't allocate event buffer\n"); 549 return PTR_ERR(evt); 550 } 551 dwc->ev_buf = evt; 552 553 return 0; 554 } 555 556 /** 557 * dwc3_event_buffers_setup - setup our allocated event buffers 558 * @dwc: pointer to our controller context structure 559 * 560 * Returns 0 on success otherwise negative errno. 561 */ 562 int dwc3_event_buffers_setup(struct dwc3 *dwc) 563 { 564 struct dwc3_event_buffer *evt; 565 u32 reg; 566 567 if (!dwc->ev_buf) 568 return 0; 569 570 evt = dwc->ev_buf; 571 evt->lpos = 0; 572 dwc3_writel(dwc, DWC3_GEVNTADRLO(0), 573 lower_32_bits(evt->dma)); 574 dwc3_writel(dwc, DWC3_GEVNTADRHI(0), 575 upper_32_bits(evt->dma)); 576 dwc3_writel(dwc, DWC3_GEVNTSIZ(0), 577 DWC3_GEVNTSIZ_SIZE(evt->length)); 578 579 /* Clear any stale event */ 580 reg = dwc3_readl(dwc, DWC3_GEVNTCOUNT(0)); 581 dwc3_writel(dwc, DWC3_GEVNTCOUNT(0), reg); 582 return 0; 583 } 584 585 void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 586 { 587 struct dwc3_event_buffer *evt; 588 u32 reg; 589 590 if (!dwc->ev_buf) 591 return; 592 /* 593 * Exynos platforms may not be able to access event buffer if the 594 * controller failed to halt on dwc3_core_exit(). 595 */ 596 reg = dwc3_readl(dwc, DWC3_DSTS); 597 if (!(reg & DWC3_DSTS_DEVCTRLHLT)) 598 return; 599 600 evt = dwc->ev_buf; 601 602 evt->lpos = 0; 603 604 dwc3_writel(dwc, DWC3_GEVNTADRLO(0), 0); 605 dwc3_writel(dwc, DWC3_GEVNTADRHI(0), 0); 606 dwc3_writel(dwc, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 607 | DWC3_GEVNTSIZ_SIZE(0)); 608 609 /* Clear any stale event */ 610 reg = dwc3_readl(dwc, DWC3_GEVNTCOUNT(0)); 611 dwc3_writel(dwc, DWC3_GEVNTCOUNT(0), reg); 612 } 613 614 static void dwc3_core_num_eps(struct dwc3 *dwc) 615 { 616 struct dwc3_hwparams *parms = &dwc->hwparams; 617 618 dwc->num_eps = DWC3_NUM_EPS(parms); 619 } 620 621 static void dwc3_cache_hwparams(struct dwc3 *dwc) 622 { 623 struct dwc3_hwparams *parms = &dwc->hwparams; 624 625 parms->hwparams0 = dwc3_readl(dwc, DWC3_GHWPARAMS0); 626 parms->hwparams1 = dwc3_readl(dwc, DWC3_GHWPARAMS1); 627 parms->hwparams2 = dwc3_readl(dwc, DWC3_GHWPARAMS2); 628 parms->hwparams3 = dwc3_readl(dwc, DWC3_GHWPARAMS3); 629 parms->hwparams4 = dwc3_readl(dwc, DWC3_GHWPARAMS4); 630 parms->hwparams5 = dwc3_readl(dwc, DWC3_GHWPARAMS5); 631 parms->hwparams6 = dwc3_readl(dwc, DWC3_GHWPARAMS6); 632 parms->hwparams7 = dwc3_readl(dwc, DWC3_GHWPARAMS7); 633 parms->hwparams8 = dwc3_readl(dwc, DWC3_GHWPARAMS8); 634 635 if (DWC3_IP_IS(DWC32)) 636 parms->hwparams9 = dwc3_readl(dwc, DWC3_GHWPARAMS9); 637 } 638 639 static void dwc3_config_soc_bus(struct dwc3 *dwc) 640 { 641 if (dwc->gsbuscfg0_reqinfo != DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED) { 642 u32 reg; 643 644 reg = dwc3_readl(dwc, DWC3_GSBUSCFG0); 645 reg &= ~DWC3_GSBUSCFG0_REQINFO(~0); 646 reg |= DWC3_GSBUSCFG0_REQINFO(dwc->gsbuscfg0_reqinfo); 647 dwc3_writel(dwc, DWC3_GSBUSCFG0, reg); 648 } 649 } 650 651 static int dwc3_core_ulpi_init(struct dwc3 *dwc) 652 { 653 int intf; 654 int ret = 0; 655 656 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); 657 658 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || 659 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && 660 dwc->hsphy_interface && 661 !strncmp(dwc->hsphy_interface, "ulpi", 4))) 662 ret = dwc3_ulpi_init(dwc); 663 664 return ret; 665 } 666 667 static int dwc3_ss_phy_setup(struct dwc3 *dwc, int index) 668 { 669 u32 reg; 670 671 reg = dwc3_readl(dwc, DWC3_GUSB3PIPECTL(index)); 672 673 /* 674 * Make sure UX_EXIT_PX is cleared as that causes issues with some 675 * PHYs. Also, this bit is not supposed to be used in normal operation. 676 */ 677 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 678 679 /* Ensure the GUSB3PIPECTL.SUSPENDENABLE is cleared prior to phy init. */ 680 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 681 682 if (dwc->u2ss_inp3_quirk) 683 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 684 685 if (dwc->dis_rxdet_inp3_quirk) 686 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 687 688 if (dwc->req_p1p2p3_quirk) 689 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 690 691 if (dwc->del_p1p2p3_quirk) 692 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 693 694 if (dwc->del_phy_power_chg_quirk) 695 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 696 697 if (dwc->lfps_filter_quirk) 698 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 699 700 if (dwc->rx_detect_poll_quirk) 701 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 702 703 if (dwc->tx_de_emphasis_quirk) 704 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 705 706 if (dwc->dis_del_phy_power_chg_quirk) 707 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 708 709 dwc3_writel(dwc, DWC3_GUSB3PIPECTL(index), reg); 710 711 return 0; 712 } 713 714 static int dwc3_hs_phy_setup(struct dwc3 *dwc, int index) 715 { 716 u32 reg; 717 718 reg = dwc3_readl(dwc, DWC3_GUSB2PHYCFG(index)); 719 720 /* Select the HS PHY interface */ 721 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 722 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 723 if (dwc->hsphy_interface && 724 !strncmp(dwc->hsphy_interface, "utmi", 4)) { 725 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 726 break; 727 } else if (dwc->hsphy_interface && 728 !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 729 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 730 dwc3_writel(dwc, DWC3_GUSB2PHYCFG(index), reg); 731 } else { 732 /* Relying on default value. */ 733 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 734 break; 735 } 736 fallthrough; 737 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 738 default: 739 break; 740 } 741 742 switch (dwc->hsphy_mode) { 743 case USBPHY_INTERFACE_MODE_UTMI: 744 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 745 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 746 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 747 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 748 break; 749 case USBPHY_INTERFACE_MODE_UTMIW: 750 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 751 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 752 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 753 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 754 break; 755 default: 756 break; 757 } 758 759 /* Ensure the GUSB2PHYCFG.SUSPHY is cleared prior to phy init. */ 760 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 761 762 if (dwc->dis_enblslpm_quirk) 763 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 764 else 765 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; 766 767 if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel) 768 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 769 770 /* 771 * Some ULPI USB PHY does not support internal VBUS supply, to drive 772 * the CPEN pin requires the configuration of the ULPI DRVVBUSEXTERNAL 773 * bit of OTG_CTRL register. Controller configures the USB2 PHY 774 * ULPIEXTVBUSDRV bit[17] of the GUSB2PHYCFG register to drive vBus 775 * with an external supply. 776 */ 777 if (dwc->ulpi_ext_vbus_drv) 778 reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV; 779 780 dwc3_writel(dwc, DWC3_GUSB2PHYCFG(index), reg); 781 782 return 0; 783 } 784 785 static void dwc3_ulpi_setup(struct dwc3 *dwc) 786 { 787 int index; 788 u32 reg; 789 790 /* Don't do anything if there is no ULPI PHY */ 791 if (!dwc->ulpi) 792 return; 793 794 if (dwc->enable_usb2_transceiver_delay) { 795 for (index = 0; index < dwc->num_usb2_ports; index++) { 796 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(index)); 797 reg |= DWC3_GUSB2PHYCFG_XCVRDLY; 798 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg); 799 } 800 } 801 } 802 803 /** 804 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 805 * @dwc: Pointer to our controller context structure 806 * 807 * Returns 0 on success. The USB PHY interfaces are configured but not 808 * initialized. The PHY interfaces and the PHYs get initialized together with 809 * the core in dwc3_core_init. 810 */ 811 static int dwc3_phy_setup(struct dwc3 *dwc) 812 { 813 int i; 814 int ret; 815 816 for (i = 0; i < dwc->num_usb3_ports; i++) { 817 ret = dwc3_ss_phy_setup(dwc, i); 818 if (ret) 819 return ret; 820 } 821 822 for (i = 0; i < dwc->num_usb2_ports; i++) { 823 ret = dwc3_hs_phy_setup(dwc, i); 824 if (ret) 825 return ret; 826 } 827 828 return 0; 829 } 830 831 static int dwc3_phy_init(struct dwc3 *dwc) 832 { 833 int ret; 834 int i; 835 int j; 836 837 usb_phy_init(dwc->usb2_phy); 838 usb_phy_init(dwc->usb3_phy); 839 840 for (i = 0; i < dwc->num_usb2_ports; i++) { 841 ret = phy_init(dwc->usb2_generic_phy[i]); 842 if (ret < 0) 843 goto err_exit_usb2_phy; 844 } 845 846 for (j = 0; j < dwc->num_usb3_ports; j++) { 847 ret = phy_init(dwc->usb3_generic_phy[j]); 848 if (ret < 0) 849 goto err_exit_usb3_phy; 850 } 851 852 /* 853 * Above DWC_usb3.0 1.94a, it is recommended to set 854 * DWC3_GUSB3PIPECTL_SUSPHY and DWC3_GUSB2PHYCFG_SUSPHY to '0' during 855 * coreConsultant configuration. So default value will be '0' when the 856 * core is reset. Application needs to set it to '1' after the core 857 * initialization is completed. 858 * 859 * Certain phy requires to be in P0 power state during initialization. 860 * Make sure GUSB3PIPECTL.SUSPENDENABLE and GUSB2PHYCFG.SUSPHY are clear 861 * prior to phy init to maintain in the P0 state. 862 * 863 * After phy initialization, some phy operations can only be executed 864 * while in lower P states. Ensure GUSB3PIPECTL.SUSPENDENABLE and 865 * GUSB2PHYCFG.SUSPHY are set soon after initialization to avoid 866 * blocking phy ops. 867 */ 868 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 869 dwc3_enable_susphy(dwc, true); 870 871 return 0; 872 873 err_exit_usb3_phy: 874 while (--j >= 0) 875 phy_exit(dwc->usb3_generic_phy[j]); 876 877 err_exit_usb2_phy: 878 while (--i >= 0) 879 phy_exit(dwc->usb2_generic_phy[i]); 880 881 usb_phy_shutdown(dwc->usb3_phy); 882 usb_phy_shutdown(dwc->usb2_phy); 883 884 return ret; 885 } 886 887 static void dwc3_phy_exit(struct dwc3 *dwc) 888 { 889 int i; 890 891 for (i = 0; i < dwc->num_usb3_ports; i++) 892 phy_exit(dwc->usb3_generic_phy[i]); 893 894 for (i = 0; i < dwc->num_usb2_ports; i++) 895 phy_exit(dwc->usb2_generic_phy[i]); 896 897 usb_phy_shutdown(dwc->usb3_phy); 898 usb_phy_shutdown(dwc->usb2_phy); 899 } 900 901 static int dwc3_phy_power_on(struct dwc3 *dwc) 902 { 903 int ret; 904 int i; 905 int j; 906 907 usb_phy_set_suspend(dwc->usb2_phy, 0); 908 usb_phy_set_suspend(dwc->usb3_phy, 0); 909 910 for (i = 0; i < dwc->num_usb2_ports; i++) { 911 ret = phy_power_on(dwc->usb2_generic_phy[i]); 912 if (ret < 0) 913 goto err_power_off_usb2_phy; 914 } 915 916 for (j = 0; j < dwc->num_usb3_ports; j++) { 917 ret = phy_power_on(dwc->usb3_generic_phy[j]); 918 if (ret < 0) 919 goto err_power_off_usb3_phy; 920 } 921 922 return 0; 923 924 err_power_off_usb3_phy: 925 while (--j >= 0) 926 phy_power_off(dwc->usb3_generic_phy[j]); 927 928 err_power_off_usb2_phy: 929 while (--i >= 0) 930 phy_power_off(dwc->usb2_generic_phy[i]); 931 932 usb_phy_set_suspend(dwc->usb3_phy, 1); 933 usb_phy_set_suspend(dwc->usb2_phy, 1); 934 935 return ret; 936 } 937 938 static void dwc3_phy_power_off(struct dwc3 *dwc) 939 { 940 int i; 941 942 for (i = 0; i < dwc->num_usb3_ports; i++) 943 phy_power_off(dwc->usb3_generic_phy[i]); 944 945 for (i = 0; i < dwc->num_usb2_ports; i++) 946 phy_power_off(dwc->usb2_generic_phy[i]); 947 948 usb_phy_set_suspend(dwc->usb3_phy, 1); 949 usb_phy_set_suspend(dwc->usb2_phy, 1); 950 } 951 952 static int dwc3_clk_enable(struct dwc3 *dwc) 953 { 954 int ret; 955 956 ret = clk_prepare_enable(dwc->bus_clk); 957 if (ret) 958 return ret; 959 960 ret = clk_prepare_enable(dwc->ref_clk); 961 if (ret) 962 goto disable_bus_clk; 963 964 ret = clk_prepare_enable(dwc->susp_clk); 965 if (ret) 966 goto disable_ref_clk; 967 968 ret = clk_prepare_enable(dwc->utmi_clk); 969 if (ret) 970 goto disable_susp_clk; 971 972 ret = clk_prepare_enable(dwc->pipe_clk); 973 if (ret) 974 goto disable_utmi_clk; 975 976 return 0; 977 978 disable_utmi_clk: 979 clk_disable_unprepare(dwc->utmi_clk); 980 disable_susp_clk: 981 clk_disable_unprepare(dwc->susp_clk); 982 disable_ref_clk: 983 clk_disable_unprepare(dwc->ref_clk); 984 disable_bus_clk: 985 clk_disable_unprepare(dwc->bus_clk); 986 return ret; 987 } 988 989 static void dwc3_clk_disable(struct dwc3 *dwc) 990 { 991 clk_disable_unprepare(dwc->pipe_clk); 992 clk_disable_unprepare(dwc->utmi_clk); 993 clk_disable_unprepare(dwc->susp_clk); 994 clk_disable_unprepare(dwc->ref_clk); 995 clk_disable_unprepare(dwc->bus_clk); 996 } 997 998 void dwc3_core_exit(struct dwc3 *dwc) 999 { 1000 dwc3_event_buffers_cleanup(dwc); 1001 dwc3_phy_power_off(dwc); 1002 dwc3_phy_exit(dwc); 1003 dwc3_clk_disable(dwc); 1004 reset_control_assert(dwc->reset); 1005 } 1006 EXPORT_SYMBOL_GPL(dwc3_core_exit); 1007 1008 static bool dwc3_core_is_valid(struct dwc3 *dwc) 1009 { 1010 u32 reg; 1011 1012 reg = dwc3_readl(dwc, DWC3_GSNPSID); 1013 dwc->ip = DWC3_GSNPS_ID(reg); 1014 if (dwc->ip == DWC4_IP) 1015 dwc->ip = DWC32_IP; 1016 1017 /* This should read as U3 followed by revision number */ 1018 if (DWC3_IP_IS(DWC3)) { 1019 dwc->revision = reg; 1020 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) { 1021 dwc->revision = dwc3_readl(dwc, DWC3_VER_NUMBER); 1022 dwc->version_type = dwc3_readl(dwc, DWC3_VER_TYPE); 1023 } else { 1024 return false; 1025 } 1026 1027 return true; 1028 } 1029 1030 static void dwc3_core_setup_global_control(struct dwc3 *dwc) 1031 { 1032 unsigned int power_opt; 1033 unsigned int hw_mode; 1034 u32 reg; 1035 1036 reg = dwc3_readl(dwc, DWC3_GCTL); 1037 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 1038 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 1039 power_opt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); 1040 1041 switch (power_opt) { 1042 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 1043 /** 1044 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 1045 * issue which would cause xHCI compliance tests to fail. 1046 * 1047 * Because of that we cannot enable clock gating on such 1048 * configurations. 1049 * 1050 * Refers to: 1051 * 1052 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 1053 * SOF/ITP Mode Used 1054 */ 1055 if ((dwc->dr_mode == USB_DR_MODE_HOST || 1056 dwc->dr_mode == USB_DR_MODE_OTG) && 1057 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A)) 1058 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 1059 else 1060 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 1061 break; 1062 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 1063 /* 1064 * REVISIT Enabling this bit so that host-mode hibernation 1065 * will work. Device-mode hibernation is not yet implemented. 1066 */ 1067 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 1068 break; 1069 default: 1070 /* nothing */ 1071 break; 1072 } 1073 1074 /* 1075 * This is a workaround for STAR#4846132, which only affects 1076 * DWC_usb31 version2.00a operating in host mode. 1077 * 1078 * There is a problem in DWC_usb31 version 2.00a operating 1079 * in host mode that would cause a CSR read timeout When CSR 1080 * read coincides with RAM Clock Gating Entry. By disable 1081 * Clock Gating, sacrificing power consumption for normal 1082 * operation. 1083 */ 1084 if (power_opt != DWC3_GHWPARAMS1_EN_PWROPT_NO && 1085 hw_mode != DWC3_GHWPARAMS0_MODE_GADGET && DWC3_VER_IS(DWC31, 200A)) 1086 reg |= DWC3_GCTL_DSBLCLKGTNG; 1087 1088 /* check if current dwc3 is on simulation board */ 1089 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 1090 dev_info(dwc->dev, "Running with FPGA optimizations\n"); 1091 dwc->is_fpga = true; 1092 } 1093 1094 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 1095 "disable_scramble cannot be used on non-FPGA builds\n"); 1096 1097 if (dwc->disable_scramble_quirk && dwc->is_fpga) 1098 reg |= DWC3_GCTL_DISSCRAMBLE; 1099 else 1100 reg &= ~DWC3_GCTL_DISSCRAMBLE; 1101 1102 if (dwc->u2exit_lfps_quirk) 1103 reg |= DWC3_GCTL_U2EXIT_LFPS; 1104 1105 /* 1106 * WORKAROUND: DWC3 revisions <1.90a have a bug 1107 * where the device can fail to connect at SuperSpeed 1108 * and falls back to high-speed mode which causes 1109 * the device to enter a Connect/Disconnect loop 1110 */ 1111 if (DWC3_VER_IS_PRIOR(DWC3, 190A)) 1112 reg |= DWC3_GCTL_U2RSTECN; 1113 1114 dwc3_writel(dwc, DWC3_GCTL, reg); 1115 } 1116 1117 static int dwc3_core_get_phy(struct dwc3 *dwc); 1118 static int dwc3_core_ulpi_init(struct dwc3 *dwc); 1119 1120 /* set global incr burst type configuration registers */ 1121 static void dwc3_set_incr_burst_type(struct dwc3 *dwc) 1122 { 1123 struct device *dev = dwc->dev; 1124 /* incrx_mode : for INCR burst type. */ 1125 bool incrx_mode; 1126 /* incrx_size : for size of INCRX burst. */ 1127 u32 incrx_size; 1128 u32 *vals; 1129 u32 cfg; 1130 int ntype; 1131 int ret; 1132 int i; 1133 1134 cfg = dwc3_readl(dwc, DWC3_GSBUSCFG0); 1135 1136 /* 1137 * Handle property "snps,incr-burst-type-adjustment". 1138 * Get the number of value from this property: 1139 * result <= 0, means this property is not supported. 1140 * result = 1, means INCRx burst mode supported. 1141 * result > 1, means undefined length burst mode supported. 1142 */ 1143 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment"); 1144 if (ntype <= 0) 1145 return; 1146 1147 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); 1148 if (!vals) 1149 return; 1150 1151 /* Get INCR burst type, and parse it */ 1152 ret = device_property_read_u32_array(dev, 1153 "snps,incr-burst-type-adjustment", vals, ntype); 1154 if (ret) { 1155 kfree(vals); 1156 dev_err(dev, "Error to get property\n"); 1157 return; 1158 } 1159 1160 incrx_size = *vals; 1161 1162 if (ntype > 1) { 1163 /* INCRX (undefined length) burst mode */ 1164 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; 1165 for (i = 1; i < ntype; i++) { 1166 if (vals[i] > incrx_size) 1167 incrx_size = vals[i]; 1168 } 1169 } else { 1170 /* INCRX burst mode */ 1171 incrx_mode = INCRX_BURST_MODE; 1172 } 1173 1174 kfree(vals); 1175 1176 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ 1177 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; 1178 if (incrx_mode) 1179 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; 1180 switch (incrx_size) { 1181 case 256: 1182 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; 1183 break; 1184 case 128: 1185 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; 1186 break; 1187 case 64: 1188 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; 1189 break; 1190 case 32: 1191 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; 1192 break; 1193 case 16: 1194 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; 1195 break; 1196 case 8: 1197 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; 1198 break; 1199 case 4: 1200 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; 1201 break; 1202 case 1: 1203 break; 1204 default: 1205 dev_err(dev, "Invalid property\n"); 1206 break; 1207 } 1208 1209 dwc3_writel(dwc, DWC3_GSBUSCFG0, cfg); 1210 } 1211 1212 static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc) 1213 { 1214 u32 scale; 1215 u32 reg; 1216 1217 if (!dwc->susp_clk) 1218 return; 1219 1220 /* 1221 * The power down scale field specifies how many suspend_clk 1222 * periods fit into a 16KHz clock period. When performing 1223 * the division, round up the remainder. 1224 * 1225 * The power down scale value is calculated using the fastest 1226 * frequency of the suspend_clk. If it isn't fixed (but within 1227 * the accuracy requirement), the driver may not know the max 1228 * rate of the suspend_clk, so only update the power down scale 1229 * if the default is less than the calculated value from 1230 * clk_get_rate() or if the default is questionably high 1231 * (3x or more) to be within the requirement. 1232 */ 1233 scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000); 1234 reg = dwc3_readl(dwc, DWC3_GCTL); 1235 if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) || 1236 (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) { 1237 reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK); 1238 reg |= DWC3_GCTL_PWRDNSCALE(scale); 1239 dwc3_writel(dwc, DWC3_GCTL, reg); 1240 } 1241 } 1242 1243 static void dwc3_config_threshold(struct dwc3 *dwc) 1244 { 1245 u32 reg; 1246 u8 rx_thr_num; 1247 u8 rx_maxburst; 1248 u8 tx_thr_num; 1249 u8 tx_maxburst; 1250 1251 /* 1252 * Must config both number of packets and max burst settings to enable 1253 * RX and/or TX threshold. 1254 */ 1255 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) { 1256 rx_thr_num = dwc->rx_thr_num_pkt_prd; 1257 rx_maxburst = dwc->rx_max_burst_prd; 1258 tx_thr_num = dwc->tx_thr_num_pkt_prd; 1259 tx_maxburst = dwc->tx_max_burst_prd; 1260 1261 if (rx_thr_num && rx_maxburst) { 1262 reg = dwc3_readl(dwc, DWC3_GRXTHRCFG); 1263 reg |= DWC31_RXTHRNUMPKTSEL_PRD; 1264 1265 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); 1266 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); 1267 1268 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); 1269 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); 1270 1271 dwc3_writel(dwc, DWC3_GRXTHRCFG, reg); 1272 } 1273 1274 if (tx_thr_num && tx_maxburst) { 1275 reg = dwc3_readl(dwc, DWC3_GTXTHRCFG); 1276 reg |= DWC31_TXTHRNUMPKTSEL_PRD; 1277 1278 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); 1279 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); 1280 1281 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); 1282 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); 1283 1284 dwc3_writel(dwc, DWC3_GTXTHRCFG, reg); 1285 } 1286 } 1287 1288 rx_thr_num = dwc->rx_thr_num_pkt; 1289 rx_maxburst = dwc->rx_max_burst; 1290 tx_thr_num = dwc->tx_thr_num_pkt; 1291 tx_maxburst = dwc->tx_max_burst; 1292 1293 if (DWC3_IP_IS(DWC3)) { 1294 if (rx_thr_num && rx_maxburst) { 1295 reg = dwc3_readl(dwc, DWC3_GRXTHRCFG); 1296 reg |= DWC3_GRXTHRCFG_PKTCNTSEL; 1297 1298 reg &= ~DWC3_GRXTHRCFG_RXPKTCNT(~0); 1299 reg |= DWC3_GRXTHRCFG_RXPKTCNT(rx_thr_num); 1300 1301 reg &= ~DWC3_GRXTHRCFG_MAXRXBURSTSIZE(~0); 1302 reg |= DWC3_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst); 1303 1304 dwc3_writel(dwc, DWC3_GRXTHRCFG, reg); 1305 } 1306 1307 if (tx_thr_num && tx_maxburst) { 1308 reg = dwc3_readl(dwc, DWC3_GTXTHRCFG); 1309 reg |= DWC3_GTXTHRCFG_PKTCNTSEL; 1310 1311 reg &= ~DWC3_GTXTHRCFG_TXPKTCNT(~0); 1312 reg |= DWC3_GTXTHRCFG_TXPKTCNT(tx_thr_num); 1313 1314 reg &= ~DWC3_GTXTHRCFG_MAXTXBURSTSIZE(~0); 1315 reg |= DWC3_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst); 1316 1317 dwc3_writel(dwc, DWC3_GTXTHRCFG, reg); 1318 } 1319 } else { 1320 if (rx_thr_num && rx_maxburst) { 1321 reg = dwc3_readl(dwc, DWC3_GRXTHRCFG); 1322 reg |= DWC31_GRXTHRCFG_PKTCNTSEL; 1323 1324 reg &= ~DWC31_GRXTHRCFG_RXPKTCNT(~0); 1325 reg |= DWC31_GRXTHRCFG_RXPKTCNT(rx_thr_num); 1326 1327 reg &= ~DWC31_GRXTHRCFG_MAXRXBURSTSIZE(~0); 1328 reg |= DWC31_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst); 1329 1330 dwc3_writel(dwc, DWC3_GRXTHRCFG, reg); 1331 } 1332 1333 if (tx_thr_num && tx_maxburst) { 1334 reg = dwc3_readl(dwc, DWC3_GTXTHRCFG); 1335 reg |= DWC31_GTXTHRCFG_PKTCNTSEL; 1336 1337 reg &= ~DWC31_GTXTHRCFG_TXPKTCNT(~0); 1338 reg |= DWC31_GTXTHRCFG_TXPKTCNT(tx_thr_num); 1339 1340 reg &= ~DWC31_GTXTHRCFG_MAXTXBURSTSIZE(~0); 1341 reg |= DWC31_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst); 1342 1343 dwc3_writel(dwc, DWC3_GTXTHRCFG, reg); 1344 } 1345 } 1346 } 1347 1348 /** 1349 * dwc3_core_init - Low-level initialization of DWC3 Core 1350 * @dwc: Pointer to our controller context structure 1351 * 1352 * Returns 0 on success otherwise negative errno. 1353 */ 1354 int dwc3_core_init(struct dwc3 *dwc) 1355 { 1356 unsigned int hw_mode; 1357 u32 reg; 1358 int ret; 1359 1360 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 1361 1362 /* 1363 * Write Linux Version Code to our GUID register so it's easy to figure 1364 * out which kernel version a bug was found. 1365 */ 1366 dwc3_writel(dwc, DWC3_GUID, LINUX_VERSION_CODE); 1367 1368 ret = dwc3_phy_setup(dwc); 1369 if (ret) 1370 return ret; 1371 1372 if (!dwc->ulpi_ready) { 1373 ret = dwc3_core_ulpi_init(dwc); 1374 if (ret) { 1375 if (ret == -ETIMEDOUT) { 1376 dwc3_core_soft_reset(dwc); 1377 ret = -EPROBE_DEFER; 1378 } 1379 return ret; 1380 } 1381 dwc->ulpi_ready = true; 1382 } 1383 1384 dwc3_ulpi_setup(dwc); 1385 1386 if (!dwc->phys_ready) { 1387 ret = dwc3_core_get_phy(dwc); 1388 if (ret) 1389 goto err_exit_ulpi; 1390 dwc->phys_ready = true; 1391 } 1392 1393 ret = dwc3_phy_init(dwc); 1394 if (ret) 1395 goto err_exit_ulpi; 1396 1397 ret = dwc3_core_soft_reset(dwc); 1398 if (ret) 1399 goto err_exit_phy; 1400 1401 dwc3_core_setup_global_control(dwc); 1402 dwc3_core_num_eps(dwc); 1403 1404 /* Set power down scale of suspend_clk */ 1405 dwc3_set_power_down_clk_scale(dwc); 1406 1407 /* Adjust Frame Length */ 1408 dwc3_frame_length_adjustment(dwc); 1409 1410 /* Adjust Reference Clock Period */ 1411 dwc3_ref_clk_period(dwc); 1412 1413 dwc3_set_incr_burst_type(dwc); 1414 1415 dwc3_config_soc_bus(dwc); 1416 1417 ret = dwc3_phy_power_on(dwc); 1418 if (ret) 1419 goto err_exit_phy; 1420 1421 ret = dwc3_event_buffers_setup(dwc); 1422 if (ret) { 1423 dev_err(dwc->dev, "failed to setup event buffers\n"); 1424 goto err_power_off_phy; 1425 } 1426 1427 /* 1428 * ENDXFER polling is available on version 3.10a and later of 1429 * the DWC_usb3 controller. It is NOT available in the 1430 * DWC_usb31 controller. 1431 */ 1432 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) { 1433 reg = dwc3_readl(dwc, DWC3_GUCTL2); 1434 reg |= DWC3_GUCTL2_RST_ACTBITLATER; 1435 dwc3_writel(dwc, DWC3_GUCTL2, reg); 1436 } 1437 1438 /* 1439 * STAR 9001285599: This issue affects DWC_usb3 version 3.20a 1440 * only. If the PM TIMER ECM is enabled through GUCTL2[19], the 1441 * link compliance test (TD7.21) may fail. If the ECN is not 1442 * enabled (GUCTL2[19] = 0), the controller will use the old timer 1443 * value (5us), which is still acceptable for the link compliance 1444 * test. Therefore, do not enable PM TIMER ECM in 3.20a by 1445 * setting GUCTL2[19] by default; instead, use GUCTL2[19] = 0. 1446 */ 1447 if (DWC3_VER_IS(DWC3, 320A)) { 1448 reg = dwc3_readl(dwc, DWC3_GUCTL2); 1449 reg &= ~DWC3_GUCTL2_LC_TIMER; 1450 dwc3_writel(dwc, DWC3_GUCTL2, reg); 1451 } 1452 1453 /* 1454 * When configured in HOST mode, after issuing U3/L2 exit controller 1455 * fails to send proper CRC checksum in CRC5 field. Because of this 1456 * behaviour Transaction Error is generated, resulting in reset and 1457 * re-enumeration of usb device attached. All the termsel, xcvrsel, 1458 * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1 1459 * will correct this problem. This option is to support certain 1460 * legacy ULPI PHYs. 1461 */ 1462 if (dwc->resume_hs_terminations) { 1463 reg = dwc3_readl(dwc, DWC3_GUCTL1); 1464 reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST; 1465 dwc3_writel(dwc, DWC3_GUCTL1, reg); 1466 } 1467 1468 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) { 1469 reg = dwc3_readl(dwc, DWC3_GUCTL1); 1470 1471 /* 1472 * Enable hardware control of sending remote wakeup 1473 * in HS when the device is in the L1 state. 1474 */ 1475 if (!DWC3_VER_IS_PRIOR(DWC3, 290A)) 1476 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 1477 1478 /* 1479 * Decouple USB 2.0 L1 & L2 events which will allow for 1480 * gadget driver to only receive U3/L2 suspend & wakeup 1481 * events and prevent the more frequent L1 LPM transitions 1482 * from interrupting the driver. 1483 */ 1484 if (!DWC3_VER_IS_PRIOR(DWC3, 300A)) 1485 reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT; 1486 1487 if (dwc->dis_tx_ipgap_linecheck_quirk) 1488 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 1489 1490 if (dwc->parkmode_disable_ss_quirk) 1491 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; 1492 1493 if (dwc->parkmode_disable_hs_quirk) 1494 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_HS; 1495 1496 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY)) { 1497 if (dwc->maximum_speed == USB_SPEED_FULL || 1498 dwc->maximum_speed == USB_SPEED_HIGH) 1499 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; 1500 else 1501 reg &= ~DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; 1502 } 1503 1504 dwc3_writel(dwc, DWC3_GUCTL1, reg); 1505 } 1506 1507 dwc3_config_threshold(dwc); 1508 1509 if (hw_mode != DWC3_GHWPARAMS0_MODE_GADGET && 1510 (DWC3_IP_IS(DWC31)) && 1511 dwc->maximum_speed == USB_SPEED_SUPER) { 1512 int i; 1513 1514 for (i = 0; i < dwc->num_usb3_ports; i++) { 1515 reg = dwc3_readl(dwc, DWC3_LLUCTL(i)); 1516 reg |= DWC3_LLUCTL_FORCE_GEN1; 1517 dwc3_writel(dwc, DWC3_LLUCTL(i), reg); 1518 } 1519 } 1520 1521 /* 1522 * STAR 9001346572: This issue affects DWC_usb31 versions 1.80a and 1523 * prior. When an active endpoint not currently cached in the host 1524 * controller is chosen to be cached to the same index as an endpoint 1525 * receiving NAKs, the endpoint receiving NAKs enters continuous 1526 * retry mode. This prevents it from being evicted from the host 1527 * controller cache, blocking the new endpoint from being cached and 1528 * serviced. 1529 * 1530 * To resolve this, for controller versions 1.70a and 1.80a, set the 1531 * GUCTL3 bit[16] (USB2.0 Internal Retry Disable) to 1. This bit 1532 * disables the USB2.0 internal retry feature. The GUCTL3[16] register 1533 * function is available only from version 1.70a. 1534 */ 1535 if (DWC3_VER_IS_WITHIN(DWC31, 170A, 180A)) { 1536 reg = dwc3_readl(dwc, DWC3_GUCTL3); 1537 reg |= DWC3_GUCTL3_USB20_RETRY_DISABLE; 1538 dwc3_writel(dwc, DWC3_GUCTL3, reg); 1539 } 1540 1541 return 0; 1542 1543 err_power_off_phy: 1544 dwc3_phy_power_off(dwc); 1545 err_exit_phy: 1546 dwc3_phy_exit(dwc); 1547 err_exit_ulpi: 1548 dwc3_ulpi_exit(dwc); 1549 1550 return ret; 1551 } 1552 EXPORT_SYMBOL_GPL(dwc3_core_init); 1553 1554 static int dwc3_core_get_phy(struct dwc3 *dwc) 1555 { 1556 struct device *dev = dwc->dev; 1557 struct device_node *node = dev->of_node; 1558 char phy_name[9]; 1559 int ret; 1560 u8 i; 1561 1562 if (node) { 1563 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 1564 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 1565 } else { 1566 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 1567 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 1568 } 1569 1570 if (IS_ERR(dwc->usb2_phy)) { 1571 ret = PTR_ERR(dwc->usb2_phy); 1572 if (ret == -ENXIO || ret == -ENODEV) 1573 dwc->usb2_phy = NULL; 1574 else 1575 return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 1576 } 1577 1578 if (IS_ERR(dwc->usb3_phy)) { 1579 ret = PTR_ERR(dwc->usb3_phy); 1580 if (ret == -ENXIO || ret == -ENODEV) 1581 dwc->usb3_phy = NULL; 1582 else 1583 return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 1584 } 1585 1586 for (i = 0; i < dwc->num_usb2_ports; i++) { 1587 if (dwc->num_usb2_ports == 1) 1588 snprintf(phy_name, sizeof(phy_name), "usb2-phy"); 1589 else 1590 snprintf(phy_name, sizeof(phy_name), "usb2-%u", i); 1591 1592 dwc->usb2_generic_phy[i] = devm_phy_get(dev, phy_name); 1593 if (IS_ERR(dwc->usb2_generic_phy[i])) { 1594 ret = PTR_ERR(dwc->usb2_generic_phy[i]); 1595 if (ret == -ENOSYS || ret == -ENODEV) 1596 dwc->usb2_generic_phy[i] = NULL; 1597 else 1598 return dev_err_probe(dev, ret, "failed to lookup phy %s\n", 1599 phy_name); 1600 } 1601 } 1602 1603 for (i = 0; i < dwc->num_usb3_ports; i++) { 1604 if (dwc->num_usb3_ports == 1) 1605 snprintf(phy_name, sizeof(phy_name), "usb3-phy"); 1606 else 1607 snprintf(phy_name, sizeof(phy_name), "usb3-%u", i); 1608 1609 dwc->usb3_generic_phy[i] = devm_phy_get(dev, phy_name); 1610 if (IS_ERR(dwc->usb3_generic_phy[i])) { 1611 ret = PTR_ERR(dwc->usb3_generic_phy[i]); 1612 if (ret == -ENOSYS || ret == -ENODEV) 1613 dwc->usb3_generic_phy[i] = NULL; 1614 else 1615 return dev_err_probe(dev, ret, "failed to lookup phy %s\n", 1616 phy_name); 1617 } 1618 } 1619 1620 return 0; 1621 } 1622 1623 static int dwc3_core_init_mode(struct dwc3 *dwc) 1624 { 1625 struct device *dev = dwc->dev; 1626 int ret; 1627 int i; 1628 1629 switch (dwc->dr_mode) { 1630 case USB_DR_MODE_PERIPHERAL: 1631 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE, false); 1632 1633 if (dwc->usb2_phy) 1634 otg_set_vbus(dwc->usb2_phy->otg, false); 1635 phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE); 1636 phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE); 1637 1638 ret = dwc3_gadget_init(dwc); 1639 if (ret) 1640 return dev_err_probe(dev, ret, "failed to initialize gadget\n"); 1641 break; 1642 case USB_DR_MODE_HOST: 1643 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST, false); 1644 1645 if (dwc->usb2_phy) 1646 otg_set_vbus(dwc->usb2_phy->otg, true); 1647 for (i = 0; i < dwc->num_usb2_ports; i++) 1648 phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST); 1649 for (i = 0; i < dwc->num_usb3_ports; i++) 1650 phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST); 1651 1652 ret = dwc3_host_init(dwc); 1653 if (ret) 1654 return dev_err_probe(dev, ret, "failed to initialize host\n"); 1655 break; 1656 case USB_DR_MODE_OTG: 1657 INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 1658 ret = dwc3_drd_init(dwc); 1659 if (ret) 1660 return dev_err_probe(dev, ret, "failed to initialize dual-role\n"); 1661 break; 1662 default: 1663 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 1664 return -EINVAL; 1665 } 1666 1667 return 0; 1668 } 1669 1670 static void dwc3_core_exit_mode(struct dwc3 *dwc) 1671 { 1672 switch (dwc->dr_mode) { 1673 case USB_DR_MODE_PERIPHERAL: 1674 dwc3_gadget_exit(dwc); 1675 break; 1676 case USB_DR_MODE_HOST: 1677 dwc3_host_exit(dwc); 1678 break; 1679 case USB_DR_MODE_OTG: 1680 dwc3_drd_exit(dwc); 1681 break; 1682 default: 1683 /* do nothing */ 1684 break; 1685 } 1686 1687 /* de-assert DRVVBUS for HOST and OTG mode */ 1688 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE, true); 1689 } 1690 1691 static void dwc3_get_software_properties(struct dwc3 *dwc, 1692 const struct dwc3_properties *properties) 1693 { 1694 struct device *tmpdev; 1695 u16 gsbuscfg0_reqinfo; 1696 int ret; 1697 1698 if (properties->needs_full_reinit) 1699 dwc->needs_full_reinit = true; 1700 1701 dwc->gsbuscfg0_reqinfo = DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED; 1702 1703 if (properties->gsbuscfg0_reqinfo != 1704 DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED) { 1705 dwc->gsbuscfg0_reqinfo = properties->gsbuscfg0_reqinfo; 1706 return; 1707 } 1708 1709 /* 1710 * Iterate over all parent nodes for finding swnode properties 1711 * and non-DT (non-ABI) properties. 1712 */ 1713 for (tmpdev = dwc->dev; tmpdev; tmpdev = tmpdev->parent) { 1714 ret = device_property_read_u16(tmpdev, 1715 "snps,gsbuscfg0-reqinfo", 1716 &gsbuscfg0_reqinfo); 1717 if (!ret) 1718 dwc->gsbuscfg0_reqinfo = gsbuscfg0_reqinfo; 1719 } 1720 } 1721 1722 static void dwc3_get_properties(struct dwc3 *dwc) 1723 { 1724 struct device *dev = dwc->dev; 1725 u8 lpm_nyet_threshold; 1726 u8 tx_de_emphasis; 1727 u8 hird_threshold; 1728 u8 rx_thr_num_pkt = 0; 1729 u8 rx_max_burst = 0; 1730 u8 tx_thr_num_pkt = 0; 1731 u8 tx_max_burst = 0; 1732 u8 rx_thr_num_pkt_prd = 0; 1733 u8 rx_max_burst_prd = 0; 1734 u8 tx_thr_num_pkt_prd = 0; 1735 u8 tx_max_burst_prd = 0; 1736 u8 tx_fifo_resize_max_num; 1737 u16 num_hc_interrupters; 1738 1739 /* default to highest possible threshold */ 1740 lpm_nyet_threshold = 0xf; 1741 1742 /* default to -3.5dB de-emphasis */ 1743 tx_de_emphasis = 1; 1744 1745 /* 1746 * default to assert utmi_sleep_n and use maximum allowed HIRD 1747 * threshold value of 0b1100 1748 */ 1749 hird_threshold = 12; 1750 1751 /* 1752 * default to a TXFIFO size large enough to fit 6 max packets. This 1753 * allows for systems with larger bus latencies to have some headroom 1754 * for endpoints that have a large bMaxBurst value. 1755 */ 1756 tx_fifo_resize_max_num = 6; 1757 1758 /* default to a single XHCI interrupter */ 1759 num_hc_interrupters = 1; 1760 1761 dwc->maximum_speed = usb_get_maximum_speed(dev); 1762 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev); 1763 dwc->dr_mode = usb_get_dr_mode(dev); 1764 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 1765 1766 dwc->sysdev_is_parent = device_property_read_bool(dev, 1767 "linux,sysdev_is_parent"); 1768 if (dwc->sysdev_is_parent) 1769 dwc->sysdev = dwc->dev->parent; 1770 else 1771 dwc->sysdev = dwc->dev; 1772 1773 dwc->sys_wakeup = device_may_wakeup(dwc->sysdev); 1774 1775 dwc->has_lpm_erratum = device_property_read_bool(dev, 1776 "snps,has-lpm-erratum"); 1777 device_property_read_u8(dev, "snps,lpm-nyet-threshold", 1778 &lpm_nyet_threshold); 1779 dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1780 "snps,is-utmi-l1-suspend"); 1781 device_property_read_u8(dev, "snps,hird-threshold", 1782 &hird_threshold); 1783 dwc->dis_start_transfer_quirk = device_property_read_bool(dev, 1784 "snps,dis-start-transfer-quirk"); 1785 dwc->usb3_lpm_capable = device_property_read_bool(dev, 1786 "snps,usb3_lpm_capable"); 1787 dwc->usb2_lpm_disable = device_property_read_bool(dev, 1788 "snps,usb2-lpm-disable"); 1789 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev, 1790 "snps,usb2-gadget-lpm-disable"); 1791 device_property_read_u8(dev, "snps,rx-thr-num-pkt", 1792 &rx_thr_num_pkt); 1793 device_property_read_u8(dev, "snps,rx-max-burst", 1794 &rx_max_burst); 1795 device_property_read_u8(dev, "snps,tx-thr-num-pkt", 1796 &tx_thr_num_pkt); 1797 device_property_read_u8(dev, "snps,tx-max-burst", 1798 &tx_max_burst); 1799 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", 1800 &rx_thr_num_pkt_prd); 1801 device_property_read_u8(dev, "snps,rx-max-burst-prd", 1802 &rx_max_burst_prd); 1803 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", 1804 &tx_thr_num_pkt_prd); 1805 device_property_read_u8(dev, "snps,tx-max-burst-prd", 1806 &tx_max_burst_prd); 1807 device_property_read_u16(dev, "num-hc-interrupters", 1808 &num_hc_interrupters); 1809 /* DWC3 core allowed to have a max of 8 interrupters */ 1810 if (num_hc_interrupters > 8) 1811 num_hc_interrupters = 8; 1812 1813 dwc->do_fifo_resize = device_property_read_bool(dev, 1814 "tx-fifo-resize"); 1815 if (dwc->do_fifo_resize) 1816 device_property_read_u8(dev, "tx-fifo-max-num", 1817 &tx_fifo_resize_max_num); 1818 1819 dwc->disable_scramble_quirk = device_property_read_bool(dev, 1820 "snps,disable_scramble_quirk"); 1821 dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 1822 "snps,u2exit_lfps_quirk"); 1823 dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1824 "snps,u2ss_inp3_quirk"); 1825 dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1826 "snps,req_p1p2p3_quirk"); 1827 dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1828 "snps,del_p1p2p3_quirk"); 1829 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 1830 "snps,del_phy_power_chg_quirk"); 1831 dwc->lfps_filter_quirk = device_property_read_bool(dev, 1832 "snps,lfps_filter_quirk"); 1833 dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 1834 "snps,rx_detect_poll_quirk"); 1835 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 1836 "snps,dis_u3_susphy_quirk"); 1837 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 1838 "snps,dis_u2_susphy_quirk"); 1839 dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1840 "snps,dis_enblslpm_quirk"); 1841 dwc->dis_u1_entry_quirk = device_property_read_bool(dev, 1842 "snps,dis-u1-entry-quirk"); 1843 dwc->dis_u2_entry_quirk = device_property_read_bool(dev, 1844 "snps,dis-u2-entry-quirk"); 1845 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1846 "snps,dis_rxdet_inp3_quirk"); 1847 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 1848 "snps,dis-u2-freeclk-exists-quirk"); 1849 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 1850 "snps,dis-del-phy-power-chg-quirk"); 1851 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 1852 "snps,dis-tx-ipgap-linecheck-quirk"); 1853 dwc->resume_hs_terminations = device_property_read_bool(dev, 1854 "snps,resume-hs-terminations"); 1855 dwc->ulpi_ext_vbus_drv = device_property_read_bool(dev, 1856 "snps,ulpi-ext-vbus-drv"); 1857 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev, 1858 "snps,parkmode-disable-ss-quirk"); 1859 dwc->parkmode_disable_hs_quirk = device_property_read_bool(dev, 1860 "snps,parkmode-disable-hs-quirk"); 1861 dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev, 1862 "snps,gfladj-refclk-lpm-sel-quirk"); 1863 1864 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 1865 "snps,tx_de_emphasis_quirk"); 1866 device_property_read_u8(dev, "snps,tx_de_emphasis", 1867 &tx_de_emphasis); 1868 device_property_read_string(dev, "snps,hsphy_interface", 1869 &dwc->hsphy_interface); 1870 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1871 &dwc->fladj); 1872 device_property_read_u32(dev, "snps,ref-clock-period-ns", 1873 &dwc->ref_clk_per); 1874 1875 dwc->dis_metastability_quirk = device_property_read_bool(dev, 1876 "snps,dis_metastability_quirk"); 1877 1878 dwc->dis_split_quirk = device_property_read_bool(dev, 1879 "snps,dis-split-quirk"); 1880 1881 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 1882 dwc->tx_de_emphasis = tx_de_emphasis; 1883 1884 dwc->hird_threshold = hird_threshold; 1885 1886 dwc->rx_thr_num_pkt = rx_thr_num_pkt; 1887 dwc->rx_max_burst = rx_max_burst; 1888 1889 dwc->tx_thr_num_pkt = tx_thr_num_pkt; 1890 dwc->tx_max_burst = tx_max_burst; 1891 1892 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; 1893 dwc->rx_max_burst_prd = rx_max_burst_prd; 1894 1895 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; 1896 dwc->tx_max_burst_prd = tx_max_burst_prd; 1897 1898 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num; 1899 1900 dwc->num_hc_interrupters = num_hc_interrupters; 1901 } 1902 1903 /* check whether the core supports IMOD */ 1904 bool dwc3_has_imod(struct dwc3 *dwc) 1905 { 1906 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) || 1907 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) || 1908 DWC3_IP_IS(DWC32); 1909 } 1910 1911 static void dwc3_check_params(struct dwc3 *dwc) 1912 { 1913 struct device *dev = dwc->dev; 1914 unsigned int hwparam_gen = 1915 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3); 1916 1917 /* 1918 * Enable IMOD for all supporting controllers. 1919 * 1920 * Particularly, DWC_usb3 v3.00a must enable this feature for 1921 * the following reason: 1922 * 1923 * Workaround for STAR 9000961433 which affects only version 1924 * 3.00a of the DWC_usb3 core. This prevents the controller 1925 * interrupt from being masked while handling events. IMOD 1926 * allows us to work around this issue. Enable it for the 1927 * affected version. 1928 */ 1929 if (dwc3_has_imod((dwc))) 1930 dwc->imod_interval = 1; 1931 1932 /* Check the maximum_speed parameter */ 1933 switch (dwc->maximum_speed) { 1934 case USB_SPEED_FULL: 1935 case USB_SPEED_HIGH: 1936 break; 1937 case USB_SPEED_SUPER: 1938 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) 1939 dev_warn(dev, "UDC doesn't support Gen 1\n"); 1940 break; 1941 case USB_SPEED_SUPER_PLUS: 1942 if ((DWC3_IP_IS(DWC32) && 1943 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) || 1944 (!DWC3_IP_IS(DWC32) && 1945 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1946 dev_warn(dev, "UDC doesn't support SSP\n"); 1947 break; 1948 default: 1949 dev_err(dev, "invalid maximum_speed parameter %d\n", 1950 dwc->maximum_speed); 1951 fallthrough; 1952 case USB_SPEED_UNKNOWN: 1953 switch (hwparam_gen) { 1954 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 1955 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1956 break; 1957 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1958 if (DWC3_IP_IS(DWC32)) 1959 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1960 else 1961 dwc->maximum_speed = USB_SPEED_SUPER; 1962 break; 1963 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS: 1964 dwc->maximum_speed = USB_SPEED_HIGH; 1965 break; 1966 default: 1967 dwc->maximum_speed = USB_SPEED_SUPER; 1968 break; 1969 } 1970 break; 1971 } 1972 1973 /* 1974 * Currently the controller does not have visibility into the HW 1975 * parameter to determine the maximum number of lanes the HW supports. 1976 * If the number of lanes is not specified in the device property, then 1977 * set the default to support dual-lane for DWC_usb32 and single-lane 1978 * for DWC_usb31 for super-speed-plus. 1979 */ 1980 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) { 1981 switch (dwc->max_ssp_rate) { 1982 case USB_SSP_GEN_2x1: 1983 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1) 1984 dev_warn(dev, "UDC only supports Gen 1\n"); 1985 break; 1986 case USB_SSP_GEN_1x2: 1987 case USB_SSP_GEN_2x2: 1988 if (DWC3_IP_IS(DWC31)) 1989 dev_warn(dev, "UDC only supports single lane\n"); 1990 break; 1991 case USB_SSP_GEN_UNKNOWN: 1992 default: 1993 switch (hwparam_gen) { 1994 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 1995 if (DWC3_IP_IS(DWC32)) 1996 dwc->max_ssp_rate = USB_SSP_GEN_2x2; 1997 else 1998 dwc->max_ssp_rate = USB_SSP_GEN_2x1; 1999 break; 2000 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 2001 if (DWC3_IP_IS(DWC32)) 2002 dwc->max_ssp_rate = USB_SSP_GEN_1x2; 2003 break; 2004 } 2005 break; 2006 } 2007 } 2008 } 2009 2010 static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc) 2011 { 2012 struct device *dev = dwc->dev; 2013 struct device_node *np_phy; 2014 struct extcon_dev *edev = NULL; 2015 const char *name; 2016 2017 if (device_property_present(dev, "extcon")) 2018 return extcon_get_edev_by_phandle(dev, 0); 2019 2020 /* 2021 * Device tree platforms should get extcon via phandle. 2022 * On ACPI platforms, we get the name from a device property. 2023 * This device property is for kernel internal use only and 2024 * is expected to be set by the glue code. 2025 */ 2026 if (device_property_read_string(dev, "linux,extcon-name", &name) == 0) 2027 return extcon_get_extcon_dev(name); 2028 2029 /* 2030 * Check explicitly if "usb-role-switch" is used since 2031 * extcon_find_edev_by_node() can not be used to check the absence of 2032 * an extcon device. In the absence of an device it will always return 2033 * EPROBE_DEFER. 2034 */ 2035 if (IS_ENABLED(CONFIG_USB_ROLE_SWITCH) && 2036 device_property_read_bool(dev, "usb-role-switch")) 2037 return NULL; 2038 2039 /* 2040 * Try to get an extcon device from the USB PHY controller's "port" 2041 * node. Check if it has the "port" node first, to avoid printing the 2042 * error message from underlying code, as it's a valid case: extcon 2043 * device (and "port" node) may be missing in case of "usb-role-switch" 2044 * or OTG mode. 2045 */ 2046 np_phy = of_parse_phandle(dev->of_node, "phys", 0); 2047 if (of_graph_is_present(np_phy)) { 2048 struct device_node *np_conn; 2049 2050 np_conn = of_graph_get_remote_node(np_phy, -1, -1); 2051 if (np_conn) 2052 edev = extcon_find_edev_by_node(np_conn); 2053 of_node_put(np_conn); 2054 } 2055 of_node_put(np_phy); 2056 2057 return edev; 2058 } 2059 2060 static int dwc3_get_clocks(struct dwc3 *dwc) 2061 { 2062 struct device *dev = dwc->dev; 2063 2064 if (!dev->of_node) 2065 return 0; 2066 2067 /* 2068 * Clocks are optional, but new DT platforms should support all clocks 2069 * as required by the DT-binding. 2070 * Some devices have different clock names in legacy device trees, 2071 * check for them to retain backwards compatibility. 2072 */ 2073 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early"); 2074 if (IS_ERR(dwc->bus_clk)) { 2075 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 2076 "could not get bus clock\n"); 2077 } 2078 2079 if (dwc->bus_clk == NULL) { 2080 dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk"); 2081 if (IS_ERR(dwc->bus_clk)) { 2082 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 2083 "could not get bus clock\n"); 2084 } 2085 } 2086 2087 dwc->ref_clk = devm_clk_get_optional(dev, "ref"); 2088 if (IS_ERR(dwc->ref_clk)) { 2089 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 2090 "could not get ref clock\n"); 2091 } 2092 2093 if (dwc->ref_clk == NULL) { 2094 dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk"); 2095 if (IS_ERR(dwc->ref_clk)) { 2096 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 2097 "could not get ref clock\n"); 2098 } 2099 } 2100 2101 dwc->susp_clk = devm_clk_get_optional(dev, "suspend"); 2102 if (IS_ERR(dwc->susp_clk)) { 2103 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 2104 "could not get suspend clock\n"); 2105 } 2106 2107 if (dwc->susp_clk == NULL) { 2108 dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk"); 2109 if (IS_ERR(dwc->susp_clk)) { 2110 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 2111 "could not get suspend clock\n"); 2112 } 2113 } 2114 2115 /* specific to Rockchip RK3588 */ 2116 dwc->utmi_clk = devm_clk_get_optional(dev, "utmi"); 2117 if (IS_ERR(dwc->utmi_clk)) { 2118 return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk), 2119 "could not get utmi clock\n"); 2120 } 2121 2122 /* specific to Rockchip RK3588 */ 2123 dwc->pipe_clk = devm_clk_get_optional(dev, "pipe"); 2124 if (IS_ERR(dwc->pipe_clk)) { 2125 return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk), 2126 "could not get pipe clock\n"); 2127 } 2128 2129 return 0; 2130 } 2131 2132 static int dwc3_get_num_ports(struct dwc3 *dwc) 2133 { 2134 void __iomem *base; 2135 u8 major_revision; 2136 u32 offset; 2137 u32 val; 2138 2139 /* 2140 * Remap xHCI address space to access XHCI ext cap regs since it is 2141 * needed to get information on number of ports present. 2142 */ 2143 base = ioremap(dwc->xhci_resources[0].start, 2144 resource_size(&dwc->xhci_resources[0])); 2145 if (!base) 2146 return -ENOMEM; 2147 2148 offset = 0; 2149 do { 2150 offset = xhci_find_next_ext_cap(base, offset, 2151 XHCI_EXT_CAPS_PROTOCOL); 2152 if (!offset) 2153 break; 2154 2155 val = readl(base + offset); 2156 major_revision = XHCI_EXT_PORT_MAJOR(val); 2157 2158 val = readl(base + offset + 0x08); 2159 if (major_revision == 0x03) { 2160 dwc->num_usb3_ports += XHCI_EXT_PORT_COUNT(val); 2161 } else if (major_revision <= 0x02) { 2162 dwc->num_usb2_ports += XHCI_EXT_PORT_COUNT(val); 2163 } else { 2164 dev_warn(dwc->dev, "unrecognized port major revision %d\n", 2165 major_revision); 2166 } 2167 } while (1); 2168 2169 dev_dbg(dwc->dev, "hs-ports: %u ss-ports: %u\n", 2170 dwc->num_usb2_ports, dwc->num_usb3_ports); 2171 2172 iounmap(base); 2173 2174 if (dwc->num_usb2_ports > DWC3_USB2_MAX_PORTS || 2175 dwc->num_usb3_ports > DWC3_USB3_MAX_PORTS) 2176 return -EINVAL; 2177 2178 return 0; 2179 } 2180 2181 static void dwc3_vbus_draw_work(struct work_struct *work) 2182 { 2183 struct dwc3 *dwc = container_of(work, struct dwc3, vbus_draw_work); 2184 union power_supply_propval val = {0}; 2185 int ret; 2186 2187 val.intval = 1000 * (dwc->current_limit); 2188 ret = power_supply_set_property(dwc->usb_psy, POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, &val); 2189 2190 if (ret < 0) 2191 dev_dbg(dwc->dev, "Error (%d) setting vbus draw (%d mA)\n", 2192 ret, dwc->current_limit); 2193 } 2194 2195 static struct power_supply *dwc3_get_usb_power_supply(struct dwc3 *dwc) 2196 { 2197 struct power_supply *usb_psy; 2198 const char *usb_psy_name; 2199 int ret; 2200 2201 ret = device_property_read_string(dwc->dev, "usb-psy-name", &usb_psy_name); 2202 if (ret < 0) 2203 return NULL; 2204 2205 usb_psy = power_supply_get_by_name(usb_psy_name); 2206 if (!usb_psy) 2207 return ERR_PTR(-EPROBE_DEFER); 2208 2209 INIT_WORK(&dwc->vbus_draw_work, dwc3_vbus_draw_work); 2210 return usb_psy; 2211 } 2212 2213 int dwc3_core_probe(const struct dwc3_probe_data *data) 2214 { 2215 struct dwc3 *dwc = data->dwc; 2216 struct device *dev = dwc->dev; 2217 struct resource dwc_res; 2218 unsigned int hw_mode; 2219 void __iomem *regs; 2220 struct resource *res = data->res; 2221 int ret; 2222 2223 dwc->xhci_resources[0].start = res->start; 2224 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 2225 DWC3_XHCI_REGS_END; 2226 dwc->xhci_resources[0].flags = res->flags; 2227 dwc->xhci_resources[0].name = res->name; 2228 2229 /* 2230 * Request memory region but exclude xHCI regs, 2231 * since it will be requested by the xhci-plat driver. 2232 */ 2233 dwc_res = *res; 2234 dwc_res.start += DWC3_GLOBALS_REGS_START; 2235 2236 if (dev->of_node) { 2237 struct device_node *parent = of_get_parent(dev->of_node); 2238 2239 if (of_device_is_compatible(parent, "realtek,rtd-dwc3")) { 2240 dwc_res.start -= DWC3_GLOBALS_REGS_START; 2241 dwc_res.start += DWC3_RTK_RTD_GLOBALS_REGS_START; 2242 } 2243 2244 of_node_put(parent); 2245 } 2246 2247 regs = devm_ioremap_resource(dev, &dwc_res); 2248 if (IS_ERR(regs)) 2249 return PTR_ERR(regs); 2250 2251 dwc->regs = regs; 2252 dwc->regs_size = resource_size(&dwc_res); 2253 2254 dwc3_get_properties(dwc); 2255 2256 dwc3_get_software_properties(dwc, &data->properties); 2257 2258 dwc->usb_psy = dwc3_get_usb_power_supply(dwc); 2259 if (IS_ERR(dwc->usb_psy)) 2260 return dev_err_probe(dev, PTR_ERR(dwc->usb_psy), "couldn't get usb power supply\n"); 2261 2262 if (!data->ignore_clocks_and_resets) { 2263 dwc->reset = devm_reset_control_array_get_optional_shared(dev); 2264 if (IS_ERR(dwc->reset)) { 2265 ret = PTR_ERR(dwc->reset); 2266 goto err_put_psy; 2267 } 2268 2269 ret = dwc3_get_clocks(dwc); 2270 if (ret) 2271 goto err_put_psy; 2272 } 2273 2274 ret = reset_control_deassert(dwc->reset); 2275 if (ret) 2276 goto err_put_psy; 2277 2278 ret = dwc3_clk_enable(dwc); 2279 if (ret) 2280 goto err_assert_reset; 2281 2282 if (!dwc3_core_is_valid(dwc)) { 2283 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 2284 ret = -ENODEV; 2285 goto err_disable_clks; 2286 } 2287 2288 dev_set_drvdata(dev, dwc); 2289 dwc3_cache_hwparams(dwc); 2290 2291 if (!dev_is_pci(dwc->sysdev) && 2292 DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) { 2293 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64)); 2294 if (ret) 2295 goto err_disable_clks; 2296 } 2297 2298 /* 2299 * Currently only DWC3 controllers that are host-only capable 2300 * can have more than one port. 2301 */ 2302 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 2303 if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) { 2304 ret = dwc3_get_num_ports(dwc); 2305 if (ret) 2306 goto err_disable_clks; 2307 } else { 2308 dwc->num_usb2_ports = 1; 2309 dwc->num_usb3_ports = 1; 2310 } 2311 2312 spin_lock_init(&dwc->lock); 2313 mutex_init(&dwc->mutex); 2314 2315 pm_runtime_get_noresume(dev); 2316 pm_runtime_set_active(dev); 2317 pm_runtime_use_autosuspend(dev); 2318 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 2319 pm_runtime_enable(dev); 2320 2321 pm_runtime_forbid(dev); 2322 2323 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 2324 if (ret) { 2325 dev_err(dwc->dev, "failed to allocate event buffers\n"); 2326 ret = -ENOMEM; 2327 goto err_allow_rpm; 2328 } 2329 2330 dwc->edev = dwc3_get_extcon(dwc); 2331 if (IS_ERR(dwc->edev)) { 2332 ret = dev_err_probe(dwc->dev, PTR_ERR(dwc->edev), "failed to get extcon\n"); 2333 goto err_free_event_buffers; 2334 } 2335 2336 ret = dwc3_get_dr_mode(dwc); 2337 if (ret) 2338 goto err_free_event_buffers; 2339 2340 ret = dwc3_core_init(dwc); 2341 if (ret) { 2342 dev_err_probe(dev, ret, "failed to initialize core\n"); 2343 goto err_free_event_buffers; 2344 } 2345 2346 dwc3_check_params(dwc); 2347 dwc3_debugfs_init(dwc); 2348 2349 if (!data->skip_core_init_mode) { 2350 ret = dwc3_core_init_mode(dwc); 2351 if (ret) 2352 goto err_exit_debugfs; 2353 } 2354 2355 pm_runtime_put(dev); 2356 2357 dma_set_max_seg_size(dev, UINT_MAX); 2358 2359 return 0; 2360 2361 err_exit_debugfs: 2362 dwc3_debugfs_exit(dwc); 2363 dwc3_event_buffers_cleanup(dwc); 2364 dwc3_phy_power_off(dwc); 2365 dwc3_phy_exit(dwc); 2366 dwc3_ulpi_exit(dwc); 2367 err_free_event_buffers: 2368 dwc3_free_event_buffers(dwc); 2369 err_allow_rpm: 2370 pm_runtime_allow(dev); 2371 pm_runtime_disable(dev); 2372 pm_runtime_dont_use_autosuspend(dev); 2373 pm_runtime_set_suspended(dev); 2374 pm_runtime_put_noidle(dev); 2375 err_disable_clks: 2376 dwc3_clk_disable(dwc); 2377 err_assert_reset: 2378 reset_control_assert(dwc->reset); 2379 err_put_psy: 2380 if (dwc->usb_psy) 2381 power_supply_put(dwc->usb_psy); 2382 2383 return ret; 2384 } 2385 EXPORT_SYMBOL_GPL(dwc3_core_probe); 2386 2387 static int dwc3_probe(struct platform_device *pdev) 2388 { 2389 struct dwc3_probe_data probe_data = {}; 2390 struct resource *res; 2391 struct dwc3 *dwc; 2392 2393 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2394 if (!res) { 2395 dev_err(&pdev->dev, "missing memory resource\n"); 2396 return -ENODEV; 2397 } 2398 2399 dwc = devm_kzalloc(&pdev->dev, sizeof(*dwc), GFP_KERNEL); 2400 if (!dwc) 2401 return -ENOMEM; 2402 2403 dwc->dev = &pdev->dev; 2404 dwc->glue_ops = NULL; 2405 2406 probe_data.dwc = dwc; 2407 probe_data.res = res; 2408 probe_data.properties = DWC3_DEFAULT_PROPERTIES; 2409 2410 return dwc3_core_probe(&probe_data); 2411 } 2412 2413 void dwc3_core_remove(struct dwc3 *dwc) 2414 { 2415 pm_runtime_get_sync(dwc->dev); 2416 2417 dwc3_core_exit_mode(dwc); 2418 dwc3_debugfs_exit(dwc); 2419 2420 dwc3_core_exit(dwc); 2421 dwc3_ulpi_exit(dwc); 2422 2423 pm_runtime_allow(dwc->dev); 2424 pm_runtime_disable(dwc->dev); 2425 pm_runtime_dont_use_autosuspend(dwc->dev); 2426 pm_runtime_put_noidle(dwc->dev); 2427 /* 2428 * HACK: Clear the driver data, which is currently accessed by parent 2429 * glue drivers, before allowing the parent to suspend. 2430 */ 2431 dev_set_drvdata(dwc->dev, NULL); 2432 pm_runtime_set_suspended(dwc->dev); 2433 2434 dwc3_free_event_buffers(dwc); 2435 2436 if (dwc->usb_psy) { 2437 cancel_work_sync(&dwc->vbus_draw_work); 2438 power_supply_put(dwc->usb_psy); 2439 } 2440 } 2441 EXPORT_SYMBOL_GPL(dwc3_core_remove); 2442 2443 static void dwc3_remove(struct platform_device *pdev) 2444 { 2445 dwc3_core_remove(platform_get_drvdata(pdev)); 2446 } 2447 2448 #ifdef CONFIG_PM 2449 static int dwc3_core_init_for_resume(struct dwc3 *dwc) 2450 { 2451 int ret; 2452 2453 ret = reset_control_deassert(dwc->reset); 2454 if (ret) 2455 return ret; 2456 2457 ret = dwc3_clk_enable(dwc); 2458 if (ret) 2459 goto assert_reset; 2460 2461 ret = dwc3_core_init(dwc); 2462 if (ret) 2463 goto disable_clks; 2464 2465 return 0; 2466 2467 disable_clks: 2468 dwc3_clk_disable(dwc); 2469 assert_reset: 2470 reset_control_assert(dwc->reset); 2471 2472 return ret; 2473 } 2474 2475 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 2476 { 2477 u32 reg; 2478 int i; 2479 int ret; 2480 2481 if (!pm_runtime_suspended(dwc->dev) && !PMSG_IS_AUTO(msg)) { 2482 dwc->susphy_state = (dwc3_readl(dwc, DWC3_GUSB2PHYCFG(0)) & 2483 DWC3_GUSB2PHYCFG_SUSPHY) || 2484 (dwc3_readl(dwc, DWC3_GUSB3PIPECTL(0)) & 2485 DWC3_GUSB3PIPECTL_SUSPHY); 2486 /* 2487 * TI AM62 platform requires SUSPHY to be 2488 * enabled for system suspend to work. 2489 */ 2490 if (!dwc->susphy_state) 2491 dwc3_enable_susphy(dwc, true); 2492 } 2493 2494 switch (dwc->current_dr_role) { 2495 case DWC3_GCTL_PRTCAP_DEVICE: 2496 if (pm_runtime_suspended(dwc->dev)) 2497 break; 2498 ret = dwc3_gadget_suspend(dwc); 2499 if (ret) 2500 return ret; 2501 synchronize_irq(dwc->irq_gadget); 2502 dwc3_core_exit(dwc); 2503 break; 2504 case DWC3_GCTL_PRTCAP_HOST: 2505 if (!PMSG_IS_AUTO(msg) && 2506 (!device_may_wakeup(dwc->dev) || dwc->needs_full_reinit)) { 2507 dwc3_core_exit(dwc); 2508 break; 2509 } 2510 2511 /* Let controller to suspend HSPHY before PHY driver suspends */ 2512 if (dwc->dis_u2_susphy_quirk || 2513 dwc->dis_enblslpm_quirk) { 2514 for (i = 0; i < dwc->num_usb2_ports; i++) { 2515 reg = dwc3_readl(dwc, DWC3_GUSB2PHYCFG(i)); 2516 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | 2517 DWC3_GUSB2PHYCFG_SUSPHY; 2518 dwc3_writel(dwc, DWC3_GUSB2PHYCFG(i), reg); 2519 } 2520 2521 /* Give some time for USB2 PHY to suspend */ 2522 usleep_range(5000, 6000); 2523 } 2524 2525 for (i = 0; i < dwc->num_usb2_ports; i++) 2526 phy_pm_runtime_put_sync(dwc->usb2_generic_phy[i]); 2527 for (i = 0; i < dwc->num_usb3_ports; i++) 2528 phy_pm_runtime_put_sync(dwc->usb3_generic_phy[i]); 2529 break; 2530 case DWC3_GCTL_PRTCAP_OTG: 2531 /* do nothing during runtime_suspend */ 2532 if (PMSG_IS_AUTO(msg)) 2533 break; 2534 2535 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2536 ret = dwc3_gadget_suspend(dwc); 2537 if (ret) 2538 return ret; 2539 synchronize_irq(dwc->irq_gadget); 2540 } 2541 2542 dwc3_otg_exit(dwc); 2543 dwc3_core_exit(dwc); 2544 break; 2545 default: 2546 /* do nothing */ 2547 break; 2548 } 2549 2550 return 0; 2551 } 2552 2553 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 2554 { 2555 int ret; 2556 u32 reg; 2557 int i; 2558 2559 switch (dwc->current_dr_role) { 2560 case DWC3_GCTL_PRTCAP_DEVICE: 2561 ret = dwc3_core_init_for_resume(dwc); 2562 if (ret) 2563 return ret; 2564 2565 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE, true); 2566 dwc3_gadget_resume(dwc); 2567 break; 2568 case DWC3_GCTL_PRTCAP_HOST: 2569 if (!PMSG_IS_AUTO(msg) && 2570 (!device_may_wakeup(dwc->dev) || dwc->needs_full_reinit)) { 2571 ret = dwc3_core_init_for_resume(dwc); 2572 if (ret) 2573 return ret; 2574 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST, true); 2575 break; 2576 } 2577 /* Restore GUSB2PHYCFG bits that were modified in suspend */ 2578 for (i = 0; i < dwc->num_usb2_ports; i++) { 2579 reg = dwc3_readl(dwc, DWC3_GUSB2PHYCFG(i)); 2580 if (dwc->dis_u2_susphy_quirk) 2581 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 2582 2583 if (dwc->dis_enblslpm_quirk) 2584 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 2585 2586 dwc3_writel(dwc, DWC3_GUSB2PHYCFG(i), reg); 2587 } 2588 2589 for (i = 0; i < dwc->num_usb2_ports; i++) 2590 phy_pm_runtime_get_sync(dwc->usb2_generic_phy[i]); 2591 for (i = 0; i < dwc->num_usb3_ports; i++) 2592 phy_pm_runtime_get_sync(dwc->usb3_generic_phy[i]); 2593 break; 2594 case DWC3_GCTL_PRTCAP_OTG: 2595 /* nothing to do on runtime_resume */ 2596 if (PMSG_IS_AUTO(msg)) 2597 break; 2598 2599 ret = dwc3_core_init_for_resume(dwc); 2600 if (ret) 2601 return ret; 2602 2603 dwc3_set_prtcap(dwc, dwc->current_dr_role, true); 2604 2605 dwc3_otg_init(dwc); 2606 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { 2607 dwc3_otg_host_init(dwc); 2608 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2609 dwc3_gadget_resume(dwc); 2610 } 2611 2612 break; 2613 default: 2614 /* do nothing */ 2615 break; 2616 } 2617 2618 if (!PMSG_IS_AUTO(msg)) { 2619 /* restore SUSPHY state to that before system suspend. */ 2620 dwc3_enable_susphy(dwc, dwc->susphy_state); 2621 } 2622 2623 return 0; 2624 } 2625 2626 static int dwc3_runtime_checks(struct dwc3 *dwc) 2627 { 2628 switch (dwc->current_dr_role) { 2629 case DWC3_GCTL_PRTCAP_DEVICE: 2630 if (dwc->connected) 2631 return -EBUSY; 2632 break; 2633 case DWC3_GCTL_PRTCAP_HOST: 2634 default: 2635 /* do nothing */ 2636 break; 2637 } 2638 2639 return 0; 2640 } 2641 2642 int dwc3_runtime_suspend(struct dwc3 *dwc) 2643 { 2644 int ret; 2645 2646 if (dwc3_runtime_checks(dwc)) 2647 return -EBUSY; 2648 2649 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); 2650 if (ret) 2651 return ret; 2652 2653 return 0; 2654 } 2655 EXPORT_SYMBOL_GPL(dwc3_runtime_suspend); 2656 2657 int dwc3_runtime_resume(struct dwc3 *dwc) 2658 { 2659 struct device *dev = dwc->dev; 2660 int ret; 2661 2662 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); 2663 if (ret) 2664 return ret; 2665 2666 switch (dwc->current_dr_role) { 2667 case DWC3_GCTL_PRTCAP_DEVICE: 2668 if (dwc->pending_events) { 2669 pm_runtime_put(dev); 2670 dwc->pending_events = false; 2671 enable_irq(dwc->irq_gadget); 2672 } 2673 break; 2674 case DWC3_GCTL_PRTCAP_HOST: 2675 default: 2676 /* do nothing */ 2677 break; 2678 } 2679 2680 pm_runtime_mark_last_busy(dev); 2681 2682 return 0; 2683 } 2684 EXPORT_SYMBOL_GPL(dwc3_runtime_resume); 2685 2686 int dwc3_runtime_idle(struct dwc3 *dwc) 2687 { 2688 struct device *dev = dwc->dev; 2689 2690 switch (dwc->current_dr_role) { 2691 case DWC3_GCTL_PRTCAP_DEVICE: 2692 if (dwc3_runtime_checks(dwc)) 2693 return -EBUSY; 2694 break; 2695 case DWC3_GCTL_PRTCAP_HOST: 2696 default: 2697 /* do nothing */ 2698 break; 2699 } 2700 2701 pm_runtime_autosuspend(dev); 2702 2703 return 0; 2704 } 2705 EXPORT_SYMBOL_GPL(dwc3_runtime_idle); 2706 2707 static int dwc3_plat_runtime_suspend(struct device *dev) 2708 { 2709 return dwc3_runtime_suspend(dev_get_drvdata(dev)); 2710 } 2711 2712 static int dwc3_plat_runtime_resume(struct device *dev) 2713 { 2714 return dwc3_runtime_resume(dev_get_drvdata(dev)); 2715 } 2716 2717 static int dwc3_plat_runtime_idle(struct device *dev) 2718 { 2719 return dwc3_runtime_idle(dev_get_drvdata(dev)); 2720 } 2721 #endif /* CONFIG_PM */ 2722 2723 #ifdef CONFIG_PM_SLEEP 2724 int dwc3_pm_suspend(struct dwc3 *dwc) 2725 { 2726 struct device *dev = dwc->dev; 2727 int ret; 2728 2729 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); 2730 if (ret) 2731 return ret; 2732 2733 pinctrl_pm_select_sleep_state(dev); 2734 2735 return 0; 2736 } 2737 EXPORT_SYMBOL_GPL(dwc3_pm_suspend); 2738 2739 int dwc3_pm_resume(struct dwc3 *dwc) 2740 { 2741 struct device *dev = dwc->dev; 2742 int ret = 0; 2743 2744 pinctrl_pm_select_default_state(dev); 2745 2746 pm_runtime_disable(dev); 2747 ret = pm_runtime_set_active(dev); 2748 if (ret) 2749 goto out; 2750 2751 ret = dwc3_resume_common(dwc, PMSG_RESUME); 2752 if (ret) 2753 pm_runtime_set_suspended(dev); 2754 2755 out: 2756 pm_runtime_enable(dev); 2757 2758 return ret; 2759 } 2760 EXPORT_SYMBOL_GPL(dwc3_pm_resume); 2761 2762 void dwc3_pm_complete(struct dwc3 *dwc) 2763 { 2764 u32 reg; 2765 2766 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST && 2767 dwc->dis_split_quirk) { 2768 reg = dwc3_readl(dwc, DWC3_GUCTL3); 2769 reg |= DWC3_GUCTL3_SPLITDISABLE; 2770 dwc3_writel(dwc, DWC3_GUCTL3, reg); 2771 } 2772 } 2773 EXPORT_SYMBOL_GPL(dwc3_pm_complete); 2774 2775 int dwc3_pm_prepare(struct dwc3 *dwc) 2776 { 2777 struct device *dev = dwc->dev; 2778 2779 /* 2780 * Indicate to the PM core that it may safely leave the device in 2781 * runtime suspend if runtime-suspended already in device mode. 2782 */ 2783 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_DEVICE && 2784 pm_runtime_suspended(dev) && 2785 !dev_pinctrl(dev)) 2786 return 1; 2787 2788 return 0; 2789 } 2790 EXPORT_SYMBOL_GPL(dwc3_pm_prepare); 2791 2792 static int dwc3_plat_suspend(struct device *dev) 2793 { 2794 return dwc3_pm_suspend(dev_get_drvdata(dev)); 2795 } 2796 2797 static int dwc3_plat_resume(struct device *dev) 2798 { 2799 return dwc3_pm_resume(dev_get_drvdata(dev)); 2800 } 2801 2802 static void dwc3_plat_complete(struct device *dev) 2803 { 2804 dwc3_pm_complete(dev_get_drvdata(dev)); 2805 } 2806 2807 static int dwc3_plat_prepare(struct device *dev) 2808 { 2809 return dwc3_pm_prepare(dev_get_drvdata(dev)); 2810 } 2811 #else 2812 #define dwc3_plat_complete NULL 2813 #define dwc3_plat_prepare NULL 2814 #endif /* CONFIG_PM_SLEEP */ 2815 2816 static const struct dev_pm_ops dwc3_dev_pm_ops = { 2817 SET_SYSTEM_SLEEP_PM_OPS(dwc3_plat_suspend, dwc3_plat_resume) 2818 .complete = dwc3_plat_complete, 2819 .prepare = dwc3_plat_prepare, 2820 /* 2821 * Runtime suspend halts the controller on disconnection. It relies on 2822 * platforms with custom connection notification to start the controller 2823 * again. 2824 */ 2825 SET_RUNTIME_PM_OPS(dwc3_plat_runtime_suspend, dwc3_plat_runtime_resume, 2826 dwc3_plat_runtime_idle) 2827 }; 2828 2829 #ifdef CONFIG_OF 2830 static const struct of_device_id of_dwc3_match[] = { 2831 { 2832 .compatible = "snps,dwc3" 2833 }, 2834 { 2835 .compatible = "synopsys,dwc3" 2836 }, 2837 { }, 2838 }; 2839 MODULE_DEVICE_TABLE(of, of_dwc3_match); 2840 #endif 2841 2842 #ifdef CONFIG_ACPI 2843 2844 #define ACPI_ID_INTEL_BSW "808622B7" 2845 2846 static const struct acpi_device_id dwc3_acpi_match[] = { 2847 { ACPI_ID_INTEL_BSW, 0 }, 2848 { }, 2849 }; 2850 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 2851 #endif 2852 2853 static struct platform_driver dwc3_driver = { 2854 .probe = dwc3_probe, 2855 .remove = dwc3_remove, 2856 .driver = { 2857 .name = "dwc3", 2858 .of_match_table = of_match_ptr(of_dwc3_match), 2859 .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 2860 .pm = &dwc3_dev_pm_ops, 2861 }, 2862 }; 2863 2864 module_platform_driver(dwc3_driver); 2865 2866 MODULE_ALIAS("platform:dwc3"); 2867 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 2868 MODULE_LICENSE("GPL v2"); 2869 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 2870