1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Synopsys DesignWare PCIe host controller driver
4 *
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 * https://www.samsung.com
7 *
8 * Author: Jingoo Han <jg1.han@samsung.com>
9 */
10
11 #include <linux/align.h>
12 #include <linux/bitops.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/dma/edma.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/ioport.h>
18 #include <linux/of.h>
19 #include <linux/of_address.h>
20 #include <linux/pcie-dwc.h>
21 #include <linux/platform_device.h>
22 #include <linux/sizes.h>
23 #include <linux/types.h>
24
25 #include "../../pci.h"
26 #include "pcie-designware.h"
27
28 static const char * const dw_pcie_app_clks[DW_PCIE_NUM_APP_CLKS] = {
29 [DW_PCIE_DBI_CLK] = "dbi",
30 [DW_PCIE_MSTR_CLK] = "mstr",
31 [DW_PCIE_SLV_CLK] = "slv",
32 };
33
34 static const char * const dw_pcie_core_clks[DW_PCIE_NUM_CORE_CLKS] = {
35 [DW_PCIE_PIPE_CLK] = "pipe",
36 [DW_PCIE_CORE_CLK] = "core",
37 [DW_PCIE_AUX_CLK] = "aux",
38 [DW_PCIE_REF_CLK] = "ref",
39 };
40
41 static const char * const dw_pcie_app_rsts[DW_PCIE_NUM_APP_RSTS] = {
42 [DW_PCIE_DBI_RST] = "dbi",
43 [DW_PCIE_MSTR_RST] = "mstr",
44 [DW_PCIE_SLV_RST] = "slv",
45 };
46
47 static const char * const dw_pcie_core_rsts[DW_PCIE_NUM_CORE_RSTS] = {
48 [DW_PCIE_NON_STICKY_RST] = "non-sticky",
49 [DW_PCIE_STICKY_RST] = "sticky",
50 [DW_PCIE_CORE_RST] = "core",
51 [DW_PCIE_PIPE_RST] = "pipe",
52 [DW_PCIE_PHY_RST] = "phy",
53 [DW_PCIE_HOT_RST] = "hot",
54 [DW_PCIE_PWR_RST] = "pwr",
55 };
56
57 static const struct dwc_pcie_vsec_id dwc_pcie_ptm_vsec_ids[] = {
58 { .vendor_id = PCI_VENDOR_ID_QCOM, /* EP */
59 .vsec_id = 0x03, .vsec_rev = 0x1 },
60 { .vendor_id = PCI_VENDOR_ID_QCOM, /* RC */
61 .vsec_id = 0x04, .vsec_rev = 0x1 },
62 { }
63 };
64
dw_pcie_get_clocks(struct dw_pcie * pci)65 static int dw_pcie_get_clocks(struct dw_pcie *pci)
66 {
67 int i, ret;
68
69 for (i = 0; i < DW_PCIE_NUM_APP_CLKS; i++)
70 pci->app_clks[i].id = dw_pcie_app_clks[i];
71
72 for (i = 0; i < DW_PCIE_NUM_CORE_CLKS; i++)
73 pci->core_clks[i].id = dw_pcie_core_clks[i];
74
75 ret = devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_APP_CLKS,
76 pci->app_clks);
77 if (ret)
78 return ret;
79
80 return devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_CORE_CLKS,
81 pci->core_clks);
82 }
83
dw_pcie_get_resets(struct dw_pcie * pci)84 static int dw_pcie_get_resets(struct dw_pcie *pci)
85 {
86 int i, ret;
87
88 for (i = 0; i < DW_PCIE_NUM_APP_RSTS; i++)
89 pci->app_rsts[i].id = dw_pcie_app_rsts[i];
90
91 for (i = 0; i < DW_PCIE_NUM_CORE_RSTS; i++)
92 pci->core_rsts[i].id = dw_pcie_core_rsts[i];
93
94 ret = devm_reset_control_bulk_get_optional_shared(pci->dev,
95 DW_PCIE_NUM_APP_RSTS,
96 pci->app_rsts);
97 if (ret)
98 return ret;
99
100 ret = devm_reset_control_bulk_get_optional_exclusive(pci->dev,
101 DW_PCIE_NUM_CORE_RSTS,
102 pci->core_rsts);
103 if (ret)
104 return ret;
105
106 pci->pe_rst = devm_gpiod_get_optional(pci->dev, "reset", GPIOD_OUT_HIGH);
107 if (IS_ERR(pci->pe_rst))
108 return PTR_ERR(pci->pe_rst);
109
110 return 0;
111 }
112
dw_pcie_get_resources(struct dw_pcie * pci)113 int dw_pcie_get_resources(struct dw_pcie *pci)
114 {
115 struct platform_device *pdev = to_platform_device(pci->dev);
116 struct device_node *np = dev_of_node(pci->dev);
117 struct resource *res;
118 int ret;
119
120 if (!pci->dbi_base) {
121 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
122 pci->dbi_base = devm_pci_remap_cfg_resource(pci->dev, res);
123 if (IS_ERR(pci->dbi_base))
124 return PTR_ERR(pci->dbi_base);
125 pci->dbi_phys_addr = res->start;
126 }
127
128 /* DBI2 is mainly useful for the endpoint controller */
129 if (!pci->dbi_base2) {
130 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2");
131 if (res) {
132 pci->dbi_base2 = devm_pci_remap_cfg_resource(pci->dev, res);
133 if (IS_ERR(pci->dbi_base2))
134 return PTR_ERR(pci->dbi_base2);
135 } else {
136 pci->dbi_base2 = pci->dbi_base + SZ_4K;
137 }
138 }
139
140 /* For non-unrolled iATU/eDMA platforms this range will be ignored */
141 if (!pci->atu_base) {
142 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu");
143 if (res) {
144 pci->atu_size = resource_size(res);
145 pci->atu_base = devm_ioremap_resource(pci->dev, res);
146 if (IS_ERR(pci->atu_base))
147 return PTR_ERR(pci->atu_base);
148 pci->atu_phys_addr = res->start;
149 } else {
150 pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
151 }
152 }
153
154 /* Set a default value suitable for at most 8 in and 8 out windows */
155 if (!pci->atu_size)
156 pci->atu_size = SZ_4K;
157
158 /* eDMA region can be mapped to a custom base address */
159 if (!pci->edma.reg_base) {
160 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
161 if (res) {
162 pci->edma.reg_base = devm_ioremap_resource(pci->dev, res);
163 if (IS_ERR(pci->edma.reg_base))
164 return PTR_ERR(pci->edma.reg_base);
165 } else if (pci->atu_size >= 2 * DEFAULT_DBI_DMA_OFFSET) {
166 pci->edma.reg_base = pci->atu_base + DEFAULT_DBI_DMA_OFFSET;
167 }
168 }
169
170 /* LLDD is supposed to manually switch the clocks and resets state */
171 if (dw_pcie_cap_is(pci, REQ_RES)) {
172 ret = dw_pcie_get_clocks(pci);
173 if (ret)
174 return ret;
175
176 ret = dw_pcie_get_resets(pci);
177 if (ret)
178 return ret;
179 }
180
181 if (pci->max_link_speed < 1)
182 pci->max_link_speed = of_pci_get_max_link_speed(np);
183
184 of_property_read_u32(np, "num-lanes", &pci->num_lanes);
185
186 if (of_property_read_bool(np, "snps,enable-cdm-check"))
187 dw_pcie_cap_set(pci, CDM_CHECK);
188
189 return 0;
190 }
191
dw_pcie_version_detect(struct dw_pcie * pci)192 void dw_pcie_version_detect(struct dw_pcie *pci)
193 {
194 u32 ver;
195
196 /* The content of the CSR is zero on DWC PCIe older than v4.70a */
197 ver = dw_pcie_readl_dbi(pci, PCIE_VERSION_NUMBER);
198 if (!ver)
199 return;
200
201 if (pci->version && pci->version != ver)
202 dev_warn(pci->dev, "Versions don't match (%08x != %08x)\n",
203 pci->version, ver);
204 else
205 pci->version = ver;
206
207 ver = dw_pcie_readl_dbi(pci, PCIE_VERSION_TYPE);
208
209 if (pci->type && pci->type != ver)
210 dev_warn(pci->dev, "Types don't match (%08x != %08x)\n",
211 pci->type, ver);
212 else
213 pci->type = ver;
214 }
215
216 /*
217 * These interfaces resemble the pci_find_*capability() interfaces, but these
218 * are for configuring host controllers, which are bridges *to* PCI devices but
219 * are not PCI devices themselves.
220 */
__dw_pcie_find_next_cap(struct dw_pcie * pci,u8 cap_ptr,u8 cap)221 static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr,
222 u8 cap)
223 {
224 u8 cap_id, next_cap_ptr;
225 u16 reg;
226
227 if (!cap_ptr)
228 return 0;
229
230 reg = dw_pcie_readw_dbi(pci, cap_ptr);
231 cap_id = (reg & 0x00ff);
232
233 if (cap_id > PCI_CAP_ID_MAX)
234 return 0;
235
236 if (cap_id == cap)
237 return cap_ptr;
238
239 next_cap_ptr = (reg & 0xff00) >> 8;
240 return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
241 }
242
dw_pcie_find_capability(struct dw_pcie * pci,u8 cap)243 u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap)
244 {
245 u8 next_cap_ptr;
246 u16 reg;
247
248 reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);
249 next_cap_ptr = (reg & 0x00ff);
250
251 return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
252 }
253 EXPORT_SYMBOL_GPL(dw_pcie_find_capability);
254
dw_pcie_find_next_ext_capability(struct dw_pcie * pci,u16 start,u8 cap)255 static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start,
256 u8 cap)
257 {
258 u32 header;
259 int ttl;
260 int pos = PCI_CFG_SPACE_SIZE;
261
262 /* minimum 8 bytes per capability */
263 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
264
265 if (start)
266 pos = start;
267
268 header = dw_pcie_readl_dbi(pci, pos);
269 /*
270 * If we have no capabilities, this is indicated by cap ID,
271 * cap version and next pointer all being 0.
272 */
273 if (header == 0)
274 return 0;
275
276 while (ttl-- > 0) {
277 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
278 return pos;
279
280 pos = PCI_EXT_CAP_NEXT(header);
281 if (pos < PCI_CFG_SPACE_SIZE)
282 break;
283
284 header = dw_pcie_readl_dbi(pci, pos);
285 }
286
287 return 0;
288 }
289
dw_pcie_find_ext_capability(struct dw_pcie * pci,u8 cap)290 u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap)
291 {
292 return dw_pcie_find_next_ext_capability(pci, 0, cap);
293 }
294 EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability);
295
__dw_pcie_find_vsec_capability(struct dw_pcie * pci,u16 vendor_id,u16 vsec_id)296 static u16 __dw_pcie_find_vsec_capability(struct dw_pcie *pci, u16 vendor_id,
297 u16 vsec_id)
298 {
299 u16 vsec = 0;
300 u32 header;
301
302 if (vendor_id != dw_pcie_readw_dbi(pci, PCI_VENDOR_ID))
303 return 0;
304
305 while ((vsec = dw_pcie_find_next_ext_capability(pci, vsec,
306 PCI_EXT_CAP_ID_VNDR))) {
307 header = dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER);
308 if (PCI_VNDR_HEADER_ID(header) == vsec_id)
309 return vsec;
310 }
311
312 return 0;
313 }
314
dw_pcie_find_vsec_capability(struct dw_pcie * pci,const struct dwc_pcie_vsec_id * vsec_ids)315 static u16 dw_pcie_find_vsec_capability(struct dw_pcie *pci,
316 const struct dwc_pcie_vsec_id *vsec_ids)
317 {
318 const struct dwc_pcie_vsec_id *vid;
319 u16 vsec;
320 u32 header;
321
322 for (vid = vsec_ids; vid->vendor_id; vid++) {
323 vsec = __dw_pcie_find_vsec_capability(pci, vid->vendor_id,
324 vid->vsec_id);
325 if (vsec) {
326 header = dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER);
327 if (PCI_VNDR_HEADER_REV(header) == vid->vsec_rev)
328 return vsec;
329 }
330 }
331
332 return 0;
333 }
334
dw_pcie_find_rasdes_capability(struct dw_pcie * pci)335 u16 dw_pcie_find_rasdes_capability(struct dw_pcie *pci)
336 {
337 return dw_pcie_find_vsec_capability(pci, dwc_pcie_rasdes_vsec_ids);
338 }
339 EXPORT_SYMBOL_GPL(dw_pcie_find_rasdes_capability);
340
dw_pcie_find_ptm_capability(struct dw_pcie * pci)341 u16 dw_pcie_find_ptm_capability(struct dw_pcie *pci)
342 {
343 return dw_pcie_find_vsec_capability(pci, dwc_pcie_ptm_vsec_ids);
344 }
345 EXPORT_SYMBOL_GPL(dw_pcie_find_ptm_capability);
346
dw_pcie_read(void __iomem * addr,int size,u32 * val)347 int dw_pcie_read(void __iomem *addr, int size, u32 *val)
348 {
349 if (!IS_ALIGNED((uintptr_t)addr, size)) {
350 *val = 0;
351 return PCIBIOS_BAD_REGISTER_NUMBER;
352 }
353
354 if (size == 4) {
355 *val = readl(addr);
356 } else if (size == 2) {
357 *val = readw(addr);
358 } else if (size == 1) {
359 *val = readb(addr);
360 } else {
361 *val = 0;
362 return PCIBIOS_BAD_REGISTER_NUMBER;
363 }
364
365 return PCIBIOS_SUCCESSFUL;
366 }
367 EXPORT_SYMBOL_GPL(dw_pcie_read);
368
dw_pcie_write(void __iomem * addr,int size,u32 val)369 int dw_pcie_write(void __iomem *addr, int size, u32 val)
370 {
371 if (!IS_ALIGNED((uintptr_t)addr, size))
372 return PCIBIOS_BAD_REGISTER_NUMBER;
373
374 if (size == 4)
375 writel(val, addr);
376 else if (size == 2)
377 writew(val, addr);
378 else if (size == 1)
379 writeb(val, addr);
380 else
381 return PCIBIOS_BAD_REGISTER_NUMBER;
382
383 return PCIBIOS_SUCCESSFUL;
384 }
385 EXPORT_SYMBOL_GPL(dw_pcie_write);
386
dw_pcie_read_dbi(struct dw_pcie * pci,u32 reg,size_t size)387 u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size)
388 {
389 int ret;
390 u32 val;
391
392 if (pci->ops && pci->ops->read_dbi)
393 return pci->ops->read_dbi(pci, pci->dbi_base, reg, size);
394
395 ret = dw_pcie_read(pci->dbi_base + reg, size, &val);
396 if (ret)
397 dev_err(pci->dev, "Read DBI address failed\n");
398
399 return val;
400 }
401 EXPORT_SYMBOL_GPL(dw_pcie_read_dbi);
402
dw_pcie_write_dbi(struct dw_pcie * pci,u32 reg,size_t size,u32 val)403 void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
404 {
405 int ret;
406
407 if (pci->ops && pci->ops->write_dbi) {
408 pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val);
409 return;
410 }
411
412 ret = dw_pcie_write(pci->dbi_base + reg, size, val);
413 if (ret)
414 dev_err(pci->dev, "Write DBI address failed\n");
415 }
416 EXPORT_SYMBOL_GPL(dw_pcie_write_dbi);
417
dw_pcie_write_dbi2(struct dw_pcie * pci,u32 reg,size_t size,u32 val)418 void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
419 {
420 int ret;
421
422 if (pci->ops && pci->ops->write_dbi2) {
423 pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val);
424 return;
425 }
426
427 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val);
428 if (ret)
429 dev_err(pci->dev, "write DBI address failed\n");
430 }
431 EXPORT_SYMBOL_GPL(dw_pcie_write_dbi2);
432
dw_pcie_select_atu(struct dw_pcie * pci,u32 dir,u32 index)433 static inline void __iomem *dw_pcie_select_atu(struct dw_pcie *pci, u32 dir,
434 u32 index)
435 {
436 if (dw_pcie_cap_is(pci, IATU_UNROLL))
437 return pci->atu_base + PCIE_ATU_UNROLL_BASE(dir, index);
438
439 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, dir | index);
440 return pci->atu_base;
441 }
442
dw_pcie_readl_atu(struct dw_pcie * pci,u32 dir,u32 index,u32 reg)443 static u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 dir, u32 index, u32 reg)
444 {
445 void __iomem *base;
446 int ret;
447 u32 val;
448
449 base = dw_pcie_select_atu(pci, dir, index);
450
451 if (pci->ops && pci->ops->read_dbi)
452 return pci->ops->read_dbi(pci, base, reg, 4);
453
454 ret = dw_pcie_read(base + reg, 4, &val);
455 if (ret)
456 dev_err(pci->dev, "Read ATU address failed\n");
457
458 return val;
459 }
460
dw_pcie_writel_atu(struct dw_pcie * pci,u32 dir,u32 index,u32 reg,u32 val)461 static void dw_pcie_writel_atu(struct dw_pcie *pci, u32 dir, u32 index,
462 u32 reg, u32 val)
463 {
464 void __iomem *base;
465 int ret;
466
467 base = dw_pcie_select_atu(pci, dir, index);
468
469 if (pci->ops && pci->ops->write_dbi) {
470 pci->ops->write_dbi(pci, base, reg, 4, val);
471 return;
472 }
473
474 ret = dw_pcie_write(base + reg, 4, val);
475 if (ret)
476 dev_err(pci->dev, "Write ATU address failed\n");
477 }
478
dw_pcie_readl_atu_ob(struct dw_pcie * pci,u32 index,u32 reg)479 static inline u32 dw_pcie_readl_atu_ob(struct dw_pcie *pci, u32 index, u32 reg)
480 {
481 return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_OB, index, reg);
482 }
483
dw_pcie_writel_atu_ob(struct dw_pcie * pci,u32 index,u32 reg,u32 val)484 static inline void dw_pcie_writel_atu_ob(struct dw_pcie *pci, u32 index, u32 reg,
485 u32 val)
486 {
487 dw_pcie_writel_atu(pci, PCIE_ATU_REGION_DIR_OB, index, reg, val);
488 }
489
dw_pcie_enable_ecrc(u32 val)490 static inline u32 dw_pcie_enable_ecrc(u32 val)
491 {
492 /*
493 * DesignWare core version 4.90A has a design issue where the 'TD'
494 * bit in the Control register-1 of the ATU outbound region acts
495 * like an override for the ECRC setting, i.e., the presence of TLP
496 * Digest (ECRC) in the outgoing TLPs is solely determined by this
497 * bit. This is contrary to the PCIe spec which says that the
498 * enablement of the ECRC is solely determined by the AER
499 * registers.
500 *
501 * Because of this, even when the ECRC is enabled through AER
502 * registers, the transactions going through ATU won't have TLP
503 * Digest as there is no way the PCI core AER code could program
504 * the TD bit which is specific to the DesignWare core.
505 *
506 * The best way to handle this scenario is to program the TD bit
507 * always. It affects only the traffic from root port to downstream
508 * devices.
509 *
510 * At this point,
511 * When ECRC is enabled in AER registers, everything works normally
512 * When ECRC is NOT enabled in AER registers, then,
513 * on Root Port:- TLP Digest (DWord size) gets appended to each packet
514 * even through it is not required. Since downstream
515 * TLPs are mostly for configuration accesses and BAR
516 * accesses, they are not in critical path and won't
517 * have much negative effect on the performance.
518 * on End Point:- TLP Digest is received for some/all the packets coming
519 * from the root port. TLP Digest is ignored because,
520 * as per the PCIe Spec r5.0 v1.0 section 2.2.3
521 * "TLP Digest Rules", when an endpoint receives TLP
522 * Digest when its ECRC check functionality is disabled
523 * in AER registers, received TLP Digest is just ignored.
524 * Since there is no issue or error reported either side, best way to
525 * handle the scenario is to program TD bit by default.
526 */
527
528 return val | PCIE_ATU_TD;
529 }
530
dw_pcie_prog_outbound_atu(struct dw_pcie * pci,const struct dw_pcie_ob_atu_cfg * atu)531 int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
532 const struct dw_pcie_ob_atu_cfg *atu)
533 {
534 u64 parent_bus_addr = atu->parent_bus_addr;
535 u32 retries, val;
536 u64 limit_addr;
537
538 limit_addr = parent_bus_addr + atu->size - 1;
539
540 if ((limit_addr & ~pci->region_limit) != (parent_bus_addr & ~pci->region_limit) ||
541 !IS_ALIGNED(parent_bus_addr, pci->region_align) ||
542 !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) {
543 return -EINVAL;
544 }
545
546 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE,
547 lower_32_bits(parent_bus_addr));
548 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_BASE,
549 upper_32_bits(parent_bus_addr));
550
551 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LIMIT,
552 lower_32_bits(limit_addr));
553 if (dw_pcie_ver_is_ge(pci, 460A))
554 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_LIMIT,
555 upper_32_bits(limit_addr));
556
557 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_TARGET,
558 lower_32_bits(atu->pci_addr));
559 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET,
560 upper_32_bits(atu->pci_addr));
561
562 val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no);
563 if (upper_32_bits(limit_addr) > upper_32_bits(parent_bus_addr) &&
564 dw_pcie_ver_is_ge(pci, 460A))
565 val |= PCIE_ATU_INCREASE_REGION_SIZE;
566 if (dw_pcie_ver_is(pci, 490A))
567 val = dw_pcie_enable_ecrc(val);
568 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
569
570 val = PCIE_ATU_ENABLE;
571 if (atu->type == PCIE_ATU_TYPE_MSG) {
572 /* The data-less messages only for now */
573 val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code;
574 }
575 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, val);
576
577 /*
578 * Make sure ATU enable takes effect before any subsequent config
579 * and I/O accesses.
580 */
581 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
582 val = dw_pcie_readl_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2);
583 if (val & PCIE_ATU_ENABLE)
584 return 0;
585
586 mdelay(LINK_WAIT_IATU);
587 }
588
589 dev_err(pci->dev, "Outbound iATU is not being enabled\n");
590
591 return -ETIMEDOUT;
592 }
593
dw_pcie_readl_atu_ib(struct dw_pcie * pci,u32 index,u32 reg)594 static inline u32 dw_pcie_readl_atu_ib(struct dw_pcie *pci, u32 index, u32 reg)
595 {
596 return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg);
597 }
598
dw_pcie_writel_atu_ib(struct dw_pcie * pci,u32 index,u32 reg,u32 val)599 static inline void dw_pcie_writel_atu_ib(struct dw_pcie *pci, u32 index, u32 reg,
600 u32 val)
601 {
602 dw_pcie_writel_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg, val);
603 }
604
dw_pcie_prog_inbound_atu(struct dw_pcie * pci,int index,int type,u64 parent_bus_addr,u64 pci_addr,u64 size)605 int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,
606 u64 parent_bus_addr, u64 pci_addr, u64 size)
607 {
608 u64 limit_addr = pci_addr + size - 1;
609 u32 retries, val;
610
611 if ((limit_addr & ~pci->region_limit) != (pci_addr & ~pci->region_limit) ||
612 !IS_ALIGNED(parent_bus_addr, pci->region_align) ||
613 !IS_ALIGNED(pci_addr, pci->region_align) || !size) {
614 return -EINVAL;
615 }
616
617 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_BASE,
618 lower_32_bits(pci_addr));
619 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_BASE,
620 upper_32_bits(pci_addr));
621
622 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LIMIT,
623 lower_32_bits(limit_addr));
624 if (dw_pcie_ver_is_ge(pci, 460A))
625 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_LIMIT,
626 upper_32_bits(limit_addr));
627
628 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET,
629 lower_32_bits(parent_bus_addr));
630 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_TARGET,
631 upper_32_bits(parent_bus_addr));
632
633 val = type;
634 if (upper_32_bits(limit_addr) > upper_32_bits(pci_addr) &&
635 dw_pcie_ver_is_ge(pci, 460A))
636 val |= PCIE_ATU_INCREASE_REGION_SIZE;
637 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL1, val);
638 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
639
640 /*
641 * Make sure ATU enable takes effect before any subsequent config
642 * and I/O accesses.
643 */
644 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
645 val = dw_pcie_readl_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2);
646 if (val & PCIE_ATU_ENABLE)
647 return 0;
648
649 mdelay(LINK_WAIT_IATU);
650 }
651
652 dev_err(pci->dev, "Inbound iATU is not being enabled\n");
653
654 return -ETIMEDOUT;
655 }
656
dw_pcie_prog_ep_inbound_atu(struct dw_pcie * pci,u8 func_no,int index,int type,u64 parent_bus_addr,u8 bar,size_t size)657 int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
658 int type, u64 parent_bus_addr, u8 bar, size_t size)
659 {
660 u32 retries, val;
661
662 if (!IS_ALIGNED(parent_bus_addr, pci->region_align) ||
663 !IS_ALIGNED(parent_bus_addr, size))
664 return -EINVAL;
665
666 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET,
667 lower_32_bits(parent_bus_addr));
668 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_TARGET,
669 upper_32_bits(parent_bus_addr));
670
671 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL1, type |
672 PCIE_ATU_FUNC_NUM(func_no));
673 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2,
674 PCIE_ATU_ENABLE | PCIE_ATU_FUNC_NUM_MATCH_EN |
675 PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
676
677 /*
678 * Make sure ATU enable takes effect before any subsequent config
679 * and I/O accesses.
680 */
681 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
682 val = dw_pcie_readl_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2);
683 if (val & PCIE_ATU_ENABLE)
684 return 0;
685
686 mdelay(LINK_WAIT_IATU);
687 }
688
689 dev_err(pci->dev, "Inbound iATU is not being enabled\n");
690
691 return -ETIMEDOUT;
692 }
693
dw_pcie_disable_atu(struct dw_pcie * pci,u32 dir,int index)694 void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index)
695 {
696 dw_pcie_writel_atu(pci, dir, index, PCIE_ATU_REGION_CTRL2, 0);
697 }
698
dw_pcie_wait_for_link(struct dw_pcie * pci)699 int dw_pcie_wait_for_link(struct dw_pcie *pci)
700 {
701 u32 offset, val;
702 int retries;
703
704 /* Check if the link is up or not */
705 for (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) {
706 if (dw_pcie_link_up(pci))
707 break;
708
709 msleep(PCIE_LINK_WAIT_SLEEP_MS);
710 }
711
712 if (retries >= PCIE_LINK_WAIT_MAX_RETRIES) {
713 dev_info(pci->dev, "Phy link never came up\n");
714 return -ETIMEDOUT;
715 }
716
717 /*
718 * As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link
719 * speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms
720 * after Link training completes before sending a Configuration Request.
721 */
722 if (pci->max_link_speed > 2)
723 msleep(PCIE_RESET_CONFIG_WAIT_MS);
724
725 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
726 val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);
727
728 dev_info(pci->dev, "PCIe Gen.%u x%u link up\n",
729 FIELD_GET(PCI_EXP_LNKSTA_CLS, val),
730 FIELD_GET(PCI_EXP_LNKSTA_NLW, val));
731
732 return 0;
733 }
734 EXPORT_SYMBOL_GPL(dw_pcie_wait_for_link);
735
dw_pcie_link_up(struct dw_pcie * pci)736 bool dw_pcie_link_up(struct dw_pcie *pci)
737 {
738 u32 val;
739
740 if (pci->ops && pci->ops->link_up)
741 return pci->ops->link_up(pci);
742
743 val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1);
744 return ((val & PCIE_PORT_DEBUG1_LINK_UP) &&
745 (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));
746 }
747 EXPORT_SYMBOL_GPL(dw_pcie_link_up);
748
dw_pcie_upconfig_setup(struct dw_pcie * pci)749 void dw_pcie_upconfig_setup(struct dw_pcie *pci)
750 {
751 u32 val;
752
753 val = dw_pcie_readl_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL);
754 val |= PORT_MLTI_UPCFG_SUPPORT;
755 dw_pcie_writel_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL, val);
756 }
757 EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup);
758
dw_pcie_link_set_max_speed(struct dw_pcie * pci)759 static void dw_pcie_link_set_max_speed(struct dw_pcie *pci)
760 {
761 u32 cap, ctrl2, link_speed;
762 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
763
764 cap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
765
766 /*
767 * Even if the platform doesn't want to limit the maximum link speed,
768 * just cache the hardware default value so that the vendor drivers can
769 * use it to do any link specific configuration.
770 */
771 if (pci->max_link_speed < 1) {
772 pci->max_link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap);
773 return;
774 }
775
776 ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2);
777 ctrl2 &= ~PCI_EXP_LNKCTL2_TLS;
778
779 switch (pcie_link_speed[pci->max_link_speed]) {
780 case PCIE_SPEED_2_5GT:
781 link_speed = PCI_EXP_LNKCTL2_TLS_2_5GT;
782 break;
783 case PCIE_SPEED_5_0GT:
784 link_speed = PCI_EXP_LNKCTL2_TLS_5_0GT;
785 break;
786 case PCIE_SPEED_8_0GT:
787 link_speed = PCI_EXP_LNKCTL2_TLS_8_0GT;
788 break;
789 case PCIE_SPEED_16_0GT:
790 link_speed = PCI_EXP_LNKCTL2_TLS_16_0GT;
791 break;
792 default:
793 /* Use hardware capability */
794 link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap);
795 ctrl2 &= ~PCI_EXP_LNKCTL2_HASD;
796 break;
797 }
798
799 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | link_speed);
800
801 cap &= ~((u32)PCI_EXP_LNKCAP_SLS);
802 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | link_speed);
803
804 }
805
dw_pcie_link_get_max_link_width(struct dw_pcie * pci)806 int dw_pcie_link_get_max_link_width(struct dw_pcie *pci)
807 {
808 u8 cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
809 u32 lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);
810
811 return FIELD_GET(PCI_EXP_LNKCAP_MLW, lnkcap);
812 }
813
dw_pcie_link_set_max_link_width(struct dw_pcie * pci,u32 num_lanes)814 static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
815 {
816 u32 lnkcap, lwsc, plc;
817 u8 cap;
818
819 if (!num_lanes)
820 return;
821
822 /* Set the number of lanes */
823 plc = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
824 plc &= ~PORT_LINK_FAST_LINK_MODE;
825 plc &= ~PORT_LINK_MODE_MASK;
826
827 /* Set link width speed control register */
828 lwsc = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
829 lwsc &= ~PORT_LOGIC_LINK_WIDTH_MASK;
830 lwsc |= PORT_LOGIC_LINK_WIDTH_1_LANES;
831 switch (num_lanes) {
832 case 1:
833 plc |= PORT_LINK_MODE_1_LANES;
834 break;
835 case 2:
836 plc |= PORT_LINK_MODE_2_LANES;
837 break;
838 case 4:
839 plc |= PORT_LINK_MODE_4_LANES;
840 break;
841 case 8:
842 plc |= PORT_LINK_MODE_8_LANES;
843 break;
844 default:
845 dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes);
846 return;
847 }
848 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc);
849 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc);
850
851 cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
852 lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);
853 lnkcap &= ~PCI_EXP_LNKCAP_MLW;
854 lnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes);
855 dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap);
856 }
857
dw_pcie_iatu_detect(struct dw_pcie * pci)858 void dw_pcie_iatu_detect(struct dw_pcie *pci)
859 {
860 int max_region, ob, ib;
861 u32 val, min, dir;
862 u64 max;
863
864 val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
865 if (val == 0xFFFFFFFF) {
866 dw_pcie_cap_set(pci, IATU_UNROLL);
867
868 max_region = min((int)pci->atu_size / 512, 256);
869 } else {
870 pci->atu_base = pci->dbi_base + PCIE_ATU_VIEWPORT_BASE;
871 pci->atu_size = PCIE_ATU_VIEWPORT_SIZE;
872
873 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, 0xFF);
874 max_region = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT) + 1;
875 }
876
877 for (ob = 0; ob < max_region; ob++) {
878 dw_pcie_writel_atu_ob(pci, ob, PCIE_ATU_LOWER_TARGET, 0x11110000);
879 val = dw_pcie_readl_atu_ob(pci, ob, PCIE_ATU_LOWER_TARGET);
880 if (val != 0x11110000)
881 break;
882 }
883
884 for (ib = 0; ib < max_region; ib++) {
885 dw_pcie_writel_atu_ib(pci, ib, PCIE_ATU_LOWER_TARGET, 0x11110000);
886 val = dw_pcie_readl_atu_ib(pci, ib, PCIE_ATU_LOWER_TARGET);
887 if (val != 0x11110000)
888 break;
889 }
890
891 if (ob) {
892 dir = PCIE_ATU_REGION_DIR_OB;
893 } else if (ib) {
894 dir = PCIE_ATU_REGION_DIR_IB;
895 } else {
896 dev_err(pci->dev, "No iATU regions found\n");
897 return;
898 }
899
900 dw_pcie_writel_atu(pci, dir, 0, PCIE_ATU_LIMIT, 0x0);
901 min = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_LIMIT);
902
903 if (dw_pcie_ver_is_ge(pci, 460A)) {
904 dw_pcie_writel_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT, 0xFFFFFFFF);
905 max = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT);
906 } else {
907 max = 0;
908 }
909
910 pci->num_ob_windows = ob;
911 pci->num_ib_windows = ib;
912 pci->region_align = 1 << fls(min);
913 pci->region_limit = (max << 32) | (SZ_4G - 1);
914
915 dev_info(pci->dev, "iATU: unroll %s, %u ob, %u ib, align %uK, limit %lluG\n",
916 dw_pcie_cap_is(pci, IATU_UNROLL) ? "T" : "F",
917 pci->num_ob_windows, pci->num_ib_windows,
918 pci->region_align / SZ_1K, (pci->region_limit + 1) / SZ_1G);
919 }
920
dw_pcie_readl_dma(struct dw_pcie * pci,u32 reg)921 static u32 dw_pcie_readl_dma(struct dw_pcie *pci, u32 reg)
922 {
923 u32 val = 0;
924 int ret;
925
926 if (pci->ops && pci->ops->read_dbi)
927 return pci->ops->read_dbi(pci, pci->edma.reg_base, reg, 4);
928
929 ret = dw_pcie_read(pci->edma.reg_base + reg, 4, &val);
930 if (ret)
931 dev_err(pci->dev, "Read DMA address failed\n");
932
933 return val;
934 }
935
dw_pcie_edma_irq_vector(struct device * dev,unsigned int nr)936 static int dw_pcie_edma_irq_vector(struct device *dev, unsigned int nr)
937 {
938 struct platform_device *pdev = to_platform_device(dev);
939 char name[6];
940 int ret;
941
942 if (nr >= EDMA_MAX_WR_CH + EDMA_MAX_RD_CH)
943 return -EINVAL;
944
945 ret = platform_get_irq_byname_optional(pdev, "dma");
946 if (ret > 0)
947 return ret;
948
949 snprintf(name, sizeof(name), "dma%u", nr);
950
951 return platform_get_irq_byname_optional(pdev, name);
952 }
953
954 static struct dw_edma_plat_ops dw_pcie_edma_ops = {
955 .irq_vector = dw_pcie_edma_irq_vector,
956 };
957
dw_pcie_edma_init_data(struct dw_pcie * pci)958 static void dw_pcie_edma_init_data(struct dw_pcie *pci)
959 {
960 pci->edma.dev = pci->dev;
961
962 if (!pci->edma.ops)
963 pci->edma.ops = &dw_pcie_edma_ops;
964
965 pci->edma.flags |= DW_EDMA_CHIP_LOCAL;
966 }
967
dw_pcie_edma_find_mf(struct dw_pcie * pci)968 static int dw_pcie_edma_find_mf(struct dw_pcie *pci)
969 {
970 u32 val;
971
972 /*
973 * Bail out finding the mapping format if it is already set by the glue
974 * driver. Also ensure that the edma.reg_base is pointing to a valid
975 * memory region.
976 */
977 if (pci->edma.mf != EDMA_MF_EDMA_LEGACY)
978 return pci->edma.reg_base ? 0 : -ENODEV;
979
980 /*
981 * Indirect eDMA CSRs access has been completely removed since v5.40a
982 * thus no space is now reserved for the eDMA channels viewport and
983 * former DMA CTRL register is no longer fixed to FFs.
984 */
985 if (dw_pcie_ver_is_ge(pci, 540A))
986 val = 0xFFFFFFFF;
987 else
988 val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL);
989
990 if (val == 0xFFFFFFFF && pci->edma.reg_base) {
991 pci->edma.mf = EDMA_MF_EDMA_UNROLL;
992 } else if (val != 0xFFFFFFFF) {
993 pci->edma.mf = EDMA_MF_EDMA_LEGACY;
994
995 pci->edma.reg_base = pci->dbi_base + PCIE_DMA_VIEWPORT_BASE;
996 } else {
997 return -ENODEV;
998 }
999
1000 return 0;
1001 }
1002
dw_pcie_edma_find_channels(struct dw_pcie * pci)1003 static int dw_pcie_edma_find_channels(struct dw_pcie *pci)
1004 {
1005 u32 val;
1006
1007 /*
1008 * Autodetect the read/write channels count only for non-HDMA platforms.
1009 * HDMA platforms with native CSR mapping doesn't support autodetect,
1010 * so the glue drivers should've passed the valid count already. If not,
1011 * the below sanity check will catch it.
1012 */
1013 if (pci->edma.mf != EDMA_MF_HDMA_NATIVE) {
1014 val = dw_pcie_readl_dma(pci, PCIE_DMA_CTRL);
1015
1016 pci->edma.ll_wr_cnt = FIELD_GET(PCIE_DMA_NUM_WR_CHAN, val);
1017 pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val);
1018 }
1019
1020 /* Sanity check the channels count if the mapping was incorrect */
1021 if (!pci->edma.ll_wr_cnt || pci->edma.ll_wr_cnt > EDMA_MAX_WR_CH ||
1022 !pci->edma.ll_rd_cnt || pci->edma.ll_rd_cnt > EDMA_MAX_RD_CH)
1023 return -EINVAL;
1024
1025 return 0;
1026 }
1027
dw_pcie_edma_find_chip(struct dw_pcie * pci)1028 static int dw_pcie_edma_find_chip(struct dw_pcie *pci)
1029 {
1030 int ret;
1031
1032 dw_pcie_edma_init_data(pci);
1033
1034 ret = dw_pcie_edma_find_mf(pci);
1035 if (ret)
1036 return ret;
1037
1038 return dw_pcie_edma_find_channels(pci);
1039 }
1040
dw_pcie_edma_irq_verify(struct dw_pcie * pci)1041 static int dw_pcie_edma_irq_verify(struct dw_pcie *pci)
1042 {
1043 struct platform_device *pdev = to_platform_device(pci->dev);
1044 u16 ch_cnt = pci->edma.ll_wr_cnt + pci->edma.ll_rd_cnt;
1045 char name[15];
1046 int ret;
1047
1048 if (pci->edma.nr_irqs == 1)
1049 return 0;
1050 else if (pci->edma.nr_irqs > 1)
1051 return pci->edma.nr_irqs != ch_cnt ? -EINVAL : 0;
1052
1053 ret = platform_get_irq_byname_optional(pdev, "dma");
1054 if (ret > 0) {
1055 pci->edma.nr_irqs = 1;
1056 return 0;
1057 }
1058
1059 for (; pci->edma.nr_irqs < ch_cnt; pci->edma.nr_irqs++) {
1060 snprintf(name, sizeof(name), "dma%d", pci->edma.nr_irqs);
1061
1062 ret = platform_get_irq_byname_optional(pdev, name);
1063 if (ret <= 0)
1064 return -EINVAL;
1065 }
1066
1067 return 0;
1068 }
1069
dw_pcie_edma_ll_alloc(struct dw_pcie * pci)1070 static int dw_pcie_edma_ll_alloc(struct dw_pcie *pci)
1071 {
1072 struct dw_edma_region *ll;
1073 dma_addr_t paddr;
1074 int i;
1075
1076 for (i = 0; i < pci->edma.ll_wr_cnt; i++) {
1077 ll = &pci->edma.ll_region_wr[i];
1078 ll->sz = DMA_LLP_MEM_SIZE;
1079 ll->vaddr.mem = dmam_alloc_coherent(pci->dev, ll->sz,
1080 &paddr, GFP_KERNEL);
1081 if (!ll->vaddr.mem)
1082 return -ENOMEM;
1083
1084 ll->paddr = paddr;
1085 }
1086
1087 for (i = 0; i < pci->edma.ll_rd_cnt; i++) {
1088 ll = &pci->edma.ll_region_rd[i];
1089 ll->sz = DMA_LLP_MEM_SIZE;
1090 ll->vaddr.mem = dmam_alloc_coherent(pci->dev, ll->sz,
1091 &paddr, GFP_KERNEL);
1092 if (!ll->vaddr.mem)
1093 return -ENOMEM;
1094
1095 ll->paddr = paddr;
1096 }
1097
1098 return 0;
1099 }
1100
dw_pcie_edma_detect(struct dw_pcie * pci)1101 int dw_pcie_edma_detect(struct dw_pcie *pci)
1102 {
1103 int ret;
1104
1105 /* Don't fail if no eDMA was found (for the backward compatibility) */
1106 ret = dw_pcie_edma_find_chip(pci);
1107 if (ret)
1108 return 0;
1109
1110 /* Don't fail on the IRQs verification (for the backward compatibility) */
1111 ret = dw_pcie_edma_irq_verify(pci);
1112 if (ret) {
1113 dev_err(pci->dev, "Invalid eDMA IRQs found\n");
1114 return 0;
1115 }
1116
1117 ret = dw_pcie_edma_ll_alloc(pci);
1118 if (ret) {
1119 dev_err(pci->dev, "Couldn't allocate LLP memory\n");
1120 return ret;
1121 }
1122
1123 /* Don't fail if the DW eDMA driver can't find the device */
1124 ret = dw_edma_probe(&pci->edma);
1125 if (ret && ret != -ENODEV) {
1126 dev_err(pci->dev, "Couldn't register eDMA device\n");
1127 return ret;
1128 }
1129
1130 dev_info(pci->dev, "eDMA: unroll %s, %hu wr, %hu rd\n",
1131 pci->edma.mf == EDMA_MF_EDMA_UNROLL ? "T" : "F",
1132 pci->edma.ll_wr_cnt, pci->edma.ll_rd_cnt);
1133
1134 return 0;
1135 }
1136
dw_pcie_edma_remove(struct dw_pcie * pci)1137 void dw_pcie_edma_remove(struct dw_pcie *pci)
1138 {
1139 dw_edma_remove(&pci->edma);
1140 }
1141
dw_pcie_setup(struct dw_pcie * pci)1142 void dw_pcie_setup(struct dw_pcie *pci)
1143 {
1144 u32 val;
1145
1146 dw_pcie_link_set_max_speed(pci);
1147
1148 /* Configure Gen1 N_FTS */
1149 if (pci->n_fts[0]) {
1150 val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
1151 val &= ~(PORT_AFR_N_FTS_MASK | PORT_AFR_CC_N_FTS_MASK);
1152 val |= PORT_AFR_N_FTS(pci->n_fts[0]);
1153 val |= PORT_AFR_CC_N_FTS(pci->n_fts[0]);
1154 dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
1155 }
1156
1157 /* Configure Gen2+ N_FTS */
1158 if (pci->n_fts[1]) {
1159 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
1160 val &= ~PORT_LOGIC_N_FTS_MASK;
1161 val |= pci->n_fts[1];
1162 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
1163 }
1164
1165 if (dw_pcie_cap_is(pci, CDM_CHECK)) {
1166 val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
1167 val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS |
1168 PCIE_PL_CHK_REG_CHK_REG_START;
1169 dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
1170 }
1171
1172 val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
1173 val &= ~PORT_LINK_FAST_LINK_MODE;
1174 val |= PORT_LINK_DLL_LINK_EN;
1175 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
1176
1177 dw_pcie_link_set_max_link_width(pci, pci->num_lanes);
1178 }
1179
dw_pcie_parent_bus_offset(struct dw_pcie * pci,const char * reg_name,resource_size_t cpu_phys_addr)1180 resource_size_t dw_pcie_parent_bus_offset(struct dw_pcie *pci,
1181 const char *reg_name,
1182 resource_size_t cpu_phys_addr)
1183 {
1184 struct device *dev = pci->dev;
1185 struct device_node *np = dev->of_node;
1186 int index;
1187 u64 reg_addr, fixup_addr;
1188 u64 (*fixup)(struct dw_pcie *pcie, u64 cpu_addr);
1189
1190 /* Look up reg_name address on parent bus */
1191 index = of_property_match_string(np, "reg-names", reg_name);
1192
1193 if (index < 0) {
1194 dev_err(dev, "No %s in devicetree \"reg\" property\n", reg_name);
1195 return 0;
1196 }
1197
1198 of_property_read_reg(np, index, ®_addr, NULL);
1199
1200 fixup = pci->ops ? pci->ops->cpu_addr_fixup : NULL;
1201 if (fixup) {
1202 fixup_addr = fixup(pci, cpu_phys_addr);
1203 if (reg_addr == fixup_addr) {
1204 dev_info(dev, "%s reg[%d] %#010llx == %#010llx == fixup(cpu %#010llx); %ps is redundant with this devicetree\n",
1205 reg_name, index, reg_addr, fixup_addr,
1206 (unsigned long long) cpu_phys_addr, fixup);
1207 } else {
1208 dev_warn(dev, "%s reg[%d] %#010llx != %#010llx == fixup(cpu %#010llx); devicetree is broken\n",
1209 reg_name, index, reg_addr, fixup_addr,
1210 (unsigned long long) cpu_phys_addr);
1211 reg_addr = fixup_addr;
1212 }
1213
1214 return cpu_phys_addr - reg_addr;
1215 }
1216
1217 if (pci->use_parent_dt_ranges) {
1218
1219 /*
1220 * This platform once had a fixup, presumably because it
1221 * translates between CPU and PCI controller addresses.
1222 * Log a note if devicetree didn't describe a translation.
1223 */
1224 if (reg_addr == cpu_phys_addr)
1225 dev_info(dev, "%s reg[%d] %#010llx == cpu %#010llx\n; no fixup was ever needed for this devicetree\n",
1226 reg_name, index, reg_addr,
1227 (unsigned long long) cpu_phys_addr);
1228 } else {
1229 if (reg_addr != cpu_phys_addr) {
1230 dev_warn(dev, "%s reg[%d] %#010llx != cpu %#010llx; no fixup and devicetree \"ranges\" is broken, assuming no translation\n",
1231 reg_name, index, reg_addr,
1232 (unsigned long long) cpu_phys_addr);
1233 return 0;
1234 }
1235 }
1236
1237 return cpu_phys_addr - reg_addr;
1238 }
1239