1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
5 */
6
7 #include <linux/msi.h>
8 #include <linux/pci.h>
9 #include <linux/firmware.h>
10
11 #include "core.h"
12 #include "debug.h"
13 #include "mhi.h"
14 #include "pci.h"
15
16 #define MHI_TIMEOUT_DEFAULT_MS 90000
17 #define OTP_INVALID_BOARD_ID 0xFFFF
18 #define OTP_VALID_DUALMAC_BOARD_ID_MASK 0x1000
19 #define MHI_CB_INVALID 0xff
20
ath12k_mhi_set_mhictrl_reset(struct ath12k_base * ab)21 void ath12k_mhi_set_mhictrl_reset(struct ath12k_base *ab)
22 {
23 u32 val;
24
25 val = ath12k_pci_read32(ab, MHISTATUS);
26
27 ath12k_dbg(ab, ATH12K_DBG_PCI, "MHISTATUS 0x%x\n", val);
28
29 /* Observed on some targets that after SOC_GLOBAL_RESET, MHISTATUS
30 * has SYSERR bit set and thus need to set MHICTRL_RESET
31 * to clear SYSERR.
32 */
33 ath12k_pci_write32(ab, MHICTRL, MHICTRL_RESET_MASK);
34
35 mdelay(10);
36 }
37
ath12k_mhi_reset_txvecdb(struct ath12k_base * ab)38 static void ath12k_mhi_reset_txvecdb(struct ath12k_base *ab)
39 {
40 ath12k_pci_write32(ab, PCIE_TXVECDB, 0);
41 }
42
ath12k_mhi_reset_txvecstatus(struct ath12k_base * ab)43 static void ath12k_mhi_reset_txvecstatus(struct ath12k_base *ab)
44 {
45 ath12k_pci_write32(ab, PCIE_TXVECSTATUS, 0);
46 }
47
ath12k_mhi_reset_rxvecdb(struct ath12k_base * ab)48 static void ath12k_mhi_reset_rxvecdb(struct ath12k_base *ab)
49 {
50 ath12k_pci_write32(ab, PCIE_RXVECDB, 0);
51 }
52
ath12k_mhi_reset_rxvecstatus(struct ath12k_base * ab)53 static void ath12k_mhi_reset_rxvecstatus(struct ath12k_base *ab)
54 {
55 ath12k_pci_write32(ab, PCIE_RXVECSTATUS, 0);
56 }
57
ath12k_mhi_clear_vector(struct ath12k_base * ab)58 void ath12k_mhi_clear_vector(struct ath12k_base *ab)
59 {
60 ath12k_mhi_reset_txvecdb(ab);
61 ath12k_mhi_reset_txvecstatus(ab);
62 ath12k_mhi_reset_rxvecdb(ab);
63 ath12k_mhi_reset_rxvecstatus(ab);
64 }
65
ath12k_mhi_get_msi(struct ath12k_pci * ab_pci)66 static int ath12k_mhi_get_msi(struct ath12k_pci *ab_pci)
67 {
68 struct ath12k_base *ab = ab_pci->ab;
69 u32 user_base_data, base_vector;
70 int ret, num_vectors, i;
71 int *irq;
72 unsigned int msi_data;
73
74 ret = ath12k_pci_get_user_msi_assignment(ab,
75 "MHI", &num_vectors,
76 &user_base_data, &base_vector);
77 if (ret)
78 return ret;
79
80 ath12k_dbg(ab, ATH12K_DBG_PCI, "Number of assigned MSI for MHI is %d, base vector is %d\n",
81 num_vectors, base_vector);
82
83 irq = kzalloc_objs(*irq, num_vectors);
84 if (!irq)
85 return -ENOMEM;
86
87 msi_data = base_vector;
88 for (i = 0; i < num_vectors; i++) {
89 if (test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
90 irq[i] = ath12k_pci_get_msi_irq(ab->dev,
91 msi_data++);
92 else
93 irq[i] = ath12k_pci_get_msi_irq(ab->dev,
94 msi_data);
95 }
96
97 ab_pci->mhi_ctrl->irq = irq;
98 ab_pci->mhi_ctrl->nr_irqs = num_vectors;
99
100 return 0;
101 }
102
ath12k_mhi_op_runtime_get(struct mhi_controller * mhi_cntrl)103 static int ath12k_mhi_op_runtime_get(struct mhi_controller *mhi_cntrl)
104 {
105 return 0;
106 }
107
ath12k_mhi_op_runtime_put(struct mhi_controller * mhi_cntrl)108 static void ath12k_mhi_op_runtime_put(struct mhi_controller *mhi_cntrl)
109 {
110 }
111
ath12k_mhi_op_callback_to_str(enum mhi_callback reason)112 static char *ath12k_mhi_op_callback_to_str(enum mhi_callback reason)
113 {
114 switch (reason) {
115 case MHI_CB_IDLE:
116 return "MHI_CB_IDLE";
117 case MHI_CB_PENDING_DATA:
118 return "MHI_CB_PENDING_DATA";
119 case MHI_CB_LPM_ENTER:
120 return "MHI_CB_LPM_ENTER";
121 case MHI_CB_LPM_EXIT:
122 return "MHI_CB_LPM_EXIT";
123 case MHI_CB_EE_RDDM:
124 return "MHI_CB_EE_RDDM";
125 case MHI_CB_EE_MISSION_MODE:
126 return "MHI_CB_EE_MISSION_MODE";
127 case MHI_CB_SYS_ERROR:
128 return "MHI_CB_SYS_ERROR";
129 case MHI_CB_FATAL_ERROR:
130 return "MHI_CB_FATAL_ERROR";
131 case MHI_CB_BW_REQ:
132 return "MHI_CB_BW_REQ";
133 default:
134 return "UNKNOWN";
135 }
136 }
137
ath12k_mhi_op_status_cb(struct mhi_controller * mhi_cntrl,enum mhi_callback cb)138 static void ath12k_mhi_op_status_cb(struct mhi_controller *mhi_cntrl,
139 enum mhi_callback cb)
140 {
141 struct ath12k_base *ab = dev_get_drvdata(mhi_cntrl->cntrl_dev);
142 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
143
144 ath12k_dbg(ab, ATH12K_DBG_BOOT, "mhi notify status reason %s\n",
145 ath12k_mhi_op_callback_to_str(cb));
146
147 switch (cb) {
148 case MHI_CB_SYS_ERROR:
149 ath12k_warn(ab, "firmware crashed: MHI_CB_SYS_ERROR\n");
150 break;
151 case MHI_CB_EE_RDDM:
152 if (ab_pci->mhi_pre_cb == MHI_CB_EE_RDDM) {
153 ath12k_dbg(ab, ATH12K_DBG_BOOT,
154 "do not queue again for consecutive RDDM event\n");
155 break;
156 }
157
158 if (!(test_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags))) {
159 set_bit(ATH12K_FLAG_CRASH_FLUSH, &ab->dev_flags);
160 set_bit(ATH12K_FLAG_RECOVERY, &ab->dev_flags);
161 queue_work(ab->workqueue_aux, &ab->reset_work);
162 }
163 break;
164 default:
165 break;
166 }
167
168 ab_pci->mhi_pre_cb = cb;
169 }
170
ath12k_mhi_op_read_reg(struct mhi_controller * mhi_cntrl,void __iomem * addr,u32 * out)171 static int ath12k_mhi_op_read_reg(struct mhi_controller *mhi_cntrl,
172 void __iomem *addr,
173 u32 *out)
174 {
175 *out = readl(addr);
176
177 return 0;
178 }
179
ath12k_mhi_op_write_reg(struct mhi_controller * mhi_cntrl,void __iomem * addr,u32 val)180 static void ath12k_mhi_op_write_reg(struct mhi_controller *mhi_cntrl,
181 void __iomem *addr,
182 u32 val)
183 {
184 writel(val, addr);
185 }
186
ath12k_mhi_register(struct ath12k_pci * ab_pci)187 int ath12k_mhi_register(struct ath12k_pci *ab_pci)
188 {
189 struct ath12k_base *ab = ab_pci->ab;
190 struct mhi_controller *mhi_ctrl;
191 unsigned int board_id;
192 int ret;
193 bool dualmac = false;
194
195 mhi_ctrl = mhi_alloc_controller();
196 if (!mhi_ctrl)
197 return -ENOMEM;
198
199 ab_pci->mhi_pre_cb = MHI_CB_INVALID;
200 ab_pci->mhi_ctrl = mhi_ctrl;
201 mhi_ctrl->cntrl_dev = ab->dev;
202 mhi_ctrl->regs = ab->mem;
203 mhi_ctrl->reg_len = ab->mem_len;
204 mhi_ctrl->rddm_size = ab->hw_params->rddm_size;
205
206 if (ab->hw_params->otp_board_id_register) {
207 board_id =
208 ath12k_pci_read32(ab, ab->hw_params->otp_board_id_register);
209 board_id = u32_get_bits(board_id, OTP_BOARD_ID_MASK);
210
211 if (!board_id || (board_id == OTP_INVALID_BOARD_ID)) {
212 ath12k_dbg(ab, ATH12K_DBG_BOOT,
213 "failed to read board id\n");
214 } else if (board_id & OTP_VALID_DUALMAC_BOARD_ID_MASK) {
215 dualmac = true;
216 ath12k_dbg(ab, ATH12K_DBG_BOOT,
217 "dualmac fw selected for board id: %x\n", board_id);
218 }
219 }
220
221 if (dualmac) {
222 if (ab->fw.amss_dualmac_data && ab->fw.amss_dualmac_len > 0) {
223 /* use MHI firmware file from firmware-N.bin */
224 mhi_ctrl->fw_data = ab->fw.amss_dualmac_data;
225 mhi_ctrl->fw_sz = ab->fw.amss_dualmac_len;
226 } else {
227 ath12k_warn(ab, "dualmac firmware IE not present in firmware-N.bin\n");
228 ret = -ENOENT;
229 goto free_controller;
230 }
231 } else {
232 if (ab->fw.amss_data && ab->fw.amss_len > 0) {
233 /* use MHI firmware file from firmware-N.bin */
234 mhi_ctrl->fw_data = ab->fw.amss_data;
235 mhi_ctrl->fw_sz = ab->fw.amss_len;
236 } else {
237 /* use the old separate mhi.bin MHI firmware file */
238 ath12k_core_create_firmware_path(ab, ATH12K_AMSS_FILE,
239 ab_pci->amss_path,
240 sizeof(ab_pci->amss_path));
241 mhi_ctrl->fw_image = ab_pci->amss_path;
242 }
243 }
244
245 ret = ath12k_mhi_get_msi(ab_pci);
246 if (ret) {
247 ath12k_err(ab, "failed to get msi for mhi\n");
248 goto free_controller;
249 }
250
251 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
252 mhi_ctrl->irq_flags = IRQF_SHARED | IRQF_NOBALANCING;
253
254 mhi_ctrl->iova_start = 0;
255 mhi_ctrl->iova_stop = ab_pci->dma_mask;
256 mhi_ctrl->sbl_size = SZ_512K;
257 mhi_ctrl->seg_len = SZ_512K;
258 mhi_ctrl->fbc_download = true;
259 mhi_ctrl->runtime_get = ath12k_mhi_op_runtime_get;
260 mhi_ctrl->runtime_put = ath12k_mhi_op_runtime_put;
261 mhi_ctrl->status_cb = ath12k_mhi_op_status_cb;
262 mhi_ctrl->read_reg = ath12k_mhi_op_read_reg;
263 mhi_ctrl->write_reg = ath12k_mhi_op_write_reg;
264
265 ret = mhi_register_controller(mhi_ctrl, ab->hw_params->mhi_config);
266 if (ret) {
267 ath12k_err(ab, "failed to register to mhi bus, err = %d\n", ret);
268 goto free_controller;
269 }
270
271 return 0;
272
273 free_controller:
274 mhi_free_controller(mhi_ctrl);
275 ab_pci->mhi_ctrl = NULL;
276 return ret;
277 }
278
ath12k_mhi_unregister(struct ath12k_pci * ab_pci)279 void ath12k_mhi_unregister(struct ath12k_pci *ab_pci)
280 {
281 struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl;
282
283 mhi_unregister_controller(mhi_ctrl);
284 kfree(mhi_ctrl->irq);
285 mhi_free_controller(mhi_ctrl);
286 ab_pci->mhi_ctrl = NULL;
287 }
288
ath12k_mhi_state_to_str(enum ath12k_mhi_state mhi_state)289 static char *ath12k_mhi_state_to_str(enum ath12k_mhi_state mhi_state)
290 {
291 switch (mhi_state) {
292 case ATH12K_MHI_INIT:
293 return "INIT";
294 case ATH12K_MHI_DEINIT:
295 return "DEINIT";
296 case ATH12K_MHI_POWER_ON:
297 return "POWER_ON";
298 case ATH12K_MHI_POWER_OFF:
299 return "POWER_OFF";
300 case ATH12K_MHI_POWER_OFF_KEEP_DEV:
301 return "POWER_OFF_KEEP_DEV";
302 case ATH12K_MHI_FORCE_POWER_OFF:
303 return "FORCE_POWER_OFF";
304 case ATH12K_MHI_SUSPEND:
305 return "SUSPEND";
306 case ATH12K_MHI_RESUME:
307 return "RESUME";
308 case ATH12K_MHI_TRIGGER_RDDM:
309 return "TRIGGER_RDDM";
310 case ATH12K_MHI_RDDM_DONE:
311 return "RDDM_DONE";
312 default:
313 return "UNKNOWN";
314 }
315 };
316
ath12k_mhi_set_state_bit(struct ath12k_pci * ab_pci,enum ath12k_mhi_state mhi_state)317 static void ath12k_mhi_set_state_bit(struct ath12k_pci *ab_pci,
318 enum ath12k_mhi_state mhi_state)
319 {
320 struct ath12k_base *ab = ab_pci->ab;
321
322 switch (mhi_state) {
323 case ATH12K_MHI_INIT:
324 set_bit(ATH12K_MHI_INIT, &ab_pci->mhi_state);
325 break;
326 case ATH12K_MHI_DEINIT:
327 clear_bit(ATH12K_MHI_INIT, &ab_pci->mhi_state);
328 break;
329 case ATH12K_MHI_POWER_ON:
330 set_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state);
331 break;
332 case ATH12K_MHI_POWER_OFF:
333 case ATH12K_MHI_POWER_OFF_KEEP_DEV:
334 case ATH12K_MHI_FORCE_POWER_OFF:
335 clear_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state);
336 clear_bit(ATH12K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state);
337 clear_bit(ATH12K_MHI_RDDM_DONE, &ab_pci->mhi_state);
338 break;
339 case ATH12K_MHI_SUSPEND:
340 set_bit(ATH12K_MHI_SUSPEND, &ab_pci->mhi_state);
341 break;
342 case ATH12K_MHI_RESUME:
343 clear_bit(ATH12K_MHI_SUSPEND, &ab_pci->mhi_state);
344 break;
345 case ATH12K_MHI_TRIGGER_RDDM:
346 set_bit(ATH12K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state);
347 break;
348 case ATH12K_MHI_RDDM_DONE:
349 set_bit(ATH12K_MHI_RDDM_DONE, &ab_pci->mhi_state);
350 break;
351 default:
352 ath12k_err(ab, "unhandled mhi state (%d)\n", mhi_state);
353 }
354 }
355
ath12k_mhi_check_state_bit(struct ath12k_pci * ab_pci,enum ath12k_mhi_state mhi_state)356 static int ath12k_mhi_check_state_bit(struct ath12k_pci *ab_pci,
357 enum ath12k_mhi_state mhi_state)
358 {
359 struct ath12k_base *ab = ab_pci->ab;
360
361 switch (mhi_state) {
362 case ATH12K_MHI_INIT:
363 if (!test_bit(ATH12K_MHI_INIT, &ab_pci->mhi_state))
364 return 0;
365 break;
366 case ATH12K_MHI_DEINIT:
367 case ATH12K_MHI_POWER_ON:
368 if (test_bit(ATH12K_MHI_INIT, &ab_pci->mhi_state) &&
369 !test_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state))
370 return 0;
371 break;
372 case ATH12K_MHI_FORCE_POWER_OFF:
373 if (test_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state))
374 return 0;
375 break;
376 case ATH12K_MHI_POWER_OFF:
377 case ATH12K_MHI_POWER_OFF_KEEP_DEV:
378 case ATH12K_MHI_SUSPEND:
379 if (test_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state) &&
380 !test_bit(ATH12K_MHI_SUSPEND, &ab_pci->mhi_state))
381 return 0;
382 break;
383 case ATH12K_MHI_RESUME:
384 if (test_bit(ATH12K_MHI_SUSPEND, &ab_pci->mhi_state))
385 return 0;
386 break;
387 case ATH12K_MHI_TRIGGER_RDDM:
388 if (test_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state) &&
389 !test_bit(ATH12K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state))
390 return 0;
391 break;
392 case ATH12K_MHI_RDDM_DONE:
393 return 0;
394 default:
395 ath12k_err(ab, "unhandled mhi state: %s(%d)\n",
396 ath12k_mhi_state_to_str(mhi_state), mhi_state);
397 }
398
399 ath12k_err(ab, "failed to set mhi state %s(%d) in current mhi state (0x%lx)\n",
400 ath12k_mhi_state_to_str(mhi_state), mhi_state,
401 ab_pci->mhi_state);
402
403 return -EINVAL;
404 }
405
ath12k_mhi_set_state(struct ath12k_pci * ab_pci,enum ath12k_mhi_state mhi_state)406 static int ath12k_mhi_set_state(struct ath12k_pci *ab_pci,
407 enum ath12k_mhi_state mhi_state)
408 {
409 struct ath12k_base *ab = ab_pci->ab;
410 int ret;
411
412 ret = ath12k_mhi_check_state_bit(ab_pci, mhi_state);
413 if (ret)
414 goto out;
415
416 ath12k_dbg(ab, ATH12K_DBG_PCI, "setting mhi state: %s(%d)\n",
417 ath12k_mhi_state_to_str(mhi_state), mhi_state);
418
419 switch (mhi_state) {
420 case ATH12K_MHI_INIT:
421 ret = mhi_prepare_for_power_up(ab_pci->mhi_ctrl);
422 break;
423 case ATH12K_MHI_DEINIT:
424 mhi_unprepare_after_power_down(ab_pci->mhi_ctrl);
425 ret = 0;
426 break;
427 case ATH12K_MHI_POWER_ON:
428 /* In case of resume, QRTR's resume_early() is called
429 * right after ath12k' resume_early(). Since QRTR requires
430 * MHI mission mode state when preparing IPCR channels
431 * (see ee_mask of that channel), we need to use the 'sync'
432 * version here to make sure MHI is in that state when we
433 * return. Or QRTR might resume before that state comes,
434 * and as a result it fails.
435 *
436 * The 'sync' version works for non-resume (normal power on)
437 * case as well.
438 */
439 ret = mhi_sync_power_up(ab_pci->mhi_ctrl);
440 break;
441 case ATH12K_MHI_POWER_OFF:
442 mhi_power_down(ab_pci->mhi_ctrl, true);
443 ret = 0;
444 break;
445 case ATH12K_MHI_POWER_OFF_KEEP_DEV:
446 mhi_power_down_keep_dev(ab_pci->mhi_ctrl, true);
447 ret = 0;
448 break;
449 case ATH12K_MHI_FORCE_POWER_OFF:
450 mhi_power_down(ab_pci->mhi_ctrl, false);
451 ret = 0;
452 break;
453 case ATH12K_MHI_SUSPEND:
454 ret = mhi_pm_suspend(ab_pci->mhi_ctrl);
455 break;
456 case ATH12K_MHI_RESUME:
457 ret = mhi_pm_resume(ab_pci->mhi_ctrl);
458 break;
459 case ATH12K_MHI_TRIGGER_RDDM:
460 ret = mhi_force_rddm_mode(ab_pci->mhi_ctrl);
461 break;
462 case ATH12K_MHI_RDDM_DONE:
463 break;
464 default:
465 ath12k_err(ab, "unhandled MHI state (%d)\n", mhi_state);
466 ret = -EINVAL;
467 }
468
469 if (ret)
470 goto out;
471
472 ath12k_mhi_set_state_bit(ab_pci, mhi_state);
473
474 return 0;
475
476 out:
477 ath12k_err(ab, "failed to set mhi state: %s(%d)\n",
478 ath12k_mhi_state_to_str(mhi_state), mhi_state);
479 return ret;
480 }
481
ath12k_mhi_start(struct ath12k_pci * ab_pci)482 int ath12k_mhi_start(struct ath12k_pci *ab_pci)
483 {
484 int ret;
485
486 ab_pci->mhi_ctrl->timeout_ms = MHI_TIMEOUT_DEFAULT_MS;
487
488 ret = ath12k_mhi_set_state(ab_pci, ATH12K_MHI_INIT);
489 if (ret)
490 goto out;
491
492 ret = ath12k_mhi_set_state(ab_pci, ATH12K_MHI_POWER_ON);
493 if (ret)
494 goto out;
495
496 return 0;
497
498 out:
499 return ret;
500 }
501
ath12k_mhi_stop(struct ath12k_pci * ab_pci,bool is_suspend)502 void ath12k_mhi_stop(struct ath12k_pci *ab_pci, bool is_suspend)
503 {
504 /* During suspend we need to use mhi_power_down_keep_dev()
505 * workaround, otherwise ath12k_core_resume() will timeout
506 * during resume.
507 */
508 if (is_suspend)
509 ath12k_mhi_set_state(ab_pci, ATH12K_MHI_POWER_OFF_KEEP_DEV);
510 else
511 ath12k_mhi_set_state(ab_pci, ATH12K_MHI_POWER_OFF);
512
513 ath12k_mhi_set_state(ab_pci, ATH12K_MHI_DEINIT);
514 }
515
ath12k_mhi_suspend(struct ath12k_pci * ab_pci)516 void ath12k_mhi_suspend(struct ath12k_pci *ab_pci)
517 {
518 ath12k_mhi_set_state(ab_pci, ATH12K_MHI_SUSPEND);
519 }
520
ath12k_mhi_resume(struct ath12k_pci * ab_pci)521 void ath12k_mhi_resume(struct ath12k_pci *ab_pci)
522 {
523 ath12k_mhi_set_state(ab_pci, ATH12K_MHI_RESUME);
524 }
525
ath12k_mhi_coredump(struct mhi_controller * mhi_ctrl,bool in_panic)526 void ath12k_mhi_coredump(struct mhi_controller *mhi_ctrl, bool in_panic)
527 {
528 mhi_download_rddm_image(mhi_ctrl, in_panic);
529 }
530