1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #ifndef MTK_ETH_H 10 #define MTK_ETH_H 11 12 #include <linux/dma-mapping.h> 13 #include <linux/netdevice.h> 14 #include <linux/of_net.h> 15 #include <linux/u64_stats_sync.h> 16 #include <linux/refcount.h> 17 #include <linux/phylink.h> 18 #include <linux/rhashtable.h> 19 #include <linux/dim.h> 20 #include <linux/bitfield.h> 21 #include <net/page_pool/types.h> 22 #include <linux/bpf_trace.h> 23 #include "mtk_ppe.h" 24 25 #define MTK_MAX_DSA_PORTS 7 26 #define MTK_DSA_PORT_MASK GENMASK(2, 0) 27 28 #define MTK_QDMA_NUM_QUEUES 16 29 #define MTK_QDMA_PAGE_SIZE 2048 30 #define MTK_MAX_RX_LENGTH 1536 31 #define MTK_MAX_RX_LENGTH_2K 2048 32 #define MTK_TX_DMA_BUF_LEN 0x3fff 33 #define MTK_TX_DMA_BUF_LEN_V2 0xffff 34 #define MTK_QDMA_RING_SIZE 2048 35 #define MTK_DMA_SIZE(x) (SZ_##x) 36 #define MTK_FQ_DMA_HEAD 32 37 #define MTK_FQ_DMA_LENGTH 2048 38 #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN) 39 #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 40 #define MTK_DMA_DUMMY_DESC 0xffffffff 41 #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 42 NETIF_MSG_PROBE | \ 43 NETIF_MSG_LINK | \ 44 NETIF_MSG_TIMER | \ 45 NETIF_MSG_IFDOWN | \ 46 NETIF_MSG_IFUP | \ 47 NETIF_MSG_RX_ERR | \ 48 NETIF_MSG_TX_ERR) 49 #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 50 NETIF_F_RXCSUM | \ 51 NETIF_F_HW_VLAN_CTAG_TX | \ 52 NETIF_F_SG | NETIF_F_TSO | \ 53 NETIF_F_TSO6 | \ 54 NETIF_F_IPV6_CSUM |\ 55 NETIF_F_HW_TC) 56 #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM) 57 #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 58 59 #define MTK_PP_HEADROOM XDP_PACKET_HEADROOM 60 #define MTK_PP_PAD (MTK_PP_HEADROOM + \ 61 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 62 #define MTK_PP_MAX_BUF_SIZE (PAGE_SIZE - MTK_PP_PAD) 63 64 #define MTK_QRX_OFFSET 0x10 65 66 #define MTK_MAX_RX_RING_NUM 4 67 #define MTK_HW_LRO_DMA_SIZE 8 68 69 #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 70 #define MTK_MAX_LRO_IP_CNT 2 71 #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 72 #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 73 #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 74 #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 75 #define MTK_HW_LRO_MAX_AGG_CNT 64 76 #define MTK_HW_LRO_BW_THRE 3000 77 #define MTK_HW_LRO_REPLACE_DELTA 1000 78 #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 79 80 /* Frame Engine Global Configuration */ 81 #define MTK_FE_GLO_CFG(x) (((x) == MTK_GMAC3_ID) ? 0x24 : 0x00) 82 #define MTK_FE_LINK_DOWN_P(x) BIT(((x) + 8) % 16) 83 84 /* Frame Engine Global Reset Register */ 85 #define MTK_RST_GL 0x04 86 #define RST_GL_PSE BIT(0) 87 88 /* Frame Engine Interrupt Status Register */ 89 #define MTK_INT_STATUS2 0x08 90 #define MTK_FE_INT_ENABLE 0x0c 91 #define MTK_FE_INT_FQ_EMPTY BIT(8) 92 #define MTK_FE_INT_TSO_FAIL BIT(12) 93 #define MTK_FE_INT_TSO_ILLEGAL BIT(13) 94 #define MTK_FE_INT_TSO_ALIGN BIT(14) 95 #define MTK_FE_INT_RFIFO_OV BIT(18) 96 #define MTK_FE_INT_RFIFO_UF BIT(19) 97 #define MTK_GDM1_AF BIT(28) 98 #define MTK_GDM2_AF BIT(29) 99 100 /* PDMA HW LRO Alter Flow Timer Register */ 101 #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 102 103 /* Frame Engine Interrupt Grouping Register */ 104 #define MTK_FE_INT_GRP 0x20 105 106 /* CDMP Ingress Control Register */ 107 #define MTK_CDMQ_IG_CTRL 0x1400 108 #define MTK_CDMQ_STAG_EN BIT(0) 109 110 /* CDMQ Exgress Control Register */ 111 #define MTK_CDMQ_EG_CTRL 0x1404 112 113 /* CDMP Ingress Control Register */ 114 #define MTK_CDMP_IG_CTRL 0x400 115 #define MTK_CDMP_STAG_EN BIT(0) 116 117 /* CDMP Exgress Control Register */ 118 #define MTK_CDMP_EG_CTRL 0x404 119 120 /* GDM Exgress Control Register */ 121 #define MTK_GDMA_FWD_CFG(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \ 122 0x540 : 0x500 + (_x * 0x1000); }) 123 #define MTK_GDMA_SPECIAL_TAG BIT(24) 124 #define MTK_GDMA_ICS_EN BIT(22) 125 #define MTK_GDMA_TCS_EN BIT(21) 126 #define MTK_GDMA_UCS_EN BIT(20) 127 #define MTK_GDMA_STRP_CRC BIT(16) 128 #define MTK_GDMA_TO_PDMA 0x0 129 #define MTK_GDMA_DROP_ALL 0x7777 130 131 /* GDM Egress Control Register */ 132 #define MTK_GDMA_EG_CTRL(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \ 133 0x544 : 0x504 + (_x * 0x1000); }) 134 #define MTK_GDMA_XGDM_SEL BIT(31) 135 136 /* Unicast Filter MAC Address Register - Low */ 137 #define MTK_GDMA_MAC_ADRL(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \ 138 0x548 : 0x508 + (_x * 0x1000); }) 139 140 /* Unicast Filter MAC Address Register - High */ 141 #define MTK_GDMA_MAC_ADRH(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \ 142 0x54C : 0x50C + (_x * 0x1000); }) 143 144 /* legacy DT support for internal SRAM */ 145 #define MTK_ETH_SRAM_OFFSET 0x40000 146 #define MTK_ETH_SRAM_GRANULARITY 32 147 #define MTK_ETH_NETSYS_V2_SRAM_SIZE 0x40000 148 149 /* FE global misc reg*/ 150 #define MTK_FE_GLO_MISC 0x124 151 152 /* PSE Free Queue Flow Control */ 153 #define PSE_FQFC_CFG1 0x100 154 #define PSE_FQFC_CFG2 0x104 155 #define PSE_DROP_CFG 0x108 156 #define PSE_PPE_DROP(x) (0x110 + ((x) * 0x4)) 157 158 /* PSE Last FreeQ Page Request Control */ 159 #define PSE_DUMY_REQ 0x10C 160 /* PSE_DUMY_REQ is not a typo but actually called like that also in 161 * MediaTek's datasheet 162 */ 163 #define PSE_DUMMY_WORK_GDM(x) BIT(16 + (x)) 164 #define DUMMY_PAGE_THR 0x1 165 166 /* PSE Input Queue Reservation Register*/ 167 #define PSE_IQ_REV(x) (0x140 + (((x) - 1) << 2)) 168 169 /* PSE Output Queue Threshold Register*/ 170 #define PSE_OQ_TH(x) (0x160 + (((x) - 1) << 2)) 171 172 /* GDM and CDM Threshold */ 173 #define MTK_GDM2_THRES 0x1530 174 #define MTK_CDMW0_THRES 0x164c 175 #define MTK_CDMW1_THRES 0x1650 176 #define MTK_CDME0_THRES 0x1654 177 #define MTK_CDME1_THRES 0x1658 178 #define MTK_CDMM_THRES 0x165c 179 180 /* PDMA HW LRO Control Registers */ 181 #define MTK_PDMA_LRO_CTRL_DW0 0x980 182 #define MTK_LRO_EN BIT(0) 183 #define MTK_L3_CKS_UPD_EN BIT(7) 184 #define MTK_L3_CKS_UPD_EN_V2 BIT(19) 185 #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 186 #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 187 #define MTK_LRO_RING_RELINQUISH_REQ_V2 (0xf << 24) 188 #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 189 #define MTK_LRO_RING_RELINQUISH_DONE_V2 (0xf << 28) 190 191 #define MTK_PDMA_LRO_CTRL_DW1 0x984 192 #define MTK_PDMA_LRO_CTRL_DW2 0x988 193 #define MTK_PDMA_LRO_CTRL_DW3 0x98c 194 #define MTK_ADMA_MODE BIT(15) 195 #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 196 197 #define MTK_RX_DMA_LRO_EN BIT(8) 198 #define MTK_MULTI_EN BIT(10) 199 #define MTK_PDMA_SIZE_8DWORDS (1 << 4) 200 201 /* PDMA Global Configuration Register */ 202 #define MTK_PDMA_LRO_SDL 0x3000 203 #define MTK_RX_CFG_SDL_OFFSET 16 204 205 /* PDMA Reset Index Register */ 206 #define MTK_PST_DRX_IDX0 BIT(16) 207 #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 208 209 /* PDMA Delay Interrupt Register */ 210 #define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0) 211 #define MTK_PDMA_DELAY_RX_EN BIT(15) 212 #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 213 #define MTK_PDMA_DELAY_RX_PTIME_SHIFT 0 214 215 #define MTK_PDMA_DELAY_TX_MASK GENMASK(31, 16) 216 #define MTK_PDMA_DELAY_TX_EN BIT(31) 217 #define MTK_PDMA_DELAY_TX_PINT_SHIFT 24 218 #define MTK_PDMA_DELAY_TX_PTIME_SHIFT 16 219 220 #define MTK_PDMA_DELAY_PINT_MASK 0x7f 221 #define MTK_PDMA_DELAY_PTIME_MASK 0xff 222 223 /* PDMA HW LRO Alter Flow Delta Register */ 224 #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 225 226 /* PDMA HW LRO IP Setting Registers */ 227 #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 228 #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 229 #define MTK_RING_MYIP_VLD BIT(9) 230 231 /* PDMA HW LRO Ring Control Registers */ 232 #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 233 #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 234 #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 235 #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 236 #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 237 #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 238 #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 239 #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 240 #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 241 #define MTK_RING_VLD BIT(8) 242 #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 243 #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 244 #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 245 246 /* QDMA TX Queue Configuration Registers */ 247 #define MTK_QTX_OFFSET 0x10 248 #define QDMA_RES_THRES 4 249 250 /* QDMA Tx Queue Scheduler Configuration Registers */ 251 #define MTK_QTX_SCH_TX_SEL BIT(31) 252 #define MTK_QTX_SCH_TX_SEL_V2 GENMASK(31, 30) 253 254 #define MTK_QTX_SCH_LEAKY_BUCKET_EN BIT(30) 255 #define MTK_QTX_SCH_LEAKY_BUCKET_SIZE GENMASK(29, 28) 256 #define MTK_QTX_SCH_MIN_RATE_EN BIT(27) 257 #define MTK_QTX_SCH_MIN_RATE_MAN GENMASK(26, 20) 258 #define MTK_QTX_SCH_MIN_RATE_EXP GENMASK(19, 16) 259 #define MTK_QTX_SCH_MAX_RATE_WEIGHT GENMASK(15, 12) 260 #define MTK_QTX_SCH_MAX_RATE_EN BIT(11) 261 #define MTK_QTX_SCH_MAX_RATE_MAN GENMASK(10, 4) 262 #define MTK_QTX_SCH_MAX_RATE_EXP GENMASK(3, 0) 263 264 /* QDMA TX Scheduler Rate Control Register */ 265 #define MTK_QDMA_TX_SCH_MAX_WFQ BIT(15) 266 267 /* QDMA Global Configuration Register */ 268 #define MTK_RX_2B_OFFSET BIT(31) 269 #define MTK_RX_BT_32DWORDS (3 << 11) 270 #define MTK_NDP_CO_PRO BIT(10) 271 #define MTK_TX_WB_DDONE BIT(6) 272 #define MTK_TX_BT_32DWORDS (3 << 4) 273 #define MTK_RX_DMA_BUSY BIT(3) 274 #define MTK_TX_DMA_BUSY BIT(1) 275 #define MTK_RX_DMA_EN BIT(2) 276 #define MTK_TX_DMA_EN BIT(0) 277 #define MTK_DMA_BUSY_TIMEOUT_US 1000000 278 279 /* QDMA V2 Global Configuration Register */ 280 #define MTK_CHK_DDONE_EN BIT(28) 281 #define MTK_DMAD_WR_WDONE BIT(26) 282 #define MTK_WCOMP_EN BIT(24) 283 #define MTK_RESV_BUF (0x40 << 16) 284 #define MTK_MUTLI_CNT (0x4 << 12) 285 #define MTK_LEAKY_BUCKET_EN BIT(11) 286 287 /* QDMA Flow Control Register */ 288 #define FC_THRES_DROP_MODE BIT(20) 289 #define FC_THRES_DROP_EN (7 << 16) 290 #define FC_THRES_MIN 0x4444 291 292 /* QDMA Interrupt Status Register */ 293 #define MTK_RX_DONE_DLY BIT(30) 294 #define MTK_TX_DONE_DLY BIT(28) 295 #define MTK_RX_DONE_INT3 BIT(19) 296 #define MTK_RX_DONE_INT2 BIT(18) 297 #define MTK_RX_DONE_INT1 BIT(17) 298 #define MTK_RX_DONE_INT0 BIT(16) 299 #define MTK_TX_DONE_INT3 BIT(3) 300 #define MTK_TX_DONE_INT2 BIT(2) 301 #define MTK_TX_DONE_INT1 BIT(1) 302 #define MTK_TX_DONE_INT0 BIT(0) 303 #define MTK_RX_DONE_INT MTK_RX_DONE_DLY 304 #define MTK_TX_DONE_INT MTK_TX_DONE_DLY 305 306 #define MTK_RX_DONE_INT_V2 BIT(14) 307 308 #define MTK_CDM_TXFIFO_RDY BIT(7) 309 310 /* QDMA Interrupt grouping registers */ 311 #define MTK_RLS_DONE_INT BIT(0) 312 313 /* QDMA TX NUM */ 314 #define QID_BITS_V2(x) (((x) & 0x3f) << 16) 315 #define MTK_QDMA_GMAC2_QID 8 316 317 #define MTK_TX_DMA_BUF_SHIFT 8 318 319 /* QDMA V2 descriptor txd6 */ 320 #define TX_DMA_INS_VLAN_V2 BIT(16) 321 /* QDMA V2 descriptor txd5 */ 322 #define TX_DMA_CHKSUM_V2 (0x7 << 28) 323 #define TX_DMA_TSO_V2 BIT(31) 324 325 #define TX_DMA_SPTAG_V3 BIT(27) 326 327 /* QDMA V2 descriptor txd4 */ 328 #define TX_DMA_FPORT_SHIFT_V2 8 329 #define TX_DMA_FPORT_MASK_V2 0xf 330 #define TX_DMA_SWC_V2 BIT(30) 331 332 /* QDMA descriptor txd4 */ 333 #define TX_DMA_CHKSUM (0x7 << 29) 334 #define TX_DMA_TSO BIT(28) 335 #define TX_DMA_FPORT_SHIFT 25 336 #define TX_DMA_FPORT_MASK 0x7 337 #define TX_DMA_INS_VLAN BIT(16) 338 339 /* QDMA descriptor txd3 */ 340 #define TX_DMA_OWNER_CPU BIT(31) 341 #define TX_DMA_LS0 BIT(30) 342 #define TX_DMA_PLEN0(x) (((x) & eth->soc->tx.dma_max_len) << eth->soc->tx.dma_len_offset) 343 #define TX_DMA_PLEN1(x) ((x) & eth->soc->tx.dma_max_len) 344 #define TX_DMA_SWC BIT(14) 345 #define TX_DMA_PQID GENMASK(3, 0) 346 #define TX_DMA_ADDR64_MASK GENMASK(3, 0) 347 #if IS_ENABLED(CONFIG_64BIT) 348 # define TX_DMA_GET_ADDR64(x) (((u64)FIELD_GET(TX_DMA_ADDR64_MASK, (x))) << 32) 349 # define TX_DMA_PREP_ADDR64(x) FIELD_PREP(TX_DMA_ADDR64_MASK, ((x) >> 32)) 350 #else 351 # define TX_DMA_GET_ADDR64(x) (0) 352 # define TX_DMA_PREP_ADDR64(x) (0) 353 #endif 354 355 /* PDMA on MT7628 */ 356 #define TX_DMA_DONE BIT(31) 357 #define TX_DMA_LS1 BIT(14) 358 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE) 359 360 /* QDMA descriptor rxd2 */ 361 #define RX_DMA_DONE BIT(31) 362 #define RX_DMA_LSO BIT(30) 363 #define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->rx.dma_max_len) << eth->soc->rx.dma_len_offset) 364 #define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->rx.dma_len_offset) & eth->soc->rx.dma_max_len) 365 #define RX_DMA_VTAG BIT(15) 366 #define RX_DMA_ADDR64_MASK GENMASK(3, 0) 367 #if IS_ENABLED(CONFIG_64BIT) 368 # define RX_DMA_GET_ADDR64(x) (((u64)FIELD_GET(RX_DMA_ADDR64_MASK, (x))) << 32) 369 # define RX_DMA_PREP_ADDR64(x) FIELD_PREP(RX_DMA_ADDR64_MASK, ((x) >> 32)) 370 #else 371 # define RX_DMA_GET_ADDR64(x) (0) 372 # define RX_DMA_PREP_ADDR64(x) (0) 373 #endif 374 375 /* QDMA descriptor rxd3 */ 376 #define RX_DMA_VID(x) ((x) & VLAN_VID_MASK) 377 #define RX_DMA_TCI(x) ((x) & (VLAN_PRIO_MASK | VLAN_VID_MASK)) 378 #define RX_DMA_VPID(x) (((x) >> 16) & 0xffff) 379 380 /* QDMA descriptor rxd4 */ 381 #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0) 382 #define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14) 383 #define MTK_RXD4_SRC_PORT GENMASK(21, 19) 384 #define MTK_RXD4_ALG GENMASK(31, 22) 385 386 /* QDMA descriptor rxd4 */ 387 #define RX_DMA_L4_VALID BIT(24) 388 #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ 389 #define RX_DMA_SPECIAL_TAG BIT(22) 390 391 /* PDMA descriptor rxd5 */ 392 #define MTK_RXD5_FOE_ENTRY GENMASK(14, 0) 393 #define MTK_RXD5_PPE_CPU_REASON GENMASK(22, 18) 394 #define MTK_RXD5_SRC_PORT GENMASK(29, 26) 395 396 #define RX_DMA_GET_SPORT(x) (((x) >> 19) & 0x7) 397 #define RX_DMA_GET_SPORT_V2(x) (((x) >> 26) & 0xf) 398 399 /* PDMA V2 descriptor rxd3 */ 400 #define RX_DMA_VTAG_V2 BIT(0) 401 #define RX_DMA_L4_VALID_V2 BIT(2) 402 403 /* PHY Polling and SMI Master Control registers */ 404 #define MTK_PPSC 0x10000 405 #define PPSC_MDC_CFG GENMASK(29, 24) 406 #define PPSC_MDC_TURBO BIT(20) 407 #define MDC_MAX_FREQ 25000000 408 #define MDC_MAX_DIVIDER 63 409 410 /* PHY Indirect Access Control registers */ 411 #define MTK_PHY_IAC 0x10004 412 #define PHY_IAC_ACCESS BIT(31) 413 #define PHY_IAC_REG_MASK GENMASK(29, 25) 414 #define PHY_IAC_REG(x) FIELD_PREP(PHY_IAC_REG_MASK, (x)) 415 #define PHY_IAC_ADDR_MASK GENMASK(24, 20) 416 #define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x)) 417 #define PHY_IAC_CMD_MASK GENMASK(19, 18) 418 #define PHY_IAC_CMD_C45_ADDR FIELD_PREP(PHY_IAC_CMD_MASK, 0) 419 #define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1) 420 #define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2) 421 #define PHY_IAC_CMD_C45_READ FIELD_PREP(PHY_IAC_CMD_MASK, 3) 422 #define PHY_IAC_START_MASK GENMASK(17, 16) 423 #define PHY_IAC_START_C45 FIELD_PREP(PHY_IAC_START_MASK, 0) 424 #define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1) 425 #define PHY_IAC_DATA_MASK GENMASK(15, 0) 426 #define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x)) 427 #define PHY_IAC_TIMEOUT HZ 428 429 #define MTK_MAC_MISC 0x1000c 430 #define MTK_MAC_MISC_V3 0x10010 431 #define MTK_MUX_TO_ESW BIT(0) 432 #define MISC_MDC_TURBO BIT(4) 433 434 /* XMAC status registers */ 435 #define MTK_XGMAC_STS(x) (((x) == MTK_GMAC3_ID) ? 0x1001C : 0x1000C) 436 #define MTK_XGMAC_FORCE_MODE(x) (((x) == MTK_GMAC2_ID) ? BIT(31) : BIT(15)) 437 #define MTK_XGMAC_FORCE_LINK(x) (((x) == MTK_GMAC2_ID) ? BIT(27) : BIT(11)) 438 #define MTK_USXGMII_PCS_LINK BIT(8) 439 #define MTK_XGMAC_RX_FC BIT(5) 440 #define MTK_XGMAC_TX_FC BIT(4) 441 #define MTK_USXGMII_PCS_MODE GENMASK(3, 1) 442 #define MTK_XGMAC_LINK_STS BIT(0) 443 444 /* GSW bridge registers */ 445 #define MTK_GSW_CFG (0x10080) 446 #define GSWTX_IPG_MASK GENMASK(19, 16) 447 #define GSWTX_IPG_SHIFT 16 448 #define GSWRX_IPG_MASK GENMASK(3, 0) 449 #define GSWRX_IPG_SHIFT 0 450 #define GSW_IPG_11 11 451 452 /* Mac control registers */ 453 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 454 #define MAC_MCR_MAX_RX_MASK GENMASK(25, 24) 455 #define MAC_MCR_MAX_RX(_x) (MAC_MCR_MAX_RX_MASK & ((_x) << 24)) 456 #define MAC_MCR_MAX_RX_1518 0x0 457 #define MAC_MCR_MAX_RX_1536 0x1 458 #define MAC_MCR_MAX_RX_1552 0x2 459 #define MAC_MCR_MAX_RX_2048 0x3 460 #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 461 #define MAC_MCR_FORCE_MODE BIT(15) 462 #define MAC_MCR_TX_EN BIT(14) 463 #define MAC_MCR_RX_EN BIT(13) 464 #define MAC_MCR_RX_FIFO_CLR_DIS BIT(12) 465 #define MAC_MCR_BACKOFF_EN BIT(9) 466 #define MAC_MCR_BACKPR_EN BIT(8) 467 #define MAC_MCR_EEE1G BIT(7) 468 #define MAC_MCR_EEE100M BIT(6) 469 #define MAC_MCR_FORCE_RX_FC BIT(5) 470 #define MAC_MCR_FORCE_TX_FC BIT(4) 471 #define MAC_MCR_SPEED_1000 BIT(3) 472 #define MAC_MCR_SPEED_100 BIT(2) 473 #define MAC_MCR_FORCE_DPX BIT(1) 474 #define MAC_MCR_FORCE_LINK BIT(0) 475 #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE) 476 477 /* Mac EEE control registers */ 478 #define MTK_MAC_EEECR(x) (0x10104 + (x * 0x100)) 479 #define MAC_EEE_WAKEUP_TIME_1000 GENMASK(31, 24) 480 #define MAC_EEE_WAKEUP_TIME_100 GENMASK(23, 16) 481 #define MAC_EEE_LPI_TXIDLE_THD GENMASK(15, 8) 482 #define MAC_EEE_CKG_TXIDLE BIT(3) 483 #define MAC_EEE_CKG_RXLPI BIT(2) 484 #define MAC_EEE_LPI_MODE BIT(0) 485 486 /* Mac status registers */ 487 #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100)) 488 #define MAC_MSR_EEE1G BIT(7) 489 #define MAC_MSR_EEE100M BIT(6) 490 #define MAC_MSR_RX_FC BIT(5) 491 #define MAC_MSR_TX_FC BIT(4) 492 #define MAC_MSR_SPEED_1000 BIT(3) 493 #define MAC_MSR_SPEED_100 BIT(2) 494 #define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100) 495 #define MAC_MSR_DPX BIT(1) 496 #define MAC_MSR_LINK BIT(0) 497 498 /* TRGMII RXC control register */ 499 #define TRGMII_RCK_CTRL 0x10300 500 #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 501 #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 502 #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 503 #define RXC_RST BIT(31) 504 #define RXC_DQSISEL BIT(30) 505 #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 506 #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 507 508 #define NUM_TRGMII_CTRL 5 509 510 /* TRGMII RXC control register */ 511 #define TRGMII_TCK_CTRL 0x10340 512 #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 513 #define TXC_INV BIT(30) 514 #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 515 #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 516 517 /* TRGMII TX Drive Strength */ 518 #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i)) 519 #define TD_DM_DRVP(x) ((x) & 0xf) 520 #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 521 522 /* TRGMII Interface mode register */ 523 #define INTF_MODE 0x10390 524 #define TRGMII_INTF_DIS BIT(0) 525 #define TRGMII_MODE BIT(1) 526 #define TRGMII_CENTRAL_ALIGNED BIT(2) 527 #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 528 #define INTF_MODE_RGMII_10_100 0 529 530 /* XFI Mac control registers */ 531 #define MTK_XMAC_BASE(x) (0x12000 + (((x) - 1) * 0x1000)) 532 #define MTK_XMAC_MCR(x) (MTK_XMAC_BASE(x)) 533 #define XMAC_MCR_TRX_DISABLE 0xf 534 #define XMAC_MCR_FORCE_TX_FC BIT(5) 535 #define XMAC_MCR_FORCE_RX_FC BIT(4) 536 537 /* XFI Mac logic reset registers */ 538 #define MTK_XMAC_LOGIC_RST(x) (MTK_XMAC_BASE(x) + 0x10) 539 #define XMAC_LOGIC_RST BIT(0) 540 541 /* XFI Mac count global control */ 542 #define MTK_XMAC_CNT_CTRL(x) (MTK_XMAC_BASE(x) + 0x100) 543 #define XMAC_GLB_CNTCLR BIT(0) 544 545 /* GPIO port control registers for GMAC 2*/ 546 #define GPIO_OD33_CTRL8 0x4c0 547 #define GPIO_BIAS_CTRL 0xed0 548 #define GPIO_DRV_SEL10 0xf00 549 550 /* ethernet subsystem chip id register */ 551 #define ETHSYS_CHIPID0_3 0x0 552 #define ETHSYS_CHIPID4_7 0x4 553 #define MT7623_ETH 7623 554 #define MT7622_ETH 7622 555 #define MT7621_ETH 7621 556 557 /* ethernet system control register */ 558 #define ETHSYS_SYSCFG 0x10 559 #define SYSCFG_DRAM_TYPE_DDR2 BIT(4) 560 561 /* ethernet subsystem config register */ 562 #define ETHSYS_SYSCFG0 0x14 563 #define SYSCFG0_GE_MASK 0x3 564 #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 565 #define SYSCFG0_SGMII_MASK GENMASK(9, 7) 566 #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) 567 #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) 568 #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) 569 #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) 570 571 572 /* ethernet subsystem clock register */ 573 #define ETHSYS_CLKCFG0 0x2c 574 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 575 #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6)) 576 #define ETHSYS_TRGMII_MT7621_APLL BIT(6) 577 #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) 578 579 /* ethernet reset control register */ 580 #define ETHSYS_RSTCTRL 0x34 581 #define RSTCTRL_FE BIT(6) 582 #define RSTCTRL_WDMA0 BIT(24) 583 #define RSTCTRL_WDMA1 BIT(25) 584 #define RSTCTRL_WDMA2 BIT(26) 585 #define RSTCTRL_PPE0 BIT(31) 586 #define RSTCTRL_PPE0_V2 BIT(30) 587 #define RSTCTRL_PPE1 BIT(31) 588 #define RSTCTRL_PPE0_V3 BIT(29) 589 #define RSTCTRL_PPE1_V3 BIT(30) 590 #define RSTCTRL_PPE2 BIT(31) 591 #define RSTCTRL_ETH BIT(23) 592 593 /* ethernet reset check idle register */ 594 #define ETHSYS_FE_RST_CHK_IDLE_EN 0x28 595 596 /* ethernet dma channel agent map */ 597 #define ETHSYS_DMA_AG_MAP 0x408 598 #define ETHSYS_DMA_AG_MAP_PDMA BIT(0) 599 #define ETHSYS_DMA_AG_MAP_QDMA BIT(1) 600 #define ETHSYS_DMA_AG_MAP_PPE BIT(2) 601 602 /* Infrasys subsystem config registers */ 603 #define INFRA_MISC2 0x70c 604 #define CO_QPHY_SEL BIT(0) 605 #define GEPHY_MAC_SEL BIT(1) 606 607 /* Top misc registers */ 608 #define TOP_MISC_NETSYS_PCS_MUX 0x0 609 #define NETSYS_PCS_MUX_MASK GENMASK(1, 0) 610 #define MUX_G2_USXGMII_SEL BIT(1) 611 612 #define USB_PHY_SWITCH_REG 0x218 613 #define QPHY_SEL_MASK GENMASK(1, 0) 614 #define SGMII_QPHY_SEL 0x2 615 616 /* MT7628/88 specific stuff */ 617 #define MT7628_PDMA_OFFSET 0x0800 618 #define MT7628_SDM_OFFSET 0x0c00 619 620 #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00) 621 #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04) 622 #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08) 623 #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c) 624 #define MT7628_PST_DTX_IDX0 BIT(0) 625 626 #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c) 627 #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10) 628 629 /* Counter / stat register */ 630 #define MT7628_SDM_TPCNT (MT7628_SDM_OFFSET + 0x100) 631 #define MT7628_SDM_TBCNT (MT7628_SDM_OFFSET + 0x104) 632 #define MT7628_SDM_RPCNT (MT7628_SDM_OFFSET + 0x108) 633 #define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c) 634 #define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110) 635 636 #define MTK_FE_CDM1_FSM 0x220 637 #define MTK_FE_CDM2_FSM 0x224 638 #define MTK_FE_CDM3_FSM 0x238 639 #define MTK_FE_CDM4_FSM 0x298 640 #define MTK_FE_CDM5_FSM 0x318 641 #define MTK_FE_CDM6_FSM 0x328 642 #define MTK_FE_GDM1_FSM 0x228 643 #define MTK_FE_GDM2_FSM 0x22C 644 645 #define MTK_MAC_FSM(x) (0x1010C + ((x) * 0x100)) 646 647 #define MTK_FE_IRQ_SHARED 0 648 #define MTK_FE_IRQ_TX 0 649 #define MTK_FE_IRQ_RX 1 650 #define MTK_FE_IRQ_NUM (MTK_FE_IRQ_RX + 1) 651 652 struct mtk_rx_dma { 653 unsigned int rxd1; 654 unsigned int rxd2; 655 unsigned int rxd3; 656 unsigned int rxd4; 657 } __packed __aligned(4); 658 659 struct mtk_rx_dma_v2 { 660 unsigned int rxd1; 661 unsigned int rxd2; 662 unsigned int rxd3; 663 unsigned int rxd4; 664 unsigned int rxd5; 665 unsigned int rxd6; 666 unsigned int rxd7; 667 unsigned int rxd8; 668 } __packed __aligned(4); 669 670 struct mtk_tx_dma { 671 unsigned int txd1; 672 unsigned int txd2; 673 unsigned int txd3; 674 unsigned int txd4; 675 } __packed __aligned(4); 676 677 struct mtk_tx_dma_v2 { 678 unsigned int txd1; 679 unsigned int txd2; 680 unsigned int txd3; 681 unsigned int txd4; 682 unsigned int txd5; 683 unsigned int txd6; 684 unsigned int txd7; 685 unsigned int txd8; 686 } __packed __aligned(4); 687 688 struct mtk_eth; 689 struct mtk_mac; 690 691 struct mtk_xdp_stats { 692 u64 rx_xdp_redirect; 693 u64 rx_xdp_pass; 694 u64 rx_xdp_drop; 695 u64 rx_xdp_tx; 696 u64 rx_xdp_tx_errors; 697 u64 tx_xdp_xmit; 698 u64 tx_xdp_xmit_errors; 699 }; 700 701 /* struct mtk_hw_stats - the structure that holds the traffic statistics. 702 * @stats_lock: make sure that stats operations are atomic 703 * @reg_offset: the status register offset of the SoC 704 * @syncp: the refcount 705 * 706 * All of the supported SoCs have hardware counters for traffic statistics. 707 * Whenever the status IRQ triggers we can read the latest stats from these 708 * counters and store them in this struct. 709 */ 710 struct mtk_hw_stats { 711 u64 tx_bytes; 712 u64 tx_packets; 713 u64 tx_skip; 714 u64 tx_collisions; 715 u64 rx_bytes; 716 u64 rx_packets; 717 u64 rx_overflow; 718 u64 rx_fcs_errors; 719 u64 rx_short_errors; 720 u64 rx_long_errors; 721 u64 rx_checksum_errors; 722 u64 rx_flow_control_packets; 723 724 struct mtk_xdp_stats xdp_stats; 725 726 spinlock_t stats_lock; 727 u32 reg_offset; 728 struct u64_stats_sync syncp; 729 }; 730 731 enum mtk_tx_flags { 732 /* PDMA descriptor can point at 1-2 segments. This enum allows us to 733 * track how memory was allocated so that it can be freed properly. 734 */ 735 MTK_TX_FLAGS_SINGLE0 = 0x01, 736 MTK_TX_FLAGS_PAGE0 = 0x02, 737 }; 738 739 /* This enum allows us to identify how the clock is defined on the array of the 740 * clock in the order 741 */ 742 enum mtk_clks_map { 743 MTK_CLK_ETHIF, 744 MTK_CLK_SGMIITOP, 745 MTK_CLK_ESW, 746 MTK_CLK_GP0, 747 MTK_CLK_GP1, 748 MTK_CLK_GP2, 749 MTK_CLK_GP3, 750 MTK_CLK_XGP1, 751 MTK_CLK_XGP2, 752 MTK_CLK_XGP3, 753 MTK_CLK_CRYPTO, 754 MTK_CLK_FE, 755 MTK_CLK_TRGPLL, 756 MTK_CLK_SGMII_TX_250M, 757 MTK_CLK_SGMII_RX_250M, 758 MTK_CLK_SGMII_CDR_REF, 759 MTK_CLK_SGMII_CDR_FB, 760 MTK_CLK_SGMII2_TX_250M, 761 MTK_CLK_SGMII2_RX_250M, 762 MTK_CLK_SGMII2_CDR_REF, 763 MTK_CLK_SGMII2_CDR_FB, 764 MTK_CLK_SGMII_CK, 765 MTK_CLK_ETH2PLL, 766 MTK_CLK_WOCPU0, 767 MTK_CLK_WOCPU1, 768 MTK_CLK_NETSYS0, 769 MTK_CLK_NETSYS1, 770 MTK_CLK_ETHWARP_WOCPU2, 771 MTK_CLK_ETHWARP_WOCPU1, 772 MTK_CLK_ETHWARP_WOCPU0, 773 MTK_CLK_TOP_SGM_0_SEL, 774 MTK_CLK_TOP_SGM_1_SEL, 775 MTK_CLK_TOP_ETH_GMII_SEL, 776 MTK_CLK_TOP_ETH_REFCK_50M_SEL, 777 MTK_CLK_TOP_ETH_SYS_200M_SEL, 778 MTK_CLK_TOP_ETH_SYS_SEL, 779 MTK_CLK_TOP_ETH_XGMII_SEL, 780 MTK_CLK_TOP_ETH_MII_SEL, 781 MTK_CLK_TOP_NETSYS_SEL, 782 MTK_CLK_TOP_NETSYS_500M_SEL, 783 MTK_CLK_TOP_NETSYS_PAO_2X_SEL, 784 MTK_CLK_TOP_NETSYS_SYNC_250M_SEL, 785 MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL, 786 MTK_CLK_TOP_NETSYS_WARP_SEL, 787 MTK_CLK_MAX 788 }; 789 790 #define MT7623_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ 791 BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \ 792 BIT_ULL(MTK_CLK_TRGPLL)) 793 #define MT7622_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ 794 BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \ 795 BIT_ULL(MTK_CLK_GP2) | \ 796 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ 797 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ 798 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ 799 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ 800 BIT_ULL(MTK_CLK_SGMII_CK) | \ 801 BIT_ULL(MTK_CLK_ETH2PLL)) 802 #define MT7621_CLKS_BITMAP (0) 803 #define MT7628_CLKS_BITMAP (0) 804 #define MT7629_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ 805 BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \ 806 BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_FE) | \ 807 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ 808 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ 809 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ 810 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ 811 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ 812 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ 813 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ 814 BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \ 815 BIT_ULL(MTK_CLK_SGMII_CK) | \ 816 BIT_ULL(MTK_CLK_ETH2PLL) | BIT_ULL(MTK_CLK_SGMIITOP)) 817 #define MT7981_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \ 818 BIT_ULL(MTK_CLK_GP1) | \ 819 BIT_ULL(MTK_CLK_WOCPU0) | \ 820 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ 821 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ 822 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ 823 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ 824 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ 825 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ 826 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ 827 BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \ 828 BIT_ULL(MTK_CLK_SGMII_CK)) 829 #define MT7986_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \ 830 BIT_ULL(MTK_CLK_GP1) | \ 831 BIT_ULL(MTK_CLK_WOCPU1) | BIT_ULL(MTK_CLK_WOCPU0) | \ 832 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ 833 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ 834 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ 835 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ 836 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ 837 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ 838 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ 839 BIT_ULL(MTK_CLK_SGMII2_CDR_FB)) 840 #define MT7988_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_ESW) | \ 841 BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \ 842 BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \ 843 BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \ 844 BIT_ULL(MTK_CLK_CRYPTO) | \ 845 BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \ 846 BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \ 847 BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \ 848 BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \ 849 BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \ 850 BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \ 851 BIT_ULL(MTK_CLK_TOP_ETH_SYS_SEL) | \ 852 BIT_ULL(MTK_CLK_TOP_ETH_XGMII_SEL) | \ 853 BIT_ULL(MTK_CLK_TOP_ETH_MII_SEL) | \ 854 BIT_ULL(MTK_CLK_TOP_NETSYS_SEL) | \ 855 BIT_ULL(MTK_CLK_TOP_NETSYS_500M_SEL) | \ 856 BIT_ULL(MTK_CLK_TOP_NETSYS_PAO_2X_SEL) | \ 857 BIT_ULL(MTK_CLK_TOP_NETSYS_SYNC_250M_SEL) | \ 858 BIT_ULL(MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL) | \ 859 BIT_ULL(MTK_CLK_TOP_NETSYS_WARP_SEL)) 860 861 enum mtk_dev_state { 862 MTK_HW_INIT, 863 MTK_RESETTING 864 }; 865 866 /* PSE Port Definition */ 867 enum mtk_pse_port { 868 PSE_ADMA_PORT = 0, 869 PSE_GDM1_PORT, 870 PSE_GDM2_PORT, 871 PSE_PPE0_PORT, 872 PSE_PPE1_PORT, 873 PSE_QDMA_TX_PORT, 874 PSE_QDMA_RX_PORT, 875 PSE_DROP_PORT, 876 PSE_WDMA0_PORT, 877 PSE_WDMA1_PORT, 878 PSE_TDMA_PORT, 879 PSE_NONE_PORT, 880 PSE_PPE2_PORT, 881 PSE_WDMA2_PORT, 882 PSE_EIP197_PORT, 883 PSE_GDM3_PORT, 884 PSE_PORT_MAX 885 }; 886 887 /* GMAC Identifier */ 888 enum mtk_gmac_id { 889 MTK_GMAC1_ID = 0, 890 MTK_GMAC2_ID, 891 MTK_GMAC3_ID, 892 MTK_GMAC_ID_MAX 893 }; 894 895 enum mtk_tx_buf_type { 896 MTK_TYPE_SKB, 897 MTK_TYPE_XDP_TX, 898 MTK_TYPE_XDP_NDO, 899 }; 900 901 /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 902 * by the TX descriptor s 903 * @skb: The SKB pointer of the packet being sent 904 * @dma_addr0: The base addr of the first segment 905 * @dma_len0: The length of the first segment 906 * @dma_addr1: The base addr of the second segment 907 * @dma_len1: The length of the second segment 908 */ 909 struct mtk_tx_buf { 910 enum mtk_tx_buf_type type; 911 void *data; 912 913 u16 mac_id; 914 u16 flags; 915 DEFINE_DMA_UNMAP_ADDR(dma_addr0); 916 DEFINE_DMA_UNMAP_LEN(dma_len0); 917 DEFINE_DMA_UNMAP_ADDR(dma_addr1); 918 DEFINE_DMA_UNMAP_LEN(dma_len1); 919 }; 920 921 /* struct mtk_tx_ring - This struct holds info describing a TX ring 922 * @dma: The descriptor ring 923 * @buf: The memory pointed at by the ring 924 * @phys: The physical addr of tx_buf 925 * @next_free: Pointer to the next free descriptor 926 * @last_free: Pointer to the last free descriptor 927 * @last_free_ptr: Hardware pointer value of the last free descriptor 928 * @thresh: The threshold of minimum amount of free descriptors 929 * @free_count: QDMA uses a linked list. Track how many free descriptors 930 * are present 931 */ 932 struct mtk_tx_ring { 933 void *dma; 934 struct mtk_tx_buf *buf; 935 dma_addr_t phys; 936 struct mtk_tx_dma *next_free; 937 struct mtk_tx_dma *last_free; 938 u32 last_free_ptr; 939 u16 thresh; 940 atomic_t free_count; 941 int dma_size; 942 struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */ 943 dma_addr_t phys_pdma; 944 int cpu_idx; 945 }; 946 947 /* PDMA rx ring mode */ 948 enum mtk_rx_flags { 949 MTK_RX_FLAGS_NORMAL = 0, 950 MTK_RX_FLAGS_HWLRO, 951 MTK_RX_FLAGS_QDMA, 952 }; 953 954 /* struct mtk_rx_ring - This struct holds info describing a RX ring 955 * @dma: The descriptor ring 956 * @data: The memory pointed at by the ring 957 * @phys: The physical addr of rx_buf 958 * @frag_size: How big can each fragment be 959 * @buf_size: The size of each packet buffer 960 * @calc_idx: The current head of ring 961 */ 962 struct mtk_rx_ring { 963 void *dma; 964 u8 **data; 965 dma_addr_t phys; 966 u16 frag_size; 967 u16 buf_size; 968 u16 dma_size; 969 bool calc_idx_update; 970 u16 calc_idx; 971 u32 crx_idx_reg; 972 /* page_pool */ 973 struct page_pool *page_pool; 974 struct xdp_rxq_info xdp_q; 975 }; 976 977 enum mkt_eth_capabilities { 978 MTK_RGMII_BIT = 0, 979 MTK_TRGMII_BIT, 980 MTK_SGMII_BIT, 981 MTK_2P5GPHY_BIT, 982 MTK_ESW_BIT, 983 MTK_GEPHY_BIT, 984 MTK_MUX_BIT, 985 MTK_INFRA_BIT, 986 MTK_SHARED_SGMII_BIT, 987 MTK_HWLRO_BIT, 988 MTK_SHARED_INT_BIT, 989 MTK_TRGMII_MT7621_CLK_BIT, 990 MTK_QDMA_BIT, 991 MTK_SOC_MT7628_BIT, 992 MTK_RSTCTRL_PPE1_BIT, 993 MTK_RSTCTRL_PPE2_BIT, 994 MTK_U3_COPHY_V2_BIT, 995 MTK_SRAM_BIT, 996 MTK_36BIT_DMA_BIT, 997 MTK_GMAC_EEE_BIT, 998 999 /* MUX BITS*/ 1000 MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, 1001 MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, 1002 MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, 1003 MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT, 1004 MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, 1005 MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, 1006 1007 /* PATH BITS */ 1008 MTK_ETH_PATH_GMAC1_RGMII_BIT, 1009 MTK_ETH_PATH_GMAC1_TRGMII_BIT, 1010 MTK_ETH_PATH_GMAC1_SGMII_BIT, 1011 MTK_ETH_PATH_GMAC2_RGMII_BIT, 1012 MTK_ETH_PATH_GMAC2_SGMII_BIT, 1013 MTK_ETH_PATH_GMAC2_2P5GPHY_BIT, 1014 MTK_ETH_PATH_GMAC2_GEPHY_BIT, 1015 MTK_ETH_PATH_GDM1_ESW_BIT, 1016 }; 1017 1018 /* Supported hardware group on SoCs */ 1019 #define MTK_RGMII BIT_ULL(MTK_RGMII_BIT) 1020 #define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT) 1021 #define MTK_SGMII BIT_ULL(MTK_SGMII_BIT) 1022 #define MTK_2P5GPHY BIT_ULL(MTK_2P5GPHY_BIT) 1023 #define MTK_ESW BIT_ULL(MTK_ESW_BIT) 1024 #define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT) 1025 #define MTK_MUX BIT_ULL(MTK_MUX_BIT) 1026 #define MTK_INFRA BIT_ULL(MTK_INFRA_BIT) 1027 #define MTK_SHARED_SGMII BIT_ULL(MTK_SHARED_SGMII_BIT) 1028 #define MTK_HWLRO BIT_ULL(MTK_HWLRO_BIT) 1029 #define MTK_SHARED_INT BIT_ULL(MTK_SHARED_INT_BIT) 1030 #define MTK_TRGMII_MT7621_CLK BIT_ULL(MTK_TRGMII_MT7621_CLK_BIT) 1031 #define MTK_QDMA BIT_ULL(MTK_QDMA_BIT) 1032 #define MTK_SOC_MT7628 BIT_ULL(MTK_SOC_MT7628_BIT) 1033 #define MTK_RSTCTRL_PPE1 BIT_ULL(MTK_RSTCTRL_PPE1_BIT) 1034 #define MTK_RSTCTRL_PPE2 BIT_ULL(MTK_RSTCTRL_PPE2_BIT) 1035 #define MTK_U3_COPHY_V2 BIT_ULL(MTK_U3_COPHY_V2_BIT) 1036 #define MTK_SRAM BIT_ULL(MTK_SRAM_BIT) 1037 #define MTK_36BIT_DMA BIT_ULL(MTK_36BIT_DMA_BIT) 1038 #define MTK_GMAC_EEE BIT_ULL(MTK_GMAC_EEE_BIT) 1039 1040 #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ 1041 BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) 1042 #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ 1043 BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) 1044 #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ 1045 BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) 1046 #define MTK_ETH_MUX_GMAC2_TO_2P5GPHY \ 1047 BIT_ULL(MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT) 1048 #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 1049 BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) 1050 #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ 1051 BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) 1052 1053 /* Supported path present on SoCs */ 1054 #define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT) 1055 #define MTK_ETH_PATH_GMAC1_TRGMII BIT_ULL(MTK_ETH_PATH_GMAC1_TRGMII_BIT) 1056 #define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT) 1057 #define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT) 1058 #define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT) 1059 #define MTK_ETH_PATH_GMAC2_2P5GPHY BIT_ULL(MTK_ETH_PATH_GMAC2_2P5GPHY_BIT) 1060 #define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT) 1061 #define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT) 1062 1063 #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) 1064 #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) 1065 #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII) 1066 #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) 1067 #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) 1068 #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) 1069 #define MTK_GMAC2_2P5GPHY (MTK_ETH_PATH_GMAC2_2P5GPHY | MTK_2P5GPHY) 1070 #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) 1071 1072 /* MUXes present on SoCs */ 1073 /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ 1074 #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX) 1075 1076 /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */ 1077 #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ 1078 (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA) 1079 1080 /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ 1081 #define MTK_MUX_U3_GMAC2_TO_QPHY \ 1082 (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA) 1083 1084 /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ 1085 #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 1086 (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ 1087 MTK_SHARED_SGMII) 1088 1089 /* 2: GMAC2 -> 2P5GPHY */ 1090 #define MTK_MUX_GMAC2_TO_2P5GPHY \ 1091 (MTK_ETH_MUX_GMAC2_TO_2P5GPHY | MTK_MUX | MTK_INFRA) 1092 1093 /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ 1094 #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ 1095 (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) 1096 1097 #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) 1098 1099 #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ 1100 MTK_GMAC2_RGMII | MTK_SHARED_INT | \ 1101 MTK_TRGMII_MT7621_CLK | MTK_QDMA) 1102 1103 #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ 1104 MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ 1105 MTK_MUX_GDM1_TO_GMAC1_ESW | \ 1106 MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) 1107 1108 #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \ 1109 MTK_QDMA) 1110 1111 #define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628) 1112 1113 #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 1114 MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ 1115 MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ 1116 MTK_MUX_U3_GMAC2_TO_QPHY | \ 1117 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) 1118 1119 #define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 1120 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ 1121 MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \ 1122 MTK_RSTCTRL_PPE1 | MTK_SRAM | MTK_GMAC_EEE) 1123 1124 #define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ 1125 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ 1126 MTK_RSTCTRL_PPE1 | MTK_SRAM) 1127 1128 #define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_GMAC2_2P5GPHY | \ 1129 MTK_MUX_GMAC2_TO_2P5GPHY | MTK_QDMA | MTK_RSTCTRL_PPE1 | \ 1130 MTK_RSTCTRL_PPE2 | MTK_SRAM) 1131 1132 struct mtk_tx_dma_desc_info { 1133 dma_addr_t addr; 1134 u32 size; 1135 u16 vlan_tci; 1136 u16 qid; 1137 u8 gso:1; 1138 u8 csum:1; 1139 u8 vlan:1; 1140 u8 first:1; 1141 u8 last:1; 1142 }; 1143 1144 struct mtk_reg_map { 1145 u32 tx_irq_mask; 1146 u32 tx_irq_status; 1147 struct { 1148 u32 rx_ptr; /* rx base pointer */ 1149 u32 rx_cnt_cfg; /* rx max count configuration */ 1150 u32 pcrx_ptr; /* rx cpu pointer */ 1151 u32 glo_cfg; /* global configuration */ 1152 u32 rst_idx; /* reset index */ 1153 u32 delay_irq; /* delay interrupt */ 1154 u32 irq_status; /* interrupt status */ 1155 u32 irq_mask; /* interrupt mask */ 1156 u32 adma_rx_dbg0; 1157 u32 int_grp; 1158 } pdma; 1159 struct { 1160 u32 qtx_cfg; /* tx queue configuration */ 1161 u32 qtx_sch; /* tx queue scheduler configuration */ 1162 u32 rx_ptr; /* rx base pointer */ 1163 u32 rx_cnt_cfg; /* rx max count configuration */ 1164 u32 qcrx_ptr; /* rx cpu pointer */ 1165 u32 glo_cfg; /* global configuration */ 1166 u32 rst_idx; /* reset index */ 1167 u32 delay_irq; /* delay interrupt */ 1168 u32 fc_th; /* flow control */ 1169 u32 int_grp; 1170 u32 hred; /* interrupt mask */ 1171 u32 ctx_ptr; /* tx acquire cpu pointer */ 1172 u32 dtx_ptr; /* tx acquire dma pointer */ 1173 u32 crx_ptr; /* tx release cpu pointer */ 1174 u32 drx_ptr; /* tx release dma pointer */ 1175 u32 fq_head; /* fq head pointer */ 1176 u32 fq_tail; /* fq tail pointer */ 1177 u32 fq_count; /* fq free page count */ 1178 u32 fq_blen; /* fq free page buffer length */ 1179 u32 tx_sch_rate; /* tx scheduler rate control registers */ 1180 } qdma; 1181 u32 gdm1_cnt; 1182 u32 gdma_to_ppe[3]; 1183 u32 ppe_base; 1184 u32 wdma_base[3]; 1185 u32 pse_iq_sta; 1186 u32 pse_oq_sta; 1187 }; 1188 1189 /* struct mtk_eth_data - This is the structure holding all differences 1190 * among various platforms 1191 * @reg_map Soc register map. 1192 * @ana_rgc3: The offset for register ANA_RGC3 related to 1193 * sgmiisys syscon 1194 * @caps Flags shown the extra capability for the SoC 1195 * @hw_features Flags shown HW features 1196 * @required_clks Flags shown the bitmap for required clocks on 1197 * the target SoC 1198 * @required_pctl A bool value to show whether the SoC requires 1199 * the extra setup for those pins used by GMAC. 1200 * @hash_offset Flow table hash offset. 1201 * @version SoC version. 1202 * @foe_entry_size Foe table entry size. 1203 * @has_accounting Bool indicating support for accounting of 1204 * offloaded flows. 1205 * @desc_size Tx/Rx DMA descriptor size. 1206 * @irq_done_mask Rx irq done register mask. 1207 * @dma_l4_valid Rx DMA valid register mask. 1208 * @dma_max_len Max DMA tx/rx buffer length. 1209 * @dma_len_offset Tx/Rx DMA length field offset. 1210 */ 1211 struct mtk_soc_data { 1212 const struct mtk_reg_map *reg_map; 1213 u32 ana_rgc3; 1214 u64 caps; 1215 u64 required_clks; 1216 bool required_pctl; 1217 u8 offload_version; 1218 u8 hash_offset; 1219 u8 version; 1220 u8 ppe_num; 1221 u16 foe_entry_size; 1222 netdev_features_t hw_features; 1223 bool has_accounting; 1224 bool disable_pll_modes; 1225 struct { 1226 u32 desc_size; 1227 u32 dma_max_len; 1228 u32 dma_len_offset; 1229 u32 dma_size; 1230 u32 fq_dma_size; 1231 } tx; 1232 struct { 1233 u32 desc_size; 1234 u32 irq_done_mask; 1235 u32 dma_l4_valid; 1236 u32 dma_max_len; 1237 u32 dma_len_offset; 1238 u32 dma_size; 1239 } rx; 1240 }; 1241 1242 #define MTK_DMA_MONITOR_TIMEOUT msecs_to_jiffies(1000) 1243 1244 /* currently no SoC has more than 3 macs */ 1245 #define MTK_MAX_DEVS 3 1246 1247 /* struct mtk_eth - This is the main datasructure for holding the state 1248 * of the driver 1249 * @dev: The device pointer 1250 * @dma_dev: The device pointer used for dma mapping/alloc 1251 * @base: The mapped register i/o base 1252 * @sram_pool: Pointer to SRAM pool used for DMA descriptor rings 1253 * @page_lock: Make sure that register operations are atomic 1254 * @tx_irq__lock: Make sure that IRQ register operations are atomic 1255 * @rx_irq__lock: Make sure that IRQ register operations are atomic 1256 * @dim_lock: Make sure that Net DIM operations are atomic 1257 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 1258 * dummy for NAPI to work 1259 * @netdev: The netdev instances 1260 * @mac: Each netdev is linked to a physical MAC 1261 * @irq: The IRQ that we are using 1262 * @msg_enable: Ethtool msg level 1263 * @ethsys: The register map pointing at the range used to setup 1264 * MII modes 1265 * @infra: The register map pointing at the range used to setup 1266 * SGMII and GePHY path 1267 * @sgmii_pcs: Pointers to mtk-pcs-lynxi phylink_pcs instances 1268 * @pctl: The register map pointing at the range used to setup 1269 * GMAC port drive/slew values 1270 * @dma_refcnt: track how many netdevs are using the DMA engine 1271 * @tx_ring: Pointer to the memory holding info about the TX ring 1272 * @rx_ring: Pointer to the memory holding info about the RX ring 1273 * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring 1274 * @tx_napi: The TX NAPI struct 1275 * @rx_napi: The RX NAPI struct 1276 * @rx_events: Net DIM RX event counter 1277 * @rx_packets: Net DIM RX packet counter 1278 * @rx_bytes: Net DIM RX byte counter 1279 * @rx_dim: Net DIM RX context 1280 * @tx_events: Net DIM TX event counter 1281 * @tx_packets: Net DIM TX packet counter 1282 * @tx_bytes: Net DIM TX byte counter 1283 * @tx_dim: Net DIM TX context 1284 * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 1285 * @phy_scratch_ring: physical address of scratch_ring 1286 * @scratch_head: The scratch memory that scratch_ring points to. 1287 * @clks: clock array for all clocks required 1288 * @mii_bus: If there is a bus we need to create an instance for it 1289 * @pending_work: The workqueue used to reset the dma ring 1290 * @state: Initialization and runtime state of the device 1291 * @soc: Holding specific data among various SoCs 1292 */ 1293 1294 struct mtk_eth { 1295 struct device *dev; 1296 struct device *dma_dev; 1297 void __iomem *base; 1298 struct gen_pool *sram_pool; 1299 spinlock_t page_lock; 1300 spinlock_t tx_irq_lock; 1301 spinlock_t rx_irq_lock; 1302 struct net_device *dummy_dev; 1303 struct net_device *netdev[MTK_MAX_DEVS]; 1304 struct mtk_mac *mac[MTK_MAX_DEVS]; 1305 int irq[MTK_FE_IRQ_NUM]; 1306 u32 msg_enable; 1307 unsigned long sysclk; 1308 struct regmap *ethsys; 1309 struct regmap *infra; 1310 struct phylink_pcs *sgmii_pcs[MTK_MAX_DEVS]; 1311 struct regmap *pctl; 1312 bool hwlro; 1313 refcount_t dma_refcnt; 1314 struct mtk_tx_ring tx_ring; 1315 struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 1316 struct mtk_rx_ring rx_ring_qdma; 1317 struct napi_struct tx_napi; 1318 struct napi_struct rx_napi; 1319 void *scratch_ring; 1320 dma_addr_t phy_scratch_ring; 1321 void *scratch_head[MTK_FQ_DMA_HEAD]; 1322 struct clk *clks[MTK_CLK_MAX]; 1323 1324 struct mii_bus *mii_bus; 1325 unsigned int mdc_divider; 1326 struct work_struct pending_work; 1327 unsigned long state; 1328 1329 const struct mtk_soc_data *soc; 1330 1331 spinlock_t dim_lock; 1332 1333 u32 rx_events; 1334 u32 rx_packets; 1335 u32 rx_bytes; 1336 struct dim rx_dim; 1337 1338 u32 tx_events; 1339 u32 tx_packets; 1340 u32 tx_bytes; 1341 struct dim tx_dim; 1342 1343 int ip_align; 1344 1345 struct metadata_dst *dsa_meta[MTK_MAX_DSA_PORTS]; 1346 1347 struct mtk_ppe *ppe[3]; 1348 struct rhashtable flow_table; 1349 1350 struct bpf_prog __rcu *prog; 1351 1352 struct { 1353 struct delayed_work monitor_work; 1354 u32 wdidx; 1355 u8 wdma_hang_count; 1356 u8 qdma_hang_count; 1357 u8 adma_hang_count; 1358 } reset; 1359 }; 1360 1361 /* struct mtk_mac - the structure that holds the info about the MACs of the 1362 * SoC 1363 * @id: The number of the MAC 1364 * @interface: Interface mode kept for detecting change in hw settings 1365 * @of_node: Our devicetree node 1366 * @hw: Backpointer to our main datastruture 1367 * @hw_stats: Packet statistics counter 1368 */ 1369 struct mtk_mac { 1370 int id; 1371 phy_interface_t interface; 1372 u8 ppe_idx; 1373 int speed; 1374 struct device_node *of_node; 1375 struct phylink *phylink; 1376 struct phylink_config phylink_config; 1377 struct mtk_eth *hw; 1378 struct mtk_hw_stats *hw_stats; 1379 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 1380 int hwlro_ip_cnt; 1381 unsigned int syscfg0; 1382 struct notifier_block device_notifier; 1383 }; 1384 1385 /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 1386 extern const struct of_device_id of_mtk_match[]; 1387 1388 static inline bool mtk_is_netsys_v1(struct mtk_eth *eth) 1389 { 1390 return eth->soc->version == 1; 1391 } 1392 1393 static inline bool mtk_is_netsys_v2_or_greater(struct mtk_eth *eth) 1394 { 1395 return eth->soc->version > 1; 1396 } 1397 1398 static inline bool mtk_is_netsys_v3_or_greater(struct mtk_eth *eth) 1399 { 1400 return eth->soc->version > 2; 1401 } 1402 1403 static inline struct mtk_foe_entry * 1404 mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash) 1405 { 1406 const struct mtk_soc_data *soc = ppe->eth->soc; 1407 1408 return ppe->foe_table + hash * soc->foe_entry_size; 1409 } 1410 1411 static inline u32 mtk_get_ib1_ts_mask(struct mtk_eth *eth) 1412 { 1413 if (mtk_is_netsys_v2_or_greater(eth)) 1414 return MTK_FOE_IB1_BIND_TIMESTAMP_V2; 1415 1416 return MTK_FOE_IB1_BIND_TIMESTAMP; 1417 } 1418 1419 static inline u32 mtk_get_ib1_ppoe_mask(struct mtk_eth *eth) 1420 { 1421 if (mtk_is_netsys_v2_or_greater(eth)) 1422 return MTK_FOE_IB1_BIND_PPPOE_V2; 1423 1424 return MTK_FOE_IB1_BIND_PPPOE; 1425 } 1426 1427 static inline u32 mtk_get_ib1_vlan_tag_mask(struct mtk_eth *eth) 1428 { 1429 if (mtk_is_netsys_v2_or_greater(eth)) 1430 return MTK_FOE_IB1_BIND_VLAN_TAG_V2; 1431 1432 return MTK_FOE_IB1_BIND_VLAN_TAG; 1433 } 1434 1435 static inline u32 mtk_get_ib1_vlan_layer_mask(struct mtk_eth *eth) 1436 { 1437 if (mtk_is_netsys_v2_or_greater(eth)) 1438 return MTK_FOE_IB1_BIND_VLAN_LAYER_V2; 1439 1440 return MTK_FOE_IB1_BIND_VLAN_LAYER; 1441 } 1442 1443 static inline u32 mtk_prep_ib1_vlan_layer(struct mtk_eth *eth, u32 val) 1444 { 1445 if (mtk_is_netsys_v2_or_greater(eth)) 1446 return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val); 1447 1448 return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, val); 1449 } 1450 1451 static inline u32 mtk_get_ib1_vlan_layer(struct mtk_eth *eth, u32 val) 1452 { 1453 if (mtk_is_netsys_v2_or_greater(eth)) 1454 return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val); 1455 1456 return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER, val); 1457 } 1458 1459 static inline u32 mtk_get_ib1_pkt_type_mask(struct mtk_eth *eth) 1460 { 1461 if (mtk_is_netsys_v2_or_greater(eth)) 1462 return MTK_FOE_IB1_PACKET_TYPE_V2; 1463 1464 return MTK_FOE_IB1_PACKET_TYPE; 1465 } 1466 1467 static inline u32 mtk_get_ib1_pkt_type(struct mtk_eth *eth, u32 val) 1468 { 1469 if (mtk_is_netsys_v2_or_greater(eth)) 1470 return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE_V2, val); 1471 1472 return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, val); 1473 } 1474 1475 static inline u32 mtk_get_ib2_multicast_mask(struct mtk_eth *eth) 1476 { 1477 if (mtk_is_netsys_v2_or_greater(eth)) 1478 return MTK_FOE_IB2_MULTICAST_V2; 1479 1480 return MTK_FOE_IB2_MULTICAST; 1481 } 1482 1483 static inline bool mtk_interface_mode_is_xgmii(struct mtk_eth *eth, 1484 phy_interface_t interface) 1485 { 1486 if (!mtk_is_netsys_v3_or_greater(eth)) 1487 return false; 1488 1489 switch (interface) { 1490 case PHY_INTERFACE_MODE_INTERNAL: 1491 case PHY_INTERFACE_MODE_USXGMII: 1492 case PHY_INTERFACE_MODE_10GBASER: 1493 case PHY_INTERFACE_MODE_5GBASER: 1494 return true; 1495 default: 1496 return false; 1497 } 1498 } 1499 1500 /* read the hardware status register */ 1501 void mtk_stats_update_mac(struct mtk_mac *mac); 1502 1503 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 1504 u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 1505 u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg); 1506 1507 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); 1508 int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id); 1509 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); 1510 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); 1511 1512 int mtk_eth_offload_init(struct mtk_eth *eth, u8 id); 1513 int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, 1514 void *type_data); 1515 int mtk_flow_offload_cmd(struct mtk_eth *eth, struct flow_cls_offload *cls, 1516 int ppe_index); 1517 void mtk_flow_offload_cleanup(struct mtk_eth *eth, struct list_head *list); 1518 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev); 1519 1520 1521 #endif /* MTK_ETH_H */ 1522