1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * TI SN65DSI83,84,85 driver 4 * 5 * Currently supported: 6 * - SN65DSI83 7 * = 1x Single-link DSI ~ 1x Single-link LVDS 8 * - Supported 9 * - Single-link LVDS mode tested 10 * - SN65DSI84 11 * = 1x Single-link DSI ~ 2x Single-link or 1x Dual-link LVDS 12 * - Supported 13 * - Dual-link LVDS mode tested 14 * - 2x Single-link LVDS mode unsupported 15 * (should be easy to add by someone who has the HW) 16 * - SN65DSI85 17 * = 2x Single-link or 1x Dual-link DSI ~ 2x Single-link or 1x Dual-link LVDS 18 * - Unsupported 19 * (should be easy to add by someone who has the HW) 20 * 21 * Copyright (C) 2021 Marek Vasut <marex@denx.de> 22 * 23 * Based on previous work of: 24 * Valentin Raevsky <valentin@compulab.co.il> 25 * Philippe Schenker <philippe.schenker@toradex.com> 26 */ 27 28 #include <linux/bits.h> 29 #include <linux/clk.h> 30 #include <linux/gpio/consumer.h> 31 #include <linux/i2c.h> 32 #include <linux/media-bus-format.h> 33 #include <linux/module.h> 34 #include <linux/of.h> 35 #include <linux/of_graph.h> 36 #include <linux/regmap.h> 37 #include <linux/regulator/consumer.h> 38 #include <linux/timer.h> 39 #include <linux/workqueue.h> 40 41 #include <drm/drm_atomic_helper.h> 42 #include <drm/drm_bridge.h> 43 #include <drm/drm_bridge_helper.h> 44 #include <drm/drm_mipi_dsi.h> 45 #include <drm/drm_of.h> 46 #include <drm/drm_print.h> 47 #include <drm/drm_probe_helper.h> 48 49 /* ID registers */ 50 #define REG_ID(n) (0x00 + (n)) 51 /* Reset and clock registers */ 52 #define REG_RC_RESET 0x09 53 #define REG_RC_RESET_SOFT_RESET BIT(0) 54 #define REG_RC_LVDS_PLL 0x0a 55 #define REG_RC_LVDS_PLL_PLL_EN_STAT BIT(7) 56 #define REG_RC_LVDS_PLL_LVDS_CLK_RANGE(n) (((n) & 0x7) << 1) 57 #define REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY BIT(0) 58 #define REG_RC_DSI_CLK 0x0b 59 #define REG_RC_DSI_CLK_DSI_CLK_DIVIDER(n) (((n) & 0x1f) << 3) 60 #define REG_RC_DSI_CLK_REFCLK_MULTIPLIER(n) ((n) & 0x3) 61 #define REG_RC_PLL_EN 0x0d 62 #define REG_RC_PLL_EN_PLL_EN BIT(0) 63 /* DSI registers */ 64 #define REG_DSI_LANE 0x10 65 #define REG_DSI_LANE_LEFT_RIGHT_PIXELS BIT(7) /* DSI85-only */ 66 #define REG_DSI_LANE_DSI_CHANNEL_MODE_DUAL 0 /* DSI85-only */ 67 #define REG_DSI_LANE_DSI_CHANNEL_MODE_2SINGLE BIT(6) /* DSI85-only */ 68 #define REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE BIT(5) 69 #define REG_DSI_LANE_CHA_DSI_LANES(n) (((n) & 0x3) << 3) 70 #define REG_DSI_LANE_CHB_DSI_LANES(n) (((n) & 0x3) << 1) 71 #define REG_DSI_LANE_SOT_ERR_TOL_DIS BIT(0) 72 #define REG_DSI_EQ 0x11 73 #define REG_DSI_EQ_CHA_DSI_DATA_EQ(n) (((n) & 0x3) << 6) 74 #define REG_DSI_EQ_CHA_DSI_CLK_EQ(n) (((n) & 0x3) << 2) 75 #define REG_DSI_CLK 0x12 76 #define REG_DSI_CLK_CHA_DSI_CLK_RANGE(n) ((n) & 0xff) 77 /* LVDS registers */ 78 #define REG_LVDS_FMT 0x18 79 #define REG_LVDS_FMT_DE_NEG_POLARITY BIT(7) 80 #define REG_LVDS_FMT_HS_NEG_POLARITY BIT(6) 81 #define REG_LVDS_FMT_VS_NEG_POLARITY BIT(5) 82 #define REG_LVDS_FMT_LVDS_LINK_CFG BIT(4) /* 0:AB 1:A-only */ 83 #define REG_LVDS_FMT_CHA_24BPP_MODE BIT(3) 84 #define REG_LVDS_FMT_CHB_24BPP_MODE BIT(2) 85 #define REG_LVDS_FMT_CHA_24BPP_FORMAT1 BIT(1) 86 #define REG_LVDS_FMT_CHB_24BPP_FORMAT1 BIT(0) 87 #define REG_LVDS_VCOM 0x19 88 #define REG_LVDS_VCOM_CHA_LVDS_VOCM BIT(6) 89 #define REG_LVDS_VCOM_CHB_LVDS_VOCM BIT(4) 90 #define REG_LVDS_VCOM_CHA_LVDS_VOD_SWING(n) (((n) & 0x3) << 2) 91 #define REG_LVDS_VCOM_CHB_LVDS_VOD_SWING(n) ((n) & 0x3) 92 #define REG_LVDS_LANE 0x1a 93 #define REG_LVDS_LANE_EVEN_ODD_SWAP BIT(6) 94 #define REG_LVDS_LANE_CHA_REVERSE_LVDS BIT(5) 95 #define REG_LVDS_LANE_CHB_REVERSE_LVDS BIT(4) 96 #define REG_LVDS_LANE_CHA_LVDS_TERM BIT(1) 97 #define REG_LVDS_LANE_CHB_LVDS_TERM BIT(0) 98 #define REG_LVDS_CM 0x1b 99 #define REG_LVDS_CM_CHA_LVDS_CM_ADJUST(n) (((n) & 0x3) << 4) 100 #define REG_LVDS_CM_CHB_LVDS_CM_ADJUST(n) ((n) & 0x3) 101 /* Video registers */ 102 #define REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW 0x20 103 #define REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH 0x21 104 #define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW 0x24 105 #define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH 0x25 106 #define REG_VID_CHA_SYNC_DELAY_LOW 0x28 107 #define REG_VID_CHA_SYNC_DELAY_HIGH 0x29 108 #define REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW 0x2c 109 #define REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH 0x2d 110 #define REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW 0x30 111 #define REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH 0x31 112 #define REG_VID_CHA_HORIZONTAL_BACK_PORCH 0x34 113 #define REG_VID_CHA_VERTICAL_BACK_PORCH 0x36 114 #define REG_VID_CHA_HORIZONTAL_FRONT_PORCH 0x38 115 #define REG_VID_CHA_VERTICAL_FRONT_PORCH 0x3a 116 #define REG_VID_CHA_TEST_PATTERN 0x3c 117 #define REG_VID_CHA_TEST_PATTERN_EN BIT(4) 118 /* IRQ registers */ 119 #define REG_IRQ_GLOBAL 0xe0 120 #define REG_IRQ_GLOBAL_IRQ_EN BIT(0) 121 #define REG_IRQ_EN 0xe1 122 #define REG_IRQ_EN_CHA_SYNCH_ERR_EN BIT(7) 123 #define REG_IRQ_EN_CHA_CRC_ERR_EN BIT(6) 124 #define REG_IRQ_EN_CHA_UNC_ECC_ERR_EN BIT(5) 125 #define REG_IRQ_EN_CHA_COR_ECC_ERR_EN BIT(4) 126 #define REG_IRQ_EN_CHA_LLP_ERR_EN BIT(3) 127 #define REG_IRQ_EN_CHA_SOT_BIT_ERR_EN BIT(2) 128 #define REG_IRQ_EN_CHA_PLL_UNLOCK_EN BIT(0) 129 #define REG_IRQ_STAT 0xe5 130 #define REG_IRQ_STAT_CHA_SYNCH_ERR BIT(7) 131 #define REG_IRQ_STAT_CHA_CRC_ERR BIT(6) 132 #define REG_IRQ_STAT_CHA_UNC_ECC_ERR BIT(5) 133 #define REG_IRQ_STAT_CHA_COR_ECC_ERR BIT(4) 134 #define REG_IRQ_STAT_CHA_LLP_ERR BIT(3) 135 #define REG_IRQ_STAT_CHA_SOT_BIT_ERR BIT(2) 136 #define REG_IRQ_STAT_CHA_PLL_UNLOCK BIT(0) 137 138 static bool sn65dsi83_test_pattern; 139 module_param_named(test_pattern, sn65dsi83_test_pattern, bool, 0644); 140 141 enum sn65dsi83_channel { 142 CHANNEL_A, 143 CHANNEL_B 144 }; 145 146 enum sn65dsi83_lvds_term { 147 OHM_100, 148 OHM_200 149 }; 150 151 enum sn65dsi83_model { 152 MODEL_SN65DSI83, 153 MODEL_SN65DSI84, 154 }; 155 156 struct sn65dsi83 { 157 struct drm_bridge bridge; 158 struct device *dev; 159 struct regmap *regmap; 160 struct mipi_dsi_device *dsi; 161 struct drm_bridge *panel_bridge; 162 struct gpio_desc *enable_gpio; 163 struct regulator *vcc; 164 bool lvds_dual_link; 165 bool lvds_dual_link_even_odd_swap; 166 int lvds_vod_swing_conf[2]; 167 int lvds_term_conf[2]; 168 int irq; 169 struct delayed_work monitor_work; 170 struct work_struct reset_work; 171 }; 172 173 static const struct regmap_range sn65dsi83_readable_ranges[] = { 174 regmap_reg_range(REG_ID(0), REG_ID(8)), 175 regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_DSI_CLK), 176 regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN), 177 regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK), 178 regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM), 179 regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, 180 REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH), 181 regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, 182 REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH), 183 regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW, 184 REG_VID_CHA_SYNC_DELAY_HIGH), 185 regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, 186 REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH), 187 regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, 188 REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH), 189 regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH, 190 REG_VID_CHA_HORIZONTAL_BACK_PORCH), 191 regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH, 192 REG_VID_CHA_VERTICAL_BACK_PORCH), 193 regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH, 194 REG_VID_CHA_HORIZONTAL_FRONT_PORCH), 195 regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH, 196 REG_VID_CHA_VERTICAL_FRONT_PORCH), 197 regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN), 198 regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN), 199 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT), 200 }; 201 202 static const struct regmap_access_table sn65dsi83_readable_table = { 203 .yes_ranges = sn65dsi83_readable_ranges, 204 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_readable_ranges), 205 }; 206 207 static const struct regmap_range sn65dsi83_writeable_ranges[] = { 208 regmap_reg_range(REG_RC_RESET, REG_RC_DSI_CLK), 209 regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN), 210 regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK), 211 regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM), 212 regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, 213 REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH), 214 regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, 215 REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH), 216 regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW, 217 REG_VID_CHA_SYNC_DELAY_HIGH), 218 regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, 219 REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH), 220 regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, 221 REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH), 222 regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH, 223 REG_VID_CHA_HORIZONTAL_BACK_PORCH), 224 regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH, 225 REG_VID_CHA_VERTICAL_BACK_PORCH), 226 regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH, 227 REG_VID_CHA_HORIZONTAL_FRONT_PORCH), 228 regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH, 229 REG_VID_CHA_VERTICAL_FRONT_PORCH), 230 regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN), 231 regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN), 232 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT), 233 }; 234 235 static const struct regmap_access_table sn65dsi83_writeable_table = { 236 .yes_ranges = sn65dsi83_writeable_ranges, 237 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_writeable_ranges), 238 }; 239 240 static const struct regmap_range sn65dsi83_volatile_ranges[] = { 241 regmap_reg_range(REG_RC_RESET, REG_RC_RESET), 242 regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_LVDS_PLL), 243 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT), 244 }; 245 246 static const struct regmap_access_table sn65dsi83_volatile_table = { 247 .yes_ranges = sn65dsi83_volatile_ranges, 248 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_volatile_ranges), 249 }; 250 251 static const struct regmap_config sn65dsi83_regmap_config = { 252 .reg_bits = 8, 253 .val_bits = 8, 254 .rd_table = &sn65dsi83_readable_table, 255 .wr_table = &sn65dsi83_writeable_table, 256 .volatile_table = &sn65dsi83_volatile_table, 257 .cache_type = REGCACHE_MAPLE, 258 .max_register = REG_IRQ_STAT, 259 }; 260 261 static const int lvds_vod_swing_data_table[2][4][2] = { 262 { /* 100 Ohm */ 263 { 180000, 313000 }, 264 { 215000, 372000 }, 265 { 250000, 430000 }, 266 { 290000, 488000 }, 267 }, 268 { /* 200 Ohm */ 269 { 150000, 261000 }, 270 { 200000, 346000 }, 271 { 250000, 428000 }, 272 { 300000, 511000 }, 273 }, 274 }; 275 276 static const int lvds_vod_swing_clock_table[2][4][2] = { 277 { /* 100 Ohm */ 278 { 140000, 244000 }, 279 { 168000, 290000 }, 280 { 195000, 335000 }, 281 { 226000, 381000 }, 282 }, 283 { /* 200 Ohm */ 284 { 117000, 204000 }, 285 { 156000, 270000 }, 286 { 195000, 334000 }, 287 { 234000, 399000 }, 288 }, 289 }; 290 291 static struct sn65dsi83 *bridge_to_sn65dsi83(struct drm_bridge *bridge) 292 { 293 return container_of(bridge, struct sn65dsi83, bridge); 294 } 295 296 static int sn65dsi83_attach(struct drm_bridge *bridge, 297 struct drm_encoder *encoder, 298 enum drm_bridge_attach_flags flags) 299 { 300 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 301 302 return drm_bridge_attach(encoder, ctx->panel_bridge, 303 &ctx->bridge, flags); 304 } 305 306 static void sn65dsi83_detach(struct drm_bridge *bridge) 307 { 308 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 309 310 if (!ctx->dsi) 311 return; 312 313 ctx->dsi = NULL; 314 } 315 316 static u8 sn65dsi83_get_lvds_range(struct sn65dsi83 *ctx, 317 const struct drm_display_mode *mode) 318 { 319 /* 320 * The encoding of the LVDS_CLK_RANGE is as follows: 321 * 000 - 25 MHz <= LVDS_CLK < 37.5 MHz 322 * 001 - 37.5 MHz <= LVDS_CLK < 62.5 MHz 323 * 010 - 62.5 MHz <= LVDS_CLK < 87.5 MHz 324 * 011 - 87.5 MHz <= LVDS_CLK < 112.5 MHz 325 * 100 - 112.5 MHz <= LVDS_CLK < 137.5 MHz 326 * 101 - 137.5 MHz <= LVDS_CLK <= 154 MHz 327 * which is a range of 12.5MHz..162.5MHz in 50MHz steps, except that 328 * the ends of the ranges are clamped to the supported range. Since 329 * sn65dsi83_mode_valid() already filters the valid modes and limits 330 * the clock to 25..154 MHz, the range calculation can be simplified 331 * as follows: 332 */ 333 int mode_clock = mode->clock; 334 335 if (ctx->lvds_dual_link) 336 mode_clock /= 2; 337 338 return (mode_clock - 12500) / 25000; 339 } 340 341 static u8 sn65dsi83_get_dsi_range(struct sn65dsi83 *ctx, 342 const struct drm_display_mode *mode) 343 { 344 /* 345 * The encoding of the CHA_DSI_CLK_RANGE is as follows: 346 * 0x00 through 0x07 - Reserved 347 * 0x08 - 40 <= DSI_CLK < 45 MHz 348 * 0x09 - 45 <= DSI_CLK < 50 MHz 349 * ... 350 * 0x63 - 495 <= DSI_CLK < 500 MHz 351 * 0x64 - 500 MHz 352 * 0x65 through 0xFF - Reserved 353 * which is DSI clock in 5 MHz steps, clamped to 40..500 MHz. 354 * The DSI clock are calculated as: 355 * DSI_CLK = mode clock * bpp / dsi_data_lanes / 2 356 * the 2 is there because the bus is DDR. 357 */ 358 return clamp((unsigned int)mode->clock * 359 mipi_dsi_pixel_format_to_bpp(ctx->dsi->format) / 360 ctx->dsi->lanes / 2, 40000U, 500000U) / 5000U; 361 } 362 363 static u8 sn65dsi83_get_dsi_div(struct sn65dsi83 *ctx) 364 { 365 /* The divider is (DSI_CLK / LVDS_CLK) - 1, which really is: */ 366 unsigned int dsi_div = mipi_dsi_pixel_format_to_bpp(ctx->dsi->format); 367 368 dsi_div /= ctx->dsi->lanes; 369 370 if (!ctx->lvds_dual_link) 371 dsi_div /= 2; 372 373 return dsi_div - 1; 374 } 375 376 static int sn65dsi83_reset_pipe(struct sn65dsi83 *sn65dsi83) 377 { 378 struct drm_modeset_acquire_ctx ctx; 379 int err; 380 381 /* 382 * Reset active outputs of the related CRTC. 383 * 384 * This way, drm core will reconfigure each components in the CRTC 385 * outputs path. In our case, this will force the previous component to 386 * go back in LP11 mode and so allow the reconfiguration of SN65DSI83 387 * bridge. 388 * 389 * Keep the lock during the whole operation to be atomic. 390 */ 391 392 drm_modeset_acquire_init(&ctx, 0); 393 394 dev_warn(sn65dsi83->dev, "reset the pipe\n"); 395 396 retry: 397 err = drm_bridge_helper_reset_crtc(&sn65dsi83->bridge, &ctx); 398 if (err == -EDEADLK) { 399 drm_modeset_backoff(&ctx); 400 goto retry; 401 } 402 403 drm_modeset_drop_locks(&ctx); 404 drm_modeset_acquire_fini(&ctx); 405 406 return 0; 407 } 408 409 static void sn65dsi83_reset_work(struct work_struct *ws) 410 { 411 struct sn65dsi83 *ctx = container_of(ws, struct sn65dsi83, reset_work); 412 int ret; 413 int idx; 414 415 if (!drm_bridge_enter(&ctx->bridge, &idx)) 416 return; 417 418 /* Reset the pipe */ 419 ret = sn65dsi83_reset_pipe(ctx); 420 if (ret) { 421 dev_err(ctx->dev, "reset pipe failed %pe\n", ERR_PTR(ret)); 422 return; 423 } 424 if (ctx->irq) 425 enable_irq(ctx->irq); 426 427 drm_bridge_exit(idx); 428 } 429 430 static void sn65dsi83_handle_errors(struct sn65dsi83 *ctx) 431 { 432 unsigned int irq_stat; 433 int ret; 434 int idx; 435 436 if (!drm_bridge_enter(&ctx->bridge, &idx)) 437 return; 438 439 /* 440 * Schedule a reset in case of: 441 * - the bridge doesn't answer 442 * - the bridge signals an error 443 */ 444 445 ret = regmap_read(ctx->regmap, REG_IRQ_STAT, &irq_stat); 446 447 /* 448 * Some hardware (Toradex Verdin AM62) is known to report the 449 * PLL_UNLOCK error interrupt while working without visible 450 * problems. In lack of a reliable way to discriminate such cases 451 * from user-visible PLL_UNLOCK cases, ignore that bit entirely. 452 */ 453 if (ret || irq_stat & ~REG_IRQ_STAT_CHA_PLL_UNLOCK) { 454 /* 455 * IRQ acknowledged is not always possible (the bridge can be in 456 * a state where it doesn't answer anymore). To prevent an 457 * interrupt storm, disable interrupt. The interrupt will be 458 * after the reset. 459 */ 460 if (ctx->irq) 461 disable_irq_nosync(ctx->irq); 462 463 schedule_work(&ctx->reset_work); 464 } 465 466 drm_bridge_exit(idx); 467 } 468 469 static void sn65dsi83_monitor_work(struct work_struct *work) 470 { 471 struct sn65dsi83 *ctx = container_of(to_delayed_work(work), 472 struct sn65dsi83, monitor_work); 473 474 sn65dsi83_handle_errors(ctx); 475 476 schedule_delayed_work(&ctx->monitor_work, msecs_to_jiffies(1000)); 477 } 478 479 static void sn65dsi83_monitor_start(struct sn65dsi83 *ctx) 480 { 481 schedule_delayed_work(&ctx->monitor_work, msecs_to_jiffies(1000)); 482 } 483 484 static void sn65dsi83_monitor_stop(struct sn65dsi83 *ctx) 485 { 486 cancel_delayed_work_sync(&ctx->monitor_work); 487 } 488 489 /* 490 * Release resources taken by sn65dsi83_atomic_pre_enable(). 491 * 492 * Invoked by sn65dsi83_atomic_disable() normally, or by devres after 493 * sn65dsi83_remove() in case this happens befora atomic_disable. 494 */ 495 static void sn65dsi83_release_resources(void *data) 496 { 497 struct sn65dsi83 *ctx = (struct sn65dsi83 *)data; 498 int ret; 499 500 if (ctx->irq) { 501 /* Disable irq */ 502 regmap_write(ctx->regmap, REG_IRQ_EN, 0x0); 503 regmap_write(ctx->regmap, REG_IRQ_GLOBAL, 0x0); 504 } else { 505 /* Stop the polling task */ 506 sn65dsi83_monitor_stop(ctx); 507 } 508 509 /* Put the chip in reset, pull EN line low, and assure 10ms reset low timing. */ 510 gpiod_set_value_cansleep(ctx->enable_gpio, 0); 511 usleep_range(10000, 11000); 512 513 ret = regulator_disable(ctx->vcc); 514 if (ret) 515 dev_err(ctx->dev, "Failed to disable vcc: %d\n", ret); 516 517 regcache_mark_dirty(ctx->regmap); 518 } 519 520 static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge, 521 struct drm_atomic_commit *state) 522 { 523 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 524 const unsigned int dual_factor = ctx->lvds_dual_link ? 2 : 1; 525 const struct drm_bridge_state *bridge_state; 526 const struct drm_crtc_state *crtc_state; 527 const struct drm_display_mode *mode; 528 struct drm_connector *connector; 529 struct drm_crtc *crtc; 530 bool test_pattern = sn65dsi83_test_pattern; 531 bool lvds_format_24bpp; 532 bool lvds_format_jeida; 533 unsigned int pval; 534 __le16 le16val; 535 u16 val; 536 int ret; 537 int idx; 538 539 if (!drm_bridge_enter(bridge, &idx)) 540 return; 541 542 ret = regulator_enable(ctx->vcc); 543 if (ret) { 544 dev_err(ctx->dev, "Failed to enable vcc: %d\n", ret); 545 goto err_exit; 546 } 547 548 /* Deassert reset */ 549 gpiod_set_value_cansleep(ctx->enable_gpio, 1); 550 usleep_range(10000, 11000); 551 552 /* Get the LVDS format from the bridge state. */ 553 bridge_state = drm_atomic_get_new_bridge_state(state, bridge); 554 555 switch (bridge_state->output_bus_cfg.format) { 556 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 557 lvds_format_24bpp = false; 558 lvds_format_jeida = true; 559 break; 560 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 561 lvds_format_24bpp = true; 562 lvds_format_jeida = true; 563 break; 564 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 565 lvds_format_24bpp = true; 566 lvds_format_jeida = false; 567 break; 568 default: 569 /* 570 * Some bridges still don't set the correct 571 * LVDS bus pixel format, use SPWG24 default 572 * format until those are fixed. 573 */ 574 lvds_format_24bpp = true; 575 lvds_format_jeida = false; 576 dev_warn(ctx->dev, 577 "Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n", 578 bridge_state->output_bus_cfg.format); 579 break; 580 } 581 582 /* 583 * Retrieve the CRTC adjusted mode. This requires a little dance to go 584 * from the bridge to the encoder, to the connector and to the CRTC. 585 */ 586 connector = drm_atomic_get_new_connector_for_encoder(state, 587 bridge->encoder); 588 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; 589 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 590 mode = &crtc_state->adjusted_mode; 591 592 /* Clear reset, disable PLL */ 593 regmap_write(ctx->regmap, REG_RC_RESET, 0x00); 594 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00); 595 596 /* Reference clock derived from DSI link clock. */ 597 regmap_write(ctx->regmap, REG_RC_LVDS_PLL, 598 REG_RC_LVDS_PLL_LVDS_CLK_RANGE(sn65dsi83_get_lvds_range(ctx, mode)) | 599 REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY); 600 regmap_write(ctx->regmap, REG_DSI_CLK, 601 REG_DSI_CLK_CHA_DSI_CLK_RANGE(sn65dsi83_get_dsi_range(ctx, mode))); 602 regmap_write(ctx->regmap, REG_RC_DSI_CLK, 603 REG_RC_DSI_CLK_DSI_CLK_DIVIDER(sn65dsi83_get_dsi_div(ctx))); 604 605 /* Set number of DSI lanes and LVDS link config. */ 606 regmap_write(ctx->regmap, REG_DSI_LANE, 607 REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE | 608 REG_DSI_LANE_CHA_DSI_LANES(~(ctx->dsi->lanes - 1)) | 609 /* CHB is DSI85-only, set to default on DSI83/DSI84 */ 610 REG_DSI_LANE_CHB_DSI_LANES(3)); 611 /* No equalization. */ 612 regmap_write(ctx->regmap, REG_DSI_EQ, 0x00); 613 614 /* Set up sync signal polarity. */ 615 val = (mode->flags & DRM_MODE_FLAG_NHSYNC ? 616 REG_LVDS_FMT_HS_NEG_POLARITY : 0) | 617 (mode->flags & DRM_MODE_FLAG_NVSYNC ? 618 REG_LVDS_FMT_VS_NEG_POLARITY : 0); 619 val |= bridge_state->output_bus_cfg.flags & DRM_BUS_FLAG_DE_LOW ? 620 REG_LVDS_FMT_DE_NEG_POLARITY : 0; 621 622 /* Set up bits-per-pixel, 18bpp or 24bpp. */ 623 if (lvds_format_24bpp) { 624 val |= REG_LVDS_FMT_CHA_24BPP_MODE; 625 if (ctx->lvds_dual_link) 626 val |= REG_LVDS_FMT_CHB_24BPP_MODE; 627 } 628 629 /* Set up LVDS format, JEIDA/Format 1 or SPWG/Format 2 */ 630 if (lvds_format_jeida) { 631 val |= REG_LVDS_FMT_CHA_24BPP_FORMAT1; 632 if (ctx->lvds_dual_link) 633 val |= REG_LVDS_FMT_CHB_24BPP_FORMAT1; 634 } 635 636 /* Set up LVDS output config (DSI84,DSI85) */ 637 if (!ctx->lvds_dual_link) 638 val |= REG_LVDS_FMT_LVDS_LINK_CFG; 639 640 regmap_write(ctx->regmap, REG_LVDS_FMT, val); 641 regmap_write(ctx->regmap, REG_LVDS_VCOM, 642 REG_LVDS_VCOM_CHA_LVDS_VOD_SWING(ctx->lvds_vod_swing_conf[CHANNEL_A]) | 643 REG_LVDS_VCOM_CHB_LVDS_VOD_SWING(ctx->lvds_vod_swing_conf[CHANNEL_B])); 644 regmap_write(ctx->regmap, REG_LVDS_LANE, 645 (ctx->lvds_dual_link_even_odd_swap ? 646 REG_LVDS_LANE_EVEN_ODD_SWAP : 0) | 647 (ctx->lvds_term_conf[CHANNEL_A] ? 648 REG_LVDS_LANE_CHA_LVDS_TERM : 0) | 649 (ctx->lvds_term_conf[CHANNEL_B] ? 650 REG_LVDS_LANE_CHB_LVDS_TERM : 0)); 651 regmap_write(ctx->regmap, REG_LVDS_CM, 0x00); 652 653 /* 654 * Active line length needs to be halved for test pattern 655 * generation in dual LVDS output. 656 */ 657 le16val = cpu_to_le16(mode->hdisplay / (test_pattern ? dual_factor : 1)); 658 regmap_bulk_write(ctx->regmap, REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, 659 &le16val, 2); 660 le16val = cpu_to_le16(mode->vdisplay); 661 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, 662 &le16val, 2); 663 /* 32 + 1 pixel clock to ensure proper operation */ 664 le16val = cpu_to_le16(32 + 1); 665 regmap_bulk_write(ctx->regmap, REG_VID_CHA_SYNC_DELAY_LOW, &le16val, 2); 666 le16val = cpu_to_le16((mode->hsync_end - mode->hsync_start) / dual_factor); 667 regmap_bulk_write(ctx->regmap, REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, 668 &le16val, 2); 669 le16val = cpu_to_le16(mode->vsync_end - mode->vsync_start); 670 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, 671 &le16val, 2); 672 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_BACK_PORCH, 673 (mode->htotal - mode->hsync_end) / dual_factor); 674 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_BACK_PORCH, 675 mode->vtotal - mode->vsync_end); 676 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_FRONT_PORCH, 677 (mode->hsync_start - mode->hdisplay) / dual_factor); 678 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH, 679 mode->vsync_start - mode->vdisplay); 680 regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 681 test_pattern ? REG_VID_CHA_TEST_PATTERN_EN : 0); 682 683 /* Enable PLL */ 684 regmap_write(ctx->regmap, REG_RC_PLL_EN, REG_RC_PLL_EN_PLL_EN); 685 usleep_range(3000, 4000); 686 ret = regmap_read_poll_timeout(ctx->regmap, REG_RC_LVDS_PLL, pval, 687 pval & REG_RC_LVDS_PLL_PLL_EN_STAT, 688 1000, 100000); 689 if (ret) { 690 dev_err(ctx->dev, "failed to lock PLL, ret=%i\n", ret); 691 /* On failure, disable PLL again and exit. */ 692 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00); 693 goto err_add_action; 694 } 695 696 /* Trigger reset after CSR register update. */ 697 regmap_write(ctx->regmap, REG_RC_RESET, REG_RC_RESET_SOFT_RESET); 698 699 /* Wait for 10ms after soft reset as specified in datasheet */ 700 usleep_range(10000, 12000); 701 702 err_add_action: 703 devm_add_action(ctx->dev, sn65dsi83_release_resources, ctx); 704 err_exit: 705 drm_bridge_exit(idx); 706 } 707 708 static void sn65dsi83_atomic_enable(struct drm_bridge *bridge, 709 struct drm_atomic_commit *state) 710 { 711 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 712 unsigned int pval; 713 int idx; 714 715 if (!drm_bridge_enter(bridge, &idx)) 716 return; 717 718 /* Clear all errors that got asserted during initialization. */ 719 regmap_read(ctx->regmap, REG_IRQ_STAT, &pval); 720 regmap_write(ctx->regmap, REG_IRQ_STAT, pval); 721 722 /* Wait for 1ms and check for errors in status register */ 723 usleep_range(1000, 1100); 724 regmap_read(ctx->regmap, REG_IRQ_STAT, &pval); 725 if (pval) 726 dev_err(ctx->dev, "Unexpected link status 0x%02x\n", pval); 727 728 if (ctx->irq) { 729 /* Enable irq to detect errors */ 730 regmap_write(ctx->regmap, REG_IRQ_GLOBAL, REG_IRQ_GLOBAL_IRQ_EN); 731 regmap_write(ctx->regmap, REG_IRQ_EN, 0xff & ~REG_IRQ_EN_CHA_PLL_UNLOCK_EN); 732 } else { 733 /* Use the polling task */ 734 sn65dsi83_monitor_start(ctx); 735 } 736 737 drm_bridge_exit(idx); 738 } 739 740 static void sn65dsi83_atomic_disable(struct drm_bridge *bridge, 741 struct drm_atomic_commit *state) 742 { 743 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 744 int idx; 745 746 if (!drm_bridge_enter(bridge, &idx)) 747 return; 748 749 devm_release_action(ctx->dev, sn65dsi83_release_resources, ctx); 750 751 drm_bridge_exit(idx); 752 } 753 754 static enum drm_mode_status 755 sn65dsi83_mode_valid(struct drm_bridge *bridge, 756 const struct drm_display_info *info, 757 const struct drm_display_mode *mode) 758 { 759 /* LVDS output clock range 25..154 MHz */ 760 if (mode->clock < 25000) 761 return MODE_CLOCK_LOW; 762 if (mode->clock > 154000) 763 return MODE_CLOCK_HIGH; 764 765 return MODE_OK; 766 } 767 768 #define MAX_INPUT_SEL_FORMATS 1 769 770 static u32 * 771 sn65dsi83_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 772 struct drm_bridge_state *bridge_state, 773 struct drm_crtc_state *crtc_state, 774 struct drm_connector_state *conn_state, 775 u32 output_fmt, 776 unsigned int *num_input_fmts) 777 { 778 u32 *input_fmts; 779 780 *num_input_fmts = 0; 781 782 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 783 GFP_KERNEL); 784 if (!input_fmts) 785 return NULL; 786 787 /* This is the DSI-end bus format */ 788 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 789 *num_input_fmts = 1; 790 791 return input_fmts; 792 } 793 794 static const struct drm_bridge_funcs sn65dsi83_funcs = { 795 .attach = sn65dsi83_attach, 796 .detach = sn65dsi83_detach, 797 .atomic_enable = sn65dsi83_atomic_enable, 798 .atomic_pre_enable = sn65dsi83_atomic_pre_enable, 799 .atomic_disable = sn65dsi83_atomic_disable, 800 .mode_valid = sn65dsi83_mode_valid, 801 802 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 803 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 804 .atomic_reset = drm_atomic_helper_bridge_reset, 805 .atomic_get_input_bus_fmts = sn65dsi83_atomic_get_input_bus_fmts, 806 }; 807 808 static int sn65dsi83_select_lvds_vod_swing(struct device *dev, 809 u32 lvds_vod_swing_data[2], u32 lvds_vod_swing_clk[2], u8 lvds_term) 810 { 811 int i; 812 813 for (i = 0; i <= 3; i++) { 814 if (lvds_vod_swing_data_table[lvds_term][i][0] >= lvds_vod_swing_data[0] && 815 lvds_vod_swing_data_table[lvds_term][i][1] <= lvds_vod_swing_data[1] && 816 lvds_vod_swing_clock_table[lvds_term][i][0] >= lvds_vod_swing_clk[0] && 817 lvds_vod_swing_clock_table[lvds_term][i][1] <= lvds_vod_swing_clk[1]) 818 return i; 819 } 820 821 dev_err(dev, "failed to find appropriate LVDS_VOD_SWING configuration\n"); 822 return -EINVAL; 823 } 824 825 static int sn65dsi83_parse_lvds_endpoint(struct sn65dsi83 *ctx, int channel) 826 { 827 struct device *dev = ctx->dev; 828 struct device_node *endpoint; 829 int endpoint_reg; 830 /* Set so the property can be freely selected if not defined */ 831 u32 lvds_vod_swing_data[2] = { 0, 1000000 }; 832 u32 lvds_vod_swing_clk[2] = { 0, 1000000 }; 833 /* Set default near end terminataion to 200 Ohm */ 834 u32 lvds_term = 200; 835 int lvds_vod_swing_conf; 836 int ret = 0; 837 int ret_data; 838 int ret_clock; 839 840 if (channel == CHANNEL_A) 841 endpoint_reg = 2; 842 else 843 endpoint_reg = 3; 844 845 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, endpoint_reg, -1); 846 847 of_property_read_u32(endpoint, "ti,lvds-termination-ohms", &lvds_term); 848 if (lvds_term == 100) 849 ctx->lvds_term_conf[channel] = OHM_100; 850 else if (lvds_term == 200) 851 ctx->lvds_term_conf[channel] = OHM_200; 852 else { 853 ret = -EINVAL; 854 goto exit; 855 } 856 857 ret_data = of_property_read_u32_array(endpoint, "ti,lvds-vod-swing-data-microvolt", 858 lvds_vod_swing_data, ARRAY_SIZE(lvds_vod_swing_data)); 859 if (ret_data != 0 && ret_data != -EINVAL) { 860 ret = ret_data; 861 goto exit; 862 } 863 864 ret_clock = of_property_read_u32_array(endpoint, "ti,lvds-vod-swing-clock-microvolt", 865 lvds_vod_swing_clk, ARRAY_SIZE(lvds_vod_swing_clk)); 866 if (ret_clock != 0 && ret_clock != -EINVAL) { 867 ret = ret_clock; 868 goto exit; 869 } 870 871 /* Use default value if both properties are NOT defined. */ 872 if (ret_data == -EINVAL && ret_clock == -EINVAL) 873 lvds_vod_swing_conf = 0x1; 874 875 /* Use lookup table if any of the two properties is defined. */ 876 if (!ret_data || !ret_clock) { 877 lvds_vod_swing_conf = sn65dsi83_select_lvds_vod_swing(dev, lvds_vod_swing_data, 878 lvds_vod_swing_clk, ctx->lvds_term_conf[channel]); 879 if (lvds_vod_swing_conf < 0) { 880 ret = lvds_vod_swing_conf; 881 goto exit; 882 } 883 } 884 885 ctx->lvds_vod_swing_conf[channel] = lvds_vod_swing_conf; 886 ret = 0; 887 exit: 888 of_node_put(endpoint); 889 return ret; 890 } 891 892 static int sn65dsi83_parse_dt(struct sn65dsi83 *ctx, enum sn65dsi83_model model) 893 { 894 struct drm_bridge *panel_bridge; 895 struct device *dev = ctx->dev; 896 int ret; 897 898 ret = sn65dsi83_parse_lvds_endpoint(ctx, CHANNEL_A); 899 if (ret < 0) 900 return ret; 901 902 ret = sn65dsi83_parse_lvds_endpoint(ctx, CHANNEL_B); 903 if (ret < 0) 904 return ret; 905 906 ctx->lvds_dual_link = false; 907 ctx->lvds_dual_link_even_odd_swap = false; 908 if (model != MODEL_SN65DSI83) { 909 struct device_node *port2, *port3; 910 int dual_link; 911 912 port2 = of_graph_get_port_by_id(dev->of_node, 2); 913 port3 = of_graph_get_port_by_id(dev->of_node, 3); 914 dual_link = drm_of_lvds_get_dual_link_pixel_order(port2, port3); 915 of_node_put(port2); 916 of_node_put(port3); 917 918 if (dual_link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS) { 919 ctx->lvds_dual_link = true; 920 /* Odd pixels to LVDS Channel A, even pixels to B */ 921 ctx->lvds_dual_link_even_odd_swap = false; 922 } else if (dual_link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) { 923 ctx->lvds_dual_link = true; 924 /* Even pixels to LVDS Channel A, odd pixels to B */ 925 ctx->lvds_dual_link_even_odd_swap = true; 926 } 927 } 928 929 panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 2, 0); 930 if (IS_ERR(panel_bridge)) 931 return dev_err_probe(dev, PTR_ERR(panel_bridge), "Failed to get panel bridge\n"); 932 933 ctx->panel_bridge = panel_bridge; 934 935 ctx->vcc = devm_regulator_get(dev, "vcc"); 936 if (IS_ERR(ctx->vcc)) 937 return dev_err_probe(dev, PTR_ERR(ctx->vcc), 938 "Failed to get supply 'vcc'\n"); 939 940 return 0; 941 } 942 943 static int sn65dsi83_host_attach(struct sn65dsi83 *ctx) 944 { 945 struct device *dev = ctx->dev; 946 struct device_node *host_node; 947 struct device_node *endpoint; 948 struct mipi_dsi_device *dsi; 949 struct mipi_dsi_host *host; 950 const struct mipi_dsi_device_info info = { 951 .type = "sn65dsi83", 952 .channel = 0, 953 .node = NULL, 954 }; 955 int dsi_lanes, ret; 956 957 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1); 958 dsi_lanes = drm_of_get_data_lanes_count(endpoint, 1, 4); 959 host_node = of_graph_get_remote_port_parent(endpoint); 960 host = of_find_mipi_dsi_host_by_node(host_node); 961 of_node_put(host_node); 962 of_node_put(endpoint); 963 964 if (!host) 965 return -EPROBE_DEFER; 966 967 if (dsi_lanes < 0) 968 return dsi_lanes; 969 970 dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 971 if (IS_ERR(dsi)) 972 return dev_err_probe(dev, PTR_ERR(dsi), 973 "failed to create dsi device\n"); 974 975 ctx->dsi = dsi; 976 977 dsi->lanes = dsi_lanes; 978 dsi->format = MIPI_DSI_FMT_RGB888; 979 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 980 MIPI_DSI_MODE_VIDEO_NO_HFP | MIPI_DSI_MODE_VIDEO_NO_HBP | 981 MIPI_DSI_MODE_VIDEO_NO_HSA | MIPI_DSI_MODE_NO_EOT_PACKET; 982 983 ret = devm_mipi_dsi_attach(dev, dsi); 984 if (ret < 0) { 985 dev_err(dev, "failed to attach dsi to host: %d\n", ret); 986 return ret; 987 } 988 989 return 0; 990 } 991 992 static irqreturn_t sn65dsi83_irq(int irq, void *data) 993 { 994 struct sn65dsi83 *ctx = data; 995 996 sn65dsi83_handle_errors(ctx); 997 return IRQ_HANDLED; 998 } 999 1000 static int sn65dsi83_probe(struct i2c_client *client) 1001 { 1002 const struct i2c_device_id *id = i2c_client_get_device_id(client); 1003 struct device *dev = &client->dev; 1004 enum sn65dsi83_model model; 1005 struct sn65dsi83 *ctx; 1006 int ret; 1007 1008 ctx = devm_drm_bridge_alloc(dev, struct sn65dsi83, bridge, &sn65dsi83_funcs); 1009 if (IS_ERR(ctx)) 1010 return PTR_ERR(ctx); 1011 1012 ctx->dev = dev; 1013 INIT_WORK(&ctx->reset_work, sn65dsi83_reset_work); 1014 INIT_DELAYED_WORK(&ctx->monitor_work, sn65dsi83_monitor_work); 1015 1016 if (dev->of_node) { 1017 model = (enum sn65dsi83_model)(uintptr_t) 1018 of_device_get_match_data(dev); 1019 } else { 1020 model = id->driver_data; 1021 } 1022 1023 /* Put the chip in reset, pull EN line low, and assure 10ms reset low timing. */ 1024 ctx->enable_gpio = devm_gpiod_get_optional(ctx->dev, "enable", 1025 GPIOD_OUT_LOW); 1026 if (IS_ERR(ctx->enable_gpio)) 1027 return dev_err_probe(dev, PTR_ERR(ctx->enable_gpio), "failed to get enable GPIO\n"); 1028 1029 usleep_range(10000, 11000); 1030 1031 ret = sn65dsi83_parse_dt(ctx, model); 1032 if (ret) 1033 return ret; 1034 1035 ctx->regmap = devm_regmap_init_i2c(client, &sn65dsi83_regmap_config); 1036 if (IS_ERR(ctx->regmap)) 1037 return dev_err_probe(dev, PTR_ERR(ctx->regmap), "failed to get regmap\n"); 1038 1039 if (client->irq) { 1040 ctx->irq = client->irq; 1041 ret = devm_request_threaded_irq(ctx->dev, ctx->irq, NULL, sn65dsi83_irq, 1042 IRQF_ONESHOT, dev_name(ctx->dev), ctx); 1043 if (ret) 1044 return dev_err_probe(dev, ret, "failed to request irq\n"); 1045 } 1046 1047 dev_set_drvdata(dev, ctx); 1048 i2c_set_clientdata(client, ctx); 1049 1050 ctx->bridge.of_node = dev->of_node; 1051 ctx->bridge.pre_enable_prev_first = true; 1052 ctx->bridge.type = DRM_MODE_CONNECTOR_LVDS; 1053 drm_bridge_add(&ctx->bridge); 1054 1055 ret = sn65dsi83_host_attach(ctx); 1056 if (ret) { 1057 dev_err_probe(dev, ret, "failed to attach DSI host\n"); 1058 goto err_remove_bridge; 1059 } 1060 1061 return 0; 1062 1063 err_remove_bridge: 1064 drm_bridge_remove(&ctx->bridge); 1065 return ret; 1066 } 1067 1068 static void sn65dsi83_remove(struct i2c_client *client) 1069 { 1070 struct sn65dsi83 *ctx = i2c_get_clientdata(client); 1071 1072 drm_bridge_unplug(&ctx->bridge); 1073 } 1074 1075 static const struct i2c_device_id sn65dsi83_id[] = { 1076 { "ti,sn65dsi83", MODEL_SN65DSI83 }, 1077 { "ti,sn65dsi84", MODEL_SN65DSI84 }, 1078 {}, 1079 }; 1080 MODULE_DEVICE_TABLE(i2c, sn65dsi83_id); 1081 1082 static const struct of_device_id sn65dsi83_match_table[] = { 1083 { .compatible = "ti,sn65dsi83", .data = (void *)MODEL_SN65DSI83 }, 1084 { .compatible = "ti,sn65dsi84", .data = (void *)MODEL_SN65DSI84 }, 1085 {}, 1086 }; 1087 MODULE_DEVICE_TABLE(of, sn65dsi83_match_table); 1088 1089 static struct i2c_driver sn65dsi83_driver = { 1090 .probe = sn65dsi83_probe, 1091 .remove = sn65dsi83_remove, 1092 .id_table = sn65dsi83_id, 1093 .driver = { 1094 .name = "sn65dsi83", 1095 .of_match_table = sn65dsi83_match_table, 1096 }, 1097 }; 1098 module_i2c_driver(sn65dsi83_driver); 1099 1100 MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 1101 MODULE_DESCRIPTION("TI SN65DSI83 DSI to LVDS bridge driver"); 1102 MODULE_LICENSE("GPL v2"); 1103