1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2021 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/of_graph.h>
12 #include <linux/platform_device.h>
13 #include <linux/reset.h>
14 #include <linux/phy/phy.h>
15 #include <linux/bitfield.h>
16
17 #include <video/mipi_display.h>
18
19 #include <drm/bridge/dw_mipi_dsi.h>
20 #include <drm/drm_mipi_dsi.h>
21
22 #include <drm/drm_atomic_helper.h>
23 #include <drm/drm_device.h>
24 #include <drm/drm_probe_helper.h>
25 #include <drm/drm_print.h>
26
27 #include "meson_drv.h"
28 #include "meson_dw_mipi_dsi.h"
29 #include "meson_registers.h"
30 #include "meson_venc.h"
31
32 #define DRIVER_NAME "meson-dw-mipi-dsi"
33 #define DRIVER_DESC "Amlogic Meson MIPI-DSI DRM driver"
34
35 struct meson_dw_mipi_dsi {
36 struct meson_drm *priv;
37 struct device *dev;
38 void __iomem *base;
39 struct phy *phy;
40 union phy_configure_opts phy_opts;
41 struct dw_mipi_dsi *dmd;
42 struct dw_mipi_dsi_plat_data pdata;
43 struct mipi_dsi_device *dsi_device;
44 const struct drm_display_mode *mode;
45 struct clk *bit_clk;
46 struct clk *px_clk;
47 struct reset_control *top_rst;
48 };
49
50 #define encoder_to_meson_dw_mipi_dsi(x) \
51 container_of(x, struct meson_dw_mipi_dsi, encoder)
52
meson_dw_mipi_dsi_hw_init(struct meson_dw_mipi_dsi * mipi_dsi)53 static void meson_dw_mipi_dsi_hw_init(struct meson_dw_mipi_dsi *mipi_dsi)
54 {
55 /* Software reset */
56 writel_bits_relaxed(MIPI_DSI_TOP_SW_RESET_DWC | MIPI_DSI_TOP_SW_RESET_INTR |
57 MIPI_DSI_TOP_SW_RESET_DPI | MIPI_DSI_TOP_SW_RESET_TIMING,
58 MIPI_DSI_TOP_SW_RESET_DWC | MIPI_DSI_TOP_SW_RESET_INTR |
59 MIPI_DSI_TOP_SW_RESET_DPI | MIPI_DSI_TOP_SW_RESET_TIMING,
60 mipi_dsi->base + MIPI_DSI_TOP_SW_RESET);
61 writel_bits_relaxed(MIPI_DSI_TOP_SW_RESET_DWC | MIPI_DSI_TOP_SW_RESET_INTR |
62 MIPI_DSI_TOP_SW_RESET_DPI | MIPI_DSI_TOP_SW_RESET_TIMING,
63 0, mipi_dsi->base + MIPI_DSI_TOP_SW_RESET);
64
65 /* Enable clocks */
66 writel_bits_relaxed(MIPI_DSI_TOP_CLK_SYSCLK_EN | MIPI_DSI_TOP_CLK_PIXCLK_EN,
67 MIPI_DSI_TOP_CLK_SYSCLK_EN | MIPI_DSI_TOP_CLK_PIXCLK_EN,
68 mipi_dsi->base + MIPI_DSI_TOP_CLK_CNTL);
69
70 /* Take memory out of power down */
71 writel_relaxed(0, mipi_dsi->base + MIPI_DSI_TOP_MEM_PD);
72 }
73
dw_mipi_dsi_phy_init(void * priv_data)74 static int dw_mipi_dsi_phy_init(void *priv_data)
75 {
76 struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
77 unsigned int dpi_data_format, venc_data_width;
78 int ret;
79
80 /* Set the bit clock rate to hs_clk_rate */
81 ret = clk_set_rate(mipi_dsi->bit_clk,
82 mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate);
83 if (ret) {
84 dev_err(mipi_dsi->dev, "Failed to set DSI Bit clock rate %lu (ret %d)\n",
85 mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate, ret);
86 return ret;
87 }
88
89 /* Make sure the rate of the bit clock is not modified by someone else */
90 ret = clk_rate_exclusive_get(mipi_dsi->bit_clk);
91 if (ret) {
92 dev_err(mipi_dsi->dev,
93 "Failed to set the exclusivity on the bit clock rate (ret %d)\n", ret);
94 return ret;
95 }
96
97 clk_disable_unprepare(mipi_dsi->px_clk);
98 ret = clk_set_rate(mipi_dsi->px_clk, mipi_dsi->mode->clock * 1000);
99
100 if (ret) {
101 dev_err(mipi_dsi->dev, "Failed to set DSI Pixel clock rate %u (%d)\n",
102 mipi_dsi->mode->clock * 1000, ret);
103 return ret;
104 }
105
106 ret = clk_prepare_enable(mipi_dsi->px_clk);
107 if (ret) {
108 dev_err(mipi_dsi->dev, "Failed to enable DSI Pixel clock (ret %d)\n", ret);
109 return ret;
110 }
111
112 switch (mipi_dsi->dsi_device->format) {
113 case MIPI_DSI_FMT_RGB888:
114 dpi_data_format = DPI_COLOR_24BIT;
115 venc_data_width = VENC_IN_COLOR_24B;
116 break;
117 case MIPI_DSI_FMT_RGB666:
118 dpi_data_format = DPI_COLOR_18BIT_CFG_2;
119 venc_data_width = VENC_IN_COLOR_18B;
120 break;
121 default:
122 return -EINVAL;
123 }
124
125 /* Configure color format for DPI register */
126 writel_relaxed(FIELD_PREP(MIPI_DSI_TOP_DPI_COLOR_MODE, dpi_data_format) |
127 FIELD_PREP(MIPI_DSI_TOP_IN_COLOR_MODE, venc_data_width) |
128 FIELD_PREP(MIPI_DSI_TOP_COMP2_SEL, 2) |
129 FIELD_PREP(MIPI_DSI_TOP_COMP1_SEL, 1) |
130 FIELD_PREP(MIPI_DSI_TOP_COMP0_SEL, 0),
131 mipi_dsi->base + MIPI_DSI_TOP_CNTL);
132
133 return phy_configure(mipi_dsi->phy, &mipi_dsi->phy_opts);
134 }
135
dw_mipi_dsi_phy_power_on(void * priv_data)136 static void dw_mipi_dsi_phy_power_on(void *priv_data)
137 {
138 struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
139
140 if (phy_power_on(mipi_dsi->phy))
141 dev_warn(mipi_dsi->dev, "Failed to power on PHY\n");
142 }
143
dw_mipi_dsi_phy_power_off(void * priv_data)144 static void dw_mipi_dsi_phy_power_off(void *priv_data)
145 {
146 struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
147
148 if (phy_power_off(mipi_dsi->phy))
149 dev_warn(mipi_dsi->dev, "Failed to power off PHY\n");
150
151 /* Remove the exclusivity on the bit clock rate */
152 clk_rate_exclusive_put(mipi_dsi->bit_clk);
153 }
154
155 static int
dw_mipi_dsi_get_lane_mbps(void * priv_data,const struct drm_display_mode * mode,unsigned long mode_flags,u32 lanes,u32 format,unsigned int * lane_mbps)156 dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
157 unsigned long mode_flags, u32 lanes, u32 format,
158 unsigned int *lane_mbps)
159 {
160 struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
161 int bpp;
162
163 mipi_dsi->mode = mode;
164
165 bpp = mipi_dsi_pixel_format_to_bpp(mipi_dsi->dsi_device->format);
166
167 phy_mipi_dphy_get_default_config(mode->clock * 1000,
168 bpp, mipi_dsi->dsi_device->lanes,
169 &mipi_dsi->phy_opts.mipi_dphy);
170
171 *lane_mbps = DIV_ROUND_UP(mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate, USEC_PER_SEC);
172
173 return 0;
174 }
175
176 static int
dw_mipi_dsi_phy_get_timing(void * priv_data,unsigned int lane_mbps,struct dw_mipi_dsi_dphy_timing * timing)177 dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
178 struct dw_mipi_dsi_dphy_timing *timing)
179 {
180 struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
181
182 switch (mipi_dsi->mode->hdisplay) {
183 case 240:
184 case 768:
185 case 1920:
186 case 2560:
187 timing->clk_lp2hs = 23;
188 timing->clk_hs2lp = 38;
189 timing->data_lp2hs = 15;
190 timing->data_hs2lp = 9;
191 break;
192
193 default:
194 timing->clk_lp2hs = 37;
195 timing->clk_hs2lp = 135;
196 timing->data_lp2hs = 50;
197 timing->data_hs2lp = 3;
198 }
199
200 return 0;
201 }
202
203 static int
dw_mipi_dsi_get_esc_clk_rate(void * priv_data,unsigned int * esc_clk_rate)204 dw_mipi_dsi_get_esc_clk_rate(void *priv_data, unsigned int *esc_clk_rate)
205 {
206 *esc_clk_rate = 4; /* Mhz */
207
208 return 0;
209 }
210
211 static const struct dw_mipi_dsi_phy_ops meson_dw_mipi_dsi_phy_ops = {
212 .init = dw_mipi_dsi_phy_init,
213 .power_on = dw_mipi_dsi_phy_power_on,
214 .power_off = dw_mipi_dsi_phy_power_off,
215 .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
216 .get_timing = dw_mipi_dsi_phy_get_timing,
217 .get_esc_clk_rate = dw_mipi_dsi_get_esc_clk_rate,
218 };
219
meson_dw_mipi_dsi_host_attach(void * priv_data,struct mipi_dsi_device * device)220 static int meson_dw_mipi_dsi_host_attach(void *priv_data,
221 struct mipi_dsi_device *device)
222 {
223 struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
224 int ret;
225
226 mipi_dsi->dsi_device = device;
227
228 switch (device->format) {
229 case MIPI_DSI_FMT_RGB888:
230 break;
231 case MIPI_DSI_FMT_RGB666:
232 break;
233 default:
234 dev_err(mipi_dsi->dev, "invalid pixel format %d\n", device->format);
235 return -EINVAL;
236 }
237
238 ret = phy_init(mipi_dsi->phy);
239 if (ret)
240 return ret;
241
242 meson_dw_mipi_dsi_hw_init(mipi_dsi);
243
244 return 0;
245 }
246
meson_dw_mipi_dsi_host_detach(void * priv_data,struct mipi_dsi_device * device)247 static int meson_dw_mipi_dsi_host_detach(void *priv_data,
248 struct mipi_dsi_device *device)
249 {
250 struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
251
252 if (device == mipi_dsi->dsi_device)
253 mipi_dsi->dsi_device = NULL;
254 else
255 return -EINVAL;
256
257 return phy_exit(mipi_dsi->phy);
258 }
259
260 static const struct dw_mipi_dsi_host_ops meson_dw_mipi_dsi_host_ops = {
261 .attach = meson_dw_mipi_dsi_host_attach,
262 .detach = meson_dw_mipi_dsi_host_detach,
263 };
264
meson_dw_mipi_dsi_probe(struct platform_device * pdev)265 static int meson_dw_mipi_dsi_probe(struct platform_device *pdev)
266 {
267 struct meson_dw_mipi_dsi *mipi_dsi;
268 struct device *dev = &pdev->dev;
269
270 mipi_dsi = devm_kzalloc(dev, sizeof(*mipi_dsi), GFP_KERNEL);
271 if (!mipi_dsi)
272 return -ENOMEM;
273
274 mipi_dsi->base = devm_platform_ioremap_resource(pdev, 0);
275 if (IS_ERR(mipi_dsi->base))
276 return PTR_ERR(mipi_dsi->base);
277
278 mipi_dsi->phy = devm_phy_get(dev, "dphy");
279 if (IS_ERR(mipi_dsi->phy))
280 return dev_err_probe(dev, PTR_ERR(mipi_dsi->phy),
281 "failed to get mipi dphy\n");
282
283 mipi_dsi->bit_clk = devm_clk_get_enabled(dev, "bit");
284 if (IS_ERR(mipi_dsi->bit_clk)) {
285 int ret = PTR_ERR(mipi_dsi->bit_clk);
286
287 /* TOFIX GP0 on some platforms fails to lock in early boot, defer probe */
288 if (ret == -EIO)
289 ret = -EPROBE_DEFER;
290
291 return dev_err_probe(dev, ret, "Unable to get enabled bit_clk\n");
292 }
293
294 mipi_dsi->px_clk = devm_clk_get_enabled(dev, "px");
295 if (IS_ERR(mipi_dsi->px_clk))
296 return dev_err_probe(dev, PTR_ERR(mipi_dsi->px_clk),
297 "Unable to get enabled px_clk\n");
298
299 /*
300 * We use a TOP reset signal because the APB reset signal
301 * is handled by the TOP control registers.
302 */
303 mipi_dsi->top_rst = devm_reset_control_get_exclusive(dev, "top");
304 if (IS_ERR(mipi_dsi->top_rst))
305 return dev_err_probe(dev, PTR_ERR(mipi_dsi->top_rst),
306 "Unable to get reset control\n");
307
308 reset_control_assert(mipi_dsi->top_rst);
309 usleep_range(10, 20);
310 reset_control_deassert(mipi_dsi->top_rst);
311
312 /* MIPI DSI Controller */
313
314 mipi_dsi->dev = dev;
315 mipi_dsi->pdata.base = mipi_dsi->base;
316 mipi_dsi->pdata.max_data_lanes = 4;
317 mipi_dsi->pdata.phy_ops = &meson_dw_mipi_dsi_phy_ops;
318 mipi_dsi->pdata.host_ops = &meson_dw_mipi_dsi_host_ops;
319 mipi_dsi->pdata.priv_data = mipi_dsi;
320 platform_set_drvdata(pdev, mipi_dsi);
321
322 mipi_dsi->dmd = dw_mipi_dsi_probe(pdev, &mipi_dsi->pdata);
323 if (IS_ERR(mipi_dsi->dmd))
324 return dev_err_probe(dev, PTR_ERR(mipi_dsi->dmd),
325 "Failed to probe dw_mipi_dsi\n");
326
327 return 0;
328 }
329
meson_dw_mipi_dsi_remove(struct platform_device * pdev)330 static void meson_dw_mipi_dsi_remove(struct platform_device *pdev)
331 {
332 struct meson_dw_mipi_dsi *mipi_dsi = platform_get_drvdata(pdev);
333
334 dw_mipi_dsi_remove(mipi_dsi->dmd);
335 }
336
337 static const struct of_device_id meson_dw_mipi_dsi_of_table[] = {
338 { .compatible = "amlogic,meson-g12a-dw-mipi-dsi", },
339 { }
340 };
341 MODULE_DEVICE_TABLE(of, meson_dw_mipi_dsi_of_table);
342
343 static struct platform_driver meson_dw_mipi_dsi_platform_driver = {
344 .probe = meson_dw_mipi_dsi_probe,
345 .remove = meson_dw_mipi_dsi_remove,
346 .driver = {
347 .name = DRIVER_NAME,
348 .of_match_table = meson_dw_mipi_dsi_of_table,
349 },
350 };
351 module_platform_driver(meson_dw_mipi_dsi_platform_driver);
352
353 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
354 MODULE_DESCRIPTION(DRIVER_DESC);
355 MODULE_LICENSE("GPL");
356