1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the R-Car V4H ES3.0 Sparrow Hawk board 4 * 5 * Copyright (C) 2025 Marek Vasut <marek.vasut+renesas@mailbox.org> 6 */ 7/* 8 * DA7212 Codec settings 9 * 10 * for Playback 11 * > amixer set "Headphone" 40% 12 * > amixer set "Headphone" on 13 * > amixer set "Mixout Left DAC Left" on 14 * > amixer set "Mixout Right DAC Right" on 15 * > aplay xxx.wav 16 * 17 * for Capture (Aux/Mic) 18 * 19 * on/off (B) 20 * CONN3 (HeadSet) ---+----> MSIOF1 21 * | 22 * CONN4 AUX ---------+ on/off (A) 23 * 24 * > amixer set "Mixin PGA" on 25 * > amixer set "Mixin PGA" 50% 26 * > amixer set "ADC" on 27 * > amixer set "ADC" 80% 28 * > amixer set "Aux" on ^ 29 * > amixer set "Aux" 80% | (A) 30 * > amixer set "Mixin Left Aux Left" on | 31 * > amixer set "Mixin Right Aux Right" on v 32 * > amixer set "Mic 1" on ^ 33 * > amixer set "Mic 1" 80% | (B) 34 * > amixer set "Mixin Left Mic 1" on | 35 * > amixer set "Mixin Right Mic 1" on v 36 * > arecord -f cd xxx.wav 37 */ 38 39/dts-v1/; 40#include <dt-bindings/gpio/gpio.h> 41#include <dt-bindings/thermal/thermal.h> 42 43#include "r8a779g3.dtsi" 44 45/ { 46 model = "Retronix Sparrow Hawk board based on r8a779g3"; 47 compatible = "retronix,sparrow-hawk", "renesas,r8a779g3", 48 "renesas,r8a779g0"; 49 50 aliases { 51 ethernet0 = &avb0; 52 i2c0 = &i2c0; 53 i2c1 = &i2c1; 54 i2c2 = &i2c2; 55 i2c3 = &i2c3; 56 i2c4 = &i2c4; 57 i2c5 = &i2c5; 58 serial0 = &hscif0; 59 serial1 = &hscif1; 60 serial2 = &hscif3; 61 spi0 = &rpc; 62 }; 63 64 chosen { 65 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; 66 stdout-path = "serial0:921600n8"; 67 }; 68 69 /* Page 31 / FAN */ 70 fan: pwm-fan { 71 pinctrl-0 = <&irq4_pins>; 72 pinctrl-names = "default"; 73 compatible = "pwm-fan"; 74 #cooling-cells = <2>; 75 interrupts-extended = <&intc_ex 4 IRQ_TYPE_EDGE_FALLING>; 76 /* 77 * The fan model connected to this device can be selected 78 * by user. Set "cooling-levels" DT property to single 255 79 * entry to force the fan PWM into constant HIGH, which 80 * forces the fan to spin at maximum RPM, thus providing 81 * maximum cooling to this device and protection against 82 * misconfigured PWM duty cycle to the fan. 83 * 84 * User has to configure "pwms" and "pulses-per-revolution" 85 * DT properties according to fan datasheet first, and then 86 * extend "cooling-levels = <0 m n ... 255>" property to 87 * achieve proper fan control compatible with fan model 88 * installed by user. 89 */ 90 cooling-levels = <255>; 91 pulses-per-revolution = <2>; 92 pwms = <&pwm0 0 50000>; 93 }; 94 95 /* 96 * Page 15 / LPDDR5 97 * 98 * This configuration listed below is for the 8 GiB board variant 99 * with MT62F1G64D8EK-023 WT:C LPDDR5 part populated on the board. 100 * 101 * A variant with 16 GiB MT62F2G64D8EK-023 WT:C part populated on 102 * the board is automatically handled by the bootloader, which 103 * adjusts the correct DRAM size into the memory nodes below. 104 */ 105 memory@48000000 { 106 device_type = "memory"; 107 /* first 128MB is reserved for secure area. */ 108 reg = <0x0 0x48000000 0x0 0x78000000>; 109 }; 110 111 memory@480000000 { 112 device_type = "memory"; 113 reg = <0x4 0x80000000 0x0 0x80000000>; 114 }; 115 116 memory@600000000 { 117 device_type = "memory"; 118 reg = <0x6 0x00000000 0x1 0x00000000>; 119 }; 120 121 reserved-memory { 122 #address-cells = <2>; 123 #size-cells = <2>; 124 ranges; 125 126 tfa@40000000 { 127 reg = <0x0 0x40000000 0x0 0x8000000>; 128 no-map; 129 }; 130 }; 131 132 /* Page 27 / DSI to Display */ 133 dp-con { 134 compatible = "dp-connector"; 135 label = "CN6"; 136 type = "full-size"; 137 138 port { 139 dp_con_in: endpoint { 140 remote-endpoint = <&sn65dsi86_out>; 141 }; 142 }; 143 }; 144 145 /* Page 26 / PCIe.0/1 CLK */ 146 pcie_refclk: clk-x8 { 147 compatible = "fixed-clock"; 148 #clock-cells = <0>; 149 clock-frequency = <25000000>; 150 }; 151 152 reg_1p2v: regulator-1p2v { 153 compatible = "regulator-fixed"; 154 regulator-name = "fixed-1.2V"; 155 regulator-min-microvolt = <1200000>; 156 regulator-max-microvolt = <1200000>; 157 regulator-boot-on; 158 regulator-always-on; 159 }; 160 161 reg_1p8v: regulator-1p8v { 162 compatible = "regulator-fixed"; 163 regulator-name = "fixed-1.8V"; 164 regulator-min-microvolt = <1800000>; 165 regulator-max-microvolt = <1800000>; 166 regulator-boot-on; 167 regulator-always-on; 168 }; 169 170 reg_3p3v: regulator-3p3v { 171 compatible = "regulator-fixed"; 172 regulator-name = "fixed-3.3V"; 173 regulator-min-microvolt = <3300000>; 174 regulator-max-microvolt = <3300000>; 175 regulator-boot-on; 176 regulator-always-on; 177 }; 178 179 /* Page 27 / DSI to Display */ 180 sn65dsi86_refclk: clk-x9 { 181 compatible = "fixed-clock"; 182 #clock-cells = <0>; 183 clock-frequency = <38400000>; 184 }; 185 186 /* Page 30 / Audio_Codec */ 187 sound_card: sound { 188 compatible = "audio-graph-card2"; 189 links = <&msiof1_snd>; 190 }; 191 192 /* Page 17 uSD-Slot */ 193 vcc_sdhi: regulator-vcc-sdhi { 194 compatible = "regulator-gpio"; 195 regulator-name = "SDHI VccQ"; 196 regulator-min-microvolt = <1800000>; 197 regulator-max-microvolt = <3300000>; 198 gpios = <&gpio8 13 GPIO_ACTIVE_HIGH>; 199 gpios-states = <1>; 200 states = <1800000 0>, <3300000 1>; 201 }; 202}; 203 204/* Use thermal-idle cooling for all SoC cores */ 205&a76_0 { 206 #cooling-cells = <2>; 207 208 a76_0_thermal_idle: thermal-idle { 209 #cooling-cells = <2>; 210 duration-us = <10000>; 211 exit-latency-us = <500>; 212 }; 213}; 214 215&a76_1 { 216 a76_1_thermal_idle: thermal-idle { 217 #cooling-cells = <2>; 218 duration-us = <10000>; 219 exit-latency-us = <500>; 220 }; 221}; 222 223&a76_2 { 224 a76_2_thermal_idle: thermal-idle { 225 #cooling-cells = <2>; 226 duration-us = <10000>; 227 exit-latency-us = <500>; 228 }; 229}; 230 231&a76_3 { 232 a76_3_thermal_idle: thermal-idle { 233 #cooling-cells = <2>; 234 duration-us = <10000>; 235 exit-latency-us = <500>; 236 }; 237}; 238 239&audio_clkin { 240 clock-frequency = <24576000>; 241}; 242 243/* Page 22 / Ether_AVB0 */ 244&avb0 { 245 pinctrl-0 = <&avb0_pins>; 246 pinctrl-names = "default"; 247 phy-handle = <&avb0_phy>; 248 tx-internal-delay-ps = <2000>; 249 status = "okay"; 250 251 mdio { 252 #address-cells = <1>; 253 #size-cells = <0>; 254 255 avb0_phy: ethernet-phy@0 { /* KSZ9031RNXVB */ 256 compatible = "ethernet-phy-id0022.1622", 257 "ethernet-phy-ieee802.3-c22"; 258 rxc-skew-ps = <1500>; 259 reg = <0>; 260 /* AVB0_PHY_INT_V */ 261 interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>; 262 /* GP7_10/AVB0_RESETN_V */ 263 reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; 264 reset-assert-us = <10000>; 265 reset-deassert-us = <300>; 266 }; 267 }; 268}; 269 270/* Page 28 / CANFD_IF */ 271&can_clk { 272 clock-frequency = <40000000>; 273}; 274 275/* Page 28 / CANFD_IF */ 276&canfd { 277 pinctrl-0 = <&canfd3_pins>, <&canfd4_pins>, <&can_clk_pins>; 278 pinctrl-names = "default"; 279 280 status = "okay"; 281 282 channel3 { 283 status = "okay"; 284 }; 285 286 channel4 { 287 status = "okay"; 288 }; 289}; 290 291/* Page 27 / DSI to Display */ 292&dsi1 { 293 status = "okay"; 294 295 ports { 296 port@1 { 297 dsi1_out: endpoint { 298 remote-endpoint = <&sn65dsi86_in>; 299 data-lanes = <1 2 3 4>; 300 }; 301 }; 302 }; 303}; 304 305/* Page 27 / DSI to Display */ 306&du { 307 status = "okay"; 308}; 309 310/* Page 5 / R-Car V4H_INT_I2C */ 311&extal_clk { /* X3 */ 312 clock-frequency = <16666666>; 313}; 314 315/* Page 5 / R-Car V4H_INT_I2C */ 316&extalr_clk { /* X2 */ 317 clock-frequency = <32768>; 318}; 319 320/* Page 26 / 2230 Key M M.2 */ 321&gpio4 { 322 /* 9FGV0441 nOE inputs 0 and 1 */ 323 pcie-m2-oe-hog { 324 gpio-hog; 325 gpios = <21 GPIO_ACTIVE_HIGH>; 326 output-low; 327 line-name = "PCIe-CLK-nOE-M2"; 328 }; 329 330 /* 9FGV0441 nOE inputs 2 and 3 */ 331 pcie-usb-oe-hog { 332 gpio-hog; 333 gpios = <22 GPIO_ACTIVE_HIGH>; 334 output-low; 335 line-name = "PCIe-CLK-nOE-USB"; 336 }; 337}; 338 339/* Page 23 / DEBUG */ 340&hscif0 { /* FTDI ADBUS[3:0] */ 341 pinctrl-0 = <&hscif0_pins>; 342 pinctrl-names = "default"; 343 uart-has-rtscts; 344 bootph-all; 345 346 status = "okay"; 347}; 348 349/* Page 23 / DEBUG */ 350&hscif1 { /* FTDI BDBUS[3:0] */ 351 pinctrl-0 = <&hscif1_pins>; 352 pinctrl-names = "default"; 353 uart-has-rtscts; 354 355 status = "okay"; 356}; 357 358/* Page 24 / UART */ 359&hscif3 { /* CN7 pins 8 (TX) and 10 (RX) */ 360 pinctrl-0 = <&hscif3_pins>; 361 pinctrl-names = "default"; 362 363 status = "okay"; 364}; 365 366/* Page 24 / I2C SWITCH */ 367&i2c0 { 368 #address-cells = <1>; 369 #size-cells = <0>; 370 pinctrl-0 = <&i2c0_pins>; 371 pinctrl-names = "default"; 372 clock-frequency = <400000>; 373 status = "okay"; 374 375 mux@71 { 376 compatible = "nxp,pca9544"; /* TCA9544 */ 377 reg = <0x71>; 378 #address-cells = <1>; 379 #size-cells = <0>; 380 vdd-supply = <®_3p3v>; 381 382 i2c0_mux0: i2c@0 { 383 reg = <0>; 384 #address-cells = <1>; 385 #size-cells = <0>; 386 387 /* Page 27 / DSI to Display */ 388 bridge@2c { 389 pinctrl-0 = <&irq0_pins>; 390 pinctrl-names = "default"; 391 392 compatible = "ti,sn65dsi86"; 393 reg = <0x2c>; 394 395 clocks = <&sn65dsi86_refclk>; 396 clock-names = "refclk"; 397 398 interrupts-extended = <&intc_ex 0 IRQ_TYPE_LEVEL_HIGH>; 399 400 enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; 401 402 vccio-supply = <®_1p8v>; 403 vpll-supply = <®_1p8v>; 404 vcca-supply = <®_1p2v>; 405 vcc-supply = <®_1p2v>; 406 407 ports { 408 #address-cells = <1>; 409 #size-cells = <0>; 410 411 port@0 { 412 reg = <0>; 413 sn65dsi86_in: endpoint { 414 remote-endpoint = <&dsi1_out>; 415 }; 416 }; 417 418 port@1 { 419 reg = <1>; 420 sn65dsi86_out: endpoint { 421 remote-endpoint = <&dp_con_in>; 422 }; 423 }; 424 }; 425 }; 426 }; 427 428 i2c0_mux1: i2c@1 { 429 reg = <1>; 430 #address-cells = <1>; 431 #size-cells = <0>; 432 433 /* Page 30 / Audio_Codec */ 434 codec@1a { 435 compatible = "dlg,da7212"; 436 437 #sound-dai-cells = <0>; 438 reg = <0x1a>; 439 440 clocks = <&rcar_sound>; 441 clock-names = "mclk"; 442 443 VDDA-supply = <®_1p8v>; 444 VDDMIC-supply = <®_3p3v>; 445 VDDIO-supply = <®_3p3v>; 446 447 port { 448 da7212_endpoint: endpoint { 449 bitclock-master; 450 frame-master; 451 remote-endpoint = <&msiof1_snd_endpoint>; 452 }; 453 }; 454 }; 455 }; 456 457 i2c0_mux2: i2c@2 { 458 reg = <2>; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 462 /* Page 26 / PCIe.0/1 CLK */ 463 pcie_clk: clk@68 { 464 compatible = "renesas,9fgv0441"; 465 reg = <0x68>; 466 clocks = <&pcie_refclk>; 467 #clock-cells = <1>; 468 }; 469 }; 470 471 i2c0_mux3: i2c@3 { 472 reg = <3>; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 }; 476 }; 477}; 478 479/* Page 29 / CSI_IF_CN / CAM_CN0 */ 480&i2c1 { 481 #address-cells = <1>; 482 #size-cells = <0>; 483 pinctrl-0 = <&i2c1_pins>; 484 pinctrl-names = "default"; 485}; 486 487/* Page 29 / CSI_IF_CN / CAM_CN1 */ 488&i2c2 { 489 #address-cells = <1>; 490 #size-cells = <0>; 491 pinctrl-0 = <&i2c2_pins>; 492 pinctrl-names = "default"; 493}; 494 495/* Page 31 / IO_CN */ 496&i2c3 { 497 #address-cells = <1>; 498 #size-cells = <0>; 499 pinctrl-0 = <&i2c3_pins>; 500 pinctrl-names = "default"; 501}; 502 503/* Page 31 / IO_CN */ 504&i2c4 { 505 #address-cells = <1>; 506 #size-cells = <0>; 507 pinctrl-0 = <&i2c4_pins>; 508 pinctrl-names = "default"; 509}; 510 511/* Page 18 / POWER_CORE and Page 19 / POWER_PMIC */ 512&i2c5 { 513 #address-cells = <1>; 514 #size-cells = <0>; 515 pinctrl-0 = <&i2c5_pins>; 516 pinctrl-names = "default"; 517}; 518 519/* Page 17 uSD-Slot */ 520&mmc0 { 521 pinctrl-0 = <&sd_pins>; 522 pinctrl-1 = <&sd_uhs_pins>; 523 pinctrl-names = "default", "state_uhs"; 524 bus-width = <4>; 525 cd-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; /* SD_CD */ 526 sd-uhs-sdr50; 527 sd-uhs-sdr104; 528 vmmc-supply = <®_3p3v>; 529 vqmmc-supply = <&vcc_sdhi>; 530 status = "okay"; 531}; 532 533&msiof1 { 534 pinctrl-0 = <&msiof1_pins>; 535 pinctrl-names = "default"; 536 537 status = "okay"; 538 539 /* ignore DT warning */ 540 /delete-property/#address-cells; 541 /delete-property/#size-cells; 542 543 msiof1_snd: port { 544 msiof1_snd_endpoint: endpoint { 545 remote-endpoint = <&da7212_endpoint>; 546 }; 547 }; 548}; 549 550&otp { 551 bootph-all; 552}; 553 554/* Page 26 / 2230 Key M M.2 */ 555&pcie0_clkref { 556 status = "disabled"; 557}; 558 559&pciec0 { 560 clocks = <&cpg CPG_MOD 624>, <&pcie_clk 0>; 561 reset-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; 562 status = "okay"; 563}; 564 565&pciec0_rp { 566 clocks = <&pcie_clk 1>; 567 vpcie3v3-supply = <®_3p3v>; 568}; 569 570/* Page 25 / PCIe to USB */ 571&pcie1_clkref { 572 status = "disabled"; 573}; 574 575&pciec1 { 576 clocks = <&cpg CPG_MOD 625>, <&pcie_clk 2>; 577 /* uPD720201 is PCIe Gen2 x1 device */ 578 num-lanes = <1>; 579 reset-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 580 status = "okay"; 581}; 582 583&pciec1_rp { 584 clocks = <&pcie_clk 3>; 585 vpcie3v3-supply = <®_3p3v>; 586}; 587 588&pfc { 589 pinctrl-0 = <&scif_clk_pins>; 590 pinctrl-names = "default"; 591 592 /* Page 22 / Ether_AVB0 */ 593 avb0_pins: avb0 { 594 mux { 595 groups = "avb0_link", "avb0_mdio", "avb0_rgmii", 596 "avb0_txcrefclk"; 597 function = "avb0"; 598 }; 599 600 pins-mdio { 601 groups = "avb0_mdio"; 602 drive-strength = <21>; 603 }; 604 605 pins-mii { 606 groups = "avb0_rgmii"; 607 drive-strength = <21>; 608 }; 609 610 pins-vddq18-25-avb { 611 pins = "PIN_VDDQ_AVB0", "PIN_VDDQ_AVB1", "PIN_VDDQ_AVB2", "PIN_VDDQ_TSN0"; 612 power-source = <1800>; 613 }; 614 }; 615 616 /* Page 28 / CANFD_IF */ 617 can_clk_pins: can-clk { 618 groups = "can_clk"; 619 function = "can_clk"; 620 }; 621 622 /* Page 28 / CANFD_IF */ 623 canfd3_pins: canfd3 { 624 groups = "canfd3_data"; 625 function = "canfd3"; 626 }; 627 628 /* Page 28 / CANFD_IF */ 629 canfd4_pins: canfd4 { 630 groups = "canfd4_data"; 631 function = "canfd4"; 632 }; 633 634 /* Page 23 / DEBUG */ 635 hscif0_pins: hscif0 { 636 groups = "hscif0_data", "hscif0_ctrl"; 637 function = "hscif0"; 638 bootph-all; 639 }; 640 641 /* Page 23 / DEBUG */ 642 hscif1_pins: hscif1 { 643 groups = "hscif1_data_a", "hscif1_ctrl_a"; 644 function = "hscif1"; 645 }; 646 647 /* Page 24 / UART */ 648 hscif3_pins: hscif3 { 649 groups = "hscif3_data_a"; 650 function = "hscif3"; 651 }; 652 653 /* Page 24 / I2C SWITCH */ 654 i2c0_pins: i2c0 { 655 groups = "i2c0"; 656 function = "i2c0"; 657 }; 658 659 /* Page 29 / CSI_IF_CN / CAM_CN0 */ 660 i2c1_pins: i2c1 { 661 groups = "i2c1"; 662 function = "i2c1"; 663 }; 664 665 /* Page 29 / CSI_IF_CN / CAM_CN1 */ 666 i2c2_pins: i2c2 { 667 groups = "i2c2"; 668 function = "i2c2"; 669 }; 670 671 /* Page 31 / IO_CN */ 672 i2c3_pins: i2c3 { 673 groups = "i2c3"; 674 function = "i2c3"; 675 }; 676 677 /* Page 31 / IO_CN */ 678 i2c4_pins: i2c4 { 679 groups = "i2c4"; 680 function = "i2c4"; 681 }; 682 683 /* Page 18 / POWER_CORE */ 684 i2c5_pins: i2c5 { 685 groups = "i2c5"; 686 function = "i2c5"; 687 }; 688 689 /* Page 27 / DSI to Display */ 690 irq0_pins: irq0 { 691 groups = "intc_ex_irq0_a"; 692 function = "intc_ex"; 693 }; 694 695 /* Page 31 / FAN */ 696 irq4_pins: irq4 { 697 groups = "intc_ex_irq4_b"; 698 function = "intc_ex"; 699 }; 700 701 /* Page 31 / FAN */ 702 pwm0_pins: pwm0 { 703 groups = "pwm0"; 704 function = "pwm0"; 705 }; 706 707 /* Page 31 / CN7 pin 12 */ 708 pwm1_pins: pwm1 { 709 groups = "pwm1_b"; 710 function = "pwm1"; 711 }; 712 713 /* Page 31 / CN7 pin 32 */ 714 pwm6_pins: pwm6 { 715 groups = "pwm6"; 716 function = "pwm6"; 717 }; 718 719 /* Page 31 / CN7 pin 33 */ 720 pwm7_pins: pwm7 { 721 groups = "pwm7"; 722 function = "pwm7"; 723 }; 724 725 /* Page 16 / QSPI_FLASH */ 726 qspi0_pins: qspi0 { 727 groups = "qspi0_ctrl", "qspi0_data4"; 728 function = "qspi0"; 729 bootph-all; 730 }; 731 732 /* Page 6 / SCIF_CLK_SOC_V */ 733 scif_clk_pins: scif-clk { 734 groups = "scif_clk"; 735 function = "scif_clk"; 736 }; 737 738 /* Page 17 uSD-Slot */ 739 sd_pins: sd { 740 groups = "mmc_data4", "mmc_ctrl"; 741 function = "mmc"; 742 power-source = <3300>; 743 }; 744 745 /* Page 17 uSD-Slot */ 746 sd_uhs_pins: sd-uhs { 747 groups = "mmc_data4", "mmc_ctrl"; 748 function = "mmc"; 749 power-source = <1800>; 750 }; 751 752 /* Page 30 / Audio_Codec */ 753 msiof1_pins: sound { 754 groups = "msiof1_clk", "msiof1_sync", "msiof1_txd", "msiof1_rxd"; 755 function = "msiof1"; 756 }; 757 758 /* Page 30 / Audio_Codec */ 759 sound_clk_pins: sound-clk { 760 groups = "audio_clkin", "audio_clkout"; 761 function = "audio_clk"; 762 }; 763}; 764 765/* Page 31 / FAN */ 766&pwm0 { 767 pinctrl-0 = <&pwm0_pins>; 768 pinctrl-names = "default"; 769 status = "okay"; 770}; 771 772/* Page 31 / CN7 pin 12 */ 773&pwm1 { 774 pinctrl-0 = <&pwm1_pins>; 775 pinctrl-names = "default"; 776 status = "okay"; 777}; 778 779/* Page 31 / CN7 pin 32 */ 780&pwm6 { 781 pinctrl-0 = <&pwm6_pins>; 782 pinctrl-names = "default"; 783 status = "okay"; 784}; 785 786/* Page 31 / CN7 pin 33 */ 787&pwm7 { 788 pinctrl-0 = <&pwm7_pins>; 789 pinctrl-names = "default"; 790 status = "okay"; 791}; 792 793/* Page 30 / Audio_Codec */ 794&rcar_sound { 795 pinctrl-0 = <&sound_clk_pins>; 796 pinctrl-names = "default"; 797 798 /* It is used for ADG output as DA7212_MCLK */ 799 800 /* audio_clkout */ 801 clock-frequency = <12288000>; /* 48 kHz groups */ 802 803 status = "okay"; 804}; 805 806/* Page 16 / QSPI_FLASH */ 807&rpc { 808 pinctrl-0 = <&qspi0_pins>; 809 pinctrl-names = "default"; 810 bootph-all; 811 812 status = "okay"; 813 814 flash@0 { 815 /* 816 * EVTA1 is populated with Spansion S25FS512S 817 * EVTB1 is populated with Winbond W77Q51NW 818 */ 819 compatible = "jedec,spi-nor"; 820 reg = <0>; 821 spi-max-frequency = <40000000>; 822 spi-rx-bus-width = <4>; 823 spi-tx-bus-width = <4>; 824 bootph-all; 825 826 partitions { 827 compatible = "fixed-partitions"; 828 #address-cells = <1>; 829 #size-cells = <1>; 830 831 boot@0 { 832 reg = <0x0 0x1000000>; 833 read-only; 834 }; 835 836 user@1000000 { 837 reg = <0x1000000 0x2f80000>; 838 }; 839 840 env1@3f80000 { 841 reg = <0x3f80000 0x40000>; 842 }; 843 844 env2@3fc0000 { 845 reg = <0x3fc0000 0x40000>; 846 }; 847 }; 848 }; 849}; 850 851&rwdt { 852 timeout-sec = <60>; 853 status = "okay"; 854}; 855 856/* Page 6 / SCIF_CLK_SOC_V */ 857&scif_clk { /* X12 */ 858 clock-frequency = <24000000>; 859}; 860 861/* THS sensors in SoC, critical temperature trip point is 100C */ 862&sensor1_crit { 863 temperature = <100000>; 864}; 865 866&sensor2_crit { 867 temperature = <100000>; 868}; 869 870&sensor3_crit { 871 temperature = <100000>; 872}; 873 874&sensor4_crit { 875 temperature = <100000>; 876}; 877 878/* THS sensor in SoC near CA76 cores does more progressive cooling. */ 879&sensor_thermal_ca76 { 880 critical-action = "shutdown"; 881 882 cooling-maps { 883 /* 884 * The cooling-device minimum and maximum parameters inversely 885 * match opp-table-0 {} node entries in r8a779g0.dtsi, in other 886 * words, 0 refers to 1.8 GHz OPP and 4 refers to 500 MHz OPP. 887 * This is because they refer to cooling levels, where maximum 888 * cooling level happens at 500 MHz OPP, when the CPU core is 889 * running slowly and therefore generates least heat. 890 */ 891 map0 { 892 /* At 68C, inhibit 1.7 GHz and 1.8 GHz modes */ 893 trip = <&sensor3_passive_low>; 894 cooling-device = <&a76_0 2 4>; 895 contribution = <128>; 896 }; 897 898 map1 { 899 /* At 72C, inhibit 1.5 GHz mode */ 900 trip = <&sensor3_passive_mid>; 901 cooling-device = <&a76_0 3 4>; 902 contribution = <256>; 903 }; 904 905 map2 { 906 /* At 76C, start injecting idle states 0..80% of time */ 907 trip = <&sensor3_passive_hi>; 908 cooling-device = <&a76_0_thermal_idle 0 80>, 909 <&a76_1_thermal_idle 0 80>, 910 <&a76_2_thermal_idle 0 80>, 911 <&a76_3_thermal_idle 0 80>; 912 contribution = <512>; 913 }; 914 915 map3 { 916 /* At 80C, inhibit 1.0 GHz mode */ 917 trip = <&sensor3_passive_crit>; 918 cooling-device = <&a76_0 4 4>; 919 contribution = <1024>; 920 }; 921 }; 922 923 trips { 924 sensor3_passive_low: sensor3-passive-low { 925 temperature = <68000>; 926 hysteresis = <2000>; 927 type = "passive"; 928 }; 929 930 sensor3_passive_mid: sensor3-passive-mid { 931 temperature = <72000>; 932 hysteresis = <2000>; 933 type = "passive"; 934 }; 935 936 sensor3_passive_hi: sensor3-passive-hi { 937 temperature = <76000>; 938 hysteresis = <2000>; 939 type = "passive"; 940 }; 941 942 sensor3_passive_crit: sensor3-passive-crit { 943 temperature = <80000>; 944 hysteresis = <2000>; 945 type = "passive"; 946 }; 947 }; 948}; 949 950&sensor_thermal_cnn { 951 critical-action = "shutdown"; 952}; 953 954&sensor_thermal_cr52 { 955 critical-action = "shutdown"; 956}; 957 958&sensor_thermal_ddr1 { 959 critical-action = "shutdown"; 960}; 961