1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "dm_services.h"
28 #include "dm_helpers.h"
29 #include "core_types.h"
30 #include "resource.h"
31 #include "dccg.h"
32 #include "dce/dce_hwseq.h"
33 #include "dcn30/dcn30_cm_common.h"
34 #include "reg_helper.h"
35 #include "abm.h"
36 #include "hubp.h"
37 #include "dchubbub.h"
38 #include "timing_generator.h"
39 #include "opp.h"
40 #include "ipp.h"
41 #include "mpc.h"
42 #include "mcif_wb.h"
43 #include "dc_dmub_srv.h"
44 #include "link_hwss.h"
45 #include "dpcd_defs.h"
46 #include "dcn32_hwseq.h"
47 #include "clk_mgr.h"
48 #include "dsc.h"
49 #include "dcn20/dcn20_optc.h"
50 #include "dce/dmub_hw_lock_mgr.h"
51 #include "dcn32/dcn32_resource.h"
52 #include "link.h"
53 #include "../dcn20/dcn20_hwseq.h"
54 #include "dc_state_priv.h"
55
56 #define DC_LOGGER_INIT(logger)
57
58 #define CTX \
59 hws->ctx
60 #define REG(reg)\
61 hws->regs->reg
62 #define DC_LOGGER \
63 dc->ctx->logger
64
65 #undef FN
66 #define FN(reg_name, field_name) \
67 hws->shifts->field_name, hws->masks->field_name
68
dcn32_dsc_pg_control(struct dce_hwseq * hws,unsigned int dsc_inst,bool power_on)69 void dcn32_dsc_pg_control(
70 struct dce_hwseq *hws,
71 unsigned int dsc_inst,
72 bool power_on)
73 {
74 uint32_t power_gate = power_on ? 0 : 1;
75 uint32_t pwr_status = power_on ? 0 : 2;
76 uint32_t org_ip_request_cntl = 0;
77 struct dc *dc = hws->ctx->dc;
78
79 if (dc->debug.disable_dsc_power_gate)
80 return;
81
82 if (!dc->debug.enable_double_buffered_dsc_pg_support)
83 return;
84
85 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
86 if (org_ip_request_cntl == 0)
87 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
88
89 DC_LOG_DSC("%s DSC power gate for inst %d", power_gate ? "enable" : "disable", dsc_inst);
90 switch (dsc_inst) {
91 case 0: /* DSC0 */
92 REG_UPDATE(DOMAIN16_PG_CONFIG,
93 DOMAIN_POWER_GATE, power_gate);
94
95 REG_WAIT(DOMAIN16_PG_STATUS,
96 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
97 1, 1000);
98 break;
99 case 1: /* DSC1 */
100 REG_UPDATE(DOMAIN17_PG_CONFIG,
101 DOMAIN_POWER_GATE, power_gate);
102
103 REG_WAIT(DOMAIN17_PG_STATUS,
104 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
105 1, 1000);
106 break;
107 case 2: /* DSC2 */
108 REG_UPDATE(DOMAIN18_PG_CONFIG,
109 DOMAIN_POWER_GATE, power_gate);
110
111 REG_WAIT(DOMAIN18_PG_STATUS,
112 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
113 1, 1000);
114 break;
115 case 3: /* DSC3 */
116 REG_UPDATE(DOMAIN19_PG_CONFIG,
117 DOMAIN_POWER_GATE, power_gate);
118
119 REG_WAIT(DOMAIN19_PG_STATUS,
120 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
121 1, 1000);
122 break;
123 default:
124 BREAK_TO_DEBUGGER();
125 break;
126 }
127
128 if (org_ip_request_cntl == 0)
129 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
130 }
131
132
dcn32_enable_power_gating_plane(struct dce_hwseq * hws,bool enable)133 void dcn32_enable_power_gating_plane(
134 struct dce_hwseq *hws,
135 bool enable)
136 {
137 bool force_on = true; /* disable power gating */
138 uint32_t org_ip_request_cntl = 0;
139
140 if (enable)
141 force_on = false;
142
143 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
144 if (org_ip_request_cntl == 0)
145 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
146
147 /* DCHUBP0/1/2/3 */
148 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
149 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
150 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
151 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
152
153 /* DCS0/1/2/3 */
154 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
155 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
156 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
157 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
158
159 if (org_ip_request_cntl == 0)
160 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
161 }
162
dcn32_hubp_pg_control(struct dce_hwseq * hws,unsigned int hubp_inst,bool power_on)163 void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
164 {
165 uint32_t power_gate = power_on ? 0 : 1;
166 uint32_t pwr_status = power_on ? 0 : 2;
167
168 if (hws->ctx->dc->debug.disable_hubp_power_gate)
169 return;
170
171 if (REG(DOMAIN0_PG_CONFIG) == 0)
172 return;
173
174 switch (hubp_inst) {
175 case 0:
176 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
177 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
178 break;
179 case 1:
180 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
181 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
182 break;
183 case 2:
184 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
185 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
186 break;
187 case 3:
188 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
189 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
190 break;
191 default:
192 BREAK_TO_DEBUGGER();
193 break;
194 }
195 }
196
dcn32_check_no_memory_request_for_cab(struct dc * dc)197 static bool dcn32_check_no_memory_request_for_cab(struct dc *dc)
198 {
199 int i;
200
201 /* First, check no-memory-request case */
202 for (i = 0; i < dc->current_state->stream_count; i++) {
203 if ((dc->current_state->stream_status[i].plane_count) &&
204 (dc->current_state->streams[i]->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED))
205 /* Fail eligibility on a visible stream */
206 break;
207 }
208
209 if (i == dc->current_state->stream_count)
210 return true;
211
212 return false;
213 }
214
215
216 /* This function loops through every surface that needs to be cached in CAB for SS,
217 * and calculates the total number of ways required to store all surfaces (primary,
218 * meta, cursor).
219 */
dcn32_calculate_cab_allocation(struct dc * dc,struct dc_state * ctx)220 static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx)
221 {
222 int i;
223 uint32_t num_ways = 0;
224 uint32_t mall_ss_size_bytes = 0;
225
226 mall_ss_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_size_bytes;
227 // TODO add additional logic for PSR active stream exclusion optimization
228 // mall_ss_psr_active_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes;
229
230 // Include cursor size for CAB allocation
231 for (i = 0; i < dc->res_pool->pipe_count; i++) {
232 struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[i];
233
234 if (!pipe->stream || !pipe->plane_state)
235 continue;
236
237 mall_ss_size_bytes += dcn32_helper_calculate_mall_bytes_for_cursor(dc, pipe, false);
238 }
239
240 // Convert number of cache lines required to number of ways
241 if (dc->debug.force_mall_ss_num_ways > 0) {
242 num_ways = dc->debug.force_mall_ss_num_ways;
243 } else if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) {
244 num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, mall_ss_size_bytes);
245 } else {
246 num_ways = 0;
247 }
248
249 return num_ways;
250 }
251
dcn32_apply_idle_power_optimizations(struct dc * dc,bool enable)252 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable)
253 {
254 union dmub_rb_cmd cmd;
255 uint8_t i;
256 uint32_t ways;
257 int j;
258 bool mall_ss_unsupported = false;
259 struct dc_plane_state *plane = NULL;
260
261 if (!dc->ctx->dmub_srv)
262 return false;
263
264 for (i = 0; i < dc->current_state->stream_count; i++) {
265 /* MALL SS messaging is not supported with PSR at this time */
266 if (dc->current_state->streams[i] != NULL &&
267 dc->current_state->streams[i]->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
268 (dc->current_state->stream_count > 1 || (!dc->current_state->streams[i]->dpms_off &&
269 dc->current_state->stream_status[i].plane_count > 0)))
270 return false;
271 }
272
273 if (enable) {
274 /* 1. Check no memory request case for CAB.
275 * If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message
276 */
277 if (dcn32_check_no_memory_request_for_cab(dc)) {
278 /* Enable no-memory-requests case */
279 memset(&cmd, 0, sizeof(cmd));
280 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
281 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ;
282 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
283
284 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
285
286 return true;
287 }
288
289 /* 2. Check if all surfaces can fit in CAB.
290 * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message
291 * and configure HUBP's to fetch from MALL
292 */
293 ways = dcn32_calculate_cab_allocation(dc, dc->current_state);
294
295 /* MALL not supported with Stereo3D or TMZ surface. If any plane is using stereo,
296 * or TMZ surface, don't try to enter MALL.
297 */
298 for (i = 0; i < dc->current_state->stream_count; i++) {
299 for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) {
300 plane = dc->current_state->stream_status[i].plane_states[j];
301
302 if (plane->address.type == PLN_ADDR_TYPE_GRPH_STEREO ||
303 plane->address.tmz_surface) {
304 mall_ss_unsupported = true;
305 break;
306 }
307 }
308 if (mall_ss_unsupported)
309 break;
310 }
311 if (ways <= dc->caps.cache_num_ways && !mall_ss_unsupported) {
312 memset(&cmd, 0, sizeof(cmd));
313 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
314 cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB;
315 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
316 cmd.cab.cab_alloc_ways = (uint8_t)ways;
317
318 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
319
320 return true;
321 }
322
323 return false;
324 }
325
326 /* Disable CAB */
327 memset(&cmd, 0, sizeof(cmd));
328 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
329 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION;
330 cmd.cab.header.payload_bytes =
331 sizeof(cmd.cab) - sizeof(cmd.cab.header);
332
333 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
334
335 return true;
336 }
337
338 /* Send DMCUB message with SubVP pipe info
339 * - For each pipe in context, populate payload with required SubVP information
340 * if the pipe is using SubVP for MCLK switch
341 * - This function must be called while the DMUB HW lock is acquired by driver
342 */
dcn32_commit_subvp_config(struct dc * dc,struct dc_state * context)343 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context)
344 {
345 int i;
346 bool enable_subvp = false;
347
348 if (!dc->ctx || !dc->ctx->dmub_srv)
349 return;
350
351 for (i = 0; i < dc->res_pool->pipe_count; i++) {
352 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
353
354 if (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_MAIN) {
355 // There is at least 1 SubVP pipe, so enable SubVP
356 enable_subvp = true;
357 break;
358 }
359 }
360 dc_dmub_setup_subvp_dmub_command(dc, context, enable_subvp);
361 }
362
363 /* Sub-Viewport DMUB lock needs to be acquired by driver whenever SubVP is active and:
364 * 1. Any full update for any SubVP main pipe
365 * 2. Any immediate flip for any SubVP pipe
366 * 3. Any flip for DRR pipe
367 * 4. If SubVP was previously in use (i.e. in old context)
368 */
dcn32_subvp_pipe_control_lock(struct dc * dc,struct dc_state * context,bool lock,bool should_lock_all_pipes,struct pipe_ctx * top_pipe_to_program,bool subvp_prev_use)369 void dcn32_subvp_pipe_control_lock(struct dc *dc,
370 struct dc_state *context,
371 bool lock,
372 bool should_lock_all_pipes,
373 struct pipe_ctx *top_pipe_to_program,
374 bool subvp_prev_use)
375 {
376 unsigned int i = 0;
377 bool subvp_immediate_flip = false;
378 bool subvp_in_use = false;
379 struct pipe_ctx *pipe;
380 enum mall_stream_type pipe_mall_type = SUBVP_NONE;
381
382 for (i = 0; i < dc->res_pool->pipe_count; i++) {
383 pipe = &context->res_ctx.pipe_ctx[i];
384 pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);
385
386 if (pipe->stream && pipe->plane_state && pipe_mall_type == SUBVP_MAIN) {
387 subvp_in_use = true;
388 break;
389 }
390 }
391
392 if (top_pipe_to_program && top_pipe_to_program->stream && top_pipe_to_program->plane_state) {
393 if (dc_state_get_pipe_subvp_type(context, top_pipe_to_program) == SUBVP_MAIN &&
394 top_pipe_to_program->plane_state->flip_immediate)
395 subvp_immediate_flip = true;
396 }
397
398 // Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared.
399 if ((subvp_in_use && (should_lock_all_pipes || subvp_immediate_flip)) || (!subvp_in_use && subvp_prev_use)) {
400 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 };
401
402 if (!lock) {
403 for (i = 0; i < dc->res_pool->pipe_count; i++) {
404 pipe = &context->res_ctx.pipe_ctx[i];
405 if (pipe->stream && pipe->plane_state && pipe_mall_type == SUBVP_MAIN &&
406 should_lock_all_pipes)
407 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK);
408 }
409 }
410
411 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK;
412 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER;
413 hw_lock_cmd.bits.lock = lock;
414 hw_lock_cmd.bits.should_release = !lock;
415 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);
416 }
417 }
418
dcn32_subvp_pipe_control_lock_fast(union block_sequence_params * params)419 void dcn32_subvp_pipe_control_lock_fast(union block_sequence_params *params)
420 {
421 struct dc *dc = params->subvp_pipe_control_lock_fast_params.dc;
422 bool lock = params->subvp_pipe_control_lock_fast_params.lock;
423 bool subvp_immediate_flip = params->subvp_pipe_control_lock_fast_params.subvp_immediate_flip;
424
425 // Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared.
426 if (subvp_immediate_flip) {
427 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 };
428
429 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK;
430 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER;
431 hw_lock_cmd.bits.lock = lock;
432 hw_lock_cmd.bits.should_release = !lock;
433 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);
434 }
435 }
436
dcn32_set_mpc_shaper_3dlut(struct pipe_ctx * pipe_ctx,const struct dc_stream_state * stream)437 bool dcn32_set_mpc_shaper_3dlut(
438 struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream)
439 {
440 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
441 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
442 struct dc *dc = pipe_ctx->stream->ctx->dc;
443 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
444 bool result = false;
445
446 const struct pwl_params *shaper_lut = NULL;
447 //get the shaper lut params
448 if (stream->func_shaper) {
449 if (stream->func_shaper->type == TF_TYPE_HWPWL)
450 shaper_lut = &stream->func_shaper->pwl;
451 else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) {
452 cm_helper_translate_curve_to_hw_format(stream->ctx,
453 stream->func_shaper,
454 &dpp_base->shaper_params, true);
455 shaper_lut = &dpp_base->shaper_params;
456 }
457 }
458
459 if (stream->lut3d_func &&
460 stream->lut3d_func->state.bits.initialized == 1) {
461
462 result = mpc->funcs->program_3dlut(mpc, &stream->lut3d_func->lut_3d, mpcc_id);
463 if (!result)
464 DC_LOG_ERROR("%s: program_3dlut failed\n", __func__);
465
466 result = mpc->funcs->program_shaper(mpc, shaper_lut, mpcc_id);
467 if (!result)
468 DC_LOG_ERROR("%s: program_shaper failed\n", __func__);
469 }
470
471 return result;
472 }
473
dcn32_set_mcm_luts(struct pipe_ctx * pipe_ctx,const struct dc_plane_state * plane_state)474 bool dcn32_set_mcm_luts(
475 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
476 {
477 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
478 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
479 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
480 bool result = true;
481 const struct pwl_params *lut_params = NULL;
482
483 // 1D LUT
484 if (plane_state->blend_tf.type == TF_TYPE_HWPWL)
485 lut_params = &plane_state->blend_tf.pwl;
486 else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) {
487 result = cm3_helper_translate_curve_to_hw_format(&plane_state->blend_tf,
488 &dpp_base->regamma_params, false);
489 if (!result)
490 return result;
491
492 lut_params = &dpp_base->regamma_params;
493 }
494 mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id);
495 lut_params = NULL;
496
497 // Shaper
498 if (plane_state->in_shaper_func.type == TF_TYPE_HWPWL)
499 lut_params = &plane_state->in_shaper_func.pwl;
500 else if (plane_state->in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) {
501 // TODO: dpp_base replace
502 ASSERT(false);
503 cm3_helper_translate_curve_to_hw_format(&plane_state->in_shaper_func,
504 &dpp_base->shaper_params, true);
505 lut_params = &dpp_base->shaper_params;
506 }
507
508 mpc->funcs->program_shaper(mpc, lut_params, mpcc_id);
509
510 // 3D
511 if (plane_state->lut3d_func.state.bits.initialized == 1)
512 result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func.lut_3d, mpcc_id);
513 else
514 result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id);
515
516 return result;
517 }
518
dcn32_set_input_transfer_func(struct dc * dc,struct pipe_ctx * pipe_ctx,const struct dc_plane_state * plane_state)519 bool dcn32_set_input_transfer_func(struct dc *dc,
520 struct pipe_ctx *pipe_ctx,
521 const struct dc_plane_state *plane_state)
522 {
523 struct dce_hwseq *hws = dc->hwseq;
524 struct mpc *mpc = dc->res_pool->mpc;
525 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
526
527 enum dc_transfer_func_predefined tf;
528 bool result = true;
529 const struct pwl_params *params = NULL;
530
531 if (mpc == NULL || plane_state == NULL)
532 return false;
533
534 tf = TRANSFER_FUNCTION_UNITY;
535
536 if (plane_state->in_transfer_func.type == TF_TYPE_PREDEFINED)
537 tf = plane_state->in_transfer_func.tf;
538
539 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf);
540
541 if (plane_state->in_transfer_func.type == TF_TYPE_HWPWL)
542 params = &plane_state->in_transfer_func.pwl;
543 else if (plane_state->in_transfer_func.type == TF_TYPE_DISTRIBUTED_POINTS &&
544 cm3_helper_translate_curve_to_hw_format(&plane_state->in_transfer_func,
545 &dpp_base->degamma_params, false))
546 params = &dpp_base->degamma_params;
547
548 dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params);
549
550 if (pipe_ctx->stream_res.opp &&
551 pipe_ctx->stream_res.opp->ctx &&
552 hws->funcs.set_mcm_luts)
553 result = hws->funcs.set_mcm_luts(pipe_ctx, plane_state);
554
555 return result;
556 }
557
dcn32_set_output_transfer_func(struct dc * dc,struct pipe_ctx * pipe_ctx,const struct dc_stream_state * stream)558 bool dcn32_set_output_transfer_func(struct dc *dc,
559 struct pipe_ctx *pipe_ctx,
560 const struct dc_stream_state *stream)
561 {
562 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
563 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
564 const struct pwl_params *params = NULL;
565 bool ret = false;
566
567 /* program OGAM or 3DLUT only for the top pipe*/
568 if (resource_is_pipe_type(pipe_ctx, OPP_HEAD)) {
569 /*program shaper and 3dlut in MPC*/
570 ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream);
571 if (ret == false && mpc->funcs->set_output_gamma) {
572 if (stream->out_transfer_func.type == TF_TYPE_HWPWL)
573 params = &stream->out_transfer_func.pwl;
574 else if (pipe_ctx->stream->out_transfer_func.type ==
575 TF_TYPE_DISTRIBUTED_POINTS &&
576 cm3_helper_translate_curve_to_hw_format(
577 &stream->out_transfer_func,
578 &mpc->blender_params, false))
579 params = &mpc->blender_params;
580 /* there are no ROM LUTs in OUTGAM */
581 if (stream->out_transfer_func.type == TF_TYPE_PREDEFINED)
582 BREAK_TO_DEBUGGER();
583 }
584 }
585
586 if (mpc->funcs->set_output_gamma)
587 mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
588
589 return ret;
590 }
591
592 /* Program P-State force value according to if pipe is using SubVP / FPO or not:
593 * 1. Reset P-State force on all pipes first
594 * 2. For each main pipe, force P-State disallow (P-State allow moderated by DMUB)
595 */
dcn32_update_force_pstate(struct dc * dc,struct dc_state * context)596 void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context)
597 {
598 int i;
599
600 /* Unforce p-state for each pipe if it is not FPO or SubVP.
601 * For FPO and SubVP, if it's already forced disallow, leave
602 * it as disallow.
603 */
604 for (i = 0; i < dc->res_pool->pipe_count; i++) {
605 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
606 struct hubp *hubp = pipe->plane_res.hubp;
607 struct dc_stream_status *stream_status = NULL;
608
609 if (pipe->stream)
610 stream_status = dc_state_get_stream_status(context, pipe->stream);
611
612 if (!pipe->stream || !(dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN ||
613 (stream_status && stream_status->fpo_in_use))) {
614 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)
615 hubp->funcs->hubp_update_force_pstate_disallow(hubp, false);
616 if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow)
617 hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, false);
618 }
619 }
620
621 /* Loop through each pipe -- for each subvp main pipe force p-state allow equal to false.
622 */
623 for (i = 0; i < dc->res_pool->pipe_count; i++) {
624 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
625 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
626 struct hubp *hubp = pipe->plane_res.hubp;
627 struct dc_stream_status *stream_status = NULL;
628 struct dc_stream_status *old_stream_status = NULL;
629
630 /* Today for MED update type we do not call update clocks. However, for FPO
631 * the assumption is that update clocks should be called to disable P-State
632 * switch before any HW programming since FPO in FW and driver are not
633 * synchronized. This causes an issue where on a MED update, an FPO P-State
634 * switch could be taking place, then driver forces P-State disallow in the below
635 * code and prevents FPO from completing the sequence. In this case we add a check
636 * to avoid re-programming (and thus re-setting) the P-State force register by
637 * only reprogramming if the pipe was not previously Subvp or FPO. The assumption
638 * is that the P-State force register should be programmed correctly the first
639 * time SubVP / FPO was enabled, so there's no need to update / reset it if the
640 * pipe config has never exited SubVP / FPO.
641 */
642 if (pipe->stream)
643 stream_status = dc_state_get_stream_status(context, pipe->stream);
644 if (old_pipe->stream)
645 old_stream_status = dc_state_get_stream_status(dc->current_state, old_pipe->stream);
646
647 if (pipe->stream && (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN ||
648 (stream_status && stream_status->fpo_in_use)) &&
649 (!old_pipe->stream || (dc_state_get_pipe_subvp_type(dc->current_state, old_pipe) != SUBVP_MAIN &&
650 (old_stream_status && !old_stream_status->fpo_in_use)))) {
651 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)
652 hubp->funcs->hubp_update_force_pstate_disallow(hubp, true);
653 if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow)
654 hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, true);
655 }
656 }
657 }
658
659 /* Update MALL_SEL register based on if pipe / plane
660 * is a phantom pipe, main pipe, and if using MALL
661 * for SS.
662 */
dcn32_update_mall_sel(struct dc * dc,struct dc_state * context)663 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context)
664 {
665 int i;
666 unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context);
667 bool cache_cursor = false;
668
669 for (i = 0; i < dc->res_pool->pipe_count; i++) {
670 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
671 struct hubp *hubp = pipe->plane_res.hubp;
672
673 if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) {
674 int cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height;
675
676 switch (hubp->curs_attr.color_format) {
677 case CURSOR_MODE_MONO:
678 cursor_size /= 2;
679 break;
680 case CURSOR_MODE_COLOR_1BIT_AND:
681 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
682 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
683 cursor_size *= 4;
684 break;
685
686 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
687 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
688 default:
689 cursor_size *= 8;
690 break;
691 }
692
693 if (cursor_size > 16384)
694 cache_cursor = true;
695
696 if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {
697 hubp->funcs->hubp_update_mall_sel(hubp, 1, false);
698 } else {
699 // MALL not supported with Stereo3D
700 hubp->funcs->hubp_update_mall_sel(hubp,
701 num_ways <= dc->caps.cache_num_ways &&
702 pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &&
703 pipe->plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO &&
704 !pipe->plane_state->address.tmz_surface ? 2 : 0,
705 cache_cursor);
706 }
707 }
708 }
709 }
710
711 /* Program the sub-viewport pipe configuration after the main / phantom pipes
712 * have been programmed in hardware.
713 * 1. Update force P-State for all the main pipes (disallow P-state)
714 * 2. Update MALL_SEL register
715 * 3. Program FORCE_ONE_ROW_FOR_FRAME for main subvp pipes
716 */
dcn32_program_mall_pipe_config(struct dc * dc,struct dc_state * context)717 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context)
718 {
719 int i;
720 struct dce_hwseq *hws = dc->hwseq;
721
722 // Don't force p-state disallow -- can't block dummy p-state
723
724 // Update MALL_SEL register for each pipe
725 if (hws && hws->funcs.update_mall_sel)
726 hws->funcs.update_mall_sel(dc, context);
727
728 // Program FORCE_ONE_ROW_FOR_FRAME and CURSOR_REQ_MODE for main subvp pipes
729 for (i = 0; i < dc->res_pool->pipe_count; i++) {
730 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
731 struct hubp *hubp = pipe->plane_res.hubp;
732
733 if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) {
734 /* TODO - remove setting CURSOR_REQ_MODE to 0 for legacy cases
735 * - need to investigate single pipe MPO + SubVP case to
736 * see if CURSOR_REQ_MODE will be back to 1 for SubVP
737 * when it should be 0 for MPO
738 */
739 if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN)
740 hubp->funcs->hubp_prepare_subvp_buffering(hubp, true);
741 }
742 }
743 }
744
dcn32_initialize_min_clocks(struct dc * dc)745 static void dcn32_initialize_min_clocks(struct dc *dc)
746 {
747 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk;
748
749 clocks->dcfclk_deep_sleep_khz = DCN3_2_DCFCLK_DS_INIT_KHZ;
750 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000;
751 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000;
752 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000;
753 clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000;
754 clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
755 clocks->fclk_p_state_change_support = true;
756 clocks->p_state_change_support = true;
757 if (dc->debug.disable_boot_optimizations) {
758 clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000;
759 } else {
760 /* Even though DPG_EN = 1 for the connected display, it still requires the
761 * correct timing so we cannot set DISPCLK to min freq or it could cause
762 * audio corruption. Read current DISPCLK from DENTIST and request the same
763 * freq to ensure that the timing is valid and unchanged.
764 */
765 clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr);
766 }
767
768 dc->clk_mgr->funcs->update_clocks(
769 dc->clk_mgr,
770 dc->current_state,
771 true);
772 }
773
dcn32_init_hw(struct dc * dc)774 void dcn32_init_hw(struct dc *dc)
775 {
776 struct abm **abms = dc->res_pool->multiple_abms;
777 struct dce_hwseq *hws = dc->hwseq;
778 struct dc_bios *dcb = dc->ctx->dc_bios;
779 struct resource_pool *res_pool = dc->res_pool;
780 int i;
781 int edp_num;
782 uint32_t backlight = MAX_BACKLIGHT_LEVEL;
783 uint32_t user_level = MAX_BACKLIGHT_LEVEL;
784
785 if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->init_clocks)
786 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
787
788 // Initialize the dccg
789 if (res_pool->dccg->funcs->dccg_init)
790 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
791
792 if (!dcb->funcs->is_accelerated_mode(dcb)) {
793 hws->funcs.bios_golden_init(dc);
794 hws->funcs.disable_vga(dc->hwseq);
795 }
796
797 // Set default OPTC memory power states
798 if (dc->debug.enable_mem_low_power.bits.optc) {
799 // Shutdown when unassigned and light sleep in VBLANK
800 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
801 }
802
803 if (dc->debug.enable_mem_low_power.bits.vga) {
804 // Power down VGA memory
805 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
806 }
807
808 if (dc->ctx->dc_bios->fw_info_valid) {
809 res_pool->ref_clocks.xtalin_clock_inKhz =
810 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
811
812 if (res_pool->hubbub) {
813 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
814 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
815 &res_pool->ref_clocks.dccg_ref_clock_inKhz);
816
817 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
818 res_pool->ref_clocks.dccg_ref_clock_inKhz,
819 &res_pool->ref_clocks.dchub_ref_clock_inKhz);
820 } else {
821 // Not all ASICs have DCCG sw component
822 res_pool->ref_clocks.dccg_ref_clock_inKhz =
823 res_pool->ref_clocks.xtalin_clock_inKhz;
824 res_pool->ref_clocks.dchub_ref_clock_inKhz =
825 res_pool->ref_clocks.xtalin_clock_inKhz;
826 }
827 } else
828 ASSERT_CRITICAL(false);
829
830 for (i = 0; i < dc->link_count; i++) {
831 /* Power up AND update implementation according to the
832 * required signal (which may be different from the
833 * default signal on connector).
834 */
835 struct dc_link *link = dc->links[i];
836
837 link->link_enc->funcs->hw_init(link->link_enc);
838
839 /* Check for enabled DIG to identify enabled display */
840 if (link->link_enc->funcs->is_dig_enabled &&
841 link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
842 link->link_status.link_active = true;
843 link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
844 if (link->link_enc->funcs->fec_is_active &&
845 link->link_enc->funcs->fec_is_active(link->link_enc))
846 link->fec_state = dc_link_fec_enabled;
847 }
848 }
849
850 /* enable_power_gating_plane before dsc_pg_control because
851 * FORCEON = 1 with hw default value on bootup, resume from s3
852 */
853 if (hws->funcs.enable_power_gating_plane)
854 hws->funcs.enable_power_gating_plane(dc->hwseq, true);
855
856 /* we want to turn off all dp displays before doing detection */
857 dc->link_srv->blank_all_dp_displays(dc);
858
859 /* If taking control over from VBIOS, we may want to optimize our first
860 * mode set, so we need to skip powering down pipes until we know which
861 * pipes we want to use.
862 * Otherwise, if taking control is not possible, we need to power
863 * everything down.
864 */
865 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {
866 /* Disable boot optimizations means power down everything including PHY, DIG,
867 * and OTG (i.e. the boot is not optimized because we do a full power down).
868 */
869 if (dc->hwss.enable_accelerated_mode && dc->debug.disable_boot_optimizations)
870 dc->hwss.enable_accelerated_mode(dc, dc->current_state);
871 else
872 hws->funcs.init_pipes(dc, dc->current_state);
873
874 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
875 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
876 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
877
878 dcn32_initialize_min_clocks(dc);
879
880 /* On HW init, allow idle optimizations after pipes have been turned off.
881 *
882 * In certain D3 cases (i.e. BOCO / BOMACO) it's possible that hardware state
883 * is reset (i.e. not in idle at the time hw init is called), but software state
884 * still has idle_optimizations = true, so we must disable idle optimizations first
885 * (i.e. set false), then re-enable (set true).
886 */
887 dc_allow_idle_optimizations(dc, false);
888 dc_allow_idle_optimizations(dc, true);
889 }
890
891 /* In headless boot cases, DIG may be turned
892 * on which causes HW/SW discrepancies.
893 * To avoid this, power down hardware on boot
894 * if DIG is turned on and seamless boot not enabled
895 */
896 if (!dc->config.seamless_boot_edp_requested) {
897 struct dc_link *edp_links[MAX_NUM_EDP];
898 struct dc_link *edp_link;
899
900 dc_get_edp_links(dc, edp_links, &edp_num);
901 if (edp_num) {
902 for (i = 0; i < edp_num; i++) {
903 edp_link = edp_links[i];
904 if (edp_link->link_enc->funcs->is_dig_enabled &&
905 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
906 dc->hwss.edp_backlight_control &&
907 hws->funcs.power_down &&
908 dc->hwss.edp_power_control) {
909 dc->hwss.edp_backlight_control(edp_link, false);
910 hws->funcs.power_down(dc);
911 dc->hwss.edp_power_control(edp_link, false);
912 }
913 }
914 } else {
915 for (i = 0; i < dc->link_count; i++) {
916 struct dc_link *link = dc->links[i];
917
918 if (link->link_enc->funcs->is_dig_enabled &&
919 link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
920 hws->funcs.power_down) {
921 hws->funcs.power_down(dc);
922 break;
923 }
924
925 }
926 }
927 }
928
929 for (i = 0; i < res_pool->audio_count; i++) {
930 struct audio *audio = res_pool->audios[i];
931
932 audio->funcs->hw_init(audio);
933 }
934
935 for (i = 0; i < dc->link_count; i++) {
936 struct dc_link *link = dc->links[i];
937
938 if (link->panel_cntl) {
939 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
940 user_level = link->panel_cntl->stored_backlight_registers.USER_LEVEL;
941 }
942 }
943
944 for (i = 0; i < dc->res_pool->pipe_count; i++) {
945 if (abms[i] != NULL && abms[i]->funcs != NULL)
946 abms[i]->funcs->abm_init(abms[i], backlight, user_level);
947 }
948
949 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
950 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
951
952 if (!dc->debug.disable_clock_gate) {
953 /* enable all DCN clock gating */
954 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
955
956 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
957
958 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
959 }
960
961 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
962 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
963
964 if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->notify_wm_ranges)
965 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
966
967 if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->set_hard_max_memclk &&
968 !dc->clk_mgr->dc_mode_softmax_enabled)
969 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
970
971 if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
972 dc->res_pool->hubbub->funcs->force_pstate_change_control(
973 dc->res_pool->hubbub, false, false);
974
975 if (dc->res_pool->hubbub->funcs->init_crb)
976 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
977
978 if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0)
979 dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc);
980
981 // Get DMCUB capabilities
982 if (dc->ctx->dmub_srv) {
983 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);
984 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
985 dc->caps.dmub_caps.subvp_psr = dc->ctx->dmub_srv->dmub->feature_caps.subvp_psr_support;
986 dc->caps.dmub_caps.gecc_enable = dc->ctx->dmub_srv->dmub->feature_caps.gecc_enable;
987 dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;
988 dc->caps.dmub_caps.aux_backlight_support = dc->ctx->dmub_srv->dmub->feature_caps.abm_aux_backlight_support;
989
990 /* for DCN401 testing only */
991 dc->caps.dmub_caps.fams_ver = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;
992 if (dc->caps.dmub_caps.fams_ver == 2) {
993 /* FAMS2 is enabled */
994 dc->debug.fams2_config.bits.enable &= true;
995 } else if (dc->ctx->dmub_srv->dmub->fw_version <
996 DMUB_FW_VERSION(7, 0, 35)) {
997 /* FAMS2 is disabled */
998 dc->debug.fams2_config.bits.enable = false;
999 if (dc->debug.using_dml2 && dc->res_pool->funcs->update_bw_bounding_box) {
1000 /* update bounding box if FAMS2 disabled */
1001 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
1002 }
1003 dc->debug.force_disable_subvp = true;
1004 dc->debug.disable_fpo_optimizations = true;
1005 }
1006 }
1007 }
1008
dcn32_update_dsc_on_stream(struct pipe_ctx * pipe_ctx,bool enable)1009 void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
1010 {
1011 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
1012 struct dc *dc = pipe_ctx->stream->ctx->dc;
1013 struct dc_stream_state *stream = pipe_ctx->stream;
1014 struct pipe_ctx *odm_pipe;
1015 int opp_cnt = 1;
1016 struct dccg *dccg = dc->res_pool->dccg;
1017 /* It has been found that when DSCCLK is lower than 16Mhz, we will get DCN
1018 * register access hung. When DSCCLk is based on refclk, DSCCLk is always a
1019 * fixed value higher than 16Mhz so the issue doesn't occur. When DSCCLK is
1020 * generated by DTO, DSCCLK would be based on 1/3 dispclk. For small timings
1021 * with DSC such as 480p60Hz, the dispclk could be low enough to trigger
1022 * this problem. We are implementing a workaround here to keep using dscclk
1023 * based on fixed value refclk when timing is smaller than 3x16Mhz (i.e
1024 * 48Mhz) pixel clock to avoid hitting this problem.
1025 */
1026 bool should_use_dto_dscclk = (dccg->funcs->set_dto_dscclk != NULL) &&
1027 stream->timing.pix_clk_100hz > 480000;
1028
1029 ASSERT(dsc);
1030 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1031 opp_cnt++;
1032
1033 if (enable) {
1034 struct dsc_config dsc_cfg;
1035 struct dsc_optc_config dsc_optc_cfg = {0};
1036 enum optc_dsc_mode optc_dsc_mode;
1037 struct dcn_dsc_state dsc_state = {0};
1038
1039 if (!dsc) {
1040 DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst);
1041 return;
1042 }
1043
1044 if (dsc->funcs->dsc_read_state) {
1045 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1046 if (!dsc_state.dsc_fw_en) {
1047 DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst);
1048 return;
1049 }
1050 }
1051
1052 /* Enable DSC hw block */
1053 dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->hblank_borrow +
1054 stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
1055 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
1056 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
1057 dsc_cfg.color_depth = stream->timing.display_color_depth;
1058 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
1059 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
1060 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
1061 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
1062
1063 if (should_use_dto_dscclk)
1064 dccg->funcs->set_dto_dscclk(dccg, dsc->inst);
1065 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
1066 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
1067 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1068 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;
1069
1070 ASSERT(odm_dsc);
1071 if (should_use_dto_dscclk)
1072 dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst);
1073 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg);
1074 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);
1075 }
1076 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
1077 /* Enable DSC in OPTC */
1078 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
1079 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,
1080 optc_dsc_mode,
1081 dsc_optc_cfg.bytes_per_pixel,
1082 dsc_optc_cfg.slice_width);
1083 } else {
1084 /* disable DSC in OPTC */
1085 pipe_ctx->stream_res.tg->funcs->set_dsc_config(
1086 pipe_ctx->stream_res.tg,
1087 OPTC_DSC_DISABLED, 0, 0);
1088
1089 /* only disconnect DSC block, DSC is disabled when OPP head pipe is reset */
1090 dsc->funcs->dsc_disconnect(pipe_ctx->stream_res.dsc);
1091 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1092 ASSERT(odm_pipe->stream_res.dsc);
1093 odm_pipe->stream_res.dsc->funcs->dsc_disconnect(odm_pipe->stream_res.dsc);
1094 }
1095 }
1096 }
1097
1098 /*
1099 * Given any pipe_ctx, return the total ODM combine factor, and optionally return
1100 * the OPPids which are used
1101 * */
get_odm_config(struct pipe_ctx * pipe_ctx,unsigned int * opp_instances)1102 static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances)
1103 {
1104 unsigned int opp_count = 1;
1105 struct pipe_ctx *odm_pipe;
1106
1107 /* First get to the top pipe */
1108 for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe)
1109 ;
1110
1111 /* First pipe is always used */
1112 if (opp_instances)
1113 opp_instances[0] = odm_pipe->stream_res.opp->inst;
1114
1115 /* Find and count odm pipes, if any */
1116 for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1117 if (opp_instances)
1118 opp_instances[opp_count] = odm_pipe->stream_res.opp->inst;
1119 opp_count++;
1120 }
1121
1122 return opp_count;
1123 }
1124
dcn32_update_odm(struct dc * dc,struct dc_state * context,struct pipe_ctx * pipe_ctx)1125 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
1126 {
1127 struct pipe_ctx *odm_pipe;
1128 int opp_cnt = 0;
1129 int opp_inst[MAX_PIPES] = {0};
1130 int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);
1131 int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);
1132
1133 opp_cnt = get_odm_config(pipe_ctx, opp_inst);
1134
1135 if (opp_cnt > 1)
1136 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
1137 pipe_ctx->stream_res.tg,
1138 opp_inst, opp_cnt,
1139 odm_slice_width, last_odm_slice_width);
1140 else
1141 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
1142 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1143
1144 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1145 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
1146 odm_pipe->stream_res.opp,
1147 true);
1148 odm_pipe->stream_res.opp->funcs->opp_program_left_edge_extra_pixel(
1149 odm_pipe->stream_res.opp,
1150 pipe_ctx->stream->timing.pixel_encoding,
1151 resource_is_pipe_type(odm_pipe, OTG_MASTER));
1152 }
1153
1154 if (pipe_ctx->stream_res.dsc) {
1155 struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
1156
1157 dcn32_update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);
1158
1159 /* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */
1160 if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe &&
1161 current_pipe_ctx->next_odm_pipe->stream_res.dsc) {
1162 struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc;
1163
1164 /* disconnect DSC block from stream */
1165 dsc->funcs->dsc_disconnect(dsc);
1166 }
1167 }
1168
1169 if (!resource_is_pipe_type(pipe_ctx, DPP_PIPE))
1170 /*
1171 * blank pattern is generated by OPP, reprogram blank pattern
1172 * due to OPP count change
1173 */
1174 dc->hwseq->funcs.blank_pixel_data(dc, pipe_ctx, true);
1175 }
1176
dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx * pipe_ctx,unsigned int * k1_div,unsigned int * k2_div)1177 unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)
1178 {
1179 struct dc_stream_state *stream = pipe_ctx->stream;
1180 unsigned int odm_combine_factor = 0;
1181 bool two_pix_per_container = false;
1182
1183 two_pix_per_container = pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);
1184 odm_combine_factor = get_odm_config(pipe_ctx, NULL);
1185
1186 if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1187 *k1_div = PIXEL_RATE_DIV_BY_1;
1188 *k2_div = PIXEL_RATE_DIV_BY_1;
1189 } else if (dc_is_hdmi_tmds_signal(stream->signal) || dc_is_dvi_signal(stream->signal)) {
1190 *k1_div = PIXEL_RATE_DIV_BY_1;
1191 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1192 *k2_div = PIXEL_RATE_DIV_BY_2;
1193 else
1194 *k2_div = PIXEL_RATE_DIV_BY_4;
1195 } else if (dc_is_dp_signal(stream->signal) || dc_is_virtual_signal(stream->signal)) {
1196 if (two_pix_per_container) {
1197 *k1_div = PIXEL_RATE_DIV_BY_1;
1198 *k2_div = PIXEL_RATE_DIV_BY_2;
1199 } else {
1200 *k1_div = PIXEL_RATE_DIV_BY_1;
1201 *k2_div = PIXEL_RATE_DIV_BY_4;
1202 if ((odm_combine_factor == 2) || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx))
1203 *k2_div = PIXEL_RATE_DIV_BY_2;
1204 }
1205 }
1206
1207 if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA))
1208 ASSERT(false);
1209
1210 return odm_combine_factor;
1211 }
1212
dcn32_calculate_pix_rate_divider(struct dc * dc,struct dc_state * context,const struct dc_stream_state * stream)1213 void dcn32_calculate_pix_rate_divider(
1214 struct dc *dc,
1215 struct dc_state *context,
1216 const struct dc_stream_state *stream)
1217 {
1218 struct dce_hwseq *hws = dc->hwseq;
1219 struct pipe_ctx *pipe_ctx = NULL;
1220 unsigned int k1_div = PIXEL_RATE_DIV_NA;
1221 unsigned int k2_div = PIXEL_RATE_DIV_NA;
1222
1223 pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);
1224
1225 if (pipe_ctx) {
1226
1227 if (hws->funcs.calculate_dccg_k1_k2_values)
1228 hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);
1229
1230 pipe_ctx->pixel_rate_divider.div_factor1 = k1_div;
1231 pipe_ctx->pixel_rate_divider.div_factor2 = k2_div;
1232 }
1233 }
1234
dcn32_resync_fifo_dccg_dio(struct dce_hwseq * hws,struct dc * dc,struct dc_state * context,unsigned int current_pipe_idx)1235 void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx)
1236 {
1237 unsigned int i;
1238 struct pipe_ctx *pipe = NULL;
1239 bool otg_disabled[MAX_PIPES] = {false};
1240 struct dc_state *dc_state = NULL;
1241
1242 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1243 if (i <= current_pipe_idx) {
1244 pipe = &context->res_ctx.pipe_ctx[i];
1245 dc_state = context;
1246 } else {
1247 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1248 dc_state = dc->current_state;
1249 }
1250
1251 if (!resource_is_pipe_type(pipe, OTG_MASTER))
1252 continue;
1253
1254 if ((pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))
1255 && dc_state_get_pipe_subvp_type(dc_state, pipe) != SUBVP_PHANTOM) {
1256 pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg);
1257 reset_sync_context_for_pipe(dc, context, i);
1258 otg_disabled[i] = true;
1259 }
1260 }
1261
1262 hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg);
1263
1264 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1265 if (i <= current_pipe_idx)
1266 pipe = &context->res_ctx.pipe_ctx[i];
1267 else
1268 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1269
1270 if (otg_disabled[i]) {
1271 int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst };
1272 int opp_cnt = 1;
1273 int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe, true);
1274 int odm_slice_width = resource_get_odm_slice_dst_width(pipe, false);
1275 struct pipe_ctx *odm_pipe;
1276
1277 for (odm_pipe = pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1278 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
1279 opp_cnt++;
1280 }
1281 if (opp_cnt > 1)
1282 pipe->stream_res.tg->funcs->set_odm_combine(
1283 pipe->stream_res.tg,
1284 opp_inst, opp_cnt,
1285 odm_slice_width,
1286 last_odm_slice_width);
1287 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
1288 }
1289 }
1290
1291 dc_trigger_sync(dc, dc->current_state);
1292 }
1293
dcn32_unblank_stream(struct pipe_ctx * pipe_ctx,struct dc_link_settings * link_settings)1294 void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx,
1295 struct dc_link_settings *link_settings)
1296 {
1297 struct encoder_unblank_param params = {0};
1298 struct dc_stream_state *stream = pipe_ctx->stream;
1299 struct dc_link *link = stream->link;
1300 struct dce_hwseq *hws = link->dc->hwseq;
1301 struct pipe_ctx *odm_pipe;
1302
1303 params.opp_cnt = 1;
1304 params.pix_per_cycle = pipe_ctx->stream_res.pix_clk_params.dio_se_pix_per_cycle;
1305
1306 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1307 params.opp_cnt++;
1308
1309 /* only 3 items below are used by unblank */
1310 params.timing = pipe_ctx->stream->timing;
1311
1312 params.link_settings.link_rate = link_settings->link_rate;
1313
1314 if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1315 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */
1316 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(
1317 pipe_ctx->stream_res.hpo_dp_stream_enc,
1318 pipe_ctx->stream_res.tg->inst);
1319 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1320 if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing) ||
1321 params.opp_cnt > 1) {
1322 params.timing.pix_clk_100hz /= 2;
1323 params.pix_per_cycle = 2;
1324 }
1325 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
1326 pipe_ctx->stream_res.stream_enc, params.pix_per_cycle > 1);
1327 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms);
1328 }
1329
1330 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP)
1331 hws->funcs.edp_backlight_control(link, true);
1332 }
1333
dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx * pipe_ctx)1334 bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx)
1335 {
1336 struct dc *dc = pipe_ctx->stream->ctx->dc;
1337
1338 if (!is_h_timing_divisible_by_2(pipe_ctx->stream))
1339 return false;
1340
1341 if (dc_is_dp_signal(pipe_ctx->stream->signal) && !dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) &&
1342 dc->debug.enable_dp_dig_pixel_rate_div_policy)
1343 return true;
1344 return false;
1345 }
1346
apply_symclk_on_tx_off_wa(struct dc_link * link)1347 static void apply_symclk_on_tx_off_wa(struct dc_link *link)
1348 {
1349 /* There are use cases where SYMCLK is referenced by OTG. For instance
1350 * for TMDS signal, OTG relies SYMCLK even if TX video output is off.
1351 * However current link interface will power off PHY when disabling link
1352 * output. This will turn off SYMCLK generated by PHY. The workaround is
1353 * to identify such case where SYMCLK is still in use by OTG when we
1354 * power off PHY. When this is detected, we will temporarily power PHY
1355 * back on and move PHY's SYMCLK state to SYMCLK_ON_TX_OFF by calling
1356 * program_pix_clk interface. When OTG is disabled, we will then power
1357 * off PHY by calling disable link output again.
1358 *
1359 * In future dcn generations, we plan to rework transmitter control
1360 * interface so that we could have an option to set SYMCLK ON TX OFF
1361 * state in one step without this workaround
1362 */
1363
1364 struct dc *dc = link->ctx->dc;
1365 struct pipe_ctx *pipe_ctx = NULL;
1366 uint8_t i;
1367
1368 if (link->phy_state.symclk_ref_cnts.otg > 0) {
1369 for (i = 0; i < MAX_PIPES; i++) {
1370 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
1371 if (resource_is_pipe_type(pipe_ctx, OPP_HEAD) && pipe_ctx->stream->link == link) {
1372 pipe_ctx->clock_source->funcs->program_pix_clk(
1373 pipe_ctx->clock_source,
1374 &pipe_ctx->stream_res.pix_clk_params,
1375 dc->link_srv->dp_get_encoding_format(
1376 &pipe_ctx->link_config.dp_link_settings),
1377 &pipe_ctx->pll_settings);
1378 link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
1379 break;
1380 }
1381 }
1382 }
1383 }
1384
dcn32_disable_link_output(struct dc_link * link,const struct link_resource * link_res,enum signal_type signal)1385 void dcn32_disable_link_output(struct dc_link *link,
1386 const struct link_resource *link_res,
1387 enum signal_type signal)
1388 {
1389 struct dc *dc = link->ctx->dc;
1390 const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
1391 struct dmcu *dmcu = dc->res_pool->dmcu;
1392
1393 if (signal == SIGNAL_TYPE_EDP &&
1394 link->dc->hwss.edp_backlight_control &&
1395 !link->skip_implict_edp_power_control)
1396 link->dc->hwss.edp_backlight_control(link, false);
1397 else if (dmcu != NULL && dmcu->funcs->lock_phy)
1398 dmcu->funcs->lock_phy(dmcu);
1399
1400 link_hwss->disable_link_output(link, link_res, signal);
1401 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
1402 /*
1403 * Add the logic to extract BOTH power up and power down sequences
1404 * from enable/disable link output and only call edp panel control
1405 * in enable_link_dp and disable_link_dp once.
1406 */
1407 if (dmcu != NULL && dmcu->funcs->unlock_phy)
1408 dmcu->funcs->unlock_phy(dmcu);
1409
1410 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);
1411
1412 apply_symclk_on_tx_off_wa(link);
1413 }
1414
1415 /* For SubVP the main pipe can have a viewport position change
1416 * without a full update. In this case we must also update the
1417 * viewport positions for the phantom pipe accordingly.
1418 */
dcn32_update_phantom_vp_position(struct dc * dc,struct dc_state * context,struct pipe_ctx * phantom_pipe)1419 void dcn32_update_phantom_vp_position(struct dc *dc,
1420 struct dc_state *context,
1421 struct pipe_ctx *phantom_pipe)
1422 {
1423 uint32_t i;
1424 struct dc_plane_state *phantom_plane = phantom_pipe->plane_state;
1425
1426 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1427 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1428
1429 if (pipe->stream && dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN &&
1430 dc_state_get_paired_subvp_stream(context, pipe->stream) == phantom_pipe->stream) {
1431 if (pipe->plane_state && pipe->plane_state->update_flags.bits.position_change) {
1432
1433 phantom_plane->src_rect.x = pipe->plane_state->src_rect.x;
1434 phantom_plane->src_rect.y = pipe->plane_state->src_rect.y;
1435 phantom_plane->clip_rect.x = pipe->plane_state->clip_rect.x;
1436 phantom_plane->dst_rect.x = pipe->plane_state->dst_rect.x;
1437 phantom_plane->dst_rect.y = pipe->plane_state->dst_rect.y;
1438
1439 phantom_pipe->plane_state->update_flags.bits.position_change = 1;
1440 resource_build_scaling_params(phantom_pipe);
1441 return;
1442 }
1443 }
1444 }
1445 }
1446
1447 /* Treat the phantom pipe as if it needs to be fully enabled.
1448 * If the pipe was previously in use but not phantom, it would
1449 * have been disabled earlier in the sequence so we need to run
1450 * the full enable sequence.
1451 */
dcn32_apply_update_flags_for_phantom(struct pipe_ctx * phantom_pipe)1452 void dcn32_apply_update_flags_for_phantom(struct pipe_ctx *phantom_pipe)
1453 {
1454 phantom_pipe->update_flags.raw = 0;
1455 if (resource_is_pipe_type(phantom_pipe, DPP_PIPE)) {
1456 phantom_pipe->update_flags.bits.enable = 1;
1457 phantom_pipe->update_flags.bits.mpcc = 1;
1458 phantom_pipe->update_flags.bits.dppclk = 1;
1459 phantom_pipe->update_flags.bits.hubp_interdependent = 1;
1460 phantom_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1461 phantom_pipe->update_flags.bits.gamut_remap = 1;
1462 phantom_pipe->update_flags.bits.scaler = 1;
1463 phantom_pipe->update_flags.bits.viewport = 1;
1464 phantom_pipe->update_flags.bits.det_size = 1;
1465 if (resource_is_pipe_type(phantom_pipe, OTG_MASTER)) {
1466 phantom_pipe->update_flags.bits.odm = 1;
1467 phantom_pipe->update_flags.bits.global_sync = 1;
1468 }
1469 }
1470 }
1471
dcn32_dsc_pg_status(struct dce_hwseq * hws,unsigned int dsc_inst)1472 bool dcn32_dsc_pg_status(
1473 struct dce_hwseq *hws,
1474 unsigned int dsc_inst)
1475 {
1476 uint32_t pwr_status = 0;
1477
1478 switch (dsc_inst) {
1479 case 0: /* DSC0 */
1480 REG_GET(DOMAIN16_PG_STATUS,
1481 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
1482 break;
1483 case 1: /* DSC1 */
1484
1485 REG_GET(DOMAIN17_PG_STATUS,
1486 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
1487 break;
1488 case 2: /* DSC2 */
1489 REG_GET(DOMAIN18_PG_STATUS,
1490 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
1491 break;
1492 case 3: /* DSC3 */
1493 REG_GET(DOMAIN19_PG_STATUS,
1494 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
1495 break;
1496 default:
1497 BREAK_TO_DEBUGGER();
1498 break;
1499 }
1500
1501 return pwr_status == 0;
1502 }
1503
dcn32_update_dsc_pg(struct dc * dc,struct dc_state * context,bool safe_to_disable)1504 void dcn32_update_dsc_pg(struct dc *dc,
1505 struct dc_state *context,
1506 bool safe_to_disable)
1507 {
1508 struct dce_hwseq *hws = dc->hwseq;
1509 int i;
1510
1511 for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {
1512 struct display_stream_compressor *dsc = dc->res_pool->dscs[i];
1513 bool is_dsc_ungated = hws->funcs.dsc_pg_status(hws, dsc->inst);
1514
1515 if (context->res_ctx.is_dsc_acquired[i]) {
1516 if (!is_dsc_ungated) {
1517 hws->funcs.dsc_pg_control(hws, dsc->inst, true);
1518 }
1519 } else if (safe_to_disable) {
1520 if (is_dsc_ungated) {
1521 hws->funcs.dsc_pg_control(hws, dsc->inst, false);
1522 }
1523 }
1524 }
1525 }
1526
dcn32_disable_phantom_streams(struct dc * dc,struct dc_state * context)1527 void dcn32_disable_phantom_streams(struct dc *dc, struct dc_state *context)
1528 {
1529 struct dce_hwseq *hws = dc->hwseq;
1530 int i;
1531
1532 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
1533 struct pipe_ctx *pipe_ctx_old =
1534 &dc->current_state->res_ctx.pipe_ctx[i];
1535 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1536
1537 if (!pipe_ctx_old->stream)
1538 continue;
1539
1540 if (dc_state_get_pipe_subvp_type(dc->current_state, pipe_ctx_old) != SUBVP_PHANTOM)
1541 continue;
1542
1543 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
1544 continue;
1545
1546 if (!pipe_ctx->stream || pipe_need_reprogram(pipe_ctx_old, pipe_ctx) ||
1547 (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)) {
1548 struct clock_source *old_clk = pipe_ctx_old->clock_source;
1549
1550 if (hws->funcs.reset_back_end_for_pipe)
1551 hws->funcs.reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
1552 if (hws->funcs.enable_stream_gating)
1553 hws->funcs.enable_stream_gating(dc, pipe_ctx_old);
1554 if (old_clk)
1555 old_clk->funcs->cs_power_down(old_clk);
1556 }
1557 }
1558 }
1559
dcn32_enable_phantom_streams(struct dc * dc,struct dc_state * context)1560 void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context)
1561 {
1562 unsigned int i;
1563 enum dc_status status = DC_OK;
1564 struct dce_hwseq *hws = dc->hwseq;
1565
1566 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1567 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1568 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1569
1570 /* If an active, non-phantom pipe is being transitioned into a phantom
1571 * pipe, wait for the double buffer update to complete first before we do
1572 * ANY phantom pipe programming.
1573 */
1574 if (pipe->stream && dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM &&
1575 old_pipe->stream && dc_state_get_pipe_subvp_type(dc->current_state, old_pipe) != SUBVP_PHANTOM) {
1576 old_pipe->stream_res.tg->funcs->wait_for_state(
1577 old_pipe->stream_res.tg,
1578 CRTC_STATE_VBLANK);
1579 old_pipe->stream_res.tg->funcs->wait_for_state(
1580 old_pipe->stream_res.tg,
1581 CRTC_STATE_VACTIVE);
1582 }
1583 }
1584 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1585 struct pipe_ctx *pipe_ctx_old =
1586 &dc->current_state->res_ctx.pipe_ctx[i];
1587 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1588
1589 if (pipe_ctx->stream == NULL)
1590 continue;
1591
1592 if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)
1593 continue;
1594
1595 if (pipe_ctx->stream == pipe_ctx_old->stream &&
1596 pipe_ctx->stream->link->link_state_valid) {
1597 continue;
1598 }
1599
1600 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
1601 continue;
1602
1603 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe)
1604 continue;
1605
1606 if (hws->funcs.apply_single_controller_ctx_to_hw)
1607 status = hws->funcs.apply_single_controller_ctx_to_hw(
1608 pipe_ctx,
1609 context,
1610 dc);
1611
1612 ASSERT(status == DC_OK);
1613
1614 #ifdef CONFIG_DRM_AMD_DC_FP
1615 if (hws->funcs.resync_fifo_dccg_dio)
1616 hws->funcs.resync_fifo_dccg_dio(hws, dc, context, i);
1617 #endif
1618 }
1619 }
1620
1621 /* Blank pixel data during initialization */
dcn32_init_blank(struct dc * dc,struct timing_generator * tg)1622 void dcn32_init_blank(
1623 struct dc *dc,
1624 struct timing_generator *tg)
1625 {
1626 struct dce_hwseq *hws = dc->hwseq;
1627 enum dc_color_space color_space;
1628 struct tg_color black_color = {0};
1629 struct output_pixel_processor *opp = NULL;
1630 struct output_pixel_processor *bottom_opp = NULL;
1631 uint32_t num_opps, opp_id_src0, opp_id_src1;
1632 uint32_t otg_active_width = 0, otg_active_height = 0;
1633 uint32_t i;
1634
1635 /* program opp dpg blank color */
1636 color_space = COLOR_SPACE_SRGB;
1637 color_space_to_black_color(dc, color_space, &black_color);
1638
1639 /* get the OTG active size */
1640 tg->funcs->get_otg_active_size(tg,
1641 &otg_active_width,
1642 &otg_active_height);
1643
1644 /* get the OPTC source */
1645 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);
1646
1647 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) {
1648 ASSERT(false);
1649 return;
1650 }
1651
1652 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
1653 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) {
1654 opp = dc->res_pool->opps[i];
1655 break;
1656 }
1657 }
1658
1659 if (num_opps == 2) {
1660 otg_active_width = otg_active_width / 2;
1661
1662 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) {
1663 ASSERT(false);
1664 return;
1665 }
1666 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
1667 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src1) {
1668 bottom_opp = dc->res_pool->opps[i];
1669 break;
1670 }
1671 }
1672 }
1673
1674 if (opp && opp->funcs->opp_set_disp_pattern_generator)
1675 opp->funcs->opp_set_disp_pattern_generator(
1676 opp,
1677 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
1678 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
1679 COLOR_DEPTH_UNDEFINED,
1680 &black_color,
1681 otg_active_width,
1682 otg_active_height,
1683 0);
1684
1685 if (num_opps == 2) {
1686 if (bottom_opp && bottom_opp->funcs->opp_set_disp_pattern_generator) {
1687 bottom_opp->funcs->opp_set_disp_pattern_generator(
1688 bottom_opp,
1689 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
1690 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
1691 COLOR_DEPTH_UNDEFINED,
1692 &black_color,
1693 otg_active_width,
1694 otg_active_height,
1695 0);
1696 hws->funcs.wait_for_blank_complete(bottom_opp);
1697 }
1698 }
1699
1700 if (opp)
1701 hws->funcs.wait_for_blank_complete(opp);
1702 }
1703
1704 /* phantom stream id's can change often, but can be identical between contexts.
1705 * This function checks for the condition the streams are identical to avoid
1706 * redundant pipe transitions.
1707 */
is_subvp_phantom_topology_transition_seamless(const struct dc_state * cur_ctx,const struct dc_state * new_ctx,const struct pipe_ctx * cur_pipe,const struct pipe_ctx * new_pipe)1708 static bool is_subvp_phantom_topology_transition_seamless(
1709 const struct dc_state *cur_ctx,
1710 const struct dc_state *new_ctx,
1711 const struct pipe_ctx *cur_pipe,
1712 const struct pipe_ctx *new_pipe)
1713 {
1714 enum mall_stream_type cur_pipe_type = dc_state_get_pipe_subvp_type(cur_ctx, cur_pipe);
1715 enum mall_stream_type new_pipe_type = dc_state_get_pipe_subvp_type(new_ctx, new_pipe);
1716
1717 const struct dc_stream_state *cur_paired_stream = dc_state_get_paired_subvp_stream(cur_ctx, cur_pipe->stream);
1718 const struct dc_stream_state *new_paired_stream = dc_state_get_paired_subvp_stream(new_ctx, new_pipe->stream);
1719
1720 return cur_pipe_type == SUBVP_PHANTOM &&
1721 cur_pipe_type == new_pipe_type &&
1722 cur_paired_stream && new_paired_stream &&
1723 cur_paired_stream->stream_id == new_paired_stream->stream_id;
1724 }
1725
dcn32_is_pipe_topology_transition_seamless(struct dc * dc,const struct dc_state * cur_ctx,const struct dc_state * new_ctx)1726 bool dcn32_is_pipe_topology_transition_seamless(struct dc *dc,
1727 const struct dc_state *cur_ctx,
1728 const struct dc_state *new_ctx)
1729 {
1730 int i;
1731 const struct pipe_ctx *cur_pipe, *new_pipe;
1732 bool is_seamless = true;
1733
1734 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1735 cur_pipe = &cur_ctx->res_ctx.pipe_ctx[i];
1736 new_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1737
1738 if (resource_is_pipe_type(cur_pipe, FREE_PIPE) ||
1739 resource_is_pipe_type(new_pipe, FREE_PIPE))
1740 /* adding or removing free pipes is always seamless */
1741 continue;
1742 else if (resource_is_pipe_type(cur_pipe, OTG_MASTER)) {
1743 if (resource_is_pipe_type(new_pipe, OTG_MASTER))
1744 if (cur_pipe->stream->stream_id == new_pipe->stream->stream_id ||
1745 is_subvp_phantom_topology_transition_seamless(cur_ctx, new_ctx, cur_pipe, new_pipe))
1746 /* OTG master with the same stream is seamless */
1747 continue;
1748 } else if (resource_is_pipe_type(cur_pipe, OPP_HEAD)) {
1749 if (resource_is_pipe_type(new_pipe, OPP_HEAD)) {
1750 if (cur_pipe->stream_res.tg == new_pipe->stream_res.tg)
1751 /*
1752 * OPP heads sharing the same timing
1753 * generator is seamless
1754 */
1755 continue;
1756 }
1757 } else if (resource_is_pipe_type(cur_pipe, DPP_PIPE)) {
1758 if (resource_is_pipe_type(new_pipe, DPP_PIPE)) {
1759 if (cur_pipe->stream_res.opp == new_pipe->stream_res.opp)
1760 /*
1761 * DPP pipes sharing the same OPP head is
1762 * seamless
1763 */
1764 continue;
1765 }
1766 }
1767
1768 /*
1769 * This pipe's transition doesn't fall under any seamless
1770 * conditions
1771 */
1772 is_seamless = false;
1773 break;
1774 }
1775
1776 return is_seamless;
1777 }
1778
dcn32_prepare_bandwidth(struct dc * dc,struct dc_state * context)1779 void dcn32_prepare_bandwidth(struct dc *dc,
1780 struct dc_state *context)
1781 {
1782 bool p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support;
1783 /* Any transition into an FPO config should disable MCLK switching first to avoid
1784 * driver and FW P-State synchronization issues.
1785 */
1786 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {
1787 dc->optimized_required = true;
1788 context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
1789 }
1790
1791 if (dc->clk_mgr->dc_mode_softmax_enabled)
1792 if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
1793 context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
1794 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);
1795
1796 dcn20_prepare_bandwidth(dc, context);
1797
1798 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching)
1799 dc_dmub_srv_p_state_delegate(dc, false, context);
1800
1801 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {
1802 /* After disabling P-State, restore the original value to ensure we get the correct P-State
1803 * on the next optimize.
1804 */
1805 context->bw_ctx.bw.dcn.clk.p_state_change_support = p_state_change_support;
1806 }
1807 }
1808
dcn32_interdependent_update_lock(struct dc * dc,struct dc_state * context,bool lock)1809 void dcn32_interdependent_update_lock(struct dc *dc,
1810 struct dc_state *context, bool lock)
1811 {
1812 unsigned int i;
1813 struct pipe_ctx *pipe;
1814 struct timing_generator *tg;
1815
1816 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1817 pipe = &context->res_ctx.pipe_ctx[i];
1818 tg = pipe->stream_res.tg;
1819
1820 if (!resource_is_pipe_type(pipe, OTG_MASTER) ||
1821 !tg->funcs->is_tg_enabled(tg) ||
1822 dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM)
1823 continue;
1824
1825 if (lock)
1826 dc->hwss.pipe_control_lock(dc, pipe, true);
1827 else
1828 dc->hwss.pipe_control_lock(dc, pipe, false);
1829 }
1830 }
1831
dcn32_program_outstanding_updates(struct dc * dc,struct dc_state * context)1832 void dcn32_program_outstanding_updates(struct dc *dc,
1833 struct dc_state *context)
1834 {
1835 struct hubbub *hubbub = dc->res_pool->hubbub;
1836
1837 /* update compbuf if required */
1838 if (hubbub->funcs->program_compbuf_size)
1839 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true);
1840 }
1841