1 /* 2 * Copyright © 2008 Keith Packard 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that copyright 7 * notice and this permission notice appear in supporting documentation, and 8 * that the name of the copyright holders not be used in advertising or 9 * publicity pertaining to distribution of the software without specific, 10 * written prior permission. The copyright holders make no representations 11 * about the suitability of this software for any purpose. It is provided "as 12 * is" without express or implied warranty. 13 * 14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 20 * OF THIS SOFTWARE. 21 */ 22 23 #ifndef _DRM_DP_HELPER_H_ 24 #define _DRM_DP_HELPER_H_ 25 26 #include <linux/delay.h> 27 #include <linux/i2c.h> 28 29 #include <drm/display/drm_dp.h> 30 #include <drm/drm_connector.h> 31 32 struct drm_device; 33 struct drm_dp_aux; 34 struct drm_panel; 35 36 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 37 int lane_count); 38 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 39 int lane_count); 40 bool drm_dp_post_lt_adj_req_in_progress(const u8 link_status[DP_LINK_STATUS_SIZE]); 41 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], 42 int lane); 43 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], 44 int lane); 45 u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], 46 int lane); 47 48 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 49 enum drm_dp_phy dp_phy, bool uhbr); 50 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 51 enum drm_dp_phy dp_phy, bool uhbr); 52 53 void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, 54 const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 55 void drm_dp_lttpr_link_train_clock_recovery_delay(void); 56 void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 57 const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 58 void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 59 const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 60 61 int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux); 62 bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE], 63 int lane_count); 64 bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE], 65 int lane_count); 66 bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]); 67 bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]); 68 bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]); 69 70 u8 drm_dp_link_rate_to_bw_code(int link_rate); 71 int drm_dp_bw_code_to_link_rate(u8 link_bw); 72 73 const char *drm_dp_phy_name(enum drm_dp_phy dp_phy); 74 75 /** 76 * struct drm_dp_vsc_sdp - drm DP VSC SDP 77 * 78 * This structure represents a DP VSC SDP of drm 79 * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and 80 * [Table 2-117: VSC SDP Payload for DB16 through DB18] 81 * 82 * @sdp_type: secondary-data packet type 83 * @revision: revision number 84 * @length: number of valid data bytes 85 * @pixelformat: pixel encoding format 86 * @colorimetry: colorimetry format 87 * @bpc: bit per color 88 * @dynamic_range: dynamic range information 89 * @content_type: CTA-861-G defines content types and expected processing by a sink device 90 */ 91 struct drm_dp_vsc_sdp { 92 unsigned char sdp_type; 93 unsigned char revision; 94 unsigned char length; 95 enum dp_pixelformat pixelformat; 96 enum dp_colorimetry colorimetry; 97 int bpc; 98 enum dp_dynamic_range dynamic_range; 99 enum dp_content_type content_type; 100 }; 101 102 /** 103 * struct drm_dp_as_sdp - drm DP Adaptive Sync SDP 104 * 105 * This structure represents a DP AS SDP of drm 106 * It is based on DP 2.1 spec [Table 2-126: Adaptive-Sync SDP Header Bytes] and 107 * [Table 2-127: Adaptive-Sync SDP Payload for DB0 through DB8] 108 * 109 * @sdp_type: Secondary-data packet type 110 * @revision: Revision Number 111 * @length: Number of valid data bytes 112 * @vtotal: Minimum Vertical Vtotal 113 * @target_rr: Target Refresh 114 * @duration_incr_ms: Successive frame duration increase 115 * @duration_decr_ms: Successive frame duration decrease 116 * @target_rr_divider: Target refresh rate divider 117 * @mode: Adaptive Sync Operation Mode 118 */ 119 struct drm_dp_as_sdp { 120 unsigned char sdp_type; 121 unsigned char revision; 122 unsigned char length; 123 int vtotal; 124 int target_rr; 125 int duration_incr_ms; 126 int duration_decr_ms; 127 bool target_rr_divider; 128 enum operation_mode mode; 129 int coasting_vtotal; 130 }; 131 132 void drm_dp_as_sdp_log(struct drm_printer *p, 133 const struct drm_dp_as_sdp *as_sdp); 134 void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc); 135 136 bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 137 bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 138 139 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]); 140 141 static inline int 142 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 143 { 144 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); 145 } 146 147 static inline u8 148 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 149 { 150 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; 151 } 152 153 static inline bool 154 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 155 { 156 return dpcd[DP_DPCD_REV] >= 0x11 && 157 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); 158 } 159 160 static inline bool 161 drm_dp_post_lt_adj_req_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 162 { 163 return dpcd[DP_DPCD_REV] >= 0x13 && 164 (dpcd[DP_MAX_LANE_COUNT] & DP_POST_LT_ADJ_REQ_SUPPORTED); 165 } 166 167 static inline bool 168 drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 169 { 170 return dpcd[DP_DPCD_REV] >= 0x11 && 171 (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING); 172 } 173 174 static inline bool 175 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 176 { 177 return dpcd[DP_DPCD_REV] >= 0x12 && 178 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED; 179 } 180 181 static inline bool 182 drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 183 { 184 return dpcd[DP_DPCD_REV] >= 0x11 || 185 dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5; 186 } 187 188 static inline bool 189 drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 190 { 191 return dpcd[DP_DPCD_REV] >= 0x14 && 192 dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED; 193 } 194 195 static inline u8 196 drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 197 { 198 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 : 199 DP_TRAINING_PATTERN_MASK; 200 } 201 202 static inline bool 203 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 204 { 205 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT; 206 } 207 208 /* DP/eDP DSC support */ 209 u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); 210 u32 drm_dp_dsc_slice_count_to_mask(int slice_count); 211 u32 drm_dp_dsc_sink_slice_count_mask(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 212 bool is_edp); 213 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 214 bool is_edp); 215 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); 216 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE], 217 u8 dsc_bpc[3]); 218 int drm_dp_dsc_sink_max_slice_throughput(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 219 int peak_pixel_rate, bool is_rgb_yuv444); 220 int drm_dp_dsc_branch_max_overall_throughput(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE], 221 bool is_rgb_yuv444); 222 int drm_dp_dsc_branch_max_line_width(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE]); 223 224 static inline bool 225 drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 226 { 227 return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] & 228 DP_DSC_DECOMPRESSION_IS_SUPPORTED; 229 } 230 231 static inline u16 232 drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 233 { 234 return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] | 235 ((dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] & 236 DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK) << 8); 237 } 238 239 static inline u32 240 drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 241 { 242 /* Max Slicewidth = Number of Pixels * 320 */ 243 return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] * 244 DP_DSC_SLICE_WIDTH_MULTIPLIER; 245 } 246 247 /** 248 * drm_dp_dsc_sink_supports_format() - check if sink supports DSC with given output format 249 * @dsc_dpcd : DSC-capability DPCDs of the sink 250 * @output_format: output_format which is to be checked 251 * 252 * Returns true if the sink supports DSC with the given output_format, false otherwise. 253 */ 254 static inline bool 255 drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 output_format) 256 { 257 return dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & output_format; 258 } 259 260 /* Forward Error Correction Support on DP 1.4 */ 261 static inline bool 262 drm_dp_sink_supports_fec(const u8 fec_capable) 263 { 264 return fec_capable & DP_FEC_CAPABLE; 265 } 266 267 static inline bool 268 drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 269 { 270 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B; 271 } 272 273 static inline bool 274 drm_dp_128b132b_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 275 { 276 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B; 277 } 278 279 static inline bool 280 drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 281 { 282 return dpcd[DP_EDP_CONFIGURATION_CAP] & 283 DP_ALTERNATE_SCRAMBLER_RESET_CAP; 284 } 285 286 /* Ignore MSA timing for Adaptive Sync support on DP 1.4 */ 287 static inline bool 288 drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 289 { 290 return dpcd[DP_DOWN_STREAM_PORT_COUNT] & 291 DP_MSA_TIMING_PAR_IGNORED; 292 } 293 294 /** 295 * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support 296 * @edp_dpcd: The DPCD to check 297 * 298 * Note that currently this function will return %false for panels which support various DPCD 299 * backlight features but which require the brightness be set through PWM, and don't support setting 300 * the brightness level via the DPCD. 301 * 302 * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false 303 * otherwise 304 */ 305 static inline bool 306 drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]) 307 { 308 return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP); 309 } 310 311 /** 312 * drm_dp_is_uhbr_rate - Determine if a link rate is UHBR 313 * @link_rate: link rate in 10kbits/s units 314 * 315 * Determine if the provided link rate is an UHBR rate. 316 * 317 * Returns: %True if @link_rate is an UHBR rate. 318 */ 319 static inline bool drm_dp_is_uhbr_rate(int link_rate) 320 { 321 return link_rate >= 1000000; 322 } 323 324 /* 325 * DisplayPort AUX channel 326 */ 327 328 /** 329 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction 330 * @address: address of the (first) register to access 331 * @request: contains the type of transaction (see DP_AUX_* macros) 332 * @reply: upon completion, contains the reply type of the transaction 333 * @buffer: pointer to a transmission or reception buffer 334 * @size: size of @buffer 335 */ 336 struct drm_dp_aux_msg { 337 unsigned int address; 338 u8 request; 339 u8 reply; 340 void *buffer; 341 size_t size; 342 }; 343 344 struct cec_adapter; 345 struct drm_connector; 346 struct drm_edid; 347 348 /** 349 * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX 350 * @lock: mutex protecting this struct 351 * @adap: the CEC adapter for CEC-Tunneling-over-AUX support. 352 * @connector: the connector this CEC adapter is associated with 353 * @unregister_work: unregister the CEC adapter 354 */ 355 struct drm_dp_aux_cec { 356 struct mutex lock; 357 struct cec_adapter *adap; 358 struct drm_connector *connector; 359 struct delayed_work unregister_work; 360 }; 361 362 /** 363 * struct drm_dp_aux - DisplayPort AUX channel 364 * 365 * An AUX channel can also be used to transport I2C messages to a sink. A 366 * typical application of that is to access an EDID that's present in the sink 367 * device. The @transfer() function can also be used to execute such 368 * transactions. The drm_dp_aux_register() function registers an I2C adapter 369 * that can be passed to drm_probe_ddc(). Upon removal, drivers should call 370 * drm_dp_aux_unregister() to remove the I2C adapter. The I2C adapter uses long 371 * transfers by default; if a partial response is received, the adapter will 372 * drop down to the size given by the partial response for this transaction 373 * only. 374 */ 375 struct drm_dp_aux { 376 /** 377 * @name: user-visible name of this AUX channel and the 378 * I2C-over-AUX adapter. 379 * 380 * It's also used to specify the name of the I2C adapter. If set 381 * to %NULL, dev_name() of @dev will be used. 382 */ 383 const char *name; 384 385 /** 386 * @ddc: I2C adapter that can be used for I2C-over-AUX 387 * communication 388 */ 389 struct i2c_adapter ddc; 390 391 /** 392 * @dev: pointer to struct device that is the parent for this 393 * AUX channel. 394 */ 395 struct device *dev; 396 397 /** 398 * @drm_dev: pointer to the &drm_device that owns this AUX channel. 399 * Beware, this may be %NULL before drm_dp_aux_register() has been 400 * called. 401 * 402 * It should be set to the &drm_device that will be using this AUX 403 * channel as early as possible. For many graphics drivers this should 404 * happen before drm_dp_aux_init(), however it's perfectly fine to set 405 * this field later so long as it's assigned before calling 406 * drm_dp_aux_register(). 407 */ 408 struct drm_device *drm_dev; 409 410 /** 411 * @crtc: backpointer to the crtc that is currently using this 412 * AUX channel 413 */ 414 struct drm_crtc *crtc; 415 416 /** 417 * @hw_mutex: internal mutex used for locking transfers. 418 * 419 * Note that if the underlying hardware is shared among multiple 420 * channels, the driver needs to do additional locking to 421 * prevent concurrent access. 422 */ 423 struct mutex hw_mutex; 424 425 /** 426 * @crc_work: worker that captures CRCs for each frame 427 */ 428 struct work_struct crc_work; 429 430 /** 431 * @crc_count: counter of captured frame CRCs 432 */ 433 u8 crc_count; 434 435 /** 436 * @transfer: transfers a message representing a single AUX 437 * transaction. 438 * 439 * This is a hardware-specific implementation of how 440 * transactions are executed that the drivers must provide. 441 * 442 * A pointer to a &drm_dp_aux_msg structure describing the 443 * transaction is passed into this function. Upon success, the 444 * implementation should return the number of payload bytes that 445 * were transferred, or a negative error-code on failure. 446 * 447 * Helpers will propagate these errors, with the exception of 448 * the %-EBUSY error, which causes a transaction to be retried. 449 * On a short, helpers will return %-EPROTO to make it simpler 450 * to check for failure. 451 * 452 * The @transfer() function must only modify the reply field of 453 * the &drm_dp_aux_msg structure. The retry logic and i2c 454 * helpers assume this is the case. 455 * 456 * Also note that this callback can be called no matter the 457 * state @dev is in and also no matter what state the panel is 458 * in. It's expected: 459 * 460 * - If the @dev providing the AUX bus is currently unpowered then 461 * it will power itself up for the transfer. 462 * 463 * - If we're on eDP (using a drm_panel) and the panel is not in a 464 * state where it can respond (it's not powered or it's in a 465 * low power state) then this function may return an error, but 466 * not crash. It's up to the caller of this code to make sure that 467 * the panel is powered on if getting an error back is not OK. If a 468 * drm_panel driver is initiating a DP AUX transfer it may power 469 * itself up however it wants. All other code should ensure that 470 * the pre_enable() bridge chain (which eventually calls the 471 * drm_panel prepare function) has powered the panel. 472 */ 473 ssize_t (*transfer)(struct drm_dp_aux *aux, 474 struct drm_dp_aux_msg *msg); 475 476 /** 477 * @wait_hpd_asserted: wait for HPD to be asserted 478 * 479 * This is mainly useful for eDP panels drivers to wait for an eDP 480 * panel to finish powering on. It is optional for DP AUX controllers 481 * to implement this function. It is required for DP AUX endpoints 482 * (panel drivers) to call this function after powering up but before 483 * doing AUX transfers unless the DP AUX endpoint driver knows that 484 * we're not using the AUX controller's HPD. One example of the panel 485 * driver not needing to call this is if HPD is hooked up to a GPIO 486 * that the panel driver can read directly. 487 * 488 * If a DP AUX controller does not implement this function then it 489 * may still support eDP panels that use the AUX controller's built-in 490 * HPD signal by implementing a long wait for HPD in the transfer() 491 * callback, though this is deprecated. 492 * 493 * This function will efficiently wait for the HPD signal to be 494 * asserted. The `wait_us` parameter that is passed in says that we 495 * know that the HPD signal is expected to be asserted within `wait_us` 496 * microseconds. This function could wait for longer than `wait_us` if 497 * the logic in the DP controller has a long debouncing time. The 498 * important thing is that if this function returns success that the 499 * DP controller is ready to send AUX transactions. 500 * 501 * This function returns 0 if HPD was asserted or -ETIMEDOUT if time 502 * expired and HPD wasn't asserted. This function should not print 503 * timeout errors to the log. 504 * 505 * The semantics of this function are designed to match the 506 * readx_poll_timeout() function. That means a `wait_us` of 0 means 507 * to wait forever. Like readx_poll_timeout(), this function may sleep. 508 * 509 * NOTE: this function specifically reports the state of the HPD pin 510 * that's associated with the DP AUX channel. This is different from 511 * the HPD concept in much of the rest of DRM which is more about 512 * physical presence of a display. For eDP, for instance, a display is 513 * assumed always present even if the HPD pin is deasserted. 514 */ 515 int (*wait_hpd_asserted)(struct drm_dp_aux *aux, unsigned long wait_us); 516 517 /** 518 * @i2c_nack_count: Counts I2C NACKs, used for DP validation. 519 */ 520 unsigned i2c_nack_count; 521 /** 522 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation. 523 */ 524 unsigned i2c_defer_count; 525 /** 526 * @cec: struct containing fields used for CEC-Tunneling-over-AUX. 527 */ 528 struct drm_dp_aux_cec cec; 529 /** 530 * @is_remote: Is this AUX CH actually using sideband messaging. 531 */ 532 bool is_remote; 533 534 /** 535 * @powered_down: If true then the remote endpoint is powered down. 536 */ 537 bool powered_down; 538 539 /** 540 * @no_zero_sized: If the hw can't use zero sized transfers (NVIDIA) 541 */ 542 bool no_zero_sized; 543 544 /** 545 * @dpcd_probe_disabled: If probing before a DPCD access is disabled. 546 */ 547 bool dpcd_probe_disabled; 548 }; 549 550 int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset); 551 void drm_dp_dpcd_set_powered(struct drm_dp_aux *aux, bool powered); 552 void drm_dp_dpcd_set_probe(struct drm_dp_aux *aux, bool enable); 553 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, 554 void *buffer, size_t size); 555 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, 556 void *buffer, size_t size); 557 558 /** 559 * drm_dp_dpcd_readb() - read a single byte from the DPCD 560 * @aux: DisplayPort AUX channel 561 * @offset: address of the register to read 562 * @valuep: location where the value of the register will be stored 563 * 564 * Returns the number of bytes transferred (1) on success, or a negative 565 * error code on failure. In most of the cases you should be using 566 * drm_dp_dpcd_read_byte() instead. 567 */ 568 static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux, 569 unsigned int offset, u8 *valuep) 570 { 571 return drm_dp_dpcd_read(aux, offset, valuep, 1); 572 } 573 574 /** 575 * drm_dp_dpcd_read_data() - read a series of bytes from the DPCD 576 * @aux: DisplayPort AUX channel (SST or MST) 577 * @offset: address of the (first) register to read 578 * @buffer: buffer to store the register values 579 * @size: number of bytes in @buffer 580 * 581 * Returns zero (0) on success, or a negative error 582 * code on failure. -EIO is returned if the request was NAKed by the sink or 583 * if the retry count was exceeded. If not all bytes were transferred, this 584 * function returns -EPROTO. Errors from the underlying AUX channel transfer 585 * function, with the exception of -EBUSY (which causes the transaction to 586 * be retried), are propagated to the caller. 587 */ 588 static inline int drm_dp_dpcd_read_data(struct drm_dp_aux *aux, 589 unsigned int offset, 590 void *buffer, size_t size) 591 { 592 int ret; 593 size_t i; 594 u8 *buf = buffer; 595 596 ret = drm_dp_dpcd_read(aux, offset, buffer, size); 597 if (ret >= 0) { 598 if (ret < size) 599 return -EPROTO; 600 return 0; 601 } 602 603 /* 604 * Workaround for USB-C hubs/adapters with buggy firmware that fail 605 * multi-byte AUX reads but work with single-byte reads. 606 * Known affected devices: 607 * - Lenovo USB-C to VGA adapter (VIA VL817, idVendor=17ef, idProduct=7217) 608 * - Dell DA310 USB-C hub (idVendor=413c, idProduct=c010) 609 * Attempt byte-by-byte reading as a fallback. 610 */ 611 for (i = 0; i < size; i++) { 612 ret = drm_dp_dpcd_readb(aux, offset + i, &buf[i]); 613 if (ret < 0) 614 return ret; 615 } 616 617 return 0; 618 } 619 620 /** 621 * drm_dp_dpcd_write_data() - write a series of bytes to the DPCD 622 * @aux: DisplayPort AUX channel (SST or MST) 623 * @offset: address of the (first) register to write 624 * @buffer: buffer containing the values to write 625 * @size: number of bytes in @buffer 626 * 627 * Returns zero (0) on success, or a negative error 628 * code on failure. -EIO is returned if the request was NAKed by the sink or 629 * if the retry count was exceeded. If not all bytes were transferred, this 630 * function returns -EPROTO. Errors from the underlying AUX channel transfer 631 * function, with the exception of -EBUSY (which causes the transaction to 632 * be retried), are propagated to the caller. 633 */ 634 static inline int drm_dp_dpcd_write_data(struct drm_dp_aux *aux, 635 unsigned int offset, 636 void *buffer, size_t size) 637 { 638 int ret; 639 640 ret = drm_dp_dpcd_write(aux, offset, buffer, size); 641 if (ret < 0) 642 return ret; 643 if (ret < size) 644 return -EPROTO; 645 646 return 0; 647 } 648 649 /** 650 * drm_dp_dpcd_writeb() - write a single byte to the DPCD 651 * @aux: DisplayPort AUX channel 652 * @offset: address of the register to write 653 * @value: value to write to the register 654 * 655 * Returns the number of bytes transferred (1) on success, or a negative 656 * error code on failure. In most of the cases you should be using 657 * drm_dp_dpcd_write_byte() instead. 658 */ 659 static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux, 660 unsigned int offset, u8 value) 661 { 662 return drm_dp_dpcd_write(aux, offset, &value, 1); 663 } 664 665 /** 666 * drm_dp_dpcd_read_byte() - read a single byte from the DPCD 667 * @aux: DisplayPort AUX channel 668 * @offset: address of the register to read 669 * @valuep: location where the value of the register will be stored 670 * 671 * Returns zero (0) on success, or a negative error code on failure. 672 */ 673 static inline int drm_dp_dpcd_read_byte(struct drm_dp_aux *aux, 674 unsigned int offset, u8 *valuep) 675 { 676 return drm_dp_dpcd_read_data(aux, offset, valuep, 1); 677 } 678 679 /** 680 * drm_dp_dpcd_write_byte() - write a single byte to the DPCD 681 * @aux: DisplayPort AUX channel 682 * @offset: address of the register to write 683 * @value: value to write to the register 684 * 685 * Returns zero (0) on success, or a negative error code on failure. 686 */ 687 static inline int drm_dp_dpcd_write_byte(struct drm_dp_aux *aux, 688 unsigned int offset, u8 value) 689 { 690 return drm_dp_dpcd_write_data(aux, offset, &value, 1); 691 } 692 693 int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, 694 u8 dpcd[DP_RECEIVER_CAP_SIZE]); 695 696 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, 697 u8 status[DP_LINK_STATUS_SIZE]); 698 699 int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux, 700 enum drm_dp_phy dp_phy, 701 u8 link_status[DP_LINK_STATUS_SIZE]); 702 int drm_dp_link_power_up(struct drm_dp_aux *aux, unsigned char revision); 703 int drm_dp_link_power_down(struct drm_dp_aux *aux, unsigned char revision); 704 705 int drm_dp_dpcd_write_payload(struct drm_dp_aux *aux, 706 int vcpid, u8 start_time_slot, u8 time_slot_count); 707 int drm_dp_dpcd_clear_payload(struct drm_dp_aux *aux); 708 int drm_dp_dpcd_poll_act_handled(struct drm_dp_aux *aux, int timeout_ms); 709 710 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux, 711 u8 real_edid_checksum); 712 713 int drm_dp_read_downstream_info(struct drm_dp_aux *aux, 714 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 715 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]); 716 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 717 const u8 port_cap[4], u8 type); 718 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 719 const u8 port_cap[4], 720 const struct drm_edid *drm_edid); 721 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 722 const u8 port_cap[4]); 723 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 724 const u8 port_cap[4], 725 const struct drm_edid *drm_edid); 726 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 727 const u8 port_cap[4], 728 const struct drm_edid *drm_edid); 729 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 730 const u8 port_cap[4], 731 const struct drm_edid *drm_edid); 732 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 733 const u8 port_cap[4]); 734 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 735 const u8 port_cap[4]); 736 struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev, 737 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 738 const u8 port_cap[4]); 739 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]); 740 void drm_dp_downstream_debug(struct seq_file *m, 741 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 742 const u8 port_cap[4], 743 const struct drm_edid *drm_edid, 744 struct drm_dp_aux *aux); 745 enum drm_mode_subconnector 746 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 747 const u8 port_cap[4]); 748 void drm_dp_set_subconnector_property(struct drm_connector *connector, 749 enum drm_connector_status status, 750 const u8 *dpcd, 751 const u8 port_cap[4]); 752 753 struct drm_dp_desc; 754 bool drm_dp_read_sink_count_cap(struct drm_connector *connector, 755 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 756 const struct drm_dp_desc *desc); 757 int drm_dp_read_sink_count(struct drm_dp_aux *aux); 758 759 int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux, 760 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 761 u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); 762 int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux, 763 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 764 enum drm_dp_phy dp_phy, 765 u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 766 int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]); 767 int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); 768 int drm_dp_lttpr_set_transparent_mode(struct drm_dp_aux *aux, bool enable); 769 int drm_dp_lttpr_init(struct drm_dp_aux *aux, int lttpr_count); 770 int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); 771 bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 772 bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 773 void drm_dp_lttpr_wake_timeout_setup(struct drm_dp_aux *aux, bool transparent_mode); 774 775 void drm_dp_remote_aux_init(struct drm_dp_aux *aux); 776 void drm_dp_aux_init(struct drm_dp_aux *aux); 777 int drm_dp_aux_register(struct drm_dp_aux *aux); 778 void drm_dp_aux_unregister(struct drm_dp_aux *aux); 779 780 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc); 781 int drm_dp_stop_crc(struct drm_dp_aux *aux); 782 783 struct drm_dp_dpcd_ident { 784 u8 oui[3]; 785 u8 device_id[6]; 786 u8 hw_rev; 787 u8 sw_major_rev; 788 u8 sw_minor_rev; 789 } __packed; 790 791 /** 792 * struct drm_dp_desc - DP branch/sink device descriptor 793 * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch). 794 * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks. 795 */ 796 struct drm_dp_desc { 797 struct drm_dp_dpcd_ident ident; 798 u32 quirks; 799 }; 800 801 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, 802 bool is_branch); 803 804 int drm_dp_dump_lttpr_desc(struct drm_dp_aux *aux, enum drm_dp_phy dp_phy); 805 806 /** 807 * enum drm_dp_quirk - Display Port sink/branch device specific quirks 808 * 809 * Display Port sink and branch devices in the wild have a variety of bugs, try 810 * to collect them here. The quirks are shared, but it's up to the drivers to 811 * implement workarounds for them. 812 */ 813 enum drm_dp_quirk { 814 /** 815 * @DP_DPCD_QUIRK_CONSTANT_N: 816 * 817 * The device requires main link attributes Mvid and Nvid to be limited 818 * to 16 bits. So will give a constant value (0x8000) for compatability. 819 */ 820 DP_DPCD_QUIRK_CONSTANT_N, 821 /** 822 * @DP_DPCD_QUIRK_NO_PSR: 823 * 824 * The device does not support PSR even if reports that it supports or 825 * driver still need to implement proper handling for such device. 826 */ 827 DP_DPCD_QUIRK_NO_PSR, 828 /** 829 * @DP_DPCD_QUIRK_NO_SINK_COUNT: 830 * 831 * The device does not set SINK_COUNT to a non-zero value. 832 * The driver should ignore SINK_COUNT during detection. Note that 833 * drm_dp_read_sink_count_cap() automatically checks for this quirk. 834 */ 835 DP_DPCD_QUIRK_NO_SINK_COUNT, 836 /** 837 * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD: 838 * 839 * The device supports MST DSC despite not supporting Virtual DPCD. 840 * The DSC caps can be read from the physical aux instead. 841 */ 842 DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD, 843 /** 844 * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS: 845 * 846 * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite 847 * the DP_MAX_LINK_RATE register reporting a lower max multiplier. 848 */ 849 DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS, 850 /** 851 * @DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC: 852 * 853 * The device applies HBLANK expansion for some modes, but this 854 * requires enabling DSC. 855 */ 856 DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC, 857 /** 858 * @DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT: 859 * 860 * The device doesn't support DSC decompression at the maximum DSC 861 * pixel throughput and compressed bpp it indicates via its DPCD DSC 862 * capabilities. The compressed bpp must be limited above a device 863 * specific DSC pixel throughput. 864 */ 865 DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT, 866 }; 867 868 /** 869 * drm_dp_has_quirk() - does the DP device have a specific quirk 870 * @desc: Device descriptor filled by drm_dp_read_desc() 871 * @quirk: Quirk to query for 872 * 873 * Return true if DP device identified by @desc has @quirk. 874 */ 875 static inline bool 876 drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk) 877 { 878 return desc->quirks & BIT(quirk); 879 } 880 881 /** 882 * struct drm_edp_backlight_info - Probed eDP backlight info struct 883 * @pwmgen_bit_count: The pwmgen bit count 884 * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any 885 * @max: The maximum backlight level that may be set 886 * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register? 887 * @aux_enable: Does the panel support the AUX enable cap? 888 * @aux_set: Does the panel support setting the brightness through AUX? 889 * @luminance_set: Does the panel support setting the brightness through AUX using luminance values? 890 * 891 * This structure contains various data about an eDP backlight, which can be populated by using 892 * drm_edp_backlight_init(). 893 */ 894 struct drm_edp_backlight_info { 895 u8 pwmgen_bit_count; 896 u8 pwm_freq_pre_divider; 897 u32 max; 898 899 bool lsb_reg_used : 1; 900 bool aux_enable : 1; 901 bool aux_set : 1; 902 bool luminance_set : 1; 903 }; 904 905 int 906 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, 907 u32 max_luminance, 908 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE], 909 u32 *current_level, u8 *current_mode, bool need_luminance); 910 int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 911 u32 level); 912 int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 913 u32 level); 914 int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl); 915 916 #if IS_ENABLED(CONFIG_DRM_KMS_HELPER) && (IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \ 917 (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE))) 918 919 int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux); 920 921 #else 922 923 static inline int drm_panel_dp_aux_backlight(struct drm_panel *panel, 924 struct drm_dp_aux *aux) 925 { 926 return 0; 927 } 928 929 #endif 930 931 #ifdef CONFIG_DRM_DISPLAY_DP_AUX_CEC 932 void drm_dp_cec_irq(struct drm_dp_aux *aux); 933 void drm_dp_cec_register_connector(struct drm_dp_aux *aux, 934 struct drm_connector *connector); 935 void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux); 936 void drm_dp_cec_attach(struct drm_dp_aux *aux, u16 source_physical_address); 937 void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid); 938 void drm_dp_cec_unset_edid(struct drm_dp_aux *aux); 939 #else 940 static inline void drm_dp_cec_irq(struct drm_dp_aux *aux) 941 { 942 } 943 944 static inline void 945 drm_dp_cec_register_connector(struct drm_dp_aux *aux, 946 struct drm_connector *connector) 947 { 948 } 949 950 static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux) 951 { 952 } 953 954 static inline void drm_dp_cec_attach(struct drm_dp_aux *aux, 955 u16 source_physical_address) 956 { 957 } 958 959 static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux, 960 const struct edid *edid) 961 { 962 } 963 964 static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux) 965 { 966 } 967 968 #endif 969 970 /** 971 * struct drm_dp_phy_test_params - DP Phy Compliance parameters 972 * @link_rate: Requested Link rate from DPCD 0x219 973 * @num_lanes: Number of lanes requested by sing through DPCD 0x220 974 * @phy_pattern: DP Phy test pattern from DPCD 0x248 975 * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B 976 * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259 977 * @enhanced_frame_cap: flag for enhanced frame capability. 978 */ 979 struct drm_dp_phy_test_params { 980 int link_rate; 981 u8 num_lanes; 982 u8 phy_pattern; 983 u8 hbr2_reset[2]; 984 u8 custom80[10]; 985 bool enhanced_frame_cap; 986 }; 987 988 int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, 989 struct drm_dp_phy_test_params *data); 990 int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux, 991 struct drm_dp_phy_test_params *data, u8 dp_rev); 992 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 993 const u8 port_cap[4]); 994 int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd); 995 bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux); 996 int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, 997 u8 frl_mode); 998 int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, 999 u8 frl_type); 1000 int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux); 1001 int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux); 1002 1003 bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux); 1004 int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask); 1005 void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux, 1006 struct drm_connector *connector); 1007 bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 1008 int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 1009 int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 1010 int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 1011 int drm_dp_pcon_pps_default(struct drm_dp_aux *aux); 1012 int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]); 1013 int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]); 1014 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1015 const u8 port_cap[4], u8 color_spc); 1016 int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc); 1017 1018 #define DRM_DP_BW_OVERHEAD_MST BIT(0) 1019 #define DRM_DP_BW_OVERHEAD_UHBR BIT(1) 1020 #define DRM_DP_BW_OVERHEAD_SSC_REF_CLK BIT(2) 1021 #define DRM_DP_BW_OVERHEAD_FEC BIT(3) 1022 #define DRM_DP_BW_OVERHEAD_DSC BIT(4) 1023 1024 int drm_dp_bw_overhead(int lane_count, int hactive, 1025 int dsc_slice_count, 1026 int bpp_x16, unsigned long flags); 1027 int drm_dp_bw_channel_coding_efficiency(bool is_uhbr); 1028 int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes); 1029 1030 ssize_t drm_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, struct dp_sdp *sdp); 1031 int drm_dp_link_symbol_cycles(int lane_count, int pixels, int dsc_slice_count, 1032 int bpp_x16, int symbol_size, bool is_mst); 1033 1034 #endif /* _DRM_DP_HELPER_H_ */ 1035