1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include <linux/pci.h>
28 #include <linux/i2c.h>
29 #include "amdgpu.h"
30 #include "amdgpu_smu.h"
31 #include "atomfirmware.h"
32 #include "amdgpu_atomfirmware.h"
33 #include "amdgpu_atombios.h"
34 #include "smu_v13_0.h"
35 #include "smu13_driver_if_v13_0_7.h"
36 #include "soc15_common.h"
37 #include "atom.h"
38 #include "smu_v13_0_7_ppt.h"
39 #include "smu_v13_0_7_pptable.h"
40 #include "smu_v13_0_7_ppsmc.h"
41 #include "nbio/nbio_4_3_0_offset.h"
42 #include "nbio/nbio_4_3_0_sh_mask.h"
43 #include "mp/mp_13_0_0_offset.h"
44 #include "mp/mp_13_0_0_sh_mask.h"
45
46 #include "asic_reg/mp/mp_13_0_0_sh_mask.h"
47 #include "smu_cmn.h"
48 #include "amdgpu_ras.h"
49
50 /*
51 * DO NOT use these for err/warn/info/debug messages.
52 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
53 * They are more MGPU friendly.
54 */
55 #undef pr_err
56 #undef pr_warn
57 #undef pr_info
58 #undef pr_debug
59
60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
61
62 static void smu_v13_0_7_get_od_setting_limits(struct smu_context *smu,
63 int od_feature_bit,
64 int32_t *min, int32_t *max);
65
66 static const struct smu_feature_bits smu_v13_0_7_dpm_features = {
67 .bits = {
68 SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT),
69 SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT),
70 SMU_FEATURE_BIT_INIT(FEATURE_DPM_LINK_BIT),
71 SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT),
72 SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT),
73 SMU_FEATURE_BIT_INIT(FEATURE_DPM_MP0CLK_BIT)
74 }
75 };
76
77 #define smnMP1_FIRMWARE_FLAGS_SMU_13_0_7 0x3b10028
78
79 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000
80
81 #define mmMP1_SMN_C2PMSG_75 0x028b
82 #define mmMP1_SMN_C2PMSG_75_BASE_IDX 0
83
84 #define mmMP1_SMN_C2PMSG_53 0x0275
85 #define mmMP1_SMN_C2PMSG_53_BASE_IDX 0
86
87 #define mmMP1_SMN_C2PMSG_54 0x0276
88 #define mmMP1_SMN_C2PMSG_54_BASE_IDX 0
89
90 #define DEBUGSMC_MSG_Mode1Reset 2
91
92 #define PP_OD_FEATURE_GFXCLK_FMIN 0
93 #define PP_OD_FEATURE_GFXCLK_FMAX 1
94 #define PP_OD_FEATURE_UCLK_FMIN 2
95 #define PP_OD_FEATURE_UCLK_FMAX 3
96 #define PP_OD_FEATURE_GFX_VF_CURVE 4
97 #define PP_OD_FEATURE_FAN_CURVE_TEMP 5
98 #define PP_OD_FEATURE_FAN_CURVE_PWM 6
99 #define PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT 7
100 #define PP_OD_FEATURE_FAN_ACOUSTIC_TARGET 8
101 #define PP_OD_FEATURE_FAN_TARGET_TEMPERATURE 9
102 #define PP_OD_FEATURE_FAN_MINIMUM_PWM 10
103 #define PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE 11
104 #define PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP 12
105
106 #define LINK_SPEED_MAX 3
107
108 static struct cmn2asic_msg_mapping smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] = {
109 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
110 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
111 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
112 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
113 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
114 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
115 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
116 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
117 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
118 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
119 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
120 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
121 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
122 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
123 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
124 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
125 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
126 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
127 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
128 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
129 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
130 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
131 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
132 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
133 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
134 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
135 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
136 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
137 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
138 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
139 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
140 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
141 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
142 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
143 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
144 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
145 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
146 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
147 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
148 MSG_MAP(AllowIHHostInterrupt, PPSMC_MSG_AllowIHHostInterrupt, 0),
149 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
150 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
151 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
152 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
153 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
154 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
155 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
156 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
157 MSG_MAP(DFCstateControl, PPSMC_MSG_SetExternalClientDfCstateAllow, 0),
158 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
159 MSG_MAP(AllowGpo, PPSMC_MSG_SetGpoAllow, 0),
160 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
161 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
162 MSG_MAP(EnableUCLKShadow, PPSMC_MSG_EnableUCLKShadow, 0),
163 };
164
165 static struct cmn2asic_mapping smu_v13_0_7_clk_map[SMU_CLK_COUNT] = {
166 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
167 CLK_MAP(SCLK, PPCLK_GFXCLK),
168 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
169 CLK_MAP(FCLK, PPCLK_FCLK),
170 CLK_MAP(UCLK, PPCLK_UCLK),
171 CLK_MAP(MCLK, PPCLK_UCLK),
172 CLK_MAP(VCLK, PPCLK_VCLK_0),
173 CLK_MAP(VCLK1, PPCLK_VCLK_1),
174 CLK_MAP(DCLK, PPCLK_DCLK_0),
175 CLK_MAP(DCLK1, PPCLK_DCLK_1),
176 CLK_MAP(DCEFCLK, PPCLK_DCFCLK),
177 };
178
179 static struct cmn2asic_mapping smu_v13_0_7_feature_mask_map[SMU_FEATURE_COUNT] = {
180 FEA_MAP(FW_DATA_READ),
181 FEA_MAP(DPM_GFXCLK),
182 FEA_MAP(DPM_GFX_POWER_OPTIMIZER),
183 FEA_MAP(DPM_UCLK),
184 FEA_MAP(DPM_FCLK),
185 FEA_MAP(DPM_SOCCLK),
186 FEA_MAP(DPM_MP0CLK),
187 FEA_MAP(DPM_LINK),
188 FEA_MAP(DPM_DCN),
189 FEA_MAP(VMEMP_SCALING),
190 FEA_MAP(VDDIO_MEM_SCALING),
191 FEA_MAP(DS_GFXCLK),
192 FEA_MAP(DS_SOCCLK),
193 FEA_MAP(DS_FCLK),
194 FEA_MAP(DS_LCLK),
195 FEA_MAP(DS_DCFCLK),
196 FEA_MAP(DS_UCLK),
197 FEA_MAP(GFX_ULV),
198 FEA_MAP(FW_DSTATE),
199 FEA_MAP(GFXOFF),
200 FEA_MAP(BACO),
201 FEA_MAP(MM_DPM),
202 FEA_MAP(SOC_MPCLK_DS),
203 FEA_MAP(BACO_MPCLK_DS),
204 FEA_MAP(THROTTLERS),
205 FEA_MAP(SMARTSHIFT),
206 FEA_MAP(GTHR),
207 FEA_MAP(ACDC),
208 FEA_MAP(VR0HOT),
209 FEA_MAP(FW_CTF),
210 FEA_MAP(FAN_CONTROL),
211 FEA_MAP(GFX_DCS),
212 FEA_MAP(GFX_READ_MARGIN),
213 FEA_MAP(LED_DISPLAY),
214 FEA_MAP(GFXCLK_SPREAD_SPECTRUM),
215 FEA_MAP(OUT_OF_BAND_MONITOR),
216 FEA_MAP(OPTIMIZED_VMIN),
217 FEA_MAP(GFX_IMU),
218 FEA_MAP(BOOT_TIME_CAL),
219 FEA_MAP(GFX_PCC_DFLL),
220 FEA_MAP(SOC_CG),
221 FEA_MAP(DF_CSTATE),
222 FEA_MAP(GFX_EDC),
223 FEA_MAP(BOOT_POWER_OPT),
224 FEA_MAP(CLOCK_POWER_DOWN_BYPASS),
225 FEA_MAP(DS_VCN),
226 FEA_MAP(BACO_CG),
227 FEA_MAP(MEM_TEMP_READ),
228 FEA_MAP(ATHUB_MMHUB_PG),
229 FEA_MAP(SOC_PCC),
230 [SMU_FEATURE_DPM_VCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
231 [SMU_FEATURE_DPM_DCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
232 [SMU_FEATURE_PPT_BIT] = {1, FEATURE_THROTTLERS_BIT},
233 };
234
235 static struct cmn2asic_mapping smu_v13_0_7_table_map[SMU_TABLE_COUNT] = {
236 TAB_MAP(PPTABLE),
237 TAB_MAP(WATERMARKS),
238 TAB_MAP(AVFS_PSM_DEBUG),
239 TAB_MAP(PMSTATUSLOG),
240 TAB_MAP(SMU_METRICS),
241 TAB_MAP(DRIVER_SMU_CONFIG),
242 TAB_MAP(ACTIVITY_MONITOR_COEFF),
243 [SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE},
244 TAB_MAP(OVERDRIVE),
245 TAB_MAP(WIFIBAND),
246 };
247
248 static struct cmn2asic_mapping smu_v13_0_7_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
249 PWR_MAP(AC),
250 PWR_MAP(DC),
251 };
252
253 static struct cmn2asic_mapping smu_v13_0_7_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
254 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
255 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
256 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
257 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
258 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
259 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
260 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
261 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_WINDOW3D, WORKLOAD_PPLIB_WINDOW_3D_BIT),
262 };
263
264 static const uint8_t smu_v13_0_7_throttler_map[] = {
265 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
266 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
267 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
268 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
269 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
270 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
271 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
272 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
273 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
274 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
275 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
276 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
277 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
278 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
279 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
280 [THROTTLER_GFX_APCC_PLUS_BIT] = (SMU_THROTTLER_APCC_BIT),
281 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
282 };
283
284 static int
smu_v13_0_7_init_allowed_features(struct smu_context * smu)285 smu_v13_0_7_init_allowed_features(struct smu_context *smu)
286 {
287 struct amdgpu_device *adev = smu->adev;
288
289 smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED);
290
291 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DATA_READ_BIT);
292
293 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
294 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT);
295 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_IMU_BIT);
296 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT);
297 }
298
299 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
300 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT);
301
302 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) {
303 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT);
304 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_FCLK_BIT);
305 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VMEMP_SCALING_BIT);
306 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VDDIO_MEM_SCALING_BIT);
307 }
308
309 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT);
310
311 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
312 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT);
313
314 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
315 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT);
316
317 if (adev->pm.pp_feature & PP_ULV_MASK)
318 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT);
319
320 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT);
321 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_MP0CLK_BIT);
322 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MM_DPM_BIT);
323 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_VCN_BIT);
324 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_FCLK_BIT);
325 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DF_CSTATE_BIT);
326 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_THROTTLERS_BIT);
327 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VR0HOT_BIT);
328 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_CTF_BIT);
329 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FAN_CONTROL_BIT);
330 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT);
331 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT);
332 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_TEMP_READ_BIT);
333 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DSTATE_BIT);
334 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_SOC_MPCLK_DS_BIT);
335 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_MPCLK_DS_BIT);
336 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_PCC_DFLL_BIT);
337 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_SOC_CG_BIT);
338 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_BIT);
339
340 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
341 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_DCN_BIT);
342
343 if ((adev->pg_flags & AMD_PG_SUPPORT_ATHUB) &&
344 (adev->pg_flags & AMD_PG_SUPPORT_MMHUB))
345 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_MMHUB_PG_BIT);
346
347 return 0;
348 }
349
smu_v13_0_7_check_powerplay_table(struct smu_context * smu)350 static int smu_v13_0_7_check_powerplay_table(struct smu_context *smu)
351 {
352 struct smu_table_context *table_context = &smu->smu_table;
353 struct smu_13_0_7_powerplay_table *powerplay_table =
354 table_context->power_play_table;
355 struct smu_baco_context *smu_baco = &smu->smu_baco;
356 PPTable_t *smc_pptable = table_context->driver_pptable;
357 BoardTable_t *BoardTable = &smc_pptable->BoardTable;
358 const OverDriveLimits_t * const overdrive_upperlimits =
359 &smc_pptable->SkuTable.OverDriveLimitsBasicMax;
360 const OverDriveLimits_t * const overdrive_lowerlimits =
361 &smc_pptable->SkuTable.OverDriveLimitsMin;
362
363 if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_HARDWAREDC)
364 smu->dc_controlled_by_gpio = true;
365
366 if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_BACO) {
367 smu_baco->platform_support = true;
368
369 if ((powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_MACO)
370 && (BoardTable->HsrEnabled || BoardTable->VddqOffEnabled))
371 smu_baco->maco_support = true;
372 }
373
374 if (!overdrive_lowerlimits->FeatureCtrlMask ||
375 !overdrive_upperlimits->FeatureCtrlMask)
376 smu->od_enabled = false;
377
378 table_context->thermal_controller_type =
379 powerplay_table->thermal_controller_type;
380
381 /*
382 * Instead of having its own buffer space and get overdrive_table copied,
383 * smu->od_settings just points to the actual overdrive_table
384 */
385 smu->od_settings = &powerplay_table->overdrive_table;
386
387 return 0;
388 }
389
smu_v13_0_7_store_powerplay_table(struct smu_context * smu)390 static int smu_v13_0_7_store_powerplay_table(struct smu_context *smu)
391 {
392 struct smu_table_context *table_context = &smu->smu_table;
393 struct smu_13_0_7_powerplay_table *powerplay_table =
394 table_context->power_play_table;
395 struct amdgpu_device *adev = smu->adev;
396
397 if (adev->pdev->device == 0x51)
398 powerplay_table->smc_pptable.SkuTable.DebugOverrides |= 0x00000080;
399
400 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
401 sizeof(PPTable_t));
402
403 return 0;
404 }
405
smu_v13_0_7_check_fw_status(struct smu_context * smu)406 static int smu_v13_0_7_check_fw_status(struct smu_context *smu)
407 {
408 struct amdgpu_device *adev = smu->adev;
409 uint32_t mp1_fw_flags;
410
411 mp1_fw_flags = RREG32_PCIE(MP1_Public |
412 (smnMP1_FIRMWARE_FLAGS_SMU_13_0_7 & 0xffffffff));
413
414 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
415 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
416 return 0;
417
418 return -EIO;
419 }
420
421 #ifndef atom_smc_dpm_info_table_13_0_7
422 struct atom_smc_dpm_info_table_13_0_7 {
423 struct atom_common_table_header table_header;
424 BoardTable_t BoardTable;
425 };
426 #endif
427
smu_v13_0_7_append_powerplay_table(struct smu_context * smu)428 static int smu_v13_0_7_append_powerplay_table(struct smu_context *smu)
429 {
430 struct smu_table_context *table_context = &smu->smu_table;
431
432 PPTable_t *smc_pptable = table_context->driver_pptable;
433
434 struct atom_smc_dpm_info_table_13_0_7 *smc_dpm_table;
435
436 BoardTable_t *BoardTable = &smc_pptable->BoardTable;
437
438 int index, ret;
439
440 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
441 smc_dpm_info);
442
443 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
444 (uint8_t **)&smc_dpm_table);
445 if (ret)
446 return ret;
447
448 memcpy(BoardTable, &smc_dpm_table->BoardTable, sizeof(BoardTable_t));
449
450 return 0;
451 }
452
smu_v13_0_7_get_pptable_from_pmfw(struct smu_context * smu,void ** table,uint32_t * size)453 static int smu_v13_0_7_get_pptable_from_pmfw(struct smu_context *smu,
454 void **table,
455 uint32_t *size)
456 {
457 struct smu_table_context *smu_table = &smu->smu_table;
458 void *combo_pptable = smu_table->combo_pptable;
459 int ret = 0;
460
461 ret = smu_cmn_get_combo_pptable(smu);
462 if (ret)
463 return ret;
464
465 *table = combo_pptable;
466 *size = sizeof(struct smu_13_0_7_powerplay_table);
467
468 return 0;
469 }
470
smu_v13_0_7_setup_pptable(struct smu_context * smu)471 static int smu_v13_0_7_setup_pptable(struct smu_context *smu)
472 {
473 struct smu_table_context *smu_table = &smu->smu_table;
474 struct amdgpu_device *adev = smu->adev;
475 int ret = 0;
476
477 /*
478 * With SCPM enabled, the pptable used will be signed. It cannot
479 * be used directly by driver. To get the raw pptable, we need to
480 * rely on the combo pptable(and its revelant SMU message).
481 */
482 ret = smu_v13_0_7_get_pptable_from_pmfw(smu,
483 &smu_table->power_play_table,
484 &smu_table->power_play_table_size);
485 if (ret)
486 return ret;
487
488 ret = smu_v13_0_7_store_powerplay_table(smu);
489 if (ret)
490 return ret;
491
492 /*
493 * With SCPM enabled, the operation below will be handled
494 * by PSP. Driver involvment is unnecessary and useless.
495 */
496 if (!adev->scpm_enabled) {
497 ret = smu_v13_0_7_append_powerplay_table(smu);
498 if (ret)
499 return ret;
500 }
501
502 ret = smu_v13_0_7_check_powerplay_table(smu);
503 if (ret)
504 return ret;
505
506 return ret;
507 }
508
smu_v13_0_7_tables_init(struct smu_context * smu)509 static int smu_v13_0_7_tables_init(struct smu_context *smu)
510 {
511 struct smu_table_context *smu_table = &smu->smu_table;
512 struct smu_table *tables = smu_table->tables;
513 int ret;
514
515 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
516 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
517
518 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
519 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
520 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
521 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
522 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
523 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
524 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTableExternal_t),
525 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
526 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
527 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
528 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
529 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
530 AMDGPU_GEM_DOMAIN_VRAM);
531 SMU_TABLE_INIT(tables, SMU_TABLE_COMBO_PPTABLE, MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE,
532 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
533 SMU_TABLE_INIT(tables, SMU_TABLE_WIFIBAND,
534 sizeof(WifiBandEntryTable_t), PAGE_SIZE,
535 AMDGPU_GEM_DOMAIN_VRAM);
536
537 smu_table->metrics_table = kzalloc_obj(SmuMetricsExternal_t);
538 if (!smu_table->metrics_table)
539 goto err0_out;
540 smu_table->metrics_time = 0;
541
542 ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPU_METRICS,
543 sizeof(struct gpu_metrics_v1_3),
544 SMU_GPU_METRICS_CACHE_INTERVAL);
545 if (ret)
546 goto err1_out;
547
548 smu_table->watermarks_table = kzalloc_obj(Watermarks_t);
549 if (!smu_table->watermarks_table)
550 goto err2_out;
551
552 return 0;
553
554 err2_out:
555 smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS);
556 err1_out:
557 kfree(smu_table->metrics_table);
558 err0_out:
559 return -ENOMEM;
560 }
561
smu_v13_0_7_allocate_dpm_context(struct smu_context * smu)562 static int smu_v13_0_7_allocate_dpm_context(struct smu_context *smu)
563 {
564 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
565
566 smu_dpm->dpm_context = kzalloc_obj(struct smu_13_0_dpm_context);
567 if (!smu_dpm->dpm_context)
568 return -ENOMEM;
569
570 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
571
572 return 0;
573 }
574
smu_v13_0_7_init_smc_tables(struct smu_context * smu)575 static int smu_v13_0_7_init_smc_tables(struct smu_context *smu)
576 {
577 int ret = 0;
578
579 ret = smu_v13_0_7_tables_init(smu);
580 if (ret)
581 return ret;
582
583 ret = smu_v13_0_7_allocate_dpm_context(smu);
584 if (ret)
585 return ret;
586
587 return smu_v13_0_init_smc_tables(smu);
588 }
589
smu_v13_0_7_set_default_dpm_table(struct smu_context * smu)590 static int smu_v13_0_7_set_default_dpm_table(struct smu_context *smu)
591 {
592 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
593 PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
594 SkuTable_t *skutable = &driver_ppt->SkuTable;
595 struct smu_dpm_table *dpm_table;
596 int ret = 0;
597
598 /* socclk dpm table setup */
599 dpm_table = &dpm_context->dpm_tables.soc_table;
600 dpm_table->clk_type = SMU_SOCCLK;
601 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
602 ret = smu_v13_0_set_single_dpm_table(smu,
603 SMU_SOCCLK,
604 dpm_table);
605 if (ret)
606 return ret;
607 } else {
608 dpm_table->count = 1;
609 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
610 dpm_table->dpm_levels[0].enabled = true;
611 }
612
613 /* gfxclk dpm table setup */
614 dpm_table = &dpm_context->dpm_tables.gfx_table;
615 dpm_table->clk_type = SMU_GFXCLK;
616 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
617 ret = smu_v13_0_set_single_dpm_table(smu,
618 SMU_GFXCLK,
619 dpm_table);
620 if (ret)
621 return ret;
622
623 if (skutable->DriverReportedClocks.GameClockAc &&
624 (dpm_table->dpm_levels[dpm_table->count - 1].value >
625 skutable->DriverReportedClocks.GameClockAc)) {
626 dpm_table->dpm_levels[dpm_table->count - 1].value =
627 skutable->DriverReportedClocks.GameClockAc;
628 }
629 } else {
630 dpm_table->count = 1;
631 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
632 dpm_table->dpm_levels[0].enabled = true;
633 }
634
635 /* uclk dpm table setup */
636 dpm_table = &dpm_context->dpm_tables.uclk_table;
637 dpm_table->clk_type = SMU_UCLK;
638 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
639 ret = smu_v13_0_set_single_dpm_table(smu,
640 SMU_UCLK,
641 dpm_table);
642 if (ret)
643 return ret;
644 } else {
645 dpm_table->count = 1;
646 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
647 dpm_table->dpm_levels[0].enabled = true;
648 }
649
650 /* fclk dpm table setup */
651 dpm_table = &dpm_context->dpm_tables.fclk_table;
652 dpm_table->clk_type = SMU_FCLK;
653 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
654 ret = smu_v13_0_set_single_dpm_table(smu,
655 SMU_FCLK,
656 dpm_table);
657 if (ret)
658 return ret;
659 } else {
660 dpm_table->count = 1;
661 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
662 dpm_table->dpm_levels[0].enabled = true;
663 }
664
665 /* vclk dpm table setup */
666 dpm_table = &dpm_context->dpm_tables.vclk_table;
667 dpm_table->clk_type = SMU_VCLK;
668 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) {
669 ret = smu_v13_0_set_single_dpm_table(smu,
670 SMU_VCLK,
671 dpm_table);
672 if (ret)
673 return ret;
674 } else {
675 dpm_table->count = 1;
676 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
677 dpm_table->dpm_levels[0].enabled = true;
678 }
679
680 /* dclk dpm table setup */
681 dpm_table = &dpm_context->dpm_tables.dclk_table;
682 dpm_table->clk_type = SMU_DCLK;
683 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) {
684 ret = smu_v13_0_set_single_dpm_table(smu,
685 SMU_DCLK,
686 dpm_table);
687 if (ret)
688 return ret;
689 } else {
690 dpm_table->count = 1;
691 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
692 dpm_table->dpm_levels[0].enabled = true;
693 }
694
695 /* dcefclk dpm table setup */
696 dpm_table = &dpm_context->dpm_tables.dcef_table;
697 dpm_table->clk_type = SMU_DCEFCLK;
698 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCN_BIT)) {
699 ret = smu_v13_0_set_single_dpm_table(smu,
700 SMU_DCEFCLK,
701 dpm_table);
702 if (ret)
703 return ret;
704 } else {
705 dpm_table->count = 1;
706 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
707 dpm_table->dpm_levels[0].enabled = true;
708 }
709
710 return 0;
711 }
712
smu_v13_0_7_is_dpm_running(struct smu_context * smu)713 static bool smu_v13_0_7_is_dpm_running(struct smu_context *smu)
714 {
715 int ret = 0;
716 struct smu_feature_bits feature_enabled;
717
718 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
719 if (ret)
720 return false;
721
722 return smu_feature_bits_test_mask(&feature_enabled,
723 smu_v13_0_7_dpm_features.bits);
724 }
725
smu_v13_0_7_get_throttler_status(SmuMetrics_t * metrics)726 static uint32_t smu_v13_0_7_get_throttler_status(SmuMetrics_t *metrics)
727 {
728 uint32_t throttler_status = 0;
729 int i;
730
731 for (i = 0; i < THROTTLER_COUNT; i++)
732 throttler_status |=
733 (metrics->ThrottlingPercentage[i] ? 1U << i : 0);
734
735 return throttler_status;
736 }
737
738 #define SMU_13_0_7_BUSY_THRESHOLD 15
smu_v13_0_7_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)739 static int smu_v13_0_7_get_smu_metrics_data(struct smu_context *smu,
740 MetricsMember_t member,
741 uint32_t *value)
742 {
743 struct smu_table_context *smu_table = &smu->smu_table;
744 SmuMetrics_t *metrics =
745 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
746 int ret = 0;
747
748 ret = smu_cmn_get_metrics_table(smu,
749 NULL,
750 false);
751 if (ret)
752 return ret;
753
754 switch (member) {
755 case METRICS_CURR_GFXCLK:
756 *value = metrics->CurrClock[PPCLK_GFXCLK];
757 break;
758 case METRICS_CURR_SOCCLK:
759 *value = metrics->CurrClock[PPCLK_SOCCLK];
760 break;
761 case METRICS_CURR_UCLK:
762 *value = metrics->CurrClock[PPCLK_UCLK];
763 break;
764 case METRICS_CURR_VCLK:
765 *value = metrics->CurrClock[PPCLK_VCLK_0];
766 break;
767 case METRICS_CURR_VCLK1:
768 *value = metrics->CurrClock[PPCLK_VCLK_1];
769 break;
770 case METRICS_CURR_DCLK:
771 *value = metrics->CurrClock[PPCLK_DCLK_0];
772 break;
773 case METRICS_CURR_DCLK1:
774 *value = metrics->CurrClock[PPCLK_DCLK_1];
775 break;
776 case METRICS_CURR_FCLK:
777 *value = metrics->CurrClock[PPCLK_FCLK];
778 break;
779 case METRICS_CURR_DCEFCLK:
780 *value = metrics->CurrClock[PPCLK_DCFCLK];
781 break;
782 case METRICS_AVERAGE_GFXCLK:
783 *value = metrics->AverageGfxclkFrequencyPreDs;
784 break;
785 case METRICS_AVERAGE_FCLK:
786 if (smu_safe_u16_nn(metrics->AverageUclkActivity) <= SMU_13_0_7_BUSY_THRESHOLD)
787 *value = metrics->AverageFclkFrequencyPostDs;
788 else
789 *value = metrics->AverageFclkFrequencyPreDs;
790 break;
791 case METRICS_AVERAGE_UCLK:
792 if (smu_safe_u16_nn(metrics->AverageUclkActivity) <= SMU_13_0_7_BUSY_THRESHOLD)
793 *value = metrics->AverageMemclkFrequencyPostDs;
794 else
795 *value = metrics->AverageMemclkFrequencyPreDs;
796 break;
797 case METRICS_AVERAGE_VCNACTIVITY:
798 *value = max(metrics->Vcn0ActivityPercentage,
799 metrics->Vcn1ActivityPercentage);
800 break;
801 case METRICS_AVERAGE_VCLK:
802 *value = metrics->AverageVclk0Frequency;
803 break;
804 case METRICS_AVERAGE_DCLK:
805 *value = metrics->AverageDclk0Frequency;
806 break;
807 case METRICS_AVERAGE_VCLK1:
808 *value = metrics->AverageVclk1Frequency;
809 break;
810 case METRICS_AVERAGE_DCLK1:
811 *value = metrics->AverageDclk1Frequency;
812 break;
813 case METRICS_AVERAGE_GFXACTIVITY:
814 *value = metrics->AverageGfxActivity;
815 break;
816 case METRICS_AVERAGE_MEMACTIVITY:
817 *value = smu_safe_u16_nn(metrics->AverageUclkActivity);
818 break;
819 case METRICS_AVERAGE_SOCKETPOWER:
820 *value = metrics->AverageSocketPower << 8;
821 break;
822 case METRICS_TEMPERATURE_EDGE:
823 *value = metrics->AvgTemperature[TEMP_EDGE] *
824 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
825 break;
826 case METRICS_TEMPERATURE_HOTSPOT:
827 *value = metrics->AvgTemperature[TEMP_HOTSPOT] *
828 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
829 break;
830 case METRICS_TEMPERATURE_MEM:
831 *value = metrics->AvgTemperature[TEMP_MEM] *
832 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
833 break;
834 case METRICS_TEMPERATURE_VRGFX:
835 *value = metrics->AvgTemperature[TEMP_VR_GFX] *
836 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
837 break;
838 case METRICS_TEMPERATURE_VRSOC:
839 *value = metrics->AvgTemperature[TEMP_VR_SOC] *
840 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
841 break;
842 case METRICS_THROTTLER_STATUS:
843 *value = smu_v13_0_7_get_throttler_status(metrics);
844 break;
845 case METRICS_CURR_FANSPEED:
846 *value = metrics->AvgFanRpm;
847 break;
848 case METRICS_CURR_FANPWM:
849 *value = metrics->AvgFanPwm;
850 break;
851 case METRICS_VOLTAGE_VDDGFX:
852 *value = metrics->AvgVoltage[SVI_PLANE_GFX];
853 break;
854 case METRICS_PCIE_RATE:
855 *value = metrics->PcieRate;
856 break;
857 case METRICS_PCIE_WIDTH:
858 *value = metrics->PcieWidth;
859 break;
860 default:
861 *value = UINT_MAX;
862 break;
863 }
864
865 return ret;
866 }
867
smu_v13_0_7_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)868 static int smu_v13_0_7_get_dpm_ultimate_freq(struct smu_context *smu,
869 enum smu_clk_type clk_type,
870 uint32_t *min,
871 uint32_t *max)
872 {
873 struct smu_13_0_dpm_context *dpm_context =
874 smu->smu_dpm.dpm_context;
875 struct smu_dpm_table *dpm_table;
876
877 switch (clk_type) {
878 case SMU_MCLK:
879 case SMU_UCLK:
880 /* uclk dpm table */
881 dpm_table = &dpm_context->dpm_tables.uclk_table;
882 break;
883 case SMU_GFXCLK:
884 case SMU_SCLK:
885 /* gfxclk dpm table */
886 dpm_table = &dpm_context->dpm_tables.gfx_table;
887 break;
888 case SMU_SOCCLK:
889 /* socclk dpm table */
890 dpm_table = &dpm_context->dpm_tables.soc_table;
891 break;
892 case SMU_FCLK:
893 /* fclk dpm table */
894 dpm_table = &dpm_context->dpm_tables.fclk_table;
895 break;
896 case SMU_VCLK:
897 case SMU_VCLK1:
898 /* vclk dpm table */
899 dpm_table = &dpm_context->dpm_tables.vclk_table;
900 break;
901 case SMU_DCLK:
902 case SMU_DCLK1:
903 /* dclk dpm table */
904 dpm_table = &dpm_context->dpm_tables.dclk_table;
905 break;
906 default:
907 dev_err(smu->adev->dev, "Unsupported clock type!\n");
908 return -EINVAL;
909 }
910
911 if (min)
912 *min = SMU_DPM_TABLE_MIN(dpm_table);
913 if (max)
914 *max = SMU_DPM_TABLE_MAX(dpm_table);
915
916 return 0;
917 }
918
smu_v13_0_7_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)919 static int smu_v13_0_7_read_sensor(struct smu_context *smu,
920 enum amd_pp_sensors sensor,
921 void *data,
922 uint32_t *size)
923 {
924 struct smu_table_context *table_context = &smu->smu_table;
925 PPTable_t *smc_pptable = table_context->driver_pptable;
926 int ret = 0;
927
928 switch (sensor) {
929 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
930 *(uint16_t *)data = smc_pptable->SkuTable.FanMaximumRpm;
931 *size = 4;
932 break;
933 case AMDGPU_PP_SENSOR_MEM_LOAD:
934 ret = smu_v13_0_7_get_smu_metrics_data(smu,
935 METRICS_AVERAGE_MEMACTIVITY,
936 (uint32_t *)data);
937 *size = 4;
938 break;
939 case AMDGPU_PP_SENSOR_GPU_LOAD:
940 ret = smu_v13_0_7_get_smu_metrics_data(smu,
941 METRICS_AVERAGE_GFXACTIVITY,
942 (uint32_t *)data);
943 *size = 4;
944 break;
945 case AMDGPU_PP_SENSOR_VCN_LOAD:
946 ret = smu_v13_0_7_get_smu_metrics_data(smu,
947 METRICS_AVERAGE_VCNACTIVITY,
948 (uint32_t *)data);
949 *size = 4;
950 break;
951 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
952 ret = smu_v13_0_7_get_smu_metrics_data(smu,
953 METRICS_AVERAGE_SOCKETPOWER,
954 (uint32_t *)data);
955 *size = 4;
956 break;
957 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
958 ret = smu_v13_0_7_get_smu_metrics_data(smu,
959 METRICS_TEMPERATURE_HOTSPOT,
960 (uint32_t *)data);
961 *size = 4;
962 break;
963 case AMDGPU_PP_SENSOR_EDGE_TEMP:
964 ret = smu_v13_0_7_get_smu_metrics_data(smu,
965 METRICS_TEMPERATURE_EDGE,
966 (uint32_t *)data);
967 *size = 4;
968 break;
969 case AMDGPU_PP_SENSOR_MEM_TEMP:
970 ret = smu_v13_0_7_get_smu_metrics_data(smu,
971 METRICS_TEMPERATURE_MEM,
972 (uint32_t *)data);
973 *size = 4;
974 break;
975 case AMDGPU_PP_SENSOR_GFX_MCLK:
976 ret = smu_v13_0_7_get_smu_metrics_data(smu,
977 METRICS_CURR_UCLK,
978 (uint32_t *)data);
979 *(uint32_t *)data *= 100;
980 *size = 4;
981 break;
982 case AMDGPU_PP_SENSOR_GFX_SCLK:
983 ret = smu_v13_0_7_get_smu_metrics_data(smu,
984 METRICS_AVERAGE_GFXCLK,
985 (uint32_t *)data);
986 *(uint32_t *)data *= 100;
987 *size = 4;
988 break;
989 case AMDGPU_PP_SENSOR_VDDGFX:
990 ret = smu_v13_0_7_get_smu_metrics_data(smu,
991 METRICS_VOLTAGE_VDDGFX,
992 (uint32_t *)data);
993 *size = 4;
994 break;
995 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
996 default:
997 ret = -EOPNOTSUPP;
998 break;
999 }
1000
1001 return ret;
1002 }
1003
smu_v13_0_7_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1004 static int smu_v13_0_7_get_current_clk_freq_by_table(struct smu_context *smu,
1005 enum smu_clk_type clk_type,
1006 uint32_t *value)
1007 {
1008 MetricsMember_t member_type;
1009 int clk_id = 0;
1010
1011 clk_id = smu_cmn_to_asic_specific_index(smu,
1012 CMN2ASIC_MAPPING_CLK,
1013 clk_type);
1014 if (clk_id < 0)
1015 return -EINVAL;
1016
1017 switch (clk_id) {
1018 case PPCLK_GFXCLK:
1019 member_type = METRICS_AVERAGE_GFXCLK;
1020 break;
1021 case PPCLK_UCLK:
1022 member_type = METRICS_CURR_UCLK;
1023 break;
1024 case PPCLK_FCLK:
1025 member_type = METRICS_CURR_FCLK;
1026 break;
1027 case PPCLK_SOCCLK:
1028 member_type = METRICS_CURR_SOCCLK;
1029 break;
1030 case PPCLK_VCLK_0:
1031 member_type = METRICS_CURR_VCLK;
1032 break;
1033 case PPCLK_DCLK_0:
1034 member_type = METRICS_CURR_DCLK;
1035 break;
1036 case PPCLK_VCLK_1:
1037 member_type = METRICS_CURR_VCLK1;
1038 break;
1039 case PPCLK_DCLK_1:
1040 member_type = METRICS_CURR_DCLK1;
1041 break;
1042 case PPCLK_DCFCLK:
1043 member_type = METRICS_CURR_DCEFCLK;
1044 break;
1045 default:
1046 return -EINVAL;
1047 }
1048
1049 return smu_v13_0_7_get_smu_metrics_data(smu,
1050 member_type,
1051 value);
1052 }
1053
smu_v13_0_7_is_od_feature_supported(struct smu_context * smu,int od_feature_bit)1054 static bool smu_v13_0_7_is_od_feature_supported(struct smu_context *smu,
1055 int od_feature_bit)
1056 {
1057 PPTable_t *pptable = smu->smu_table.driver_pptable;
1058 const OverDriveLimits_t * const overdrive_upperlimits =
1059 &pptable->SkuTable.OverDriveLimitsBasicMax;
1060 int32_t min_value, max_value;
1061 bool feature_enabled;
1062
1063 switch (od_feature_bit) {
1064 case PP_OD_FEATURE_FAN_CURVE_BIT:
1065 feature_enabled = !!(overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit));
1066 if (feature_enabled) {
1067 smu_v13_0_7_get_od_setting_limits(smu, PP_OD_FEATURE_FAN_CURVE_TEMP,
1068 &min_value, &max_value);
1069 if (!min_value && !max_value) {
1070 feature_enabled = false;
1071 goto out;
1072 }
1073
1074 smu_v13_0_7_get_od_setting_limits(smu, PP_OD_FEATURE_FAN_CURVE_PWM,
1075 &min_value, &max_value);
1076 if (!min_value && !max_value) {
1077 feature_enabled = false;
1078 goto out;
1079 }
1080 }
1081 break;
1082 default:
1083 feature_enabled = !!(overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit));
1084 break;
1085 }
1086
1087 out:
1088 return feature_enabled;
1089 }
1090
smu_v13_0_7_get_od_setting_limits(struct smu_context * smu,int od_feature_bit,int32_t * min,int32_t * max)1091 static void smu_v13_0_7_get_od_setting_limits(struct smu_context *smu,
1092 int od_feature_bit,
1093 int32_t *min,
1094 int32_t *max)
1095 {
1096 PPTable_t *pptable = smu->smu_table.driver_pptable;
1097 const OverDriveLimits_t * const overdrive_upperlimits =
1098 &pptable->SkuTable.OverDriveLimitsBasicMax;
1099 const OverDriveLimits_t * const overdrive_lowerlimits =
1100 &pptable->SkuTable.OverDriveLimitsMin;
1101 int32_t od_min_setting, od_max_setting;
1102
1103 switch (od_feature_bit) {
1104 case PP_OD_FEATURE_GFXCLK_FMIN:
1105 od_min_setting = overdrive_lowerlimits->GfxclkFmin;
1106 od_max_setting = overdrive_upperlimits->GfxclkFmin;
1107 break;
1108 case PP_OD_FEATURE_GFXCLK_FMAX:
1109 od_min_setting = overdrive_lowerlimits->GfxclkFmax;
1110 od_max_setting = overdrive_upperlimits->GfxclkFmax;
1111 break;
1112 case PP_OD_FEATURE_UCLK_FMIN:
1113 od_min_setting = overdrive_lowerlimits->UclkFmin;
1114 od_max_setting = overdrive_upperlimits->UclkFmin;
1115 break;
1116 case PP_OD_FEATURE_UCLK_FMAX:
1117 od_min_setting = overdrive_lowerlimits->UclkFmax;
1118 od_max_setting = overdrive_upperlimits->UclkFmax;
1119 break;
1120 case PP_OD_FEATURE_GFX_VF_CURVE:
1121 od_min_setting = overdrive_lowerlimits->VoltageOffsetPerZoneBoundary;
1122 od_max_setting = overdrive_upperlimits->VoltageOffsetPerZoneBoundary;
1123 break;
1124 case PP_OD_FEATURE_FAN_CURVE_TEMP:
1125 od_min_setting = overdrive_lowerlimits->FanLinearTempPoints;
1126 od_max_setting = overdrive_upperlimits->FanLinearTempPoints;
1127 break;
1128 case PP_OD_FEATURE_FAN_CURVE_PWM:
1129 od_min_setting = overdrive_lowerlimits->FanLinearPwmPoints;
1130 od_max_setting = overdrive_upperlimits->FanLinearPwmPoints;
1131 break;
1132 case PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT:
1133 od_min_setting = overdrive_lowerlimits->AcousticLimitRpmThreshold;
1134 od_max_setting = overdrive_upperlimits->AcousticLimitRpmThreshold;
1135 break;
1136 case PP_OD_FEATURE_FAN_ACOUSTIC_TARGET:
1137 od_min_setting = overdrive_lowerlimits->AcousticTargetRpmThreshold;
1138 od_max_setting = overdrive_upperlimits->AcousticTargetRpmThreshold;
1139 break;
1140 case PP_OD_FEATURE_FAN_TARGET_TEMPERATURE:
1141 od_min_setting = overdrive_lowerlimits->FanTargetTemperature;
1142 od_max_setting = overdrive_upperlimits->FanTargetTemperature;
1143 break;
1144 case PP_OD_FEATURE_FAN_MINIMUM_PWM:
1145 od_min_setting = overdrive_lowerlimits->FanMinimumPwm;
1146 od_max_setting = overdrive_upperlimits->FanMinimumPwm;
1147 break;
1148 case PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE:
1149 od_min_setting = overdrive_lowerlimits->FanZeroRpmEnable;
1150 od_max_setting = overdrive_upperlimits->FanZeroRpmEnable;
1151 break;
1152 case PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP:
1153 od_min_setting = overdrive_lowerlimits->FanZeroRpmStopTemp;
1154 od_max_setting = overdrive_upperlimits->FanZeroRpmStopTemp;
1155 break;
1156 default:
1157 od_min_setting = od_max_setting = INT_MAX;
1158 break;
1159 }
1160
1161 if (min)
1162 *min = od_min_setting;
1163 if (max)
1164 *max = od_max_setting;
1165 }
1166
smu_v13_0_7_dump_od_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)1167 static void smu_v13_0_7_dump_od_table(struct smu_context *smu,
1168 OverDriveTableExternal_t *od_table)
1169 {
1170 struct amdgpu_device *adev = smu->adev;
1171
1172 dev_dbg(adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->OverDriveTable.GfxclkFmin,
1173 od_table->OverDriveTable.GfxclkFmax);
1174 dev_dbg(adev->dev, "OD: Uclk: (%d, %d)\n", od_table->OverDriveTable.UclkFmin,
1175 od_table->OverDriveTable.UclkFmax);
1176 }
1177
smu_v13_0_7_get_overdrive_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)1178 static int smu_v13_0_7_get_overdrive_table(struct smu_context *smu,
1179 OverDriveTableExternal_t *od_table)
1180 {
1181 int ret = 0;
1182
1183 ret = smu_cmn_update_table(smu,
1184 SMU_TABLE_OVERDRIVE,
1185 0,
1186 (void *)od_table,
1187 false);
1188 if (ret)
1189 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
1190
1191 return ret;
1192 }
1193
smu_v13_0_7_upload_overdrive_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)1194 static int smu_v13_0_7_upload_overdrive_table(struct smu_context *smu,
1195 OverDriveTableExternal_t *od_table)
1196 {
1197 int ret = 0;
1198
1199 ret = smu_cmn_update_table(smu,
1200 SMU_TABLE_OVERDRIVE,
1201 0,
1202 (void *)od_table,
1203 true);
1204 if (ret)
1205 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
1206
1207 return ret;
1208 }
1209
smu_v13_0_7_emit_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf,int * offset)1210 static int smu_v13_0_7_emit_clk_levels(struct smu_context *smu,
1211 enum smu_clk_type clk_type, char *buf,
1212 int *offset)
1213 {
1214 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1215 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1216 OverDriveTableExternal_t *od_table =
1217 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
1218 int i, curr_freq, size = *offset, start_offset = *offset;
1219 struct smu_dpm_table *single_dpm_table = NULL;
1220 struct smu_pcie_table *pcie_table;
1221 uint32_t gen_speed, lane_width;
1222 int32_t min_value, max_value;
1223 int ret = 0;
1224
1225 if (amdgpu_ras_intr_triggered()) {
1226 sysfs_emit_at(buf, size, "unavailable\n");
1227 return -EBUSY;
1228 }
1229
1230 switch (clk_type) {
1231 case SMU_SCLK:
1232 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1233 break;
1234 case SMU_MCLK:
1235 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1236 break;
1237 case SMU_SOCCLK:
1238 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1239 break;
1240 case SMU_FCLK:
1241 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1242 break;
1243 case SMU_VCLK:
1244 case SMU_VCLK1:
1245 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1246 break;
1247 case SMU_DCLK:
1248 case SMU_DCLK1:
1249 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1250 break;
1251 case SMU_DCEFCLK:
1252 single_dpm_table = &(dpm_context->dpm_tables.dcef_table);
1253 break;
1254 case SMU_PCIE:
1255 ret = smu_v13_0_7_get_smu_metrics_data(smu,
1256 METRICS_PCIE_RATE,
1257 &gen_speed);
1258 if (ret)
1259 return ret;
1260
1261 ret = smu_v13_0_7_get_smu_metrics_data(smu,
1262 METRICS_PCIE_WIDTH,
1263 &lane_width);
1264 if (ret)
1265 return ret;
1266
1267 pcie_table = &(dpm_context->dpm_tables.pcie_table);
1268 return smu_cmn_print_pcie_levels(smu, pcie_table,
1269 SMU_DPM_PCIE_GEN_IDX(gen_speed),
1270 SMU_DPM_PCIE_WIDTH_IDX(lane_width),
1271 buf, offset);
1272 case SMU_OD_SCLK:
1273 if (!smu_v13_0_7_is_od_feature_supported(smu,
1274 PP_OD_FEATURE_GFXCLK_BIT))
1275 break;
1276
1277 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1278 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1279 od_table->OverDriveTable.GfxclkFmin,
1280 od_table->OverDriveTable.GfxclkFmax);
1281 break;
1282
1283 case SMU_OD_MCLK:
1284 if (!smu_v13_0_7_is_od_feature_supported(smu,
1285 PP_OD_FEATURE_UCLK_BIT))
1286 break;
1287
1288 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1289 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n",
1290 od_table->OverDriveTable.UclkFmin,
1291 od_table->OverDriveTable.UclkFmax);
1292 break;
1293
1294 case SMU_OD_VDDGFX_OFFSET:
1295 if (!smu_v13_0_7_is_od_feature_supported(smu,
1296 PP_OD_FEATURE_GFX_VF_CURVE_BIT))
1297 break;
1298
1299 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1300 size += sysfs_emit_at(buf, size, "%dmV\n",
1301 od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[0]);
1302 break;
1303
1304 case SMU_OD_FAN_CURVE:
1305 if (!smu_v13_0_7_is_od_feature_supported(smu,
1306 PP_OD_FEATURE_FAN_CURVE_BIT))
1307 break;
1308
1309 size += sysfs_emit_at(buf, size, "OD_FAN_CURVE:\n");
1310 for (i = 0; i < NUM_OD_FAN_MAX_POINTS - 1; i++)
1311 size += sysfs_emit_at(buf, size, "%d: %dC %d%%\n",
1312 i,
1313 (int)od_table->OverDriveTable.FanLinearTempPoints[i],
1314 (int)od_table->OverDriveTable.FanLinearPwmPoints[i]);
1315
1316 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1317 smu_v13_0_7_get_od_setting_limits(smu,
1318 PP_OD_FEATURE_FAN_CURVE_TEMP,
1319 &min_value,
1320 &max_value);
1321 size += sysfs_emit_at(buf, size, "FAN_CURVE(hotspot temp): %uC %uC\n",
1322 min_value, max_value);
1323
1324 smu_v13_0_7_get_od_setting_limits(smu,
1325 PP_OD_FEATURE_FAN_CURVE_PWM,
1326 &min_value,
1327 &max_value);
1328 size += sysfs_emit_at(buf, size, "FAN_CURVE(fan speed): %u%% %u%%\n",
1329 min_value, max_value);
1330
1331 break;
1332
1333 case SMU_OD_ACOUSTIC_LIMIT:
1334 if (!smu_v13_0_7_is_od_feature_supported(smu,
1335 PP_OD_FEATURE_FAN_CURVE_BIT))
1336 break;
1337
1338 size += sysfs_emit_at(buf, size, "OD_ACOUSTIC_LIMIT:\n");
1339 size += sysfs_emit_at(buf, size, "%d\n",
1340 (int)od_table->OverDriveTable.AcousticLimitRpmThreshold);
1341
1342 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1343 smu_v13_0_7_get_od_setting_limits(smu,
1344 PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT,
1345 &min_value,
1346 &max_value);
1347 size += sysfs_emit_at(buf, size, "ACOUSTIC_LIMIT: %u %u\n",
1348 min_value, max_value);
1349 break;
1350
1351 case SMU_OD_ACOUSTIC_TARGET:
1352 if (!smu_v13_0_7_is_od_feature_supported(smu,
1353 PP_OD_FEATURE_FAN_CURVE_BIT))
1354 break;
1355
1356 size += sysfs_emit_at(buf, size, "OD_ACOUSTIC_TARGET:\n");
1357 size += sysfs_emit_at(buf, size, "%d\n",
1358 (int)od_table->OverDriveTable.AcousticTargetRpmThreshold);
1359
1360 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1361 smu_v13_0_7_get_od_setting_limits(smu,
1362 PP_OD_FEATURE_FAN_ACOUSTIC_TARGET,
1363 &min_value,
1364 &max_value);
1365 size += sysfs_emit_at(buf, size, "ACOUSTIC_TARGET: %u %u\n",
1366 min_value, max_value);
1367 break;
1368
1369 case SMU_OD_FAN_TARGET_TEMPERATURE:
1370 if (!smu_v13_0_7_is_od_feature_supported(smu,
1371 PP_OD_FEATURE_FAN_CURVE_BIT))
1372 break;
1373
1374 size += sysfs_emit_at(buf, size, "FAN_TARGET_TEMPERATURE:\n");
1375 size += sysfs_emit_at(buf, size, "%d\n",
1376 (int)od_table->OverDriveTable.FanTargetTemperature);
1377
1378 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1379 smu_v13_0_7_get_od_setting_limits(smu,
1380 PP_OD_FEATURE_FAN_TARGET_TEMPERATURE,
1381 &min_value,
1382 &max_value);
1383 size += sysfs_emit_at(buf, size, "TARGET_TEMPERATURE: %u %u\n",
1384 min_value, max_value);
1385 break;
1386
1387 case SMU_OD_FAN_MINIMUM_PWM:
1388 if (!smu_v13_0_7_is_od_feature_supported(smu,
1389 PP_OD_FEATURE_FAN_CURVE_BIT))
1390 break;
1391
1392 size += sysfs_emit_at(buf, size, "FAN_MINIMUM_PWM:\n");
1393 size += sysfs_emit_at(buf, size, "%d\n",
1394 (int)od_table->OverDriveTable.FanMinimumPwm);
1395
1396 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1397 smu_v13_0_7_get_od_setting_limits(smu,
1398 PP_OD_FEATURE_FAN_MINIMUM_PWM,
1399 &min_value,
1400 &max_value);
1401 size += sysfs_emit_at(buf, size, "MINIMUM_PWM: %u %u\n",
1402 min_value, max_value);
1403 break;
1404
1405 case SMU_OD_FAN_ZERO_RPM_ENABLE:
1406 if (!smu_v13_0_7_is_od_feature_supported(smu,
1407 PP_OD_FEATURE_ZERO_FAN_BIT))
1408 break;
1409
1410 size += sysfs_emit_at(buf, size, "FAN_ZERO_RPM_ENABLE:\n");
1411 size += sysfs_emit_at(buf, size, "%d\n",
1412 (int)od_table->OverDriveTable.FanZeroRpmEnable);
1413
1414 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1415 smu_v13_0_7_get_od_setting_limits(smu,
1416 PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE,
1417 &min_value,
1418 &max_value);
1419 size += sysfs_emit_at(buf, size, "ZERO_RPM_ENABLE: %u %u\n",
1420 min_value, max_value);
1421 break;
1422
1423 case SMU_OD_FAN_ZERO_RPM_STOP_TEMP:
1424 if (!smu_v13_0_7_is_od_feature_supported(smu,
1425 PP_OD_FEATURE_ZERO_FAN_BIT))
1426 break;
1427
1428 size += sysfs_emit_at(buf, size, "FAN_ZERO_RPM_STOP_TEMPERATURE:\n");
1429 size += sysfs_emit_at(buf, size, "%d\n",
1430 (int)od_table->OverDriveTable.FanZeroRpmStopTemp);
1431
1432 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1433 smu_v13_0_7_get_od_setting_limits(smu,
1434 PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP,
1435 &min_value,
1436 &max_value);
1437 size += sysfs_emit_at(buf, size, "ZERO_RPM_STOP_TEMPERATURE: %u %u\n",
1438 min_value, max_value);
1439 break;
1440
1441 case SMU_OD_RANGE:
1442 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT) &&
1443 !smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT) &&
1444 !smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT))
1445 break;
1446
1447 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1448
1449 if (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
1450 smu_v13_0_7_get_od_setting_limits(smu,
1451 PP_OD_FEATURE_GFXCLK_FMIN,
1452 &min_value,
1453 NULL);
1454 smu_v13_0_7_get_od_setting_limits(smu,
1455 PP_OD_FEATURE_GFXCLK_FMAX,
1456 NULL,
1457 &max_value);
1458 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1459 min_value, max_value);
1460 }
1461
1462 if (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {
1463 smu_v13_0_7_get_od_setting_limits(smu,
1464 PP_OD_FEATURE_UCLK_FMIN,
1465 &min_value,
1466 NULL);
1467 smu_v13_0_7_get_od_setting_limits(smu,
1468 PP_OD_FEATURE_UCLK_FMAX,
1469 NULL,
1470 &max_value);
1471 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1472 min_value, max_value);
1473 }
1474
1475 if (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
1476 smu_v13_0_7_get_od_setting_limits(smu,
1477 PP_OD_FEATURE_GFX_VF_CURVE,
1478 &min_value,
1479 &max_value);
1480 size += sysfs_emit_at(buf, size, "VDDGFX_OFFSET: %7dmv %10dmv\n",
1481 min_value, max_value);
1482 }
1483 break;
1484
1485 default:
1486 break;
1487 }
1488
1489 if (single_dpm_table) {
1490 ret = smu_v13_0_7_get_current_clk_freq_by_table(smu, clk_type,
1491 &curr_freq);
1492 if (ret) {
1493 dev_err(smu->adev->dev,
1494 "Failed to get current clock freq!");
1495 return ret;
1496 }
1497 return smu_cmn_print_dpm_clk_levels(smu, single_dpm_table,
1498 curr_freq, buf, offset);
1499 }
1500
1501 *offset += size - start_offset;
1502
1503 return 0;
1504 }
1505
smu_v13_0_7_od_restore_table_single(struct smu_context * smu,long input)1506 static int smu_v13_0_7_od_restore_table_single(struct smu_context *smu, long input)
1507 {
1508 struct smu_table_context *table_context = &smu->smu_table;
1509 OverDriveTableExternal_t *boot_overdrive_table =
1510 (OverDriveTableExternal_t *)table_context->boot_overdrive_table;
1511 OverDriveTableExternal_t *od_table =
1512 (OverDriveTableExternal_t *)table_context->overdrive_table;
1513 struct amdgpu_device *adev = smu->adev;
1514 int i;
1515
1516 switch (input) {
1517 case PP_OD_EDIT_FAN_CURVE:
1518 for (i = 0; i < NUM_OD_FAN_MAX_POINTS; i++) {
1519 od_table->OverDriveTable.FanLinearTempPoints[i] =
1520 boot_overdrive_table->OverDriveTable.FanLinearTempPoints[i];
1521 od_table->OverDriveTable.FanLinearPwmPoints[i] =
1522 boot_overdrive_table->OverDriveTable.FanLinearPwmPoints[i];
1523 }
1524 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1525 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1526 break;
1527 case PP_OD_EDIT_ACOUSTIC_LIMIT:
1528 od_table->OverDriveTable.AcousticLimitRpmThreshold =
1529 boot_overdrive_table->OverDriveTable.AcousticLimitRpmThreshold;
1530 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1531 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1532 break;
1533 case PP_OD_EDIT_ACOUSTIC_TARGET:
1534 od_table->OverDriveTable.AcousticTargetRpmThreshold =
1535 boot_overdrive_table->OverDriveTable.AcousticTargetRpmThreshold;
1536 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1537 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1538 break;
1539 case PP_OD_EDIT_FAN_TARGET_TEMPERATURE:
1540 od_table->OverDriveTable.FanTargetTemperature =
1541 boot_overdrive_table->OverDriveTable.FanTargetTemperature;
1542 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1543 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1544 break;
1545 case PP_OD_EDIT_FAN_MINIMUM_PWM:
1546 od_table->OverDriveTable.FanMinimumPwm =
1547 boot_overdrive_table->OverDriveTable.FanMinimumPwm;
1548 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1549 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1550 break;
1551 case PP_OD_EDIT_FAN_ZERO_RPM_ENABLE:
1552 od_table->OverDriveTable.FanZeroRpmEnable =
1553 boot_overdrive_table->OverDriveTable.FanZeroRpmEnable;
1554 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1555 break;
1556 case PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP:
1557 od_table->OverDriveTable.FanZeroRpmStopTemp =
1558 boot_overdrive_table->OverDriveTable.FanZeroRpmStopTemp;
1559 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1560 break;
1561 default:
1562 dev_info(adev->dev, "Invalid table index: %ld\n", input);
1563 return -EINVAL;
1564 }
1565
1566 return 0;
1567 }
1568
smu_v13_0_7_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)1569 static int smu_v13_0_7_od_edit_dpm_table(struct smu_context *smu,
1570 enum PP_OD_DPM_TABLE_COMMAND type,
1571 long input[],
1572 uint32_t size)
1573 {
1574 struct smu_table_context *table_context = &smu->smu_table;
1575 OverDriveTableExternal_t *od_table =
1576 (OverDriveTableExternal_t *)table_context->overdrive_table;
1577 struct amdgpu_device *adev = smu->adev;
1578 uint32_t offset_of_voltageoffset;
1579 int32_t minimum, maximum;
1580 uint32_t feature_ctrlmask;
1581 int i, ret = 0;
1582
1583 switch (type) {
1584 case PP_OD_EDIT_SCLK_VDDC_TABLE:
1585 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
1586 dev_warn(adev->dev, "GFXCLK_LIMITS setting not supported!\n");
1587 return -ENOTSUPP;
1588 }
1589
1590 for (i = 0; i < size; i += 2) {
1591 if (i + 2 > size) {
1592 dev_info(adev->dev, "invalid number of input parameters %d\n", size);
1593 return -EINVAL;
1594 }
1595
1596 switch (input[i]) {
1597 case 0:
1598 smu_v13_0_7_get_od_setting_limits(smu,
1599 PP_OD_FEATURE_GFXCLK_FMIN,
1600 &minimum,
1601 &maximum);
1602 if (input[i + 1] < minimum ||
1603 input[i + 1] > maximum) {
1604 dev_info(adev->dev, "GfxclkFmin (%ld) must be within [%u, %u]!\n",
1605 input[i + 1], minimum, maximum);
1606 return -EINVAL;
1607 }
1608
1609 od_table->OverDriveTable.GfxclkFmin = input[i + 1];
1610 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT;
1611 break;
1612
1613 case 1:
1614 smu_v13_0_7_get_od_setting_limits(smu,
1615 PP_OD_FEATURE_GFXCLK_FMAX,
1616 &minimum,
1617 &maximum);
1618 if (input[i + 1] < minimum ||
1619 input[i + 1] > maximum) {
1620 dev_info(adev->dev, "GfxclkFmax (%ld) must be within [%u, %u]!\n",
1621 input[i + 1], minimum, maximum);
1622 return -EINVAL;
1623 }
1624
1625 od_table->OverDriveTable.GfxclkFmax = input[i + 1];
1626 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT;
1627 break;
1628
1629 default:
1630 dev_info(adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
1631 dev_info(adev->dev, "Supported indices: [0:min,1:max]\n");
1632 return -EINVAL;
1633 }
1634 }
1635
1636 if (od_table->OverDriveTable.GfxclkFmin > od_table->OverDriveTable.GfxclkFmax) {
1637 dev_err(adev->dev,
1638 "Invalid setting: GfxclkFmin(%u) is bigger than GfxclkFmax(%u)\n",
1639 (uint32_t)od_table->OverDriveTable.GfxclkFmin,
1640 (uint32_t)od_table->OverDriveTable.GfxclkFmax);
1641 return -EINVAL;
1642 }
1643 break;
1644
1645 case PP_OD_EDIT_MCLK_VDDC_TABLE:
1646 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {
1647 dev_warn(adev->dev, "UCLK_LIMITS setting not supported!\n");
1648 return -ENOTSUPP;
1649 }
1650
1651 for (i = 0; i < size; i += 2) {
1652 if (i + 2 > size) {
1653 dev_info(adev->dev, "invalid number of input parameters %d\n", size);
1654 return -EINVAL;
1655 }
1656
1657 switch (input[i]) {
1658 case 0:
1659 smu_v13_0_7_get_od_setting_limits(smu,
1660 PP_OD_FEATURE_UCLK_FMIN,
1661 &minimum,
1662 &maximum);
1663 if (input[i + 1] < minimum ||
1664 input[i + 1] > maximum) {
1665 dev_info(adev->dev, "UclkFmin (%ld) must be within [%u, %u]!\n",
1666 input[i + 1], minimum, maximum);
1667 return -EINVAL;
1668 }
1669
1670 od_table->OverDriveTable.UclkFmin = input[i + 1];
1671 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT;
1672 break;
1673
1674 case 1:
1675 smu_v13_0_7_get_od_setting_limits(smu,
1676 PP_OD_FEATURE_UCLK_FMAX,
1677 &minimum,
1678 &maximum);
1679 if (input[i + 1] < minimum ||
1680 input[i + 1] > maximum) {
1681 dev_info(adev->dev, "UclkFmax (%ld) must be within [%u, %u]!\n",
1682 input[i + 1], minimum, maximum);
1683 return -EINVAL;
1684 }
1685
1686 od_table->OverDriveTable.UclkFmax = input[i + 1];
1687 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT;
1688 break;
1689
1690 default:
1691 dev_info(adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
1692 dev_info(adev->dev, "Supported indices: [0:min,1:max]\n");
1693 return -EINVAL;
1694 }
1695 }
1696
1697 if (od_table->OverDriveTable.UclkFmin > od_table->OverDriveTable.UclkFmax) {
1698 dev_err(adev->dev,
1699 "Invalid setting: UclkFmin(%u) is bigger than UclkFmax(%u)\n",
1700 (uint32_t)od_table->OverDriveTable.UclkFmin,
1701 (uint32_t)od_table->OverDriveTable.UclkFmax);
1702 return -EINVAL;
1703 }
1704 break;
1705
1706 case PP_OD_EDIT_VDDGFX_OFFSET:
1707 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
1708 dev_warn(adev->dev, "Gfx offset setting not supported!\n");
1709 return -ENOTSUPP;
1710 }
1711
1712 smu_v13_0_7_get_od_setting_limits(smu,
1713 PP_OD_FEATURE_GFX_VF_CURVE,
1714 &minimum,
1715 &maximum);
1716 if (input[0] < minimum ||
1717 input[0] > maximum) {
1718 dev_info(adev->dev, "Voltage offset (%ld) must be within [%d, %d]!\n",
1719 input[0], minimum, maximum);
1720 return -EINVAL;
1721 }
1722
1723 for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++)
1724 od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i] = input[0];
1725 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT);
1726 break;
1727
1728 case PP_OD_EDIT_FAN_CURVE:
1729 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1730 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1731 return -ENOTSUPP;
1732 }
1733
1734 if (input[0] >= NUM_OD_FAN_MAX_POINTS - 1 ||
1735 input[0] < 0)
1736 return -EINVAL;
1737
1738 smu_v13_0_7_get_od_setting_limits(smu,
1739 PP_OD_FEATURE_FAN_CURVE_TEMP,
1740 &minimum,
1741 &maximum);
1742 if (input[1] < minimum ||
1743 input[1] > maximum) {
1744 dev_info(adev->dev, "Fan curve temp setting(%ld) must be within [%d, %d]!\n",
1745 input[1], minimum, maximum);
1746 return -EINVAL;
1747 }
1748
1749 smu_v13_0_7_get_od_setting_limits(smu,
1750 PP_OD_FEATURE_FAN_CURVE_PWM,
1751 &minimum,
1752 &maximum);
1753 if (input[2] < minimum ||
1754 input[2] > maximum) {
1755 dev_info(adev->dev, "Fan curve pwm setting(%ld) must be within [%d, %d]!\n",
1756 input[2], minimum, maximum);
1757 return -EINVAL;
1758 }
1759
1760 od_table->OverDriveTable.FanLinearTempPoints[input[0]] = input[1];
1761 od_table->OverDriveTable.FanLinearPwmPoints[input[0]] = input[2];
1762 od_table->OverDriveTable.FanMode = FAN_MODE_MANUAL_LINEAR;
1763 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1764 break;
1765
1766 case PP_OD_EDIT_ACOUSTIC_LIMIT:
1767 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1768 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1769 return -ENOTSUPP;
1770 }
1771
1772 smu_v13_0_7_get_od_setting_limits(smu,
1773 PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT,
1774 &minimum,
1775 &maximum);
1776 if (input[0] < minimum ||
1777 input[0] > maximum) {
1778 dev_info(adev->dev, "acoustic limit threshold setting(%ld) must be within [%d, %d]!\n",
1779 input[0], minimum, maximum);
1780 return -EINVAL;
1781 }
1782
1783 od_table->OverDriveTable.AcousticLimitRpmThreshold = input[0];
1784 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1785 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1786 break;
1787
1788 case PP_OD_EDIT_ACOUSTIC_TARGET:
1789 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1790 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1791 return -ENOTSUPP;
1792 }
1793
1794 smu_v13_0_7_get_od_setting_limits(smu,
1795 PP_OD_FEATURE_FAN_ACOUSTIC_TARGET,
1796 &minimum,
1797 &maximum);
1798 if (input[0] < minimum ||
1799 input[0] > maximum) {
1800 dev_info(adev->dev, "acoustic target threshold setting(%ld) must be within [%d, %d]!\n",
1801 input[0], minimum, maximum);
1802 return -EINVAL;
1803 }
1804
1805 od_table->OverDriveTable.AcousticTargetRpmThreshold = input[0];
1806 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1807 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1808 break;
1809
1810 case PP_OD_EDIT_FAN_TARGET_TEMPERATURE:
1811 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1812 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1813 return -ENOTSUPP;
1814 }
1815
1816 smu_v13_0_7_get_od_setting_limits(smu,
1817 PP_OD_FEATURE_FAN_TARGET_TEMPERATURE,
1818 &minimum,
1819 &maximum);
1820 if (input[0] < minimum ||
1821 input[0] > maximum) {
1822 dev_info(adev->dev, "fan target temperature setting(%ld) must be within [%d, %d]!\n",
1823 input[0], minimum, maximum);
1824 return -EINVAL;
1825 }
1826
1827 od_table->OverDriveTable.FanTargetTemperature = input[0];
1828 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1829 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1830 break;
1831
1832 case PP_OD_EDIT_FAN_MINIMUM_PWM:
1833 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1834 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1835 return -ENOTSUPP;
1836 }
1837
1838 smu_v13_0_7_get_od_setting_limits(smu,
1839 PP_OD_FEATURE_FAN_MINIMUM_PWM,
1840 &minimum,
1841 &maximum);
1842 if (input[0] < minimum ||
1843 input[0] > maximum) {
1844 dev_info(adev->dev, "fan minimum pwm setting(%ld) must be within [%d, %d]!\n",
1845 input[0], minimum, maximum);
1846 return -EINVAL;
1847 }
1848
1849 od_table->OverDriveTable.FanMinimumPwm = input[0];
1850 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1851 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1852 break;
1853
1854 case PP_OD_EDIT_FAN_ZERO_RPM_ENABLE:
1855 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_ZERO_FAN_BIT)) {
1856 dev_warn(adev->dev, "Zero RPM setting not supported!\n");
1857 return -ENOTSUPP;
1858 }
1859
1860 smu_v13_0_7_get_od_setting_limits(smu,
1861 PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE,
1862 &minimum,
1863 &maximum);
1864 if (input[0] < minimum ||
1865 input[0] > maximum) {
1866 dev_info(adev->dev, "zero RPM enable setting(%ld) must be within [%d, %d]!\n",
1867 input[0], minimum, maximum);
1868 return -EINVAL;
1869 }
1870
1871 od_table->OverDriveTable.FanZeroRpmEnable = input[0];
1872 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1873 break;
1874
1875 case PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP:
1876 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_ZERO_FAN_BIT)) {
1877 dev_warn(adev->dev, "Zero RPM setting not supported!\n");
1878 return -ENOTSUPP;
1879 }
1880
1881 smu_v13_0_7_get_od_setting_limits(smu,
1882 PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP,
1883 &minimum,
1884 &maximum);
1885 if (input[0] < minimum ||
1886 input[0] > maximum) {
1887 dev_info(adev->dev, "zero RPM stop temperature setting(%ld) must be within [%d, %d]!\n",
1888 input[0], minimum, maximum);
1889 return -EINVAL;
1890 }
1891
1892 od_table->OverDriveTable.FanZeroRpmStopTemp = input[0];
1893 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1894 break;
1895
1896 case PP_OD_RESTORE_DEFAULT_TABLE:
1897 if (size == 1) {
1898 ret = smu_v13_0_7_od_restore_table_single(smu, input[0]);
1899 if (ret)
1900 return ret;
1901 } else {
1902 feature_ctrlmask = od_table->OverDriveTable.FeatureCtrlMask;
1903 memcpy(od_table,
1904 table_context->boot_overdrive_table,
1905 sizeof(OverDriveTableExternal_t));
1906 od_table->OverDriveTable.FeatureCtrlMask = feature_ctrlmask;
1907 }
1908 fallthrough;
1909
1910 case PP_OD_COMMIT_DPM_TABLE:
1911 /*
1912 * The member below instructs PMFW the settings focused in
1913 * this single operation.
1914 * `uint32_t FeatureCtrlMask;`
1915 * It does not contain actual informations about user's custom
1916 * settings. Thus we do not cache it.
1917 */
1918 offset_of_voltageoffset = offsetof(OverDriveTable_t, VoltageOffsetPerZoneBoundary);
1919 if (memcmp((u8 *)od_table + offset_of_voltageoffset,
1920 table_context->user_overdrive_table + offset_of_voltageoffset,
1921 sizeof(OverDriveTableExternal_t) - offset_of_voltageoffset)) {
1922 smu_v13_0_7_dump_od_table(smu, od_table);
1923
1924 ret = smu_v13_0_7_upload_overdrive_table(smu, od_table);
1925 if (ret) {
1926 dev_err(adev->dev, "Failed to upload overdrive table!\n");
1927 return ret;
1928 }
1929
1930 od_table->OverDriveTable.FeatureCtrlMask = 0;
1931 memcpy(table_context->user_overdrive_table + offset_of_voltageoffset,
1932 (u8 *)od_table + offset_of_voltageoffset,
1933 sizeof(OverDriveTableExternal_t) - offset_of_voltageoffset);
1934
1935 if (!memcmp(table_context->user_overdrive_table,
1936 table_context->boot_overdrive_table,
1937 sizeof(OverDriveTableExternal_t)))
1938 smu->user_dpm_profile.user_od = false;
1939 else
1940 smu->user_dpm_profile.user_od = true;
1941 }
1942 break;
1943
1944 default:
1945 return -ENOSYS;
1946 }
1947
1948 return ret;
1949 }
1950
smu_v13_0_7_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1951 static int smu_v13_0_7_force_clk_levels(struct smu_context *smu,
1952 enum smu_clk_type clk_type,
1953 uint32_t mask)
1954 {
1955 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1956 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1957 struct smu_dpm_table *single_dpm_table;
1958 uint32_t soft_min_level, soft_max_level;
1959 uint32_t min_freq, max_freq;
1960 int ret = 0;
1961
1962 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1963 soft_max_level = mask ? (fls(mask) - 1) : 0;
1964
1965 switch (clk_type) {
1966 case SMU_GFXCLK:
1967 case SMU_SCLK:
1968 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1969 break;
1970 case SMU_MCLK:
1971 case SMU_UCLK:
1972 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1973 break;
1974 case SMU_SOCCLK:
1975 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1976 break;
1977 case SMU_FCLK:
1978 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1979 break;
1980 case SMU_VCLK:
1981 case SMU_VCLK1:
1982 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1983 break;
1984 case SMU_DCLK:
1985 case SMU_DCLK1:
1986 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1987 break;
1988 default:
1989 break;
1990 }
1991
1992 switch (clk_type) {
1993 case SMU_GFXCLK:
1994 case SMU_SCLK:
1995 case SMU_MCLK:
1996 case SMU_UCLK:
1997 case SMU_SOCCLK:
1998 case SMU_FCLK:
1999 case SMU_VCLK:
2000 case SMU_VCLK1:
2001 case SMU_DCLK:
2002 case SMU_DCLK1:
2003 if (single_dpm_table->flags & SMU_DPM_TABLE_FINE_GRAINED) {
2004 /* There is only 2 levels for fine grained DPM */
2005 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
2006 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
2007 } else {
2008 if ((soft_max_level >= single_dpm_table->count) ||
2009 (soft_min_level >= single_dpm_table->count))
2010 return -EINVAL;
2011 }
2012
2013 min_freq = single_dpm_table->dpm_levels[soft_min_level].value;
2014 max_freq = single_dpm_table->dpm_levels[soft_max_level].value;
2015
2016 ret = smu_v13_0_set_soft_freq_limited_range(smu,
2017 clk_type,
2018 min_freq,
2019 max_freq,
2020 false);
2021 break;
2022 case SMU_DCEFCLK:
2023 case SMU_PCIE:
2024 default:
2025 break;
2026 }
2027
2028 return ret;
2029 }
2030
2031 static const struct smu_temperature_range smu13_thermal_policy[] = {
2032 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
2033 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
2034 };
2035
smu_v13_0_7_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)2036 static int smu_v13_0_7_get_thermal_temperature_range(struct smu_context *smu,
2037 struct smu_temperature_range *range)
2038 {
2039 struct smu_table_context *table_context = &smu->smu_table;
2040 struct smu_13_0_7_powerplay_table *powerplay_table =
2041 table_context->power_play_table;
2042 PPTable_t *pptable = smu->smu_table.driver_pptable;
2043
2044 if (!range)
2045 return -EINVAL;
2046
2047 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range));
2048
2049 range->max = pptable->SkuTable.TemperatureLimit[TEMP_EDGE] *
2050 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2051 range->edge_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
2052 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2053 range->hotspot_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] *
2054 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2055 range->hotspot_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) *
2056 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2057 range->mem_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_MEM] *
2058 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2059 range->mem_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
2060 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2061 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
2062 range->software_shutdown_temp_offset = pptable->SkuTable.FanAbnormalTempLimitOffset;
2063
2064 return 0;
2065 }
2066
smu_v13_0_7_get_gpu_metrics(struct smu_context * smu,void ** table)2067 static ssize_t smu_v13_0_7_get_gpu_metrics(struct smu_context *smu,
2068 void **table)
2069 {
2070 struct gpu_metrics_v1_3 *gpu_metrics =
2071 (struct gpu_metrics_v1_3 *)smu_driver_table_ptr(
2072 smu, SMU_DRIVER_TABLE_GPU_METRICS);
2073 SmuMetricsExternal_t metrics_ext;
2074 SmuMetrics_t *metrics = &metrics_ext.SmuMetrics;
2075 int ret = 0;
2076
2077 ret = smu_cmn_get_metrics_table(smu,
2078 &metrics_ext,
2079 true);
2080 if (ret)
2081 return ret;
2082
2083 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2084
2085 gpu_metrics->temperature_edge = metrics->AvgTemperature[TEMP_EDGE];
2086 gpu_metrics->temperature_hotspot = metrics->AvgTemperature[TEMP_HOTSPOT];
2087 gpu_metrics->temperature_mem = metrics->AvgTemperature[TEMP_MEM];
2088 gpu_metrics->temperature_vrgfx = metrics->AvgTemperature[TEMP_VR_GFX];
2089 gpu_metrics->temperature_vrsoc = metrics->AvgTemperature[TEMP_VR_SOC];
2090 gpu_metrics->temperature_vrmem = max(metrics->AvgTemperature[TEMP_VR_MEM0],
2091 metrics->AvgTemperature[TEMP_VR_MEM1]);
2092
2093 gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity;
2094 gpu_metrics->average_umc_activity = smu_safe_u16_nn(metrics->AverageUclkActivity);
2095 gpu_metrics->average_mm_activity = max(metrics->Vcn0ActivityPercentage,
2096 metrics->Vcn1ActivityPercentage);
2097
2098 gpu_metrics->average_socket_power = metrics->AverageSocketPower;
2099 gpu_metrics->energy_accumulator = smu->smc_fw_version <= 0x00521400 ?
2100 metrics->EnergyAccumulator : UINT_MAX;
2101
2102 if (metrics->AverageGfxActivity <= SMU_13_0_7_BUSY_THRESHOLD)
2103 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs;
2104 else
2105 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs;
2106
2107 if (smu_safe_u16_nn(metrics->AverageUclkActivity) <= SMU_13_0_7_BUSY_THRESHOLD)
2108 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs;
2109 else
2110 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs;
2111
2112 gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency;
2113 gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency;
2114 gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency;
2115 gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency;
2116
2117 gpu_metrics->current_gfxclk = metrics->CurrClock[PPCLK_GFXCLK];
2118 gpu_metrics->current_socclk = metrics->CurrClock[PPCLK_SOCCLK];
2119 gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK];
2120 gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0];
2121 gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0];
2122 gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1];
2123 gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1];
2124
2125 gpu_metrics->throttle_status =
2126 smu_v13_0_7_get_throttler_status(metrics);
2127 gpu_metrics->indep_throttle_status =
2128 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
2129 smu_v13_0_7_throttler_map);
2130
2131 gpu_metrics->current_fan_speed = metrics->AvgFanRpm;
2132
2133 gpu_metrics->pcie_link_width = metrics->PcieWidth;
2134 if ((metrics->PcieRate - 1) > LINK_SPEED_MAX)
2135 gpu_metrics->pcie_link_speed = pcie_gen_to_speed(1);
2136 else
2137 gpu_metrics->pcie_link_speed = pcie_gen_to_speed(metrics->PcieRate);
2138
2139 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2140
2141 gpu_metrics->voltage_gfx = metrics->AvgVoltage[SVI_PLANE_GFX];
2142 gpu_metrics->voltage_soc = metrics->AvgVoltage[SVI_PLANE_SOC];
2143 gpu_metrics->voltage_mem = metrics->AvgVoltage[SVI_PLANE_VMEMP];
2144
2145 *table = (void *)gpu_metrics;
2146
2147 smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS);
2148
2149 return sizeof(struct gpu_metrics_v1_3);
2150 }
2151
smu_v13_0_7_set_supported_od_feature_mask(struct smu_context * smu)2152 static void smu_v13_0_7_set_supported_od_feature_mask(struct smu_context *smu)
2153 {
2154 struct amdgpu_device *adev = smu->adev;
2155
2156 if (smu_v13_0_7_is_od_feature_supported(smu,
2157 PP_OD_FEATURE_FAN_CURVE_BIT))
2158 adev->pm.od_feature_mask |= OD_OPS_SUPPORT_FAN_CURVE_RETRIEVE |
2159 OD_OPS_SUPPORT_FAN_CURVE_SET |
2160 OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_RETRIEVE |
2161 OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_SET |
2162 OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_RETRIEVE |
2163 OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_SET |
2164 OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE |
2165 OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET |
2166 OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE |
2167 OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET |
2168 OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_RETRIEVE |
2169 OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_SET |
2170 OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_RETRIEVE |
2171 OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_SET;
2172 }
2173
smu_v13_0_7_set_default_od_settings(struct smu_context * smu)2174 static int smu_v13_0_7_set_default_od_settings(struct smu_context *smu)
2175 {
2176 OverDriveTableExternal_t *od_table =
2177 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
2178 OverDriveTableExternal_t *boot_od_table =
2179 (OverDriveTableExternal_t *)smu->smu_table.boot_overdrive_table;
2180 OverDriveTableExternal_t *user_od_table =
2181 (OverDriveTableExternal_t *)smu->smu_table.user_overdrive_table;
2182 OverDriveTableExternal_t user_od_table_bak;
2183 int ret = 0;
2184 int i;
2185
2186 ret = smu_v13_0_7_get_overdrive_table(smu, boot_od_table);
2187 if (ret)
2188 return ret;
2189
2190 smu_v13_0_7_dump_od_table(smu, boot_od_table);
2191
2192 memcpy(od_table,
2193 boot_od_table,
2194 sizeof(OverDriveTableExternal_t));
2195
2196 /*
2197 * For S3/S4/Runpm resume, we need to setup those overdrive tables again,
2198 * but we have to preserve user defined values in "user_od_table".
2199 */
2200 if (!smu->adev->in_suspend) {
2201 memcpy(user_od_table,
2202 boot_od_table,
2203 sizeof(OverDriveTableExternal_t));
2204 smu->user_dpm_profile.user_od = false;
2205 } else if (smu->user_dpm_profile.user_od) {
2206 memcpy(&user_od_table_bak,
2207 user_od_table,
2208 sizeof(OverDriveTableExternal_t));
2209 memcpy(user_od_table,
2210 boot_od_table,
2211 sizeof(OverDriveTableExternal_t));
2212 user_od_table->OverDriveTable.GfxclkFmin =
2213 user_od_table_bak.OverDriveTable.GfxclkFmin;
2214 user_od_table->OverDriveTable.GfxclkFmax =
2215 user_od_table_bak.OverDriveTable.GfxclkFmax;
2216 user_od_table->OverDriveTable.UclkFmin =
2217 user_od_table_bak.OverDriveTable.UclkFmin;
2218 user_od_table->OverDriveTable.UclkFmax =
2219 user_od_table_bak.OverDriveTable.UclkFmax;
2220 for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++)
2221 user_od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i] =
2222 user_od_table_bak.OverDriveTable.VoltageOffsetPerZoneBoundary[i];
2223 for (i = 0; i < NUM_OD_FAN_MAX_POINTS - 1; i++) {
2224 user_od_table->OverDriveTable.FanLinearTempPoints[i] =
2225 user_od_table_bak.OverDriveTable.FanLinearTempPoints[i];
2226 user_od_table->OverDriveTable.FanLinearPwmPoints[i] =
2227 user_od_table_bak.OverDriveTable.FanLinearPwmPoints[i];
2228 }
2229 user_od_table->OverDriveTable.AcousticLimitRpmThreshold =
2230 user_od_table_bak.OverDriveTable.AcousticLimitRpmThreshold;
2231 user_od_table->OverDriveTable.AcousticTargetRpmThreshold =
2232 user_od_table_bak.OverDriveTable.AcousticTargetRpmThreshold;
2233 user_od_table->OverDriveTable.FanTargetTemperature =
2234 user_od_table_bak.OverDriveTable.FanTargetTemperature;
2235 user_od_table->OverDriveTable.FanMinimumPwm =
2236 user_od_table_bak.OverDriveTable.FanMinimumPwm;
2237 user_od_table->OverDriveTable.FanZeroRpmEnable =
2238 user_od_table_bak.OverDriveTable.FanZeroRpmEnable;
2239 user_od_table->OverDriveTable.FanZeroRpmStopTemp =
2240 user_od_table_bak.OverDriveTable.FanZeroRpmStopTemp;
2241 }
2242
2243 smu_v13_0_7_set_supported_od_feature_mask(smu);
2244
2245 return 0;
2246 }
2247
smu_v13_0_7_restore_user_od_settings(struct smu_context * smu)2248 static int smu_v13_0_7_restore_user_od_settings(struct smu_context *smu)
2249 {
2250 struct smu_table_context *table_context = &smu->smu_table;
2251 OverDriveTableExternal_t *od_table = table_context->overdrive_table;
2252 OverDriveTableExternal_t *user_od_table = table_context->user_overdrive_table;
2253 int res;
2254
2255 user_od_table->OverDriveTable.FeatureCtrlMask = BIT(PP_OD_FEATURE_GFXCLK_BIT) |
2256 BIT(PP_OD_FEATURE_UCLK_BIT) |
2257 BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT) |
2258 BIT(PP_OD_FEATURE_FAN_CURVE_BIT) |
2259 BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
2260 res = smu_v13_0_7_upload_overdrive_table(smu, user_od_table);
2261 user_od_table->OverDriveTable.FeatureCtrlMask = 0;
2262 if (res == 0)
2263 memcpy(od_table, user_od_table, sizeof(OverDriveTableExternal_t));
2264
2265 return res;
2266 }
2267
smu_v13_0_7_populate_umd_state_clk(struct smu_context * smu)2268 static int smu_v13_0_7_populate_umd_state_clk(struct smu_context *smu)
2269 {
2270 struct smu_13_0_dpm_context *dpm_context =
2271 smu->smu_dpm.dpm_context;
2272 struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table;
2273 struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table;
2274 struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table;
2275 struct smu_dpm_table *vclk_table = &dpm_context->dpm_tables.vclk_table;
2276 struct smu_dpm_table *dclk_table = &dpm_context->dpm_tables.dclk_table;
2277 struct smu_dpm_table *fclk_table = &dpm_context->dpm_tables.fclk_table;
2278 struct smu_umd_pstate_table *pstate_table =
2279 &smu->pstate_table;
2280 struct smu_table_context *table_context = &smu->smu_table;
2281 PPTable_t *pptable = table_context->driver_pptable;
2282 DriverReportedClocks_t driver_clocks =
2283 pptable->SkuTable.DriverReportedClocks;
2284
2285 pstate_table->gfxclk_pstate.min = SMU_DPM_TABLE_MIN(gfx_table);
2286 if (driver_clocks.GameClockAc &&
2287 (driver_clocks.GameClockAc < SMU_DPM_TABLE_MAX(gfx_table)))
2288 pstate_table->gfxclk_pstate.peak = driver_clocks.GameClockAc;
2289 else
2290 pstate_table->gfxclk_pstate.peak = SMU_DPM_TABLE_MAX(gfx_table);
2291
2292 pstate_table->uclk_pstate.min = SMU_DPM_TABLE_MIN(mem_table);
2293 pstate_table->uclk_pstate.peak = SMU_DPM_TABLE_MAX(mem_table);
2294
2295 pstate_table->socclk_pstate.min = SMU_DPM_TABLE_MIN(soc_table);
2296 pstate_table->socclk_pstate.peak = SMU_DPM_TABLE_MAX(soc_table);
2297
2298 pstate_table->vclk_pstate.min = SMU_DPM_TABLE_MIN(vclk_table);
2299 pstate_table->vclk_pstate.peak = SMU_DPM_TABLE_MAX(vclk_table);
2300
2301 pstate_table->dclk_pstate.min = SMU_DPM_TABLE_MIN(dclk_table);
2302 pstate_table->dclk_pstate.peak = SMU_DPM_TABLE_MAX(dclk_table);
2303
2304 pstate_table->fclk_pstate.min = SMU_DPM_TABLE_MIN(fclk_table);
2305 pstate_table->fclk_pstate.peak = SMU_DPM_TABLE_MAX(fclk_table);
2306
2307 if (driver_clocks.BaseClockAc &&
2308 driver_clocks.BaseClockAc < SMU_DPM_TABLE_MAX(gfx_table))
2309 pstate_table->gfxclk_pstate.standard = driver_clocks.BaseClockAc;
2310 else
2311 pstate_table->gfxclk_pstate.standard =
2312 SMU_DPM_TABLE_MAX(gfx_table);
2313 pstate_table->uclk_pstate.standard = SMU_DPM_TABLE_MAX(mem_table);
2314 pstate_table->socclk_pstate.standard = SMU_DPM_TABLE_MIN(soc_table);
2315 pstate_table->vclk_pstate.standard = SMU_DPM_TABLE_MIN(vclk_table);
2316 pstate_table->dclk_pstate.standard = SMU_DPM_TABLE_MIN(dclk_table);
2317 pstate_table->fclk_pstate.standard = SMU_DPM_TABLE_MIN(fclk_table);
2318
2319 return 0;
2320 }
2321
smu_v13_0_7_get_fan_speed_pwm(struct smu_context * smu,uint32_t * speed)2322 static int smu_v13_0_7_get_fan_speed_pwm(struct smu_context *smu,
2323 uint32_t *speed)
2324 {
2325 int ret;
2326
2327 if (!speed)
2328 return -EINVAL;
2329
2330 ret = smu_v13_0_7_get_smu_metrics_data(smu,
2331 METRICS_CURR_FANPWM,
2332 speed);
2333 if (ret) {
2334 dev_err(smu->adev->dev, "Failed to get fan speed(PWM)!");
2335 return ret;
2336 }
2337
2338 /* Convert the PMFW output which is in percent to pwm(255) based */
2339 *speed = min(*speed * 255 / 100, (uint32_t)255);
2340
2341 return 0;
2342 }
2343
smu_v13_0_7_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)2344 static int smu_v13_0_7_get_fan_speed_rpm(struct smu_context *smu,
2345 uint32_t *speed)
2346 {
2347 if (!speed)
2348 return -EINVAL;
2349
2350 return smu_v13_0_7_get_smu_metrics_data(smu,
2351 METRICS_CURR_FANSPEED,
2352 speed);
2353 }
2354
smu_v13_0_7_enable_mgpu_fan_boost(struct smu_context * smu)2355 static int smu_v13_0_7_enable_mgpu_fan_boost(struct smu_context *smu)
2356 {
2357 struct smu_table_context *table_context = &smu->smu_table;
2358 PPTable_t *pptable = table_context->driver_pptable;
2359 SkuTable_t *skutable = &pptable->SkuTable;
2360
2361 /*
2362 * Skip the MGpuFanBoost setting for those ASICs
2363 * which do not support it
2364 */
2365 if (skutable->MGpuAcousticLimitRpmThreshold == 0)
2366 return 0;
2367
2368 return smu_cmn_send_smc_msg_with_param(smu,
2369 SMU_MSG_SetMGpuFanBoostLimitRpm,
2370 0,
2371 NULL);
2372 }
2373
smu_v13_0_7_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit,uint32_t * min_power_limit)2374 static int smu_v13_0_7_get_power_limit(struct smu_context *smu,
2375 uint32_t *current_power_limit,
2376 uint32_t *default_power_limit,
2377 uint32_t *max_power_limit,
2378 uint32_t *min_power_limit)
2379 {
2380 struct smu_table_context *table_context = &smu->smu_table;
2381 struct smu_13_0_7_powerplay_table *powerplay_table =
2382 (struct smu_13_0_7_powerplay_table *)table_context->power_play_table;
2383 PPTable_t *pptable = table_context->driver_pptable;
2384 SkuTable_t *skutable = &pptable->SkuTable;
2385 uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0;
2386 uint32_t msg_limit = skutable->MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];
2387
2388 if (smu_v13_0_get_current_power_limit(smu, &power_limit))
2389 power_limit = smu->adev->pm.ac_power ?
2390 skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] :
2391 skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0];
2392
2393 if (current_power_limit)
2394 *current_power_limit = power_limit;
2395 if (default_power_limit)
2396 *default_power_limit = power_limit;
2397
2398 if (powerplay_table) {
2399 if (smu->od_enabled &&
2400 (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT))) {
2401 od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_13_0_7_ODSETTING_POWERPERCENTAGE]);
2402 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_13_0_7_ODSETTING_POWERPERCENTAGE]);
2403 } else if (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) {
2404 od_percent_upper = 0;
2405 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_13_0_7_ODSETTING_POWERPERCENTAGE]);
2406 }
2407 }
2408
2409 dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",
2410 od_percent_upper, od_percent_lower, power_limit);
2411
2412 if (max_power_limit) {
2413 *max_power_limit = msg_limit * (100 + od_percent_upper);
2414 *max_power_limit /= 100;
2415 }
2416
2417 if (min_power_limit) {
2418 *min_power_limit = power_limit * (100 - od_percent_lower);
2419 *min_power_limit /= 100;
2420 }
2421
2422 return 0;
2423 }
2424
smu_v13_0_7_get_power_profile_mode(struct smu_context * smu,char * buf)2425 static int smu_v13_0_7_get_power_profile_mode(struct smu_context *smu, char *buf)
2426 {
2427 DpmActivityMonitorCoeffIntExternal_t *activity_monitor_external;
2428 uint32_t i, j, size = 0;
2429 int16_t workload_type = 0;
2430 int result = 0;
2431
2432 if (!buf)
2433 return -EINVAL;
2434
2435 activity_monitor_external = kzalloc_objs(*activity_monitor_external,
2436 PP_SMC_POWER_PROFILE_COUNT);
2437 if (!activity_monitor_external)
2438 return -ENOMEM;
2439
2440 size += sysfs_emit_at(buf, size, " ");
2441 for (i = 0; i <= PP_SMC_POWER_PROFILE_WINDOW3D; i++)
2442 size += sysfs_emit_at(buf, size, "%d %-14s%s", i, amdgpu_pp_profile_name[i],
2443 (i == smu->power_profile_mode) ? "* " : " ");
2444
2445 size += sysfs_emit_at(buf, size, "\n");
2446
2447 for (i = 0; i <= PP_SMC_POWER_PROFILE_WINDOW3D; i++) {
2448 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
2449 workload_type = smu_cmn_to_asic_specific_index(smu,
2450 CMN2ASIC_MAPPING_WORKLOAD,
2451 i);
2452 if (workload_type == -ENOTSUPP)
2453 continue;
2454 else if (workload_type < 0) {
2455 result = -EINVAL;
2456 goto out;
2457 }
2458
2459 result = smu_cmn_update_table(smu,
2460 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
2461 (void *)(&activity_monitor_external[i]), false);
2462 if (result) {
2463 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
2464 goto out;
2465 }
2466 }
2467
2468 #define PRINT_DPM_MONITOR(field) \
2469 do { \
2470 size += sysfs_emit_at(buf, size, "%-30s", #field); \
2471 for (j = 0; j <= PP_SMC_POWER_PROFILE_WINDOW3D; j++) \
2472 size += sysfs_emit_at(buf, size, "%-18d", activity_monitor_external[j].DpmActivityMonitorCoeffInt.field); \
2473 size += sysfs_emit_at(buf, size, "\n"); \
2474 } while (0)
2475
2476 PRINT_DPM_MONITOR(Gfx_ActiveHystLimit);
2477 PRINT_DPM_MONITOR(Gfx_IdleHystLimit);
2478 PRINT_DPM_MONITOR(Gfx_FPS);
2479 PRINT_DPM_MONITOR(Gfx_MinActiveFreqType);
2480 PRINT_DPM_MONITOR(Gfx_BoosterFreqType);
2481 PRINT_DPM_MONITOR(Gfx_MinActiveFreq);
2482 PRINT_DPM_MONITOR(Gfx_BoosterFreq);
2483 PRINT_DPM_MONITOR(Fclk_ActiveHystLimit);
2484 PRINT_DPM_MONITOR(Fclk_IdleHystLimit);
2485 PRINT_DPM_MONITOR(Fclk_FPS);
2486 PRINT_DPM_MONITOR(Fclk_MinActiveFreqType);
2487 PRINT_DPM_MONITOR(Fclk_BoosterFreqType);
2488 PRINT_DPM_MONITOR(Fclk_MinActiveFreq);
2489 PRINT_DPM_MONITOR(Fclk_BoosterFreq);
2490 #undef PRINT_DPM_MONITOR
2491
2492 result = size;
2493 out:
2494 kfree(activity_monitor_external);
2495 return result;
2496 }
2497
2498 #define SMU_13_0_7_CUSTOM_PARAMS_COUNT 8
2499 #define SMU_13_0_7_CUSTOM_PARAMS_CLOCK_COUNT 2
2500 #define SMU_13_0_7_CUSTOM_PARAMS_SIZE (SMU_13_0_7_CUSTOM_PARAMS_CLOCK_COUNT * SMU_13_0_7_CUSTOM_PARAMS_COUNT * sizeof(long))
2501
smu_v13_0_7_set_power_profile_mode_coeff(struct smu_context * smu,long * input)2502 static int smu_v13_0_7_set_power_profile_mode_coeff(struct smu_context *smu,
2503 long *input)
2504 {
2505
2506 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
2507 DpmActivityMonitorCoeffInt_t *activity_monitor =
2508 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
2509 int ret, idx;
2510
2511 ret = smu_cmn_update_table(smu,
2512 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
2513 (void *)(&activity_monitor_external), false);
2514 if (ret) {
2515 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
2516 return ret;
2517 }
2518
2519 idx = 0 * SMU_13_0_7_CUSTOM_PARAMS_COUNT;
2520 if (input[idx]) {
2521 /* Gfxclk */
2522 activity_monitor->Gfx_ActiveHystLimit = input[idx + 1];
2523 activity_monitor->Gfx_IdleHystLimit = input[idx + 2];
2524 activity_monitor->Gfx_FPS = input[idx + 3];
2525 activity_monitor->Gfx_MinActiveFreqType = input[idx + 4];
2526 activity_monitor->Gfx_BoosterFreqType = input[idx + 5];
2527 activity_monitor->Gfx_MinActiveFreq = input[idx + 6];
2528 activity_monitor->Gfx_BoosterFreq = input[idx + 7];
2529 }
2530 idx = 1 * SMU_13_0_7_CUSTOM_PARAMS_COUNT;
2531 if (input[idx]) {
2532 /* Fclk */
2533 activity_monitor->Fclk_ActiveHystLimit = input[idx + 1];
2534 activity_monitor->Fclk_IdleHystLimit = input[idx + 2];
2535 activity_monitor->Fclk_FPS = input[idx + 3];
2536 activity_monitor->Fclk_MinActiveFreqType = input[idx + 4];
2537 activity_monitor->Fclk_BoosterFreqType = input[idx + 5];
2538 activity_monitor->Fclk_MinActiveFreq = input[idx + 6];
2539 activity_monitor->Fclk_BoosterFreq = input[idx + 7];
2540 }
2541
2542 ret = smu_cmn_update_table(smu,
2543 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
2544 (void *)(&activity_monitor_external), true);
2545 if (ret) {
2546 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
2547 return ret;
2548 }
2549
2550 return ret;
2551 }
2552
smu_v13_0_7_set_power_profile_mode(struct smu_context * smu,u32 workload_mask,long * custom_params,u32 custom_params_max_idx)2553 static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu,
2554 u32 workload_mask,
2555 long *custom_params,
2556 u32 custom_params_max_idx)
2557 {
2558 u32 backend_workload_mask = 0;
2559 int ret, idx = -1, i;
2560
2561 smu_cmn_get_backend_workload_mask(smu, workload_mask,
2562 &backend_workload_mask);
2563
2564 if (workload_mask & (1 << PP_SMC_POWER_PROFILE_CUSTOM)) {
2565 if (!smu->custom_profile_params) {
2566 smu->custom_profile_params =
2567 kzalloc(SMU_13_0_7_CUSTOM_PARAMS_SIZE, GFP_KERNEL);
2568 if (!smu->custom_profile_params)
2569 return -ENOMEM;
2570 }
2571 if (custom_params && custom_params_max_idx) {
2572 if (custom_params_max_idx != SMU_13_0_7_CUSTOM_PARAMS_COUNT)
2573 return -EINVAL;
2574 if (custom_params[0] >= SMU_13_0_7_CUSTOM_PARAMS_CLOCK_COUNT)
2575 return -EINVAL;
2576 idx = custom_params[0] * SMU_13_0_7_CUSTOM_PARAMS_COUNT;
2577 smu->custom_profile_params[idx] = 1;
2578 for (i = 1; i < custom_params_max_idx; i++)
2579 smu->custom_profile_params[idx + i] = custom_params[i];
2580 }
2581 ret = smu_v13_0_7_set_power_profile_mode_coeff(smu,
2582 smu->custom_profile_params);
2583 if (ret) {
2584 if (idx != -1)
2585 smu->custom_profile_params[idx] = 0;
2586 return ret;
2587 }
2588 } else if (smu->custom_profile_params) {
2589 memset(smu->custom_profile_params, 0, SMU_13_0_7_CUSTOM_PARAMS_SIZE);
2590 }
2591
2592 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
2593 backend_workload_mask, NULL);
2594
2595 if (ret) {
2596 dev_err(smu->adev->dev, "Failed to set workload mask 0x%08x\n",
2597 workload_mask);
2598 if (idx != -1)
2599 smu->custom_profile_params[idx] = 0;
2600 return ret;
2601 }
2602
2603 return ret;
2604 }
2605
smu_v13_0_7_set_mp1_state(struct smu_context * smu,enum pp_mp1_state mp1_state)2606 static int smu_v13_0_7_set_mp1_state(struct smu_context *smu,
2607 enum pp_mp1_state mp1_state)
2608 {
2609 int ret;
2610
2611 switch (mp1_state) {
2612 case PP_MP1_STATE_UNLOAD:
2613 ret = smu_cmn_set_mp1_state(smu, mp1_state);
2614 break;
2615 default:
2616 /* Ignore others */
2617 ret = 0;
2618 }
2619
2620 return ret;
2621 }
2622
smu_v13_0_7_is_mode1_reset_supported(struct smu_context * smu)2623 static bool smu_v13_0_7_is_mode1_reset_supported(struct smu_context *smu)
2624 {
2625 struct amdgpu_device *adev = smu->adev;
2626
2627 /* SRIOV does not support SMU mode1 reset */
2628 if (amdgpu_sriov_vf(adev))
2629 return false;
2630
2631 return true;
2632 }
2633
smu_v13_0_7_set_df_cstate(struct smu_context * smu,enum pp_df_cstate state)2634 static int smu_v13_0_7_set_df_cstate(struct smu_context *smu,
2635 enum pp_df_cstate state)
2636 {
2637 return smu_cmn_send_smc_msg_with_param(smu,
2638 SMU_MSG_DFCstateControl,
2639 state,
2640 NULL);
2641 }
2642
smu_v13_0_7_wbrf_support_check(struct smu_context * smu)2643 static bool smu_v13_0_7_wbrf_support_check(struct smu_context *smu)
2644 {
2645 return smu->smc_fw_version > 0x00524600;
2646 }
2647
smu_v13_0_7_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)2648 static int smu_v13_0_7_set_power_limit(struct smu_context *smu,
2649 enum smu_ppt_limit_type limit_type,
2650 uint32_t limit)
2651 {
2652 PPTable_t *pptable = smu->smu_table.driver_pptable;
2653 SkuTable_t *skutable = &pptable->SkuTable;
2654 uint32_t msg_limit = skutable->MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];
2655 struct smu_table_context *table_context = &smu->smu_table;
2656 OverDriveTableExternal_t *od_table =
2657 (OverDriveTableExternal_t *)table_context->overdrive_table;
2658 int ret = 0;
2659
2660 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
2661 return -EINVAL;
2662
2663 if (limit <= msg_limit) {
2664 if (smu->current_power_limit > msg_limit) {
2665 od_table->OverDriveTable.Ppt = 0;
2666 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_PPT_BIT;
2667
2668 ret = smu_v13_0_7_upload_overdrive_table(smu, od_table);
2669 if (ret) {
2670 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
2671 return ret;
2672 }
2673 }
2674 return smu_v13_0_set_power_limit(smu, limit_type, limit);
2675 } else if (smu->od_enabled) {
2676 ret = smu_v13_0_set_power_limit(smu, limit_type, msg_limit);
2677 if (ret)
2678 return ret;
2679
2680 od_table->OverDriveTable.Ppt = (limit * 100) / msg_limit - 100;
2681 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_PPT_BIT;
2682
2683 ret = smu_v13_0_7_upload_overdrive_table(smu, od_table);
2684 if (ret) {
2685 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
2686 return ret;
2687 }
2688
2689 smu->current_power_limit = limit;
2690 } else {
2691 return -EINVAL;
2692 }
2693
2694 return 0;
2695 }
2696
smu_v13_0_7_update_pcie_parameters(struct smu_context * smu,uint8_t pcie_gen_cap,uint8_t pcie_width_cap)2697 static int smu_v13_0_7_update_pcie_parameters(struct smu_context *smu,
2698 uint8_t pcie_gen_cap,
2699 uint8_t pcie_width_cap)
2700 {
2701 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2702 struct smu_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table;
2703 int num_of_levels;
2704 int link_level;
2705 uint32_t smu_pcie_arg;
2706 struct smu_table_context *table_context = &smu->smu_table;
2707 PPTable_t *pptable = table_context->driver_pptable;
2708 SkuTable_t *skutable = &pptable->SkuTable;
2709 int ret = 0;
2710 int i;
2711
2712 pcie_table->lclk_levels = 0;
2713 for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) {
2714 if (!skutable->PcieGenSpeed[link_level] &&
2715 !skutable->PcieLaneCount[link_level] &&
2716 !skutable->LclkFreq[link_level])
2717 continue;
2718
2719 pcie_table->pcie_gen[pcie_table->lclk_levels] =
2720 skutable->PcieGenSpeed[link_level];
2721 pcie_table->pcie_lane[pcie_table->lclk_levels] =
2722 skutable->PcieLaneCount[link_level];
2723 pcie_table->lclk_freq[pcie_table->lclk_levels] =
2724 skutable->LclkFreq[link_level];
2725 pcie_table->lclk_levels++;
2726 }
2727
2728 num_of_levels = pcie_table->lclk_levels;
2729 if (!num_of_levels)
2730 return 0;
2731
2732 if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
2733 if (pcie_table->pcie_gen[num_of_levels - 1] < pcie_gen_cap)
2734 pcie_gen_cap = pcie_table->pcie_gen[num_of_levels - 1];
2735
2736 if (pcie_table->pcie_lane[num_of_levels - 1] < pcie_width_cap)
2737 pcie_width_cap = pcie_table->pcie_lane[num_of_levels - 1];
2738
2739 /* Force all levels to use the same settings */
2740 for (i = 0; i < num_of_levels; i++) {
2741 pcie_table->pcie_gen[i] = pcie_gen_cap;
2742 pcie_table->pcie_lane[i] = pcie_width_cap;
2743 smu_pcie_arg = i << 16;
2744 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
2745 smu_pcie_arg |= pcie_table->pcie_lane[i];
2746
2747 ret = smu_cmn_send_smc_msg_with_param(smu,
2748 SMU_MSG_OverridePcieParameters,
2749 smu_pcie_arg,
2750 NULL);
2751 if (ret)
2752 break;
2753 }
2754 } else {
2755 for (i = 0; i < num_of_levels; i++) {
2756 if (pcie_table->pcie_gen[i] > pcie_gen_cap ||
2757 pcie_table->pcie_lane[i] > pcie_width_cap) {
2758 pcie_table->pcie_gen[i] = pcie_table->pcie_gen[i] > pcie_gen_cap ?
2759 pcie_gen_cap : pcie_table->pcie_gen[i];
2760 pcie_table->pcie_lane[i] = pcie_table->pcie_lane[i] > pcie_width_cap ?
2761 pcie_width_cap : pcie_table->pcie_lane[i];
2762 smu_pcie_arg = i << 16;
2763 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
2764 smu_pcie_arg |= pcie_table->pcie_lane[i];
2765
2766 ret = smu_cmn_send_smc_msg_with_param(smu,
2767 SMU_MSG_OverridePcieParameters,
2768 smu_pcie_arg,
2769 NULL);
2770 if (ret)
2771 break;
2772 }
2773 }
2774 }
2775
2776 return ret;
2777 }
2778
smu_v13_0_7_mode1_reset(struct smu_context * smu)2779 static int smu_v13_0_7_mode1_reset(struct smu_context *smu)
2780 {
2781 int ret;
2782
2783 ret = smu_cmn_send_debug_smc_msg(smu, DEBUGSMC_MSG_Mode1Reset);
2784 if (!ret) {
2785 /* disable mmio access while doing mode 1 reset*/
2786 smu->adev->no_hw_access = true;
2787 /* ensure no_hw_access is globally visible before any MMIO */
2788 smp_mb();
2789 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
2790 }
2791
2792 return ret;
2793 }
2794
smu_v13_0_7_init_msg_ctl(struct smu_context * smu)2795 static void smu_v13_0_7_init_msg_ctl(struct smu_context *smu)
2796 {
2797 struct amdgpu_device *adev = smu->adev;
2798 struct smu_msg_ctl *ctl = &smu->msg_ctl;
2799
2800 smu_v13_0_init_msg_ctl(smu, smu_v13_0_7_message_map);
2801
2802 /* Set up debug mailbox registers */
2803 ctl->config.debug_param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_53);
2804 ctl->config.debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_75);
2805 ctl->config.debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_54);
2806 ctl->flags |= SMU_MSG_CTL_DEBUG_MAILBOX;
2807 }
2808
2809 static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
2810 .init_allowed_features = smu_v13_0_7_init_allowed_features,
2811 .set_default_dpm_table = smu_v13_0_7_set_default_dpm_table,
2812 .is_dpm_running = smu_v13_0_7_is_dpm_running,
2813 .init_microcode = smu_v13_0_init_microcode,
2814 .load_microcode = smu_v13_0_load_microcode,
2815 .fini_microcode = smu_v13_0_fini_microcode,
2816 .init_smc_tables = smu_v13_0_7_init_smc_tables,
2817 .fini_smc_tables = smu_v13_0_fini_smc_tables,
2818 .init_power = smu_v13_0_init_power,
2819 .fini_power = smu_v13_0_fini_power,
2820 .check_fw_status = smu_v13_0_7_check_fw_status,
2821 .setup_pptable = smu_v13_0_7_setup_pptable,
2822 .check_fw_version = smu_cmn_check_fw_version,
2823 .write_pptable = smu_cmn_write_pptable,
2824 .set_driver_table_location = smu_v13_0_set_driver_table_location,
2825 .system_features_control = smu_v13_0_system_features_control,
2826 .set_allowed_mask = smu_v13_0_set_allowed_mask,
2827 .get_enabled_mask = smu_cmn_get_enabled_mask,
2828 .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable,
2829 .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable,
2830 .init_pptable_microcode = smu_v13_0_init_pptable_microcode,
2831 .populate_umd_state_clk = smu_v13_0_7_populate_umd_state_clk,
2832 .get_dpm_ultimate_freq = smu_v13_0_7_get_dpm_ultimate_freq,
2833 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
2834 .read_sensor = smu_v13_0_7_read_sensor,
2835 .feature_is_enabled = smu_cmn_feature_is_enabled,
2836 .emit_clk_levels = smu_v13_0_7_emit_clk_levels,
2837 .force_clk_levels = smu_v13_0_7_force_clk_levels,
2838 .update_pcie_parameters = smu_v13_0_7_update_pcie_parameters,
2839 .get_thermal_temperature_range = smu_v13_0_7_get_thermal_temperature_range,
2840 .register_irq_handler = smu_v13_0_register_irq_handler,
2841 .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
2842 .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
2843 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
2844 .get_gpu_metrics = smu_v13_0_7_get_gpu_metrics,
2845 .set_soft_freq_limited_range = smu_v13_0_set_soft_freq_limited_range,
2846 .set_default_od_settings = smu_v13_0_7_set_default_od_settings,
2847 .restore_user_od_settings = smu_v13_0_7_restore_user_od_settings,
2848 .od_edit_dpm_table = smu_v13_0_7_od_edit_dpm_table,
2849 .set_performance_level = smu_v13_0_set_performance_level,
2850 .gfx_off_control = smu_v13_0_gfx_off_control,
2851 .get_fan_speed_pwm = smu_v13_0_7_get_fan_speed_pwm,
2852 .get_fan_speed_rpm = smu_v13_0_7_get_fan_speed_rpm,
2853 .set_fan_speed_pwm = smu_v13_0_set_fan_speed_pwm,
2854 .set_fan_speed_rpm = smu_v13_0_set_fan_speed_rpm,
2855 .get_fan_control_mode = smu_v13_0_get_fan_control_mode,
2856 .set_fan_control_mode = smu_v13_0_set_fan_control_mode,
2857 .enable_mgpu_fan_boost = smu_v13_0_7_enable_mgpu_fan_boost,
2858 .get_power_limit = smu_v13_0_7_get_power_limit,
2859 .set_power_limit = smu_v13_0_7_set_power_limit,
2860 .set_power_source = smu_v13_0_set_power_source,
2861 .get_power_profile_mode = smu_v13_0_7_get_power_profile_mode,
2862 .set_power_profile_mode = smu_v13_0_7_set_power_profile_mode,
2863 .set_tool_table_location = smu_v13_0_set_tool_table_location,
2864 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2865 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2866 .get_bamaco_support = smu_v13_0_get_bamaco_support,
2867 .baco_enter = smu_v13_0_baco_enter,
2868 .baco_exit = smu_v13_0_baco_exit,
2869 .mode1_reset_is_support = smu_v13_0_7_is_mode1_reset_supported,
2870 .mode1_reset = smu_v13_0_7_mode1_reset,
2871 .set_mp1_state = smu_v13_0_7_set_mp1_state,
2872 .set_df_cstate = smu_v13_0_7_set_df_cstate,
2873 .gpo_control = smu_v13_0_gpo_control,
2874 .is_asic_wbrf_supported = smu_v13_0_7_wbrf_support_check,
2875 .enable_uclk_shadow = smu_v13_0_enable_uclk_shadow,
2876 .set_wbrf_exclusion_ranges = smu_v13_0_set_wbrf_exclusion_ranges,
2877 .interrupt_work = smu_v13_0_interrupt_work,
2878 };
2879
smu_v13_0_7_set_ppt_funcs(struct smu_context * smu)2880 void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu)
2881 {
2882 smu->ppt_funcs = &smu_v13_0_7_ppt_funcs;
2883 smu->clock_map = smu_v13_0_7_clk_map;
2884 smu->feature_map = smu_v13_0_7_feature_mask_map;
2885 smu->table_map = smu_v13_0_7_table_map;
2886 smu->pwr_src_map = smu_v13_0_7_pwr_src_map;
2887 smu->workload_map = smu_v13_0_7_workload_map;
2888 smu->smc_driver_if_version = SMU13_0_7_DRIVER_IF_VERSION;
2889 smu_v13_0_7_init_msg_ctl(smu);
2890 }
2891