1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include <linux/pci.h>
28 #include <linux/i2c.h>
29 #include "amdgpu.h"
30 #include "amdgpu_smu.h"
31 #include "atomfirmware.h"
32 #include "amdgpu_atomfirmware.h"
33 #include "amdgpu_atombios.h"
34 #include "smu_v13_0.h"
35 #include "smu13_driver_if_v13_0_7.h"
36 #include "soc15_common.h"
37 #include "atom.h"
38 #include "smu_v13_0_7_ppt.h"
39 #include "smu_v13_0_7_pptable.h"
40 #include "smu_v13_0_7_ppsmc.h"
41 #include "nbio/nbio_4_3_0_offset.h"
42 #include "nbio/nbio_4_3_0_sh_mask.h"
43 #include "mp/mp_13_0_0_offset.h"
44 #include "mp/mp_13_0_0_sh_mask.h"
45
46 #include "asic_reg/mp/mp_13_0_0_sh_mask.h"
47 #include "smu_cmn.h"
48 #include "amdgpu_ras.h"
49
50 /*
51 * DO NOT use these for err/warn/info/debug messages.
52 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
53 * They are more MGPU friendly.
54 */
55 #undef pr_err
56 #undef pr_warn
57 #undef pr_info
58 #undef pr_debug
59
60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
61
62 static void smu_v13_0_7_get_od_setting_limits(struct smu_context *smu,
63 int od_feature_bit,
64 int32_t *min, int32_t *max);
65 static int smu_v13_0_7_init_ppt_limits(struct smu_context *smu);
66
67 static const struct smu_feature_bits smu_v13_0_7_dpm_features = {
68 .bits = {
69 SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT),
70 SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT),
71 SMU_FEATURE_BIT_INIT(FEATURE_DPM_LINK_BIT),
72 SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT),
73 SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT),
74 SMU_FEATURE_BIT_INIT(FEATURE_DPM_MP0CLK_BIT)
75 }
76 };
77
78 #define smnMP1_FIRMWARE_FLAGS_SMU_13_0_7 0x3b10028
79
80 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000
81
82 #define mmMP1_SMN_C2PMSG_75 0x028b
83 #define mmMP1_SMN_C2PMSG_75_BASE_IDX 0
84
85 #define mmMP1_SMN_C2PMSG_53 0x0275
86 #define mmMP1_SMN_C2PMSG_53_BASE_IDX 0
87
88 #define mmMP1_SMN_C2PMSG_54 0x0276
89 #define mmMP1_SMN_C2PMSG_54_BASE_IDX 0
90
91 #define DEBUGSMC_MSG_Mode1Reset 2
92
93 #define PP_OD_FEATURE_GFXCLK_FMIN 0
94 #define PP_OD_FEATURE_GFXCLK_FMAX 1
95 #define PP_OD_FEATURE_UCLK_FMIN 2
96 #define PP_OD_FEATURE_UCLK_FMAX 3
97 #define PP_OD_FEATURE_GFX_VF_CURVE 4
98 #define PP_OD_FEATURE_FAN_CURVE_TEMP 5
99 #define PP_OD_FEATURE_FAN_CURVE_PWM 6
100 #define PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT 7
101 #define PP_OD_FEATURE_FAN_ACOUSTIC_TARGET 8
102 #define PP_OD_FEATURE_FAN_TARGET_TEMPERATURE 9
103 #define PP_OD_FEATURE_FAN_MINIMUM_PWM 10
104 #define PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE 11
105 #define PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP 12
106
107 #define LINK_SPEED_MAX 3
108
109 static struct cmn2asic_msg_mapping smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] = {
110 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
111 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
112 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
113 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
114 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
115 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
116 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
117 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
118 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
119 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
120 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
121 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
122 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
123 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
124 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
125 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
126 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
127 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
128 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
129 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
130 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
131 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
132 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
133 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
134 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
135 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
136 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
137 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
138 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
139 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
140 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
141 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
142 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
143 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
144 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
145 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
146 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
147 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
148 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
149 MSG_MAP(AllowIHHostInterrupt, PPSMC_MSG_AllowIHHostInterrupt, 0),
150 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
151 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
152 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
153 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
154 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
155 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
156 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
157 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
158 MSG_MAP(DFCstateControl, PPSMC_MSG_SetExternalClientDfCstateAllow, 0),
159 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
160 MSG_MAP(AllowGpo, PPSMC_MSG_SetGpoAllow, 0),
161 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
162 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
163 MSG_MAP(EnableUCLKShadow, PPSMC_MSG_EnableUCLKShadow, 0),
164 };
165
166 static struct cmn2asic_mapping smu_v13_0_7_clk_map[SMU_CLK_COUNT] = {
167 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
168 CLK_MAP(SCLK, PPCLK_GFXCLK),
169 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
170 CLK_MAP(FCLK, PPCLK_FCLK),
171 CLK_MAP(UCLK, PPCLK_UCLK),
172 CLK_MAP(MCLK, PPCLK_UCLK),
173 CLK_MAP(VCLK, PPCLK_VCLK_0),
174 CLK_MAP(VCLK1, PPCLK_VCLK_1),
175 CLK_MAP(DCLK, PPCLK_DCLK_0),
176 CLK_MAP(DCLK1, PPCLK_DCLK_1),
177 CLK_MAP(DCEFCLK, PPCLK_DCFCLK),
178 };
179
180 static struct cmn2asic_mapping smu_v13_0_7_feature_mask_map[SMU_FEATURE_COUNT] = {
181 FEA_MAP(FW_DATA_READ),
182 FEA_MAP(DPM_GFXCLK),
183 FEA_MAP(DPM_GFX_POWER_OPTIMIZER),
184 FEA_MAP(DPM_UCLK),
185 FEA_MAP(DPM_FCLK),
186 FEA_MAP(DPM_SOCCLK),
187 FEA_MAP(DPM_MP0CLK),
188 FEA_MAP(DPM_LINK),
189 FEA_MAP(DPM_DCN),
190 FEA_MAP(VMEMP_SCALING),
191 FEA_MAP(VDDIO_MEM_SCALING),
192 FEA_MAP(DS_GFXCLK),
193 FEA_MAP(DS_SOCCLK),
194 FEA_MAP(DS_FCLK),
195 FEA_MAP(DS_LCLK),
196 FEA_MAP(DS_DCFCLK),
197 FEA_MAP(DS_UCLK),
198 FEA_MAP(GFX_ULV),
199 FEA_MAP(FW_DSTATE),
200 FEA_MAP(GFXOFF),
201 FEA_MAP(BACO),
202 FEA_MAP(MM_DPM),
203 FEA_MAP(SOC_MPCLK_DS),
204 FEA_MAP(BACO_MPCLK_DS),
205 FEA_MAP(THROTTLERS),
206 FEA_MAP(SMARTSHIFT),
207 FEA_MAP(GTHR),
208 FEA_MAP(ACDC),
209 FEA_MAP(VR0HOT),
210 FEA_MAP(FW_CTF),
211 FEA_MAP(FAN_CONTROL),
212 FEA_MAP(GFX_DCS),
213 FEA_MAP(GFX_READ_MARGIN),
214 FEA_MAP(LED_DISPLAY),
215 FEA_MAP(GFXCLK_SPREAD_SPECTRUM),
216 FEA_MAP(OUT_OF_BAND_MONITOR),
217 FEA_MAP(OPTIMIZED_VMIN),
218 FEA_MAP(GFX_IMU),
219 FEA_MAP(BOOT_TIME_CAL),
220 FEA_MAP(GFX_PCC_DFLL),
221 FEA_MAP(SOC_CG),
222 FEA_MAP(DF_CSTATE),
223 FEA_MAP(GFX_EDC),
224 FEA_MAP(BOOT_POWER_OPT),
225 FEA_MAP(CLOCK_POWER_DOWN_BYPASS),
226 FEA_MAP(DS_VCN),
227 FEA_MAP(BACO_CG),
228 FEA_MAP(MEM_TEMP_READ),
229 FEA_MAP(ATHUB_MMHUB_PG),
230 FEA_MAP(SOC_PCC),
231 [SMU_FEATURE_DPM_VCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
232 [SMU_FEATURE_DPM_DCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
233 [SMU_FEATURE_PPT_BIT] = {1, FEATURE_THROTTLERS_BIT},
234 };
235
236 static struct cmn2asic_mapping smu_v13_0_7_table_map[SMU_TABLE_COUNT] = {
237 TAB_MAP(PPTABLE),
238 TAB_MAP(WATERMARKS),
239 TAB_MAP(AVFS_PSM_DEBUG),
240 TAB_MAP(PMSTATUSLOG),
241 TAB_MAP(SMU_METRICS),
242 TAB_MAP(DRIVER_SMU_CONFIG),
243 TAB_MAP(ACTIVITY_MONITOR_COEFF),
244 [SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE},
245 TAB_MAP(OVERDRIVE),
246 TAB_MAP(WIFIBAND),
247 };
248
249 static struct cmn2asic_mapping smu_v13_0_7_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
250 PWR_MAP(AC),
251 PWR_MAP(DC),
252 };
253
254 static struct cmn2asic_mapping smu_v13_0_7_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
255 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
256 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
257 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
258 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
259 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
260 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
261 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
262 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_WINDOW3D, WORKLOAD_PPLIB_WINDOW_3D_BIT),
263 };
264
265 static const uint8_t smu_v13_0_7_throttler_map[] = {
266 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
267 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
268 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
269 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
270 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
271 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
272 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
273 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
274 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
275 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
276 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
277 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
278 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
279 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
280 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
281 [THROTTLER_GFX_APCC_PLUS_BIT] = (SMU_THROTTLER_APCC_BIT),
282 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
283 };
284
285 static int
smu_v13_0_7_init_allowed_features(struct smu_context * smu)286 smu_v13_0_7_init_allowed_features(struct smu_context *smu)
287 {
288 struct amdgpu_device *adev = smu->adev;
289
290 smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED);
291
292 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DATA_READ_BIT);
293
294 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
295 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT);
296 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_IMU_BIT);
297 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT);
298 }
299
300 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
301 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT);
302
303 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) {
304 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT);
305 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_FCLK_BIT);
306 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VMEMP_SCALING_BIT);
307 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VDDIO_MEM_SCALING_BIT);
308 }
309
310 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT);
311
312 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
313 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT);
314
315 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
316 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT);
317
318 if (adev->pm.pp_feature & PP_ULV_MASK)
319 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT);
320
321 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT);
322 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_MP0CLK_BIT);
323 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MM_DPM_BIT);
324 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_VCN_BIT);
325 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_FCLK_BIT);
326 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DF_CSTATE_BIT);
327 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_THROTTLERS_BIT);
328 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VR0HOT_BIT);
329 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_CTF_BIT);
330 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FAN_CONTROL_BIT);
331 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT);
332 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT);
333 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_TEMP_READ_BIT);
334 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DSTATE_BIT);
335 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_SOC_MPCLK_DS_BIT);
336 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_MPCLK_DS_BIT);
337 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_PCC_DFLL_BIT);
338 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_SOC_CG_BIT);
339 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_BIT);
340
341 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
342 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_DCN_BIT);
343
344 if ((adev->pg_flags & AMD_PG_SUPPORT_ATHUB) &&
345 (adev->pg_flags & AMD_PG_SUPPORT_MMHUB))
346 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_MMHUB_PG_BIT);
347
348 return 0;
349 }
350
smu_v13_0_7_check_powerplay_table(struct smu_context * smu)351 static int smu_v13_0_7_check_powerplay_table(struct smu_context *smu)
352 {
353 struct smu_table_context *table_context = &smu->smu_table;
354 struct smu_13_0_7_powerplay_table *powerplay_table =
355 table_context->power_play_table;
356 struct smu_baco_context *smu_baco = &smu->smu_baco;
357 PPTable_t *smc_pptable = table_context->driver_pptable;
358 BoardTable_t *BoardTable = &smc_pptable->BoardTable;
359 const OverDriveLimits_t * const overdrive_upperlimits =
360 &smc_pptable->SkuTable.OverDriveLimitsBasicMax;
361 const OverDriveLimits_t * const overdrive_lowerlimits =
362 &smc_pptable->SkuTable.OverDriveLimitsMin;
363
364 if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_HARDWAREDC)
365 smu->dc_controlled_by_gpio = true;
366
367 if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_BACO) {
368 smu_baco->platform_support = true;
369
370 if ((powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_MACO)
371 && (BoardTable->HsrEnabled || BoardTable->VddqOffEnabled))
372 smu_baco->maco_support = true;
373 }
374
375 if (!overdrive_lowerlimits->FeatureCtrlMask ||
376 !overdrive_upperlimits->FeatureCtrlMask)
377 smu->od_enabled = false;
378
379 table_context->thermal_controller_type =
380 powerplay_table->thermal_controller_type;
381
382 /*
383 * Instead of having its own buffer space and get overdrive_table copied,
384 * smu->od_settings just points to the actual overdrive_table
385 */
386 smu->od_settings = &powerplay_table->overdrive_table;
387
388 return 0;
389 }
390
smu_v13_0_7_store_powerplay_table(struct smu_context * smu)391 static int smu_v13_0_7_store_powerplay_table(struct smu_context *smu)
392 {
393 struct smu_table_context *table_context = &smu->smu_table;
394 struct smu_13_0_7_powerplay_table *powerplay_table =
395 table_context->power_play_table;
396 struct amdgpu_device *adev = smu->adev;
397
398 if (adev->pdev->device == 0x51)
399 powerplay_table->smc_pptable.SkuTable.DebugOverrides |= 0x00000080;
400
401 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
402 sizeof(PPTable_t));
403
404 return 0;
405 }
406
smu_v13_0_7_check_fw_status(struct smu_context * smu)407 static int smu_v13_0_7_check_fw_status(struct smu_context *smu)
408 {
409 struct amdgpu_device *adev = smu->adev;
410 uint32_t mp1_fw_flags;
411
412 mp1_fw_flags = RREG32_PCIE(MP1_Public |
413 (smnMP1_FIRMWARE_FLAGS_SMU_13_0_7 & 0xffffffff));
414
415 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
416 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
417 return 0;
418
419 return -EIO;
420 }
421
422 #ifndef atom_smc_dpm_info_table_13_0_7
423 struct atom_smc_dpm_info_table_13_0_7 {
424 struct atom_common_table_header table_header;
425 BoardTable_t BoardTable;
426 };
427 #endif
428
smu_v13_0_7_append_powerplay_table(struct smu_context * smu)429 static int smu_v13_0_7_append_powerplay_table(struct smu_context *smu)
430 {
431 struct smu_table_context *table_context = &smu->smu_table;
432
433 PPTable_t *smc_pptable = table_context->driver_pptable;
434
435 struct atom_smc_dpm_info_table_13_0_7 *smc_dpm_table;
436
437 BoardTable_t *BoardTable = &smc_pptable->BoardTable;
438
439 int index, ret;
440
441 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
442 smc_dpm_info);
443
444 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
445 (uint8_t **)&smc_dpm_table);
446 if (ret)
447 return ret;
448
449 memcpy(BoardTable, &smc_dpm_table->BoardTable, sizeof(BoardTable_t));
450
451 return 0;
452 }
453
smu_v13_0_7_get_pptable_from_pmfw(struct smu_context * smu,void ** table,uint32_t * size)454 static int smu_v13_0_7_get_pptable_from_pmfw(struct smu_context *smu,
455 void **table,
456 uint32_t *size)
457 {
458 struct smu_table_context *smu_table = &smu->smu_table;
459 void *combo_pptable = smu_table->combo_pptable;
460 int ret = 0;
461
462 ret = smu_cmn_get_combo_pptable(smu);
463 if (ret)
464 return ret;
465
466 *table = combo_pptable;
467 *size = sizeof(struct smu_13_0_7_powerplay_table);
468
469 return 0;
470 }
471
smu_v13_0_7_setup_pptable(struct smu_context * smu)472 static int smu_v13_0_7_setup_pptable(struct smu_context *smu)
473 {
474 struct smu_table_context *smu_table = &smu->smu_table;
475 struct amdgpu_device *adev = smu->adev;
476 int ret = 0;
477
478 /*
479 * With SCPM enabled, the pptable used will be signed. It cannot
480 * be used directly by driver. To get the raw pptable, we need to
481 * rely on the combo pptable(and its revelant SMU message).
482 */
483 ret = smu_v13_0_7_get_pptable_from_pmfw(smu,
484 &smu_table->power_play_table,
485 &smu_table->power_play_table_size);
486 if (ret)
487 return ret;
488
489 ret = smu_v13_0_7_store_powerplay_table(smu);
490 if (ret)
491 return ret;
492
493 /*
494 * With SCPM enabled, the operation below will be handled
495 * by PSP. Driver involvment is unnecessary and useless.
496 */
497 if (!adev->scpm_enabled) {
498 ret = smu_v13_0_7_append_powerplay_table(smu);
499 if (ret)
500 return ret;
501 }
502
503 ret = smu_v13_0_7_check_powerplay_table(smu);
504 if (ret)
505 return ret;
506
507 return smu_v13_0_7_init_ppt_limits(smu);
508 }
509
smu_v13_0_7_tables_init(struct smu_context * smu)510 static int smu_v13_0_7_tables_init(struct smu_context *smu)
511 {
512 struct smu_table_context *smu_table = &smu->smu_table;
513 struct smu_table *tables = smu_table->tables;
514 int ret;
515
516 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
517 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
518
519 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
520 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
521 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
522 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
523 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
524 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
525 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTableExternal_t),
526 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
527 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
528 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
529 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
530 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
531 AMDGPU_GEM_DOMAIN_VRAM);
532 SMU_TABLE_INIT(tables, SMU_TABLE_COMBO_PPTABLE, MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE,
533 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
534 SMU_TABLE_INIT(tables, SMU_TABLE_WIFIBAND,
535 sizeof(WifiBandEntryTable_t), PAGE_SIZE,
536 AMDGPU_GEM_DOMAIN_VRAM);
537
538 smu_table->metrics_table = kzalloc_obj(SmuMetricsExternal_t);
539 if (!smu_table->metrics_table)
540 goto err0_out;
541 smu_table->metrics_time = 0;
542
543 ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPU_METRICS,
544 sizeof(struct gpu_metrics_v1_3),
545 SMU_GPU_METRICS_CACHE_INTERVAL);
546 if (ret)
547 goto err1_out;
548
549 smu_table->watermarks_table = kzalloc_obj(Watermarks_t);
550 if (!smu_table->watermarks_table)
551 goto err2_out;
552
553 return 0;
554
555 err2_out:
556 smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS);
557 err1_out:
558 kfree(smu_table->metrics_table);
559 err0_out:
560 return -ENOMEM;
561 }
562
smu_v13_0_7_allocate_dpm_context(struct smu_context * smu)563 static int smu_v13_0_7_allocate_dpm_context(struct smu_context *smu)
564 {
565 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
566
567 smu_dpm->dpm_context = kzalloc_obj(struct smu_13_0_dpm_context);
568 if (!smu_dpm->dpm_context)
569 return -ENOMEM;
570
571 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
572
573 return 0;
574 }
575
smu_v13_0_7_init_smc_tables(struct smu_context * smu)576 static int smu_v13_0_7_init_smc_tables(struct smu_context *smu)
577 {
578 int ret = 0;
579
580 ret = smu_v13_0_7_tables_init(smu);
581 if (ret)
582 return ret;
583
584 ret = smu_v13_0_7_allocate_dpm_context(smu);
585 if (ret)
586 return ret;
587
588 return smu_v13_0_init_smc_tables(smu);
589 }
590
smu_v13_0_7_set_default_dpm_table(struct smu_context * smu)591 static int smu_v13_0_7_set_default_dpm_table(struct smu_context *smu)
592 {
593 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
594 PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
595 SkuTable_t *skutable = &driver_ppt->SkuTable;
596 struct smu_dpm_table *dpm_table;
597 int ret = 0;
598
599 /* socclk dpm table setup */
600 dpm_table = &dpm_context->dpm_tables.soc_table;
601 dpm_table->clk_type = SMU_SOCCLK;
602 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
603 ret = smu_v13_0_set_single_dpm_table(smu,
604 SMU_SOCCLK,
605 dpm_table);
606 if (ret)
607 return ret;
608 } else {
609 dpm_table->count = 1;
610 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
611 dpm_table->dpm_levels[0].enabled = true;
612 }
613
614 /* gfxclk dpm table setup */
615 dpm_table = &dpm_context->dpm_tables.gfx_table;
616 dpm_table->clk_type = SMU_GFXCLK;
617 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
618 ret = smu_v13_0_set_single_dpm_table(smu,
619 SMU_GFXCLK,
620 dpm_table);
621 if (ret)
622 return ret;
623
624 if (skutable->DriverReportedClocks.GameClockAc &&
625 (dpm_table->dpm_levels[dpm_table->count - 1].value >
626 skutable->DriverReportedClocks.GameClockAc)) {
627 dpm_table->dpm_levels[dpm_table->count - 1].value =
628 skutable->DriverReportedClocks.GameClockAc;
629 }
630 } else {
631 dpm_table->count = 1;
632 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
633 dpm_table->dpm_levels[0].enabled = true;
634 }
635
636 /* uclk dpm table setup */
637 dpm_table = &dpm_context->dpm_tables.uclk_table;
638 dpm_table->clk_type = SMU_UCLK;
639 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
640 ret = smu_v13_0_set_single_dpm_table(smu,
641 SMU_UCLK,
642 dpm_table);
643 if (ret)
644 return ret;
645 } else {
646 dpm_table->count = 1;
647 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
648 dpm_table->dpm_levels[0].enabled = true;
649 }
650
651 /* fclk dpm table setup */
652 dpm_table = &dpm_context->dpm_tables.fclk_table;
653 dpm_table->clk_type = SMU_FCLK;
654 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
655 ret = smu_v13_0_set_single_dpm_table(smu,
656 SMU_FCLK,
657 dpm_table);
658 if (ret)
659 return ret;
660 } else {
661 dpm_table->count = 1;
662 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
663 dpm_table->dpm_levels[0].enabled = true;
664 }
665
666 /* vclk dpm table setup */
667 dpm_table = &dpm_context->dpm_tables.vclk_table;
668 dpm_table->clk_type = SMU_VCLK;
669 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) {
670 ret = smu_v13_0_set_single_dpm_table(smu,
671 SMU_VCLK,
672 dpm_table);
673 if (ret)
674 return ret;
675 } else {
676 dpm_table->count = 1;
677 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
678 dpm_table->dpm_levels[0].enabled = true;
679 }
680
681 /* dclk dpm table setup */
682 dpm_table = &dpm_context->dpm_tables.dclk_table;
683 dpm_table->clk_type = SMU_DCLK;
684 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) {
685 ret = smu_v13_0_set_single_dpm_table(smu,
686 SMU_DCLK,
687 dpm_table);
688 if (ret)
689 return ret;
690 } else {
691 dpm_table->count = 1;
692 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
693 dpm_table->dpm_levels[0].enabled = true;
694 }
695
696 /* dcefclk dpm table setup */
697 dpm_table = &dpm_context->dpm_tables.dcef_table;
698 dpm_table->clk_type = SMU_DCEFCLK;
699 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCN_BIT)) {
700 ret = smu_v13_0_set_single_dpm_table(smu,
701 SMU_DCEFCLK,
702 dpm_table);
703 if (ret)
704 return ret;
705 } else {
706 dpm_table->count = 1;
707 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
708 dpm_table->dpm_levels[0].enabled = true;
709 }
710
711 return 0;
712 }
713
smu_v13_0_7_is_dpm_running(struct smu_context * smu)714 static bool smu_v13_0_7_is_dpm_running(struct smu_context *smu)
715 {
716 int ret = 0;
717 struct smu_feature_bits feature_enabled;
718
719 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
720 if (ret)
721 return false;
722
723 return smu_feature_bits_test_mask(&feature_enabled,
724 smu_v13_0_7_dpm_features.bits);
725 }
726
smu_v13_0_7_get_throttler_status(SmuMetrics_t * metrics)727 static uint32_t smu_v13_0_7_get_throttler_status(SmuMetrics_t *metrics)
728 {
729 uint32_t throttler_status = 0;
730 int i;
731
732 for (i = 0; i < THROTTLER_COUNT; i++)
733 throttler_status |=
734 (metrics->ThrottlingPercentage[i] ? 1U << i : 0);
735
736 return throttler_status;
737 }
738
739 #define SMU_13_0_7_BUSY_THRESHOLD 15
smu_v13_0_7_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)740 static int smu_v13_0_7_get_smu_metrics_data(struct smu_context *smu,
741 MetricsMember_t member,
742 uint32_t *value)
743 {
744 struct smu_table_context *smu_table = &smu->smu_table;
745 SmuMetrics_t *metrics =
746 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
747 int ret = 0;
748
749 ret = smu_cmn_get_metrics_table(smu,
750 NULL,
751 false);
752 if (ret)
753 return ret;
754
755 switch (member) {
756 case METRICS_CURR_GFXCLK:
757 *value = metrics->CurrClock[PPCLK_GFXCLK];
758 break;
759 case METRICS_CURR_SOCCLK:
760 *value = metrics->CurrClock[PPCLK_SOCCLK];
761 break;
762 case METRICS_CURR_UCLK:
763 *value = metrics->CurrClock[PPCLK_UCLK];
764 break;
765 case METRICS_CURR_VCLK:
766 *value = metrics->CurrClock[PPCLK_VCLK_0];
767 break;
768 case METRICS_CURR_VCLK1:
769 *value = metrics->CurrClock[PPCLK_VCLK_1];
770 break;
771 case METRICS_CURR_DCLK:
772 *value = metrics->CurrClock[PPCLK_DCLK_0];
773 break;
774 case METRICS_CURR_DCLK1:
775 *value = metrics->CurrClock[PPCLK_DCLK_1];
776 break;
777 case METRICS_CURR_FCLK:
778 *value = metrics->CurrClock[PPCLK_FCLK];
779 break;
780 case METRICS_CURR_DCEFCLK:
781 *value = metrics->CurrClock[PPCLK_DCFCLK];
782 break;
783 case METRICS_AVERAGE_GFXCLK:
784 *value = metrics->AverageGfxclkFrequencyPreDs;
785 break;
786 case METRICS_AVERAGE_FCLK:
787 if (smu_safe_u16_nn(metrics->AverageUclkActivity) <= SMU_13_0_7_BUSY_THRESHOLD)
788 *value = metrics->AverageFclkFrequencyPostDs;
789 else
790 *value = metrics->AverageFclkFrequencyPreDs;
791 break;
792 case METRICS_AVERAGE_UCLK:
793 if (smu_safe_u16_nn(metrics->AverageUclkActivity) <= SMU_13_0_7_BUSY_THRESHOLD)
794 *value = metrics->AverageMemclkFrequencyPostDs;
795 else
796 *value = metrics->AverageMemclkFrequencyPreDs;
797 break;
798 case METRICS_AVERAGE_VCNACTIVITY:
799 *value = max(metrics->Vcn0ActivityPercentage,
800 metrics->Vcn1ActivityPercentage);
801 break;
802 case METRICS_AVERAGE_VCLK:
803 *value = metrics->AverageVclk0Frequency;
804 break;
805 case METRICS_AVERAGE_DCLK:
806 *value = metrics->AverageDclk0Frequency;
807 break;
808 case METRICS_AVERAGE_VCLK1:
809 *value = metrics->AverageVclk1Frequency;
810 break;
811 case METRICS_AVERAGE_DCLK1:
812 *value = metrics->AverageDclk1Frequency;
813 break;
814 case METRICS_AVERAGE_GFXACTIVITY:
815 *value = metrics->AverageGfxActivity;
816 break;
817 case METRICS_AVERAGE_MEMACTIVITY:
818 *value = smu_safe_u16_nn(metrics->AverageUclkActivity);
819 break;
820 case METRICS_AVERAGE_SOCKETPOWER:
821 *value = metrics->AverageSocketPower * MILLIWATT_PER_WATT;
822 break;
823 case METRICS_TEMPERATURE_EDGE:
824 *value = metrics->AvgTemperature[TEMP_EDGE] *
825 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
826 break;
827 case METRICS_TEMPERATURE_HOTSPOT:
828 *value = metrics->AvgTemperature[TEMP_HOTSPOT] *
829 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
830 break;
831 case METRICS_TEMPERATURE_MEM:
832 *value = metrics->AvgTemperature[TEMP_MEM] *
833 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
834 break;
835 case METRICS_TEMPERATURE_VRGFX:
836 *value = metrics->AvgTemperature[TEMP_VR_GFX] *
837 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
838 break;
839 case METRICS_TEMPERATURE_VRSOC:
840 *value = metrics->AvgTemperature[TEMP_VR_SOC] *
841 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
842 break;
843 case METRICS_THROTTLER_STATUS:
844 *value = smu_v13_0_7_get_throttler_status(metrics);
845 break;
846 case METRICS_CURR_FANSPEED:
847 *value = metrics->AvgFanRpm;
848 break;
849 case METRICS_CURR_FANPWM:
850 *value = metrics->AvgFanPwm;
851 break;
852 case METRICS_VOLTAGE_VDDGFX:
853 *value = metrics->AvgVoltage[SVI_PLANE_GFX];
854 break;
855 case METRICS_PCIE_RATE:
856 *value = metrics->PcieRate;
857 break;
858 case METRICS_PCIE_WIDTH:
859 *value = metrics->PcieWidth;
860 break;
861 default:
862 *value = UINT_MAX;
863 break;
864 }
865
866 return ret;
867 }
868
smu_v13_0_7_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)869 static int smu_v13_0_7_get_dpm_ultimate_freq(struct smu_context *smu,
870 enum smu_clk_type clk_type,
871 uint32_t *min,
872 uint32_t *max)
873 {
874 struct smu_13_0_dpm_context *dpm_context =
875 smu->smu_dpm.dpm_context;
876 struct smu_dpm_table *dpm_table;
877
878 switch (clk_type) {
879 case SMU_MCLK:
880 case SMU_UCLK:
881 /* uclk dpm table */
882 dpm_table = &dpm_context->dpm_tables.uclk_table;
883 break;
884 case SMU_GFXCLK:
885 case SMU_SCLK:
886 /* gfxclk dpm table */
887 dpm_table = &dpm_context->dpm_tables.gfx_table;
888 break;
889 case SMU_SOCCLK:
890 /* socclk dpm table */
891 dpm_table = &dpm_context->dpm_tables.soc_table;
892 break;
893 case SMU_FCLK:
894 /* fclk dpm table */
895 dpm_table = &dpm_context->dpm_tables.fclk_table;
896 break;
897 case SMU_VCLK:
898 case SMU_VCLK1:
899 /* vclk dpm table */
900 dpm_table = &dpm_context->dpm_tables.vclk_table;
901 break;
902 case SMU_DCLK:
903 case SMU_DCLK1:
904 /* dclk dpm table */
905 dpm_table = &dpm_context->dpm_tables.dclk_table;
906 break;
907 default:
908 dev_err(smu->adev->dev, "Unsupported clock type!\n");
909 return -EINVAL;
910 }
911
912 if (min)
913 *min = SMU_DPM_TABLE_MIN(dpm_table);
914 if (max)
915 *max = SMU_DPM_TABLE_MAX(dpm_table);
916
917 return 0;
918 }
919
smu_v13_0_7_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)920 static int smu_v13_0_7_read_sensor(struct smu_context *smu,
921 enum amd_pp_sensors sensor,
922 void *data,
923 uint32_t *size)
924 {
925 struct smu_table_context *table_context = &smu->smu_table;
926 PPTable_t *smc_pptable = table_context->driver_pptable;
927 int ret = 0;
928
929 switch (sensor) {
930 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
931 *(uint16_t *)data = smc_pptable->SkuTable.FanMaximumRpm;
932 *size = 4;
933 break;
934 case AMDGPU_PP_SENSOR_MEM_LOAD:
935 ret = smu_v13_0_7_get_smu_metrics_data(smu,
936 METRICS_AVERAGE_MEMACTIVITY,
937 (uint32_t *)data);
938 *size = 4;
939 break;
940 case AMDGPU_PP_SENSOR_GPU_LOAD:
941 ret = smu_v13_0_7_get_smu_metrics_data(smu,
942 METRICS_AVERAGE_GFXACTIVITY,
943 (uint32_t *)data);
944 *size = 4;
945 break;
946 case AMDGPU_PP_SENSOR_VCN_LOAD:
947 ret = smu_v13_0_7_get_smu_metrics_data(smu,
948 METRICS_AVERAGE_VCNACTIVITY,
949 (uint32_t *)data);
950 *size = 4;
951 break;
952 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
953 ret = smu_v13_0_7_get_smu_metrics_data(smu,
954 METRICS_AVERAGE_SOCKETPOWER,
955 (uint32_t *)data);
956 *size = 4;
957 break;
958 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
959 ret = smu_v13_0_7_get_smu_metrics_data(smu,
960 METRICS_TEMPERATURE_HOTSPOT,
961 (uint32_t *)data);
962 *size = 4;
963 break;
964 case AMDGPU_PP_SENSOR_EDGE_TEMP:
965 ret = smu_v13_0_7_get_smu_metrics_data(smu,
966 METRICS_TEMPERATURE_EDGE,
967 (uint32_t *)data);
968 *size = 4;
969 break;
970 case AMDGPU_PP_SENSOR_MEM_TEMP:
971 ret = smu_v13_0_7_get_smu_metrics_data(smu,
972 METRICS_TEMPERATURE_MEM,
973 (uint32_t *)data);
974 *size = 4;
975 break;
976 case AMDGPU_PP_SENSOR_GFX_MCLK:
977 ret = smu_v13_0_7_get_smu_metrics_data(smu,
978 METRICS_CURR_UCLK,
979 (uint32_t *)data);
980 *(uint32_t *)data *= 100;
981 *size = 4;
982 break;
983 case AMDGPU_PP_SENSOR_GFX_SCLK:
984 ret = smu_v13_0_7_get_smu_metrics_data(smu,
985 METRICS_AVERAGE_GFXCLK,
986 (uint32_t *)data);
987 *(uint32_t *)data *= 100;
988 *size = 4;
989 break;
990 case AMDGPU_PP_SENSOR_VDDGFX:
991 ret = smu_v13_0_7_get_smu_metrics_data(smu,
992 METRICS_VOLTAGE_VDDGFX,
993 (uint32_t *)data);
994 *size = 4;
995 break;
996 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
997 default:
998 ret = -EOPNOTSUPP;
999 break;
1000 }
1001
1002 return ret;
1003 }
1004
smu_v13_0_7_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1005 static int smu_v13_0_7_get_current_clk_freq_by_table(struct smu_context *smu,
1006 enum smu_clk_type clk_type,
1007 uint32_t *value)
1008 {
1009 MetricsMember_t member_type;
1010 int clk_id = 0;
1011
1012 clk_id = smu_cmn_to_asic_specific_index(smu,
1013 CMN2ASIC_MAPPING_CLK,
1014 clk_type);
1015 if (clk_id < 0)
1016 return -EINVAL;
1017
1018 switch (clk_id) {
1019 case PPCLK_GFXCLK:
1020 member_type = METRICS_AVERAGE_GFXCLK;
1021 break;
1022 case PPCLK_UCLK:
1023 member_type = METRICS_CURR_UCLK;
1024 break;
1025 case PPCLK_FCLK:
1026 member_type = METRICS_CURR_FCLK;
1027 break;
1028 case PPCLK_SOCCLK:
1029 member_type = METRICS_CURR_SOCCLK;
1030 break;
1031 case PPCLK_VCLK_0:
1032 member_type = METRICS_CURR_VCLK;
1033 break;
1034 case PPCLK_DCLK_0:
1035 member_type = METRICS_CURR_DCLK;
1036 break;
1037 case PPCLK_VCLK_1:
1038 member_type = METRICS_CURR_VCLK1;
1039 break;
1040 case PPCLK_DCLK_1:
1041 member_type = METRICS_CURR_DCLK1;
1042 break;
1043 case PPCLK_DCFCLK:
1044 member_type = METRICS_CURR_DCEFCLK;
1045 break;
1046 default:
1047 return -EINVAL;
1048 }
1049
1050 return smu_v13_0_7_get_smu_metrics_data(smu,
1051 member_type,
1052 value);
1053 }
1054
smu_v13_0_7_is_od_feature_supported(struct smu_context * smu,int od_feature_bit)1055 static bool smu_v13_0_7_is_od_feature_supported(struct smu_context *smu,
1056 int od_feature_bit)
1057 {
1058 PPTable_t *pptable = smu->smu_table.driver_pptable;
1059 const OverDriveLimits_t * const overdrive_upperlimits =
1060 &pptable->SkuTable.OverDriveLimitsBasicMax;
1061 int32_t min_value, max_value;
1062 bool feature_enabled;
1063
1064 switch (od_feature_bit) {
1065 case PP_OD_FEATURE_FAN_CURVE_BIT:
1066 feature_enabled = !!(overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit));
1067 if (feature_enabled) {
1068 smu_v13_0_7_get_od_setting_limits(smu, PP_OD_FEATURE_FAN_CURVE_TEMP,
1069 &min_value, &max_value);
1070 if (!min_value && !max_value) {
1071 feature_enabled = false;
1072 goto out;
1073 }
1074
1075 smu_v13_0_7_get_od_setting_limits(smu, PP_OD_FEATURE_FAN_CURVE_PWM,
1076 &min_value, &max_value);
1077 if (!min_value && !max_value) {
1078 feature_enabled = false;
1079 goto out;
1080 }
1081 }
1082 break;
1083 default:
1084 feature_enabled = !!(overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit));
1085 break;
1086 }
1087
1088 out:
1089 return feature_enabled;
1090 }
1091
smu_v13_0_7_get_od_setting_limits(struct smu_context * smu,int od_feature_bit,int32_t * min,int32_t * max)1092 static void smu_v13_0_7_get_od_setting_limits(struct smu_context *smu,
1093 int od_feature_bit,
1094 int32_t *min,
1095 int32_t *max)
1096 {
1097 PPTable_t *pptable = smu->smu_table.driver_pptable;
1098 const OverDriveLimits_t * const overdrive_upperlimits =
1099 &pptable->SkuTable.OverDriveLimitsBasicMax;
1100 const OverDriveLimits_t * const overdrive_lowerlimits =
1101 &pptable->SkuTable.OverDriveLimitsMin;
1102 int32_t od_min_setting, od_max_setting;
1103
1104 switch (od_feature_bit) {
1105 case PP_OD_FEATURE_GFXCLK_FMIN:
1106 od_min_setting = overdrive_lowerlimits->GfxclkFmin;
1107 od_max_setting = overdrive_upperlimits->GfxclkFmin;
1108 break;
1109 case PP_OD_FEATURE_GFXCLK_FMAX:
1110 od_min_setting = overdrive_lowerlimits->GfxclkFmax;
1111 od_max_setting = overdrive_upperlimits->GfxclkFmax;
1112 break;
1113 case PP_OD_FEATURE_UCLK_FMIN:
1114 od_min_setting = overdrive_lowerlimits->UclkFmin;
1115 od_max_setting = overdrive_upperlimits->UclkFmin;
1116 break;
1117 case PP_OD_FEATURE_UCLK_FMAX:
1118 od_min_setting = overdrive_lowerlimits->UclkFmax;
1119 od_max_setting = overdrive_upperlimits->UclkFmax;
1120 break;
1121 case PP_OD_FEATURE_GFX_VF_CURVE:
1122 od_min_setting = overdrive_lowerlimits->VoltageOffsetPerZoneBoundary;
1123 od_max_setting = overdrive_upperlimits->VoltageOffsetPerZoneBoundary;
1124 break;
1125 case PP_OD_FEATURE_FAN_CURVE_TEMP:
1126 od_min_setting = overdrive_lowerlimits->FanLinearTempPoints;
1127 od_max_setting = overdrive_upperlimits->FanLinearTempPoints;
1128 break;
1129 case PP_OD_FEATURE_FAN_CURVE_PWM:
1130 od_min_setting = overdrive_lowerlimits->FanLinearPwmPoints;
1131 od_max_setting = overdrive_upperlimits->FanLinearPwmPoints;
1132 break;
1133 case PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT:
1134 od_min_setting = overdrive_lowerlimits->AcousticLimitRpmThreshold;
1135 od_max_setting = overdrive_upperlimits->AcousticLimitRpmThreshold;
1136 break;
1137 case PP_OD_FEATURE_FAN_ACOUSTIC_TARGET:
1138 od_min_setting = overdrive_lowerlimits->AcousticTargetRpmThreshold;
1139 od_max_setting = overdrive_upperlimits->AcousticTargetRpmThreshold;
1140 break;
1141 case PP_OD_FEATURE_FAN_TARGET_TEMPERATURE:
1142 od_min_setting = overdrive_lowerlimits->FanTargetTemperature;
1143 od_max_setting = overdrive_upperlimits->FanTargetTemperature;
1144 break;
1145 case PP_OD_FEATURE_FAN_MINIMUM_PWM:
1146 od_min_setting = overdrive_lowerlimits->FanMinimumPwm;
1147 od_max_setting = overdrive_upperlimits->FanMinimumPwm;
1148 break;
1149 case PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE:
1150 od_min_setting = overdrive_lowerlimits->FanZeroRpmEnable;
1151 od_max_setting = overdrive_upperlimits->FanZeroRpmEnable;
1152 break;
1153 case PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP:
1154 od_min_setting = overdrive_lowerlimits->FanZeroRpmStopTemp;
1155 od_max_setting = overdrive_upperlimits->FanZeroRpmStopTemp;
1156 break;
1157 default:
1158 od_min_setting = od_max_setting = INT_MAX;
1159 break;
1160 }
1161
1162 if (min)
1163 *min = od_min_setting;
1164 if (max)
1165 *max = od_max_setting;
1166 }
1167
smu_v13_0_7_dump_od_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)1168 static void smu_v13_0_7_dump_od_table(struct smu_context *smu,
1169 OverDriveTableExternal_t *od_table)
1170 {
1171 struct amdgpu_device *adev = smu->adev;
1172
1173 dev_dbg(adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->OverDriveTable.GfxclkFmin,
1174 od_table->OverDriveTable.GfxclkFmax);
1175 dev_dbg(adev->dev, "OD: Uclk: (%d, %d)\n", od_table->OverDriveTable.UclkFmin,
1176 od_table->OverDriveTable.UclkFmax);
1177 }
1178
smu_v13_0_7_get_overdrive_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)1179 static int smu_v13_0_7_get_overdrive_table(struct smu_context *smu,
1180 OverDriveTableExternal_t *od_table)
1181 {
1182 int ret = 0;
1183
1184 ret = smu_cmn_update_table(smu,
1185 SMU_TABLE_OVERDRIVE,
1186 0,
1187 (void *)od_table,
1188 false);
1189 if (ret)
1190 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
1191
1192 return ret;
1193 }
1194
smu_v13_0_7_upload_overdrive_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)1195 static int smu_v13_0_7_upload_overdrive_table(struct smu_context *smu,
1196 OverDriveTableExternal_t *od_table)
1197 {
1198 int ret = 0;
1199
1200 ret = smu_cmn_update_table(smu,
1201 SMU_TABLE_OVERDRIVE,
1202 0,
1203 (void *)od_table,
1204 true);
1205 if (ret)
1206 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
1207
1208 return ret;
1209 }
1210
smu_v13_0_7_emit_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf,int * offset)1211 static int smu_v13_0_7_emit_clk_levels(struct smu_context *smu,
1212 enum smu_clk_type clk_type, char *buf,
1213 int *offset)
1214 {
1215 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1216 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1217 OverDriveTableExternal_t *od_table =
1218 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
1219 int i, curr_freq, size = *offset, start_offset = *offset;
1220 struct smu_dpm_table *single_dpm_table = NULL;
1221 struct smu_pcie_table *pcie_table;
1222 uint32_t gen_speed, lane_width;
1223 int32_t min_value, max_value;
1224 int ret = 0;
1225
1226 if (amdgpu_ras_intr_triggered()) {
1227 sysfs_emit_at(buf, size, "unavailable\n");
1228 return -EBUSY;
1229 }
1230
1231 switch (clk_type) {
1232 case SMU_SCLK:
1233 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1234 break;
1235 case SMU_MCLK:
1236 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1237 break;
1238 case SMU_SOCCLK:
1239 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1240 break;
1241 case SMU_FCLK:
1242 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1243 break;
1244 case SMU_VCLK:
1245 case SMU_VCLK1:
1246 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1247 break;
1248 case SMU_DCLK:
1249 case SMU_DCLK1:
1250 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1251 break;
1252 case SMU_DCEFCLK:
1253 single_dpm_table = &(dpm_context->dpm_tables.dcef_table);
1254 break;
1255 case SMU_PCIE:
1256 ret = smu_v13_0_7_get_smu_metrics_data(smu,
1257 METRICS_PCIE_RATE,
1258 &gen_speed);
1259 if (ret)
1260 return ret;
1261
1262 ret = smu_v13_0_7_get_smu_metrics_data(smu,
1263 METRICS_PCIE_WIDTH,
1264 &lane_width);
1265 if (ret)
1266 return ret;
1267
1268 pcie_table = &(dpm_context->dpm_tables.pcie_table);
1269 return smu_cmn_print_pcie_levels(smu, pcie_table,
1270 SMU_DPM_PCIE_GEN_IDX(gen_speed),
1271 SMU_DPM_PCIE_WIDTH_IDX(lane_width),
1272 buf, offset);
1273 case SMU_OD_SCLK:
1274 if (!smu_v13_0_7_is_od_feature_supported(smu,
1275 PP_OD_FEATURE_GFXCLK_BIT))
1276 break;
1277
1278 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1279 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1280 od_table->OverDriveTable.GfxclkFmin,
1281 od_table->OverDriveTable.GfxclkFmax);
1282 break;
1283
1284 case SMU_OD_MCLK:
1285 if (!smu_v13_0_7_is_od_feature_supported(smu,
1286 PP_OD_FEATURE_UCLK_BIT))
1287 break;
1288
1289 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1290 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n",
1291 od_table->OverDriveTable.UclkFmin,
1292 od_table->OverDriveTable.UclkFmax);
1293 break;
1294
1295 case SMU_OD_VDDGFX_OFFSET:
1296 if (!smu_v13_0_7_is_od_feature_supported(smu,
1297 PP_OD_FEATURE_GFX_VF_CURVE_BIT))
1298 break;
1299
1300 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1301 size += sysfs_emit_at(buf, size, "%dmV\n",
1302 od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[0]);
1303 break;
1304
1305 case SMU_OD_FAN_CURVE:
1306 if (!smu_v13_0_7_is_od_feature_supported(smu,
1307 PP_OD_FEATURE_FAN_CURVE_BIT))
1308 break;
1309
1310 size += sysfs_emit_at(buf, size, "OD_FAN_CURVE:\n");
1311 for (i = 0; i < NUM_OD_FAN_MAX_POINTS - 1; i++)
1312 size += sysfs_emit_at(buf, size, "%d: %dC %d%%\n",
1313 i,
1314 (int)od_table->OverDriveTable.FanLinearTempPoints[i],
1315 (int)od_table->OverDriveTable.FanLinearPwmPoints[i]);
1316
1317 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1318 smu_v13_0_7_get_od_setting_limits(smu,
1319 PP_OD_FEATURE_FAN_CURVE_TEMP,
1320 &min_value,
1321 &max_value);
1322 size += sysfs_emit_at(buf, size, "FAN_CURVE(hotspot temp): %uC %uC\n",
1323 min_value, max_value);
1324
1325 smu_v13_0_7_get_od_setting_limits(smu,
1326 PP_OD_FEATURE_FAN_CURVE_PWM,
1327 &min_value,
1328 &max_value);
1329 size += sysfs_emit_at(buf, size, "FAN_CURVE(fan speed): %u%% %u%%\n",
1330 min_value, max_value);
1331
1332 break;
1333
1334 case SMU_OD_ACOUSTIC_LIMIT:
1335 if (!smu_v13_0_7_is_od_feature_supported(smu,
1336 PP_OD_FEATURE_FAN_CURVE_BIT))
1337 break;
1338
1339 size += sysfs_emit_at(buf, size, "OD_ACOUSTIC_LIMIT:\n");
1340 size += sysfs_emit_at(buf, size, "%d\n",
1341 (int)od_table->OverDriveTable.AcousticLimitRpmThreshold);
1342
1343 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1344 smu_v13_0_7_get_od_setting_limits(smu,
1345 PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT,
1346 &min_value,
1347 &max_value);
1348 size += sysfs_emit_at(buf, size, "ACOUSTIC_LIMIT: %u %u\n",
1349 min_value, max_value);
1350 break;
1351
1352 case SMU_OD_ACOUSTIC_TARGET:
1353 if (!smu_v13_0_7_is_od_feature_supported(smu,
1354 PP_OD_FEATURE_FAN_CURVE_BIT))
1355 break;
1356
1357 size += sysfs_emit_at(buf, size, "OD_ACOUSTIC_TARGET:\n");
1358 size += sysfs_emit_at(buf, size, "%d\n",
1359 (int)od_table->OverDriveTable.AcousticTargetRpmThreshold);
1360
1361 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1362 smu_v13_0_7_get_od_setting_limits(smu,
1363 PP_OD_FEATURE_FAN_ACOUSTIC_TARGET,
1364 &min_value,
1365 &max_value);
1366 size += sysfs_emit_at(buf, size, "ACOUSTIC_TARGET: %u %u\n",
1367 min_value, max_value);
1368 break;
1369
1370 case SMU_OD_FAN_TARGET_TEMPERATURE:
1371 if (!smu_v13_0_7_is_od_feature_supported(smu,
1372 PP_OD_FEATURE_FAN_CURVE_BIT))
1373 break;
1374
1375 size += sysfs_emit_at(buf, size, "FAN_TARGET_TEMPERATURE:\n");
1376 size += sysfs_emit_at(buf, size, "%d\n",
1377 (int)od_table->OverDriveTable.FanTargetTemperature);
1378
1379 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1380 smu_v13_0_7_get_od_setting_limits(smu,
1381 PP_OD_FEATURE_FAN_TARGET_TEMPERATURE,
1382 &min_value,
1383 &max_value);
1384 size += sysfs_emit_at(buf, size, "TARGET_TEMPERATURE: %u %u\n",
1385 min_value, max_value);
1386 break;
1387
1388 case SMU_OD_FAN_MINIMUM_PWM:
1389 if (!smu_v13_0_7_is_od_feature_supported(smu,
1390 PP_OD_FEATURE_FAN_CURVE_BIT))
1391 break;
1392
1393 size += sysfs_emit_at(buf, size, "FAN_MINIMUM_PWM:\n");
1394 size += sysfs_emit_at(buf, size, "%d\n",
1395 (int)od_table->OverDriveTable.FanMinimumPwm);
1396
1397 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1398 smu_v13_0_7_get_od_setting_limits(smu,
1399 PP_OD_FEATURE_FAN_MINIMUM_PWM,
1400 &min_value,
1401 &max_value);
1402 size += sysfs_emit_at(buf, size, "MINIMUM_PWM: %u %u\n",
1403 min_value, max_value);
1404 break;
1405
1406 case SMU_OD_FAN_ZERO_RPM_ENABLE:
1407 if (!smu_v13_0_7_is_od_feature_supported(smu,
1408 PP_OD_FEATURE_ZERO_FAN_BIT))
1409 break;
1410
1411 size += sysfs_emit_at(buf, size, "FAN_ZERO_RPM_ENABLE:\n");
1412 size += sysfs_emit_at(buf, size, "%d\n",
1413 (int)od_table->OverDriveTable.FanZeroRpmEnable);
1414
1415 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1416 smu_v13_0_7_get_od_setting_limits(smu,
1417 PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE,
1418 &min_value,
1419 &max_value);
1420 size += sysfs_emit_at(buf, size, "ZERO_RPM_ENABLE: %u %u\n",
1421 min_value, max_value);
1422 break;
1423
1424 case SMU_OD_FAN_ZERO_RPM_STOP_TEMP:
1425 if (!smu_v13_0_7_is_od_feature_supported(smu,
1426 PP_OD_FEATURE_ZERO_FAN_BIT))
1427 break;
1428
1429 size += sysfs_emit_at(buf, size, "FAN_ZERO_RPM_STOP_TEMPERATURE:\n");
1430 size += sysfs_emit_at(buf, size, "%d\n",
1431 (int)od_table->OverDriveTable.FanZeroRpmStopTemp);
1432
1433 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1434 smu_v13_0_7_get_od_setting_limits(smu,
1435 PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP,
1436 &min_value,
1437 &max_value);
1438 size += sysfs_emit_at(buf, size, "ZERO_RPM_STOP_TEMPERATURE: %u %u\n",
1439 min_value, max_value);
1440 break;
1441
1442 case SMU_OD_RANGE:
1443 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT) &&
1444 !smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT) &&
1445 !smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT))
1446 break;
1447
1448 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1449
1450 if (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
1451 smu_v13_0_7_get_od_setting_limits(smu,
1452 PP_OD_FEATURE_GFXCLK_FMIN,
1453 &min_value,
1454 NULL);
1455 smu_v13_0_7_get_od_setting_limits(smu,
1456 PP_OD_FEATURE_GFXCLK_FMAX,
1457 NULL,
1458 &max_value);
1459 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1460 min_value, max_value);
1461 }
1462
1463 if (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {
1464 smu_v13_0_7_get_od_setting_limits(smu,
1465 PP_OD_FEATURE_UCLK_FMIN,
1466 &min_value,
1467 NULL);
1468 smu_v13_0_7_get_od_setting_limits(smu,
1469 PP_OD_FEATURE_UCLK_FMAX,
1470 NULL,
1471 &max_value);
1472 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1473 min_value, max_value);
1474 }
1475
1476 if (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
1477 smu_v13_0_7_get_od_setting_limits(smu,
1478 PP_OD_FEATURE_GFX_VF_CURVE,
1479 &min_value,
1480 &max_value);
1481 size += sysfs_emit_at(buf, size, "VDDGFX_OFFSET: %7dmv %10dmv\n",
1482 min_value, max_value);
1483 }
1484 break;
1485
1486 default:
1487 break;
1488 }
1489
1490 if (single_dpm_table) {
1491 ret = smu_v13_0_7_get_current_clk_freq_by_table(smu, clk_type,
1492 &curr_freq);
1493 if (ret) {
1494 dev_err(smu->adev->dev,
1495 "Failed to get current clock freq!");
1496 return ret;
1497 }
1498 return smu_cmn_print_dpm_clk_levels(smu, single_dpm_table,
1499 curr_freq, buf, offset);
1500 }
1501
1502 *offset += size - start_offset;
1503
1504 return 0;
1505 }
1506
smu_v13_0_7_od_restore_table_single(struct smu_context * smu,long input)1507 static int smu_v13_0_7_od_restore_table_single(struct smu_context *smu, long input)
1508 {
1509 struct smu_table_context *table_context = &smu->smu_table;
1510 OverDriveTableExternal_t *boot_overdrive_table =
1511 (OverDriveTableExternal_t *)table_context->boot_overdrive_table;
1512 OverDriveTableExternal_t *od_table =
1513 (OverDriveTableExternal_t *)table_context->overdrive_table;
1514 struct amdgpu_device *adev = smu->adev;
1515 int i;
1516
1517 switch (input) {
1518 case PP_OD_EDIT_FAN_CURVE:
1519 for (i = 0; i < NUM_OD_FAN_MAX_POINTS; i++) {
1520 od_table->OverDriveTable.FanLinearTempPoints[i] =
1521 boot_overdrive_table->OverDriveTable.FanLinearTempPoints[i];
1522 od_table->OverDriveTable.FanLinearPwmPoints[i] =
1523 boot_overdrive_table->OverDriveTable.FanLinearPwmPoints[i];
1524 }
1525 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1526 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1527 break;
1528 case PP_OD_EDIT_ACOUSTIC_LIMIT:
1529 od_table->OverDriveTable.AcousticLimitRpmThreshold =
1530 boot_overdrive_table->OverDriveTable.AcousticLimitRpmThreshold;
1531 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1532 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1533 break;
1534 case PP_OD_EDIT_ACOUSTIC_TARGET:
1535 od_table->OverDriveTable.AcousticTargetRpmThreshold =
1536 boot_overdrive_table->OverDriveTable.AcousticTargetRpmThreshold;
1537 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1538 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1539 break;
1540 case PP_OD_EDIT_FAN_TARGET_TEMPERATURE:
1541 od_table->OverDriveTable.FanTargetTemperature =
1542 boot_overdrive_table->OverDriveTable.FanTargetTemperature;
1543 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1544 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1545 break;
1546 case PP_OD_EDIT_FAN_MINIMUM_PWM:
1547 od_table->OverDriveTable.FanMinimumPwm =
1548 boot_overdrive_table->OverDriveTable.FanMinimumPwm;
1549 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1550 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1551 break;
1552 case PP_OD_EDIT_FAN_ZERO_RPM_ENABLE:
1553 od_table->OverDriveTable.FanZeroRpmEnable =
1554 boot_overdrive_table->OverDriveTable.FanZeroRpmEnable;
1555 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1556 break;
1557 case PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP:
1558 od_table->OverDriveTable.FanZeroRpmStopTemp =
1559 boot_overdrive_table->OverDriveTable.FanZeroRpmStopTemp;
1560 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1561 break;
1562 default:
1563 dev_info(adev->dev, "Invalid table index: %ld\n", input);
1564 return -EINVAL;
1565 }
1566
1567 return 0;
1568 }
1569
smu_v13_0_7_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)1570 static int smu_v13_0_7_od_edit_dpm_table(struct smu_context *smu,
1571 enum PP_OD_DPM_TABLE_COMMAND type,
1572 long input[],
1573 uint32_t size)
1574 {
1575 struct smu_table_context *table_context = &smu->smu_table;
1576 OverDriveTableExternal_t *od_table =
1577 (OverDriveTableExternal_t *)table_context->overdrive_table;
1578 struct amdgpu_device *adev = smu->adev;
1579 uint32_t offset_of_voltageoffset;
1580 int32_t minimum, maximum;
1581 uint32_t feature_ctrlmask;
1582 int i, ret = 0;
1583
1584 switch (type) {
1585 case PP_OD_EDIT_SCLK_VDDC_TABLE:
1586 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
1587 dev_warn(adev->dev, "GFXCLK_LIMITS setting not supported!\n");
1588 return -ENOTSUPP;
1589 }
1590
1591 for (i = 0; i < size; i += 2) {
1592 if (i + 2 > size) {
1593 dev_info(adev->dev, "invalid number of input parameters %d\n", size);
1594 return -EINVAL;
1595 }
1596
1597 switch (input[i]) {
1598 case 0:
1599 smu_v13_0_7_get_od_setting_limits(smu,
1600 PP_OD_FEATURE_GFXCLK_FMIN,
1601 &minimum,
1602 &maximum);
1603 if (input[i + 1] < minimum ||
1604 input[i + 1] > maximum) {
1605 dev_info(adev->dev, "GfxclkFmin (%ld) must be within [%u, %u]!\n",
1606 input[i + 1], minimum, maximum);
1607 return -EINVAL;
1608 }
1609
1610 od_table->OverDriveTable.GfxclkFmin = input[i + 1];
1611 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT;
1612 break;
1613
1614 case 1:
1615 smu_v13_0_7_get_od_setting_limits(smu,
1616 PP_OD_FEATURE_GFXCLK_FMAX,
1617 &minimum,
1618 &maximum);
1619 if (input[i + 1] < minimum ||
1620 input[i + 1] > maximum) {
1621 dev_info(adev->dev, "GfxclkFmax (%ld) must be within [%u, %u]!\n",
1622 input[i + 1], minimum, maximum);
1623 return -EINVAL;
1624 }
1625
1626 od_table->OverDriveTable.GfxclkFmax = input[i + 1];
1627 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT;
1628 break;
1629
1630 default:
1631 dev_info(adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
1632 dev_info(adev->dev, "Supported indices: [0:min,1:max]\n");
1633 return -EINVAL;
1634 }
1635 }
1636
1637 if (od_table->OverDriveTable.GfxclkFmin > od_table->OverDriveTable.GfxclkFmax) {
1638 dev_err(adev->dev,
1639 "Invalid setting: GfxclkFmin(%u) is bigger than GfxclkFmax(%u)\n",
1640 (uint32_t)od_table->OverDriveTable.GfxclkFmin,
1641 (uint32_t)od_table->OverDriveTable.GfxclkFmax);
1642 return -EINVAL;
1643 }
1644 break;
1645
1646 case PP_OD_EDIT_MCLK_VDDC_TABLE:
1647 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {
1648 dev_warn(adev->dev, "UCLK_LIMITS setting not supported!\n");
1649 return -ENOTSUPP;
1650 }
1651
1652 for (i = 0; i < size; i += 2) {
1653 if (i + 2 > size) {
1654 dev_info(adev->dev, "invalid number of input parameters %d\n", size);
1655 return -EINVAL;
1656 }
1657
1658 switch (input[i]) {
1659 case 0:
1660 smu_v13_0_7_get_od_setting_limits(smu,
1661 PP_OD_FEATURE_UCLK_FMIN,
1662 &minimum,
1663 &maximum);
1664 if (input[i + 1] < minimum ||
1665 input[i + 1] > maximum) {
1666 dev_info(adev->dev, "UclkFmin (%ld) must be within [%u, %u]!\n",
1667 input[i + 1], minimum, maximum);
1668 return -EINVAL;
1669 }
1670
1671 od_table->OverDriveTable.UclkFmin = input[i + 1];
1672 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT;
1673 break;
1674
1675 case 1:
1676 smu_v13_0_7_get_od_setting_limits(smu,
1677 PP_OD_FEATURE_UCLK_FMAX,
1678 &minimum,
1679 &maximum);
1680 if (input[i + 1] < minimum ||
1681 input[i + 1] > maximum) {
1682 dev_info(adev->dev, "UclkFmax (%ld) must be within [%u, %u]!\n",
1683 input[i + 1], minimum, maximum);
1684 return -EINVAL;
1685 }
1686
1687 od_table->OverDriveTable.UclkFmax = input[i + 1];
1688 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT;
1689 break;
1690
1691 default:
1692 dev_info(adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
1693 dev_info(adev->dev, "Supported indices: [0:min,1:max]\n");
1694 return -EINVAL;
1695 }
1696 }
1697
1698 if (od_table->OverDriveTable.UclkFmin > od_table->OverDriveTable.UclkFmax) {
1699 dev_err(adev->dev,
1700 "Invalid setting: UclkFmin(%u) is bigger than UclkFmax(%u)\n",
1701 (uint32_t)od_table->OverDriveTable.UclkFmin,
1702 (uint32_t)od_table->OverDriveTable.UclkFmax);
1703 return -EINVAL;
1704 }
1705 break;
1706
1707 case PP_OD_EDIT_VDDGFX_OFFSET:
1708 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
1709 dev_warn(adev->dev, "Gfx offset setting not supported!\n");
1710 return -ENOTSUPP;
1711 }
1712
1713 smu_v13_0_7_get_od_setting_limits(smu,
1714 PP_OD_FEATURE_GFX_VF_CURVE,
1715 &minimum,
1716 &maximum);
1717 if (input[0] < minimum ||
1718 input[0] > maximum) {
1719 dev_info(adev->dev, "Voltage offset (%ld) must be within [%d, %d]!\n",
1720 input[0], minimum, maximum);
1721 return -EINVAL;
1722 }
1723
1724 for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++)
1725 od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i] = input[0];
1726 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT);
1727 break;
1728
1729 case PP_OD_EDIT_FAN_CURVE:
1730 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1731 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1732 return -ENOTSUPP;
1733 }
1734
1735 if (input[0] >= NUM_OD_FAN_MAX_POINTS - 1 ||
1736 input[0] < 0)
1737 return -EINVAL;
1738
1739 smu_v13_0_7_get_od_setting_limits(smu,
1740 PP_OD_FEATURE_FAN_CURVE_TEMP,
1741 &minimum,
1742 &maximum);
1743 if (input[1] < minimum ||
1744 input[1] > maximum) {
1745 dev_info(adev->dev, "Fan curve temp setting(%ld) must be within [%d, %d]!\n",
1746 input[1], minimum, maximum);
1747 return -EINVAL;
1748 }
1749
1750 smu_v13_0_7_get_od_setting_limits(smu,
1751 PP_OD_FEATURE_FAN_CURVE_PWM,
1752 &minimum,
1753 &maximum);
1754 if (input[2] < minimum ||
1755 input[2] > maximum) {
1756 dev_info(adev->dev, "Fan curve pwm setting(%ld) must be within [%d, %d]!\n",
1757 input[2], minimum, maximum);
1758 return -EINVAL;
1759 }
1760
1761 od_table->OverDriveTable.FanLinearTempPoints[input[0]] = input[1];
1762 od_table->OverDriveTable.FanLinearPwmPoints[input[0]] = input[2];
1763 od_table->OverDriveTable.FanMode = FAN_MODE_MANUAL_LINEAR;
1764 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1765 break;
1766
1767 case PP_OD_EDIT_ACOUSTIC_LIMIT:
1768 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1769 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1770 return -ENOTSUPP;
1771 }
1772
1773 smu_v13_0_7_get_od_setting_limits(smu,
1774 PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT,
1775 &minimum,
1776 &maximum);
1777 if (input[0] < minimum ||
1778 input[0] > maximum) {
1779 dev_info(adev->dev, "acoustic limit threshold setting(%ld) must be within [%d, %d]!\n",
1780 input[0], minimum, maximum);
1781 return -EINVAL;
1782 }
1783
1784 od_table->OverDriveTable.AcousticLimitRpmThreshold = input[0];
1785 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1786 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1787 break;
1788
1789 case PP_OD_EDIT_ACOUSTIC_TARGET:
1790 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1791 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1792 return -ENOTSUPP;
1793 }
1794
1795 smu_v13_0_7_get_od_setting_limits(smu,
1796 PP_OD_FEATURE_FAN_ACOUSTIC_TARGET,
1797 &minimum,
1798 &maximum);
1799 if (input[0] < minimum ||
1800 input[0] > maximum) {
1801 dev_info(adev->dev, "acoustic target threshold setting(%ld) must be within [%d, %d]!\n",
1802 input[0], minimum, maximum);
1803 return -EINVAL;
1804 }
1805
1806 od_table->OverDriveTable.AcousticTargetRpmThreshold = input[0];
1807 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1808 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1809 break;
1810
1811 case PP_OD_EDIT_FAN_TARGET_TEMPERATURE:
1812 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1813 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1814 return -ENOTSUPP;
1815 }
1816
1817 smu_v13_0_7_get_od_setting_limits(smu,
1818 PP_OD_FEATURE_FAN_TARGET_TEMPERATURE,
1819 &minimum,
1820 &maximum);
1821 if (input[0] < minimum ||
1822 input[0] > maximum) {
1823 dev_info(adev->dev, "fan target temperature setting(%ld) must be within [%d, %d]!\n",
1824 input[0], minimum, maximum);
1825 return -EINVAL;
1826 }
1827
1828 od_table->OverDriveTable.FanTargetTemperature = input[0];
1829 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1830 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1831 break;
1832
1833 case PP_OD_EDIT_FAN_MINIMUM_PWM:
1834 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1835 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1836 return -ENOTSUPP;
1837 }
1838
1839 smu_v13_0_7_get_od_setting_limits(smu,
1840 PP_OD_FEATURE_FAN_MINIMUM_PWM,
1841 &minimum,
1842 &maximum);
1843 if (input[0] < minimum ||
1844 input[0] > maximum) {
1845 dev_info(adev->dev, "fan minimum pwm setting(%ld) must be within [%d, %d]!\n",
1846 input[0], minimum, maximum);
1847 return -EINVAL;
1848 }
1849
1850 od_table->OverDriveTable.FanMinimumPwm = input[0];
1851 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1852 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1853 break;
1854
1855 case PP_OD_EDIT_FAN_ZERO_RPM_ENABLE:
1856 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_ZERO_FAN_BIT)) {
1857 dev_warn(adev->dev, "Zero RPM setting not supported!\n");
1858 return -ENOTSUPP;
1859 }
1860
1861 smu_v13_0_7_get_od_setting_limits(smu,
1862 PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE,
1863 &minimum,
1864 &maximum);
1865 if (input[0] < minimum ||
1866 input[0] > maximum) {
1867 dev_info(adev->dev, "zero RPM enable setting(%ld) must be within [%d, %d]!\n",
1868 input[0], minimum, maximum);
1869 return -EINVAL;
1870 }
1871
1872 od_table->OverDriveTable.FanZeroRpmEnable = input[0];
1873 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1874 break;
1875
1876 case PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP:
1877 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_ZERO_FAN_BIT)) {
1878 dev_warn(adev->dev, "Zero RPM setting not supported!\n");
1879 return -ENOTSUPP;
1880 }
1881
1882 smu_v13_0_7_get_od_setting_limits(smu,
1883 PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP,
1884 &minimum,
1885 &maximum);
1886 if (input[0] < minimum ||
1887 input[0] > maximum) {
1888 dev_info(adev->dev, "zero RPM stop temperature setting(%ld) must be within [%d, %d]!\n",
1889 input[0], minimum, maximum);
1890 return -EINVAL;
1891 }
1892
1893 od_table->OverDriveTable.FanZeroRpmStopTemp = input[0];
1894 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1895 break;
1896
1897 case PP_OD_RESTORE_DEFAULT_TABLE:
1898 if (size == 1) {
1899 ret = smu_v13_0_7_od_restore_table_single(smu, input[0]);
1900 if (ret)
1901 return ret;
1902 } else {
1903 feature_ctrlmask = od_table->OverDriveTable.FeatureCtrlMask;
1904 memcpy(od_table,
1905 table_context->boot_overdrive_table,
1906 sizeof(OverDriveTableExternal_t));
1907 od_table->OverDriveTable.FeatureCtrlMask = feature_ctrlmask;
1908 }
1909 fallthrough;
1910
1911 case PP_OD_COMMIT_DPM_TABLE:
1912 /*
1913 * The member below instructs PMFW the settings focused in
1914 * this single operation.
1915 * `uint32_t FeatureCtrlMask;`
1916 * It does not contain actual informations about user's custom
1917 * settings. Thus we do not cache it.
1918 */
1919 offset_of_voltageoffset = offsetof(OverDriveTable_t, VoltageOffsetPerZoneBoundary);
1920 if (memcmp((u8 *)od_table + offset_of_voltageoffset,
1921 table_context->user_overdrive_table + offset_of_voltageoffset,
1922 sizeof(OverDriveTableExternal_t) - offset_of_voltageoffset)) {
1923 smu_v13_0_7_dump_od_table(smu, od_table);
1924
1925 ret = smu_v13_0_7_upload_overdrive_table(smu, od_table);
1926 if (ret) {
1927 dev_err(adev->dev, "Failed to upload overdrive table!\n");
1928 return ret;
1929 }
1930
1931 od_table->OverDriveTable.FeatureCtrlMask = 0;
1932 memcpy(table_context->user_overdrive_table + offset_of_voltageoffset,
1933 (u8 *)od_table + offset_of_voltageoffset,
1934 sizeof(OverDriveTableExternal_t) - offset_of_voltageoffset);
1935
1936 if (!memcmp(table_context->user_overdrive_table,
1937 table_context->boot_overdrive_table,
1938 sizeof(OverDriveTableExternal_t)))
1939 smu->user_dpm_profile.user_od = false;
1940 else
1941 smu->user_dpm_profile.user_od = true;
1942 }
1943 break;
1944
1945 default:
1946 return -ENOSYS;
1947 }
1948
1949 return ret;
1950 }
1951
smu_v13_0_7_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1952 static int smu_v13_0_7_force_clk_levels(struct smu_context *smu,
1953 enum smu_clk_type clk_type,
1954 uint32_t mask)
1955 {
1956 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1957 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1958 struct smu_dpm_table *single_dpm_table;
1959 uint32_t soft_min_level, soft_max_level;
1960 uint32_t min_freq, max_freq;
1961 int ret = 0;
1962
1963 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1964 soft_max_level = mask ? (fls(mask) - 1) : 0;
1965
1966 switch (clk_type) {
1967 case SMU_GFXCLK:
1968 case SMU_SCLK:
1969 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1970 break;
1971 case SMU_MCLK:
1972 case SMU_UCLK:
1973 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1974 break;
1975 case SMU_SOCCLK:
1976 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1977 break;
1978 case SMU_FCLK:
1979 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1980 break;
1981 case SMU_VCLK:
1982 case SMU_VCLK1:
1983 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1984 break;
1985 case SMU_DCLK:
1986 case SMU_DCLK1:
1987 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1988 break;
1989 default:
1990 break;
1991 }
1992
1993 switch (clk_type) {
1994 case SMU_GFXCLK:
1995 case SMU_SCLK:
1996 case SMU_MCLK:
1997 case SMU_UCLK:
1998 case SMU_SOCCLK:
1999 case SMU_FCLK:
2000 case SMU_VCLK:
2001 case SMU_VCLK1:
2002 case SMU_DCLK:
2003 case SMU_DCLK1:
2004 if (single_dpm_table->flags & SMU_DPM_TABLE_FINE_GRAINED) {
2005 /* There is only 2 levels for fine grained DPM */
2006 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
2007 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
2008 } else {
2009 if ((soft_max_level >= single_dpm_table->count) ||
2010 (soft_min_level >= single_dpm_table->count))
2011 return -EINVAL;
2012 }
2013
2014 min_freq = single_dpm_table->dpm_levels[soft_min_level].value;
2015 max_freq = single_dpm_table->dpm_levels[soft_max_level].value;
2016
2017 ret = smu_v13_0_set_soft_freq_limited_range(smu,
2018 clk_type,
2019 min_freq,
2020 max_freq,
2021 false);
2022 break;
2023 case SMU_DCEFCLK:
2024 case SMU_PCIE:
2025 default:
2026 break;
2027 }
2028
2029 return ret;
2030 }
2031
2032 static const struct smu_temperature_range smu13_thermal_policy[] = {
2033 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
2034 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
2035 };
2036
smu_v13_0_7_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)2037 static int smu_v13_0_7_get_thermal_temperature_range(struct smu_context *smu,
2038 struct smu_temperature_range *range)
2039 {
2040 struct smu_table_context *table_context = &smu->smu_table;
2041 struct smu_13_0_7_powerplay_table *powerplay_table =
2042 table_context->power_play_table;
2043 PPTable_t *pptable = smu->smu_table.driver_pptable;
2044
2045 if (!range)
2046 return -EINVAL;
2047
2048 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range));
2049
2050 range->max = pptable->SkuTable.TemperatureLimit[TEMP_EDGE] *
2051 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2052 range->edge_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
2053 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2054 range->hotspot_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] *
2055 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2056 range->hotspot_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) *
2057 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2058 range->mem_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_MEM] *
2059 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2060 range->mem_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
2061 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2062 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
2063 range->software_shutdown_temp_offset = pptable->SkuTable.FanAbnormalTempLimitOffset;
2064
2065 return 0;
2066 }
2067
smu_v13_0_7_get_gpu_metrics(struct smu_context * smu,void ** table)2068 static ssize_t smu_v13_0_7_get_gpu_metrics(struct smu_context *smu,
2069 void **table)
2070 {
2071 struct gpu_metrics_v1_3 *gpu_metrics =
2072 (struct gpu_metrics_v1_3 *)smu_driver_table_ptr(
2073 smu, SMU_DRIVER_TABLE_GPU_METRICS);
2074 SmuMetricsExternal_t metrics_ext;
2075 SmuMetrics_t *metrics = &metrics_ext.SmuMetrics;
2076 int ret = 0;
2077
2078 ret = smu_cmn_get_metrics_table(smu,
2079 &metrics_ext,
2080 true);
2081 if (ret)
2082 return ret;
2083
2084 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2085
2086 gpu_metrics->temperature_edge = metrics->AvgTemperature[TEMP_EDGE];
2087 gpu_metrics->temperature_hotspot = metrics->AvgTemperature[TEMP_HOTSPOT];
2088 gpu_metrics->temperature_mem = metrics->AvgTemperature[TEMP_MEM];
2089 gpu_metrics->temperature_vrgfx = metrics->AvgTemperature[TEMP_VR_GFX];
2090 gpu_metrics->temperature_vrsoc = metrics->AvgTemperature[TEMP_VR_SOC];
2091 gpu_metrics->temperature_vrmem = max(metrics->AvgTemperature[TEMP_VR_MEM0],
2092 metrics->AvgTemperature[TEMP_VR_MEM1]);
2093
2094 gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity;
2095 gpu_metrics->average_umc_activity = smu_safe_u16_nn(metrics->AverageUclkActivity);
2096 gpu_metrics->average_mm_activity = max(metrics->Vcn0ActivityPercentage,
2097 metrics->Vcn1ActivityPercentage);
2098
2099 gpu_metrics->average_socket_power = metrics->AverageSocketPower;
2100 if (smu->smc_fw_version <= 0x00521400)
2101 gpu_metrics->energy_accumulator = metrics->EnergyAccumulator;
2102
2103 if (metrics->AverageGfxActivity <= SMU_13_0_7_BUSY_THRESHOLD)
2104 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs;
2105 else
2106 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs;
2107
2108 if (smu_safe_u16_nn(metrics->AverageUclkActivity) <= SMU_13_0_7_BUSY_THRESHOLD)
2109 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs;
2110 else
2111 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs;
2112
2113 gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency;
2114 gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency;
2115 gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency;
2116 gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency;
2117
2118 gpu_metrics->current_gfxclk = metrics->CurrClock[PPCLK_GFXCLK];
2119 gpu_metrics->current_socclk = metrics->CurrClock[PPCLK_SOCCLK];
2120 gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK];
2121 gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0];
2122 gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0];
2123 gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1];
2124 gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1];
2125
2126 gpu_metrics->throttle_status =
2127 smu_v13_0_7_get_throttler_status(metrics);
2128 gpu_metrics->indep_throttle_status =
2129 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
2130 smu_v13_0_7_throttler_map);
2131
2132 gpu_metrics->current_fan_speed = metrics->AvgFanRpm;
2133
2134 gpu_metrics->pcie_link_width = metrics->PcieWidth;
2135 if ((metrics->PcieRate - 1) > LINK_SPEED_MAX)
2136 gpu_metrics->pcie_link_speed = pcie_gen_to_speed(1);
2137 else
2138 gpu_metrics->pcie_link_speed = pcie_gen_to_speed(metrics->PcieRate);
2139
2140 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2141
2142 gpu_metrics->voltage_gfx = metrics->AvgVoltage[SVI_PLANE_GFX];
2143 gpu_metrics->voltage_soc = metrics->AvgVoltage[SVI_PLANE_SOC];
2144 gpu_metrics->voltage_mem = metrics->AvgVoltage[SVI_PLANE_VMEMP];
2145
2146 *table = (void *)gpu_metrics;
2147
2148 smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS);
2149
2150 return sizeof(struct gpu_metrics_v1_3);
2151 }
2152
smu_v13_0_7_set_supported_od_feature_mask(struct smu_context * smu)2153 static void smu_v13_0_7_set_supported_od_feature_mask(struct smu_context *smu)
2154 {
2155 struct amdgpu_device *adev = smu->adev;
2156
2157 if (smu_v13_0_7_is_od_feature_supported(smu,
2158 PP_OD_FEATURE_FAN_CURVE_BIT))
2159 adev->pm.od_feature_mask |= OD_OPS_SUPPORT_FAN_CURVE_RETRIEVE |
2160 OD_OPS_SUPPORT_FAN_CURVE_SET |
2161 OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_RETRIEVE |
2162 OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_SET |
2163 OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_RETRIEVE |
2164 OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_SET |
2165 OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE |
2166 OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET |
2167 OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE |
2168 OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET |
2169 OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_RETRIEVE |
2170 OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_SET |
2171 OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_RETRIEVE |
2172 OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_SET;
2173 }
2174
smu_v13_0_7_set_default_od_settings(struct smu_context * smu)2175 static int smu_v13_0_7_set_default_od_settings(struct smu_context *smu)
2176 {
2177 OverDriveTableExternal_t *od_table =
2178 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
2179 OverDriveTableExternal_t *boot_od_table =
2180 (OverDriveTableExternal_t *)smu->smu_table.boot_overdrive_table;
2181 OverDriveTableExternal_t *user_od_table =
2182 (OverDriveTableExternal_t *)smu->smu_table.user_overdrive_table;
2183 OverDriveTableExternal_t user_od_table_bak;
2184 int ret = 0;
2185 int i;
2186
2187 ret = smu_v13_0_7_get_overdrive_table(smu, boot_od_table);
2188 if (ret)
2189 return ret;
2190
2191 smu_v13_0_7_dump_od_table(smu, boot_od_table);
2192
2193 memcpy(od_table,
2194 boot_od_table,
2195 sizeof(OverDriveTableExternal_t));
2196
2197 /*
2198 * For S3/S4/Runpm resume, we need to setup those overdrive tables again,
2199 * but we have to preserve user defined values in "user_od_table".
2200 */
2201 if (!smu->adev->in_suspend) {
2202 memcpy(user_od_table,
2203 boot_od_table,
2204 sizeof(OverDriveTableExternal_t));
2205 smu->user_dpm_profile.user_od = false;
2206 } else if (smu->user_dpm_profile.user_od) {
2207 memcpy(&user_od_table_bak,
2208 user_od_table,
2209 sizeof(OverDriveTableExternal_t));
2210 memcpy(user_od_table,
2211 boot_od_table,
2212 sizeof(OverDriveTableExternal_t));
2213 user_od_table->OverDriveTable.GfxclkFmin =
2214 user_od_table_bak.OverDriveTable.GfxclkFmin;
2215 user_od_table->OverDriveTable.GfxclkFmax =
2216 user_od_table_bak.OverDriveTable.GfxclkFmax;
2217 user_od_table->OverDriveTable.UclkFmin =
2218 user_od_table_bak.OverDriveTable.UclkFmin;
2219 user_od_table->OverDriveTable.UclkFmax =
2220 user_od_table_bak.OverDriveTable.UclkFmax;
2221 for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++)
2222 user_od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i] =
2223 user_od_table_bak.OverDriveTable.VoltageOffsetPerZoneBoundary[i];
2224 for (i = 0; i < NUM_OD_FAN_MAX_POINTS - 1; i++) {
2225 user_od_table->OverDriveTable.FanLinearTempPoints[i] =
2226 user_od_table_bak.OverDriveTable.FanLinearTempPoints[i];
2227 user_od_table->OverDriveTable.FanLinearPwmPoints[i] =
2228 user_od_table_bak.OverDriveTable.FanLinearPwmPoints[i];
2229 }
2230 user_od_table->OverDriveTable.AcousticLimitRpmThreshold =
2231 user_od_table_bak.OverDriveTable.AcousticLimitRpmThreshold;
2232 user_od_table->OverDriveTable.AcousticTargetRpmThreshold =
2233 user_od_table_bak.OverDriveTable.AcousticTargetRpmThreshold;
2234 user_od_table->OverDriveTable.FanTargetTemperature =
2235 user_od_table_bak.OverDriveTable.FanTargetTemperature;
2236 user_od_table->OverDriveTable.FanMinimumPwm =
2237 user_od_table_bak.OverDriveTable.FanMinimumPwm;
2238 user_od_table->OverDriveTable.FanZeroRpmEnable =
2239 user_od_table_bak.OverDriveTable.FanZeroRpmEnable;
2240 user_od_table->OverDriveTable.FanZeroRpmStopTemp =
2241 user_od_table_bak.OverDriveTable.FanZeroRpmStopTemp;
2242 }
2243
2244 smu_v13_0_7_set_supported_od_feature_mask(smu);
2245
2246 return 0;
2247 }
2248
smu_v13_0_7_restore_user_od_settings(struct smu_context * smu)2249 static int smu_v13_0_7_restore_user_od_settings(struct smu_context *smu)
2250 {
2251 struct smu_table_context *table_context = &smu->smu_table;
2252 OverDriveTableExternal_t *od_table = table_context->overdrive_table;
2253 OverDriveTableExternal_t *user_od_table = table_context->user_overdrive_table;
2254 int res;
2255
2256 user_od_table->OverDriveTable.FeatureCtrlMask = BIT(PP_OD_FEATURE_GFXCLK_BIT) |
2257 BIT(PP_OD_FEATURE_UCLK_BIT) |
2258 BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT) |
2259 BIT(PP_OD_FEATURE_FAN_CURVE_BIT) |
2260 BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
2261 res = smu_v13_0_7_upload_overdrive_table(smu, user_od_table);
2262 user_od_table->OverDriveTable.FeatureCtrlMask = 0;
2263 if (res == 0)
2264 memcpy(od_table, user_od_table, sizeof(OverDriveTableExternal_t));
2265
2266 return res;
2267 }
2268
smu_v13_0_7_populate_umd_state_clk(struct smu_context * smu)2269 static int smu_v13_0_7_populate_umd_state_clk(struct smu_context *smu)
2270 {
2271 struct smu_13_0_dpm_context *dpm_context =
2272 smu->smu_dpm.dpm_context;
2273 struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table;
2274 struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table;
2275 struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table;
2276 struct smu_dpm_table *vclk_table = &dpm_context->dpm_tables.vclk_table;
2277 struct smu_dpm_table *dclk_table = &dpm_context->dpm_tables.dclk_table;
2278 struct smu_dpm_table *fclk_table = &dpm_context->dpm_tables.fclk_table;
2279 struct smu_umd_pstate_table *pstate_table =
2280 &smu->pstate_table;
2281 struct smu_table_context *table_context = &smu->smu_table;
2282 PPTable_t *pptable = table_context->driver_pptable;
2283 DriverReportedClocks_t driver_clocks =
2284 pptable->SkuTable.DriverReportedClocks;
2285
2286 pstate_table->gfxclk_pstate.min = SMU_DPM_TABLE_MIN(gfx_table);
2287 if (driver_clocks.GameClockAc &&
2288 (driver_clocks.GameClockAc < SMU_DPM_TABLE_MAX(gfx_table)))
2289 pstate_table->gfxclk_pstate.peak = driver_clocks.GameClockAc;
2290 else
2291 pstate_table->gfxclk_pstate.peak = SMU_DPM_TABLE_MAX(gfx_table);
2292
2293 pstate_table->uclk_pstate.min = SMU_DPM_TABLE_MIN(mem_table);
2294 pstate_table->uclk_pstate.peak = SMU_DPM_TABLE_MAX(mem_table);
2295
2296 pstate_table->socclk_pstate.min = SMU_DPM_TABLE_MIN(soc_table);
2297 pstate_table->socclk_pstate.peak = SMU_DPM_TABLE_MAX(soc_table);
2298
2299 pstate_table->vclk_pstate.min = SMU_DPM_TABLE_MIN(vclk_table);
2300 pstate_table->vclk_pstate.peak = SMU_DPM_TABLE_MAX(vclk_table);
2301
2302 pstate_table->dclk_pstate.min = SMU_DPM_TABLE_MIN(dclk_table);
2303 pstate_table->dclk_pstate.peak = SMU_DPM_TABLE_MAX(dclk_table);
2304
2305 pstate_table->fclk_pstate.min = SMU_DPM_TABLE_MIN(fclk_table);
2306 pstate_table->fclk_pstate.peak = SMU_DPM_TABLE_MAX(fclk_table);
2307
2308 if (driver_clocks.BaseClockAc &&
2309 driver_clocks.BaseClockAc < SMU_DPM_TABLE_MAX(gfx_table))
2310 pstate_table->gfxclk_pstate.standard = driver_clocks.BaseClockAc;
2311 else
2312 pstate_table->gfxclk_pstate.standard =
2313 SMU_DPM_TABLE_MAX(gfx_table);
2314 pstate_table->uclk_pstate.standard = SMU_DPM_TABLE_MAX(mem_table);
2315 pstate_table->socclk_pstate.standard = SMU_DPM_TABLE_MIN(soc_table);
2316 pstate_table->vclk_pstate.standard = SMU_DPM_TABLE_MIN(vclk_table);
2317 pstate_table->dclk_pstate.standard = SMU_DPM_TABLE_MIN(dclk_table);
2318 pstate_table->fclk_pstate.standard = SMU_DPM_TABLE_MIN(fclk_table);
2319
2320 return 0;
2321 }
2322
smu_v13_0_7_get_fan_speed_pwm(struct smu_context * smu,uint32_t * speed)2323 static int smu_v13_0_7_get_fan_speed_pwm(struct smu_context *smu,
2324 uint32_t *speed)
2325 {
2326 int ret;
2327
2328 if (!speed)
2329 return -EINVAL;
2330
2331 ret = smu_v13_0_7_get_smu_metrics_data(smu,
2332 METRICS_CURR_FANPWM,
2333 speed);
2334 if (ret) {
2335 dev_err(smu->adev->dev, "Failed to get fan speed(PWM)!");
2336 return ret;
2337 }
2338
2339 /* Convert the PMFW output which is in percent to pwm(255) based */
2340 *speed = min(*speed * 255 / 100, (uint32_t)255);
2341
2342 return 0;
2343 }
2344
smu_v13_0_7_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)2345 static int smu_v13_0_7_get_fan_speed_rpm(struct smu_context *smu,
2346 uint32_t *speed)
2347 {
2348 if (!speed)
2349 return -EINVAL;
2350
2351 return smu_v13_0_7_get_smu_metrics_data(smu,
2352 METRICS_CURR_FANSPEED,
2353 speed);
2354 }
2355
smu_v13_0_7_enable_mgpu_fan_boost(struct smu_context * smu)2356 static int smu_v13_0_7_enable_mgpu_fan_boost(struct smu_context *smu)
2357 {
2358 struct smu_table_context *table_context = &smu->smu_table;
2359 PPTable_t *pptable = table_context->driver_pptable;
2360 SkuTable_t *skutable = &pptable->SkuTable;
2361
2362 /*
2363 * Skip the MGpuFanBoost setting for those ASICs
2364 * which do not support it
2365 */
2366 if (skutable->MGpuAcousticLimitRpmThreshold == 0)
2367 return 0;
2368
2369 return smu_cmn_send_smc_msg_with_param(smu,
2370 SMU_MSG_SetMGpuFanBoostLimitRpm,
2371 0,
2372 NULL);
2373 }
2374
smu_v13_0_7_get_ppt_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t * ppt_limit)2375 static int smu_v13_0_7_get_ppt_limit(struct smu_context *smu,
2376 enum smu_ppt_limit_type limit_type,
2377 uint32_t *ppt_limit)
2378 {
2379 OverDriveTableExternal_t od_table;
2380 int ret;
2381
2382 if (limit_type != SMU_PPT_LIMIT_PPT0)
2383 return -EOPNOTSUPP;
2384
2385 ret = smu_v13_0_get_ppt_limit(smu, limit_type, ppt_limit);
2386 if (ret)
2387 return ret;
2388
2389 ret = smu_v13_0_7_get_overdrive_table(smu, &od_table);
2390 if (ret)
2391 return ret;
2392
2393 if (od_table.OverDriveTable.Ppt > 0)
2394 *ppt_limit = *ppt_limit *
2395 (100 + od_table.OverDriveTable.Ppt) / 100;
2396
2397 return 0;
2398 }
2399
smu_v13_0_7_init_ppt_limits(struct smu_context * smu)2400 static int smu_v13_0_7_init_ppt_limits(struct smu_context *smu)
2401 {
2402 struct smu_table_context *table_context = &smu->smu_table;
2403 struct smu_13_0_7_powerplay_table *powerplay_table =
2404 (struct smu_13_0_7_powerplay_table *)table_context->power_play_table;
2405 PPTable_t *pptable = table_context->driver_pptable;
2406 SkuTable_t *skutable = &pptable->SkuTable;
2407 uint32_t od_percent_upper = 0, od_percent_lower = 0;
2408 uint32_t pp_limit, msg_limit, min_limit, max_limit;
2409 int i;
2410
2411 if (powerplay_table &&
2412 smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) {
2413 od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[
2414 SMU_13_0_7_ODSETTING_POWERPERCENTAGE]);
2415 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[
2416 SMU_13_0_7_ODSETTING_POWERPERCENTAGE]);
2417 }
2418
2419 for (i = SMU_POWER_SOURCE_AC; i < SMU_POWER_SOURCE_COUNT; i++) {
2420 pp_limit = i == SMU_POWER_SOURCE_AC ?
2421 skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] :
2422 skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0];
2423 msg_limit = skutable->MsgLimits.Power[PPT_THROTTLER_PPT0][i];
2424 min_limit = min(pp_limit, msg_limit);
2425 max_limit = max(pp_limit, msg_limit);
2426
2427 smu->ppt_limits.range[i][SMU_PPT_LIMIT_PPT0].default_value =
2428 pp_limit;
2429 smu->ppt_limits.range[i][SMU_PPT_LIMIT_PPT0].max =
2430 max_limit;
2431 smu->ppt_limits.range[i][SMU_PPT_LIMIT_PPT0].min =
2432 min_limit * (100 - od_percent_lower) / 100;
2433 smu->ppt_limits.range[i][SMU_PPT_LIMIT_PPT0].od_max =
2434 max_limit * (100 + od_percent_upper) / 100;
2435 smu->ppt_limits.range[i][SMU_PPT_LIMIT_PPT0].od_min =
2436 smu->ppt_limits.range[i][SMU_PPT_LIMIT_PPT0].min;
2437 }
2438
2439 smu->ppt_limits.supported_mask |= BIT(SMU_PPT_LIMIT_PPT0);
2440
2441 return 0;
2442 }
2443
smu_v13_0_7_get_power_profile_mode(struct smu_context * smu,char * buf)2444 static int smu_v13_0_7_get_power_profile_mode(struct smu_context *smu, char *buf)
2445 {
2446 DpmActivityMonitorCoeffIntExternal_t *activity_monitor_external;
2447 uint32_t i, j, size = 0;
2448 int16_t workload_type = 0;
2449 int result = 0;
2450
2451 if (!buf)
2452 return -EINVAL;
2453
2454 activity_monitor_external = kzalloc_objs(*activity_monitor_external,
2455 PP_SMC_POWER_PROFILE_COUNT);
2456 if (!activity_monitor_external)
2457 return -ENOMEM;
2458
2459 size += sysfs_emit_at(buf, size, " ");
2460 for (i = 0; i <= PP_SMC_POWER_PROFILE_WINDOW3D; i++)
2461 size += sysfs_emit_at(buf, size, "%d %-14s%s", i, amdgpu_pp_profile_name[i],
2462 (i == smu->power_profile_mode) ? "* " : " ");
2463
2464 size += sysfs_emit_at(buf, size, "\n");
2465
2466 for (i = 0; i <= PP_SMC_POWER_PROFILE_WINDOW3D; i++) {
2467 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
2468 workload_type = smu_cmn_to_asic_specific_index(smu,
2469 CMN2ASIC_MAPPING_WORKLOAD,
2470 i);
2471 if (workload_type == -ENOTSUPP)
2472 continue;
2473 else if (workload_type < 0) {
2474 result = -EINVAL;
2475 goto out;
2476 }
2477
2478 result = smu_cmn_update_table(smu,
2479 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
2480 (void *)(&activity_monitor_external[i]), false);
2481 if (result) {
2482 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
2483 goto out;
2484 }
2485 }
2486
2487 #define PRINT_DPM_MONITOR(field) \
2488 do { \
2489 size += sysfs_emit_at(buf, size, "%-30s", #field); \
2490 for (j = 0; j <= PP_SMC_POWER_PROFILE_WINDOW3D; j++) \
2491 size += sysfs_emit_at(buf, size, "%-18d", activity_monitor_external[j].DpmActivityMonitorCoeffInt.field); \
2492 size += sysfs_emit_at(buf, size, "\n"); \
2493 } while (0)
2494
2495 PRINT_DPM_MONITOR(Gfx_ActiveHystLimit);
2496 PRINT_DPM_MONITOR(Gfx_IdleHystLimit);
2497 PRINT_DPM_MONITOR(Gfx_FPS);
2498 PRINT_DPM_MONITOR(Gfx_MinActiveFreqType);
2499 PRINT_DPM_MONITOR(Gfx_BoosterFreqType);
2500 PRINT_DPM_MONITOR(Gfx_MinActiveFreq);
2501 PRINT_DPM_MONITOR(Gfx_BoosterFreq);
2502 PRINT_DPM_MONITOR(Fclk_ActiveHystLimit);
2503 PRINT_DPM_MONITOR(Fclk_IdleHystLimit);
2504 PRINT_DPM_MONITOR(Fclk_FPS);
2505 PRINT_DPM_MONITOR(Fclk_MinActiveFreqType);
2506 PRINT_DPM_MONITOR(Fclk_BoosterFreqType);
2507 PRINT_DPM_MONITOR(Fclk_MinActiveFreq);
2508 PRINT_DPM_MONITOR(Fclk_BoosterFreq);
2509 #undef PRINT_DPM_MONITOR
2510
2511 result = size;
2512 out:
2513 kfree(activity_monitor_external);
2514 return result;
2515 }
2516
2517 #define SMU_13_0_7_CUSTOM_PARAMS_COUNT 8
2518 #define SMU_13_0_7_CUSTOM_PARAMS_CLOCK_COUNT 2
2519 #define SMU_13_0_7_CUSTOM_PARAMS_SIZE (SMU_13_0_7_CUSTOM_PARAMS_CLOCK_COUNT * SMU_13_0_7_CUSTOM_PARAMS_COUNT * sizeof(long))
2520
smu_v13_0_7_set_power_profile_mode_coeff(struct smu_context * smu,long * input)2521 static int smu_v13_0_7_set_power_profile_mode_coeff(struct smu_context *smu,
2522 long *input)
2523 {
2524
2525 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
2526 DpmActivityMonitorCoeffInt_t *activity_monitor =
2527 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
2528 int ret, idx;
2529
2530 ret = smu_cmn_update_table(smu,
2531 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
2532 (void *)(&activity_monitor_external), false);
2533 if (ret) {
2534 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
2535 return ret;
2536 }
2537
2538 idx = 0 * SMU_13_0_7_CUSTOM_PARAMS_COUNT;
2539 if (input[idx]) {
2540 /* Gfxclk */
2541 activity_monitor->Gfx_ActiveHystLimit = input[idx + 1];
2542 activity_monitor->Gfx_IdleHystLimit = input[idx + 2];
2543 activity_monitor->Gfx_FPS = input[idx + 3];
2544 activity_monitor->Gfx_MinActiveFreqType = input[idx + 4];
2545 activity_monitor->Gfx_BoosterFreqType = input[idx + 5];
2546 activity_monitor->Gfx_MinActiveFreq = input[idx + 6];
2547 activity_monitor->Gfx_BoosterFreq = input[idx + 7];
2548 }
2549 idx = 1 * SMU_13_0_7_CUSTOM_PARAMS_COUNT;
2550 if (input[idx]) {
2551 /* Fclk */
2552 activity_monitor->Fclk_ActiveHystLimit = input[idx + 1];
2553 activity_monitor->Fclk_IdleHystLimit = input[idx + 2];
2554 activity_monitor->Fclk_FPS = input[idx + 3];
2555 activity_monitor->Fclk_MinActiveFreqType = input[idx + 4];
2556 activity_monitor->Fclk_BoosterFreqType = input[idx + 5];
2557 activity_monitor->Fclk_MinActiveFreq = input[idx + 6];
2558 activity_monitor->Fclk_BoosterFreq = input[idx + 7];
2559 }
2560
2561 ret = smu_cmn_update_table(smu,
2562 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
2563 (void *)(&activity_monitor_external), true);
2564 if (ret) {
2565 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
2566 return ret;
2567 }
2568
2569 return ret;
2570 }
2571
smu_v13_0_7_set_power_profile_mode(struct smu_context * smu,u32 workload_mask,long * custom_params,u32 custom_params_max_idx)2572 static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu,
2573 u32 workload_mask,
2574 long *custom_params,
2575 u32 custom_params_max_idx)
2576 {
2577 u32 backend_workload_mask = 0;
2578 int ret, idx = -1, i;
2579
2580 smu_cmn_get_backend_workload_mask(smu, workload_mask,
2581 &backend_workload_mask);
2582
2583 if (workload_mask & (1 << PP_SMC_POWER_PROFILE_CUSTOM)) {
2584 if (!smu->custom_profile_params) {
2585 smu->custom_profile_params =
2586 kzalloc(SMU_13_0_7_CUSTOM_PARAMS_SIZE, GFP_KERNEL);
2587 if (!smu->custom_profile_params)
2588 return -ENOMEM;
2589 }
2590 if (custom_params && custom_params_max_idx) {
2591 if (!smu_cmn_custom_params_count_valid(custom_params_max_idx,
2592 SMU_13_0_7_CUSTOM_PARAMS_COUNT) ||
2593 !smu_cmn_custom_params_clock_valid(custom_params[0],
2594 SMU_13_0_7_CUSTOM_PARAMS_CLOCK_COUNT))
2595 return -EINVAL;
2596 idx = custom_params[0] * SMU_13_0_7_CUSTOM_PARAMS_COUNT;
2597 smu->custom_profile_params[idx] = 1;
2598 for (i = 1; i < custom_params_max_idx; i++)
2599 smu->custom_profile_params[idx + i] = custom_params[i];
2600 }
2601 ret = smu_v13_0_7_set_power_profile_mode_coeff(smu,
2602 smu->custom_profile_params);
2603 if (ret) {
2604 if (idx != -1)
2605 smu->custom_profile_params[idx] = 0;
2606 return ret;
2607 }
2608 } else if (smu->custom_profile_params) {
2609 memset(smu->custom_profile_params, 0, SMU_13_0_7_CUSTOM_PARAMS_SIZE);
2610 }
2611
2612 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
2613 backend_workload_mask, NULL);
2614
2615 if (ret) {
2616 dev_err(smu->adev->dev, "Failed to set workload mask 0x%08x\n",
2617 workload_mask);
2618 if (idx != -1)
2619 smu->custom_profile_params[idx] = 0;
2620 return ret;
2621 }
2622
2623 return ret;
2624 }
2625
smu_v13_0_7_set_mp1_state(struct smu_context * smu,enum pp_mp1_state mp1_state)2626 static int smu_v13_0_7_set_mp1_state(struct smu_context *smu,
2627 enum pp_mp1_state mp1_state)
2628 {
2629 int ret;
2630
2631 switch (mp1_state) {
2632 case PP_MP1_STATE_UNLOAD:
2633 ret = smu_cmn_set_mp1_state(smu, mp1_state);
2634 break;
2635 default:
2636 /* Ignore others */
2637 ret = 0;
2638 }
2639
2640 return ret;
2641 }
2642
smu_v13_0_7_is_mode1_reset_supported(struct smu_context * smu)2643 static bool smu_v13_0_7_is_mode1_reset_supported(struct smu_context *smu)
2644 {
2645 struct amdgpu_device *adev = smu->adev;
2646
2647 /* SRIOV does not support SMU mode1 reset */
2648 if (amdgpu_sriov_vf(adev))
2649 return false;
2650
2651 return true;
2652 }
2653
smu_v13_0_7_set_df_cstate(struct smu_context * smu,enum pp_df_cstate state)2654 static int smu_v13_0_7_set_df_cstate(struct smu_context *smu,
2655 enum pp_df_cstate state)
2656 {
2657 return smu_cmn_send_smc_msg_with_param(smu,
2658 SMU_MSG_DFCstateControl,
2659 state,
2660 NULL);
2661 }
2662
smu_v13_0_7_wbrf_support_check(struct smu_context * smu)2663 static bool smu_v13_0_7_wbrf_support_check(struct smu_context *smu)
2664 {
2665 return smu->smc_fw_version > 0x00524600;
2666 }
2667
smu_v13_0_7_set_ppt_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)2668 static int smu_v13_0_7_set_ppt_limit(struct smu_context *smu,
2669 enum smu_ppt_limit_type limit_type,
2670 uint32_t limit)
2671 {
2672 PPTable_t *pptable = smu->smu_table.driver_pptable;
2673 SkuTable_t *skutable = &pptable->SkuTable;
2674 uint32_t msg_limit = skutable->MsgLimits.Power
2675 [PPT_THROTTLER_PPT0][POWER_SOURCE_AC];
2676 struct smu_table_context *table_context = &smu->smu_table;
2677 OverDriveTableExternal_t *od_table =
2678 (OverDriveTableExternal_t *)table_context->overdrive_table;
2679 OverDriveTableExternal_t current_od_table;
2680 int ret = 0;
2681
2682 if (limit_type != SMU_PPT_LIMIT_PPT0)
2683 return -EINVAL;
2684
2685 if (limit <= msg_limit) {
2686 ret = smu_v13_0_7_get_overdrive_table(smu, ¤t_od_table);
2687 if (ret)
2688 return ret;
2689
2690 if (current_od_table.OverDriveTable.Ppt) {
2691 od_table->OverDriveTable.Ppt = 0;
2692 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_PPT_BIT;
2693
2694 ret = smu_v13_0_7_upload_overdrive_table(smu, od_table);
2695 if (ret) {
2696 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
2697 return ret;
2698 }
2699 }
2700 return smu_v13_0_set_ppt_limit(smu, limit_type, limit);
2701 } else if (smu->od_enabled) {
2702 ret = smu_v13_0_set_ppt_limit(smu, limit_type, msg_limit);
2703 if (ret)
2704 return ret;
2705
2706 od_table->OverDriveTable.Ppt = (limit * 100) / msg_limit - 100;
2707 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_PPT_BIT;
2708
2709 ret = smu_v13_0_7_upload_overdrive_table(smu, od_table);
2710 if (ret) {
2711 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
2712 return ret;
2713 }
2714
2715 } else {
2716 return -EINVAL;
2717 }
2718
2719 return 0;
2720 }
2721
smu_v13_0_7_update_pcie_parameters(struct smu_context * smu,uint8_t pcie_gen_cap,uint8_t pcie_width_cap)2722 static int smu_v13_0_7_update_pcie_parameters(struct smu_context *smu,
2723 uint8_t pcie_gen_cap,
2724 uint8_t pcie_width_cap)
2725 {
2726 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2727 struct smu_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table;
2728 int num_of_levels;
2729 int link_level;
2730 uint32_t smu_pcie_arg;
2731 struct smu_table_context *table_context = &smu->smu_table;
2732 PPTable_t *pptable = table_context->driver_pptable;
2733 SkuTable_t *skutable = &pptable->SkuTable;
2734 int ret = 0;
2735 int i;
2736
2737 pcie_table->lclk_levels = 0;
2738 for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) {
2739 if (!skutable->PcieGenSpeed[link_level] &&
2740 !skutable->PcieLaneCount[link_level] &&
2741 !skutable->LclkFreq[link_level])
2742 continue;
2743
2744 pcie_table->pcie_gen[pcie_table->lclk_levels] =
2745 skutable->PcieGenSpeed[link_level];
2746 pcie_table->pcie_lane[pcie_table->lclk_levels] =
2747 skutable->PcieLaneCount[link_level];
2748 pcie_table->lclk_freq[pcie_table->lclk_levels] =
2749 skutable->LclkFreq[link_level];
2750 pcie_table->lclk_levels++;
2751 }
2752
2753 num_of_levels = pcie_table->lclk_levels;
2754 if (!num_of_levels)
2755 return 0;
2756
2757 if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
2758 if (pcie_table->pcie_gen[num_of_levels - 1] < pcie_gen_cap)
2759 pcie_gen_cap = pcie_table->pcie_gen[num_of_levels - 1];
2760
2761 if (pcie_table->pcie_lane[num_of_levels - 1] < pcie_width_cap)
2762 pcie_width_cap = pcie_table->pcie_lane[num_of_levels - 1];
2763
2764 /* Force all levels to use the same settings */
2765 for (i = 0; i < num_of_levels; i++) {
2766 pcie_table->pcie_gen[i] = pcie_gen_cap;
2767 pcie_table->pcie_lane[i] = pcie_width_cap;
2768 smu_pcie_arg = i << 16;
2769 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
2770 smu_pcie_arg |= pcie_table->pcie_lane[i];
2771
2772 ret = smu_cmn_send_smc_msg_with_param(smu,
2773 SMU_MSG_OverridePcieParameters,
2774 smu_pcie_arg,
2775 NULL);
2776 if (ret)
2777 break;
2778 }
2779 } else {
2780 for (i = 0; i < num_of_levels; i++) {
2781 if (pcie_table->pcie_gen[i] > pcie_gen_cap ||
2782 pcie_table->pcie_lane[i] > pcie_width_cap) {
2783 pcie_table->pcie_gen[i] = pcie_table->pcie_gen[i] > pcie_gen_cap ?
2784 pcie_gen_cap : pcie_table->pcie_gen[i];
2785 pcie_table->pcie_lane[i] = pcie_table->pcie_lane[i] > pcie_width_cap ?
2786 pcie_width_cap : pcie_table->pcie_lane[i];
2787 smu_pcie_arg = i << 16;
2788 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
2789 smu_pcie_arg |= pcie_table->pcie_lane[i];
2790
2791 ret = smu_cmn_send_smc_msg_with_param(smu,
2792 SMU_MSG_OverridePcieParameters,
2793 smu_pcie_arg,
2794 NULL);
2795 if (ret)
2796 break;
2797 }
2798 }
2799 }
2800
2801 return ret;
2802 }
2803
smu_v13_0_7_mode1_reset(struct smu_context * smu)2804 static int smu_v13_0_7_mode1_reset(struct smu_context *smu)
2805 {
2806 int ret;
2807
2808 ret = smu_cmn_send_debug_smc_msg(smu, DEBUGSMC_MSG_Mode1Reset);
2809 if (!ret) {
2810 /* disable mmio access while doing mode 1 reset*/
2811 smu->adev->no_hw_access = true;
2812 /* ensure no_hw_access is globally visible before any MMIO */
2813 smp_mb();
2814 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
2815 }
2816
2817 return ret;
2818 }
2819
smu_v13_0_7_init_msg_ctl(struct smu_context * smu)2820 static void smu_v13_0_7_init_msg_ctl(struct smu_context *smu)
2821 {
2822 struct amdgpu_device *adev = smu->adev;
2823 struct smu_msg_ctl *ctl = &smu->msg_ctl;
2824
2825 smu_v13_0_init_msg_ctl(smu, smu_v13_0_7_message_map);
2826
2827 /* Set up debug mailbox registers */
2828 ctl->config.debug_param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_53);
2829 ctl->config.debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_75);
2830 ctl->config.debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_54);
2831 ctl->flags |= SMU_MSG_CTL_DEBUG_MAILBOX;
2832 }
2833
2834 static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
2835 .init_allowed_features = smu_v13_0_7_init_allowed_features,
2836 .set_default_dpm_table = smu_v13_0_7_set_default_dpm_table,
2837 .is_dpm_running = smu_v13_0_7_is_dpm_running,
2838 .init_microcode = smu_v13_0_init_microcode,
2839 .load_microcode = smu_v13_0_load_microcode,
2840 .fini_microcode = smu_v13_0_fini_microcode,
2841 .init_smc_tables = smu_v13_0_7_init_smc_tables,
2842 .fini_smc_tables = smu_v13_0_fini_smc_tables,
2843 .init_power = smu_v13_0_init_power,
2844 .fini_power = smu_v13_0_fini_power,
2845 .check_fw_status = smu_v13_0_7_check_fw_status,
2846 .setup_pptable = smu_v13_0_7_setup_pptable,
2847 .check_fw_version = smu_cmn_check_fw_version,
2848 .write_pptable = smu_cmn_write_pptable,
2849 .set_driver_table_location = smu_v13_0_set_driver_table_location,
2850 .system_features_control = smu_v13_0_system_features_control,
2851 .set_allowed_mask = smu_v13_0_set_allowed_mask,
2852 .get_enabled_mask = smu_cmn_get_enabled_mask,
2853 .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable,
2854 .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable,
2855 .init_pptable_microcode = smu_v13_0_init_pptable_microcode,
2856 .populate_umd_state_clk = smu_v13_0_7_populate_umd_state_clk,
2857 .get_dpm_ultimate_freq = smu_v13_0_7_get_dpm_ultimate_freq,
2858 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
2859 .read_sensor = smu_v13_0_7_read_sensor,
2860 .feature_is_enabled = smu_cmn_feature_is_enabled,
2861 .emit_clk_levels = smu_v13_0_7_emit_clk_levels,
2862 .force_clk_levels = smu_v13_0_7_force_clk_levels,
2863 .update_pcie_parameters = smu_v13_0_7_update_pcie_parameters,
2864 .get_thermal_temperature_range = smu_v13_0_7_get_thermal_temperature_range,
2865 .register_irq_handler = smu_v13_0_register_irq_handler,
2866 .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
2867 .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
2868 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
2869 .get_gpu_metrics = smu_v13_0_7_get_gpu_metrics,
2870 .set_soft_freq_limited_range = smu_v13_0_set_soft_freq_limited_range,
2871 .set_default_od_settings = smu_v13_0_7_set_default_od_settings,
2872 .restore_user_od_settings = smu_v13_0_7_restore_user_od_settings,
2873 .od_edit_dpm_table = smu_v13_0_7_od_edit_dpm_table,
2874 .set_performance_level = smu_v13_0_set_performance_level,
2875 .gfx_off_control = smu_v13_0_gfx_off_control,
2876 .get_fan_speed_pwm = smu_v13_0_7_get_fan_speed_pwm,
2877 .get_fan_speed_rpm = smu_v13_0_7_get_fan_speed_rpm,
2878 .set_fan_speed_pwm = smu_v13_0_set_fan_speed_pwm,
2879 .set_fan_speed_rpm = smu_v13_0_set_fan_speed_rpm,
2880 .get_fan_control_mode = smu_v13_0_get_fan_control_mode,
2881 .set_fan_control_mode = smu_v13_0_set_fan_control_mode,
2882 .enable_mgpu_fan_boost = smu_v13_0_7_enable_mgpu_fan_boost,
2883 .get_ppt_limit = smu_v13_0_7_get_ppt_limit,
2884 .set_ppt_limit = smu_v13_0_7_set_ppt_limit,
2885 .set_power_source = smu_v13_0_set_power_source,
2886 .get_power_profile_mode = smu_v13_0_7_get_power_profile_mode,
2887 .set_power_profile_mode = smu_v13_0_7_set_power_profile_mode,
2888 .set_tool_table_location = smu_v13_0_set_tool_table_location,
2889 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2890 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2891 .get_bamaco_support = smu_v13_0_get_bamaco_support,
2892 .baco_enter = smu_v13_0_baco_enter,
2893 .baco_exit = smu_v13_0_baco_exit,
2894 .mode1_reset_is_support = smu_v13_0_7_is_mode1_reset_supported,
2895 .mode1_reset = smu_v13_0_7_mode1_reset,
2896 .set_mp1_state = smu_v13_0_7_set_mp1_state,
2897 .set_df_cstate = smu_v13_0_7_set_df_cstate,
2898 .gpo_control = smu_v13_0_gpo_control,
2899 .is_asic_wbrf_supported = smu_v13_0_7_wbrf_support_check,
2900 .enable_uclk_shadow = smu_v13_0_enable_uclk_shadow,
2901 .set_wbrf_exclusion_ranges = smu_v13_0_set_wbrf_exclusion_ranges,
2902 .interrupt_work = smu_v13_0_interrupt_work,
2903 };
2904
smu_v13_0_7_set_ppt_funcs(struct smu_context * smu)2905 void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu)
2906 {
2907 smu->ppt_funcs = &smu_v13_0_7_ppt_funcs;
2908 smu->clock_map = smu_v13_0_7_clk_map;
2909 smu->feature_map = smu_v13_0_7_feature_mask_map;
2910 smu->table_map = smu_v13_0_7_table_map;
2911 smu->pwr_src_map = smu_v13_0_7_pwr_src_map;
2912 smu->workload_map = smu_v13_0_7_workload_map;
2913 smu->smc_driver_if_version = SMU13_0_7_DRIVER_IF_VERSION;
2914 smu_v13_0_7_init_msg_ctl(smu);
2915 }
2916