1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // cs35l41.c -- CS35l41 ALSA SoC audio driver
4 //
5 // Copyright 2017-2021 Cirrus Logic, Inc.
6 //
7 // Author: David Rhodes <david.rhodes@cirrus.com>
8
9 #include <linux/acpi.h>
10 #include <linux/delay.h>
11 #include <linux/err.h>
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/property.h>
18 #include <sound/initval.h>
19 #include <sound/pcm.h>
20 #include <sound/pcm_params.h>
21 #include <sound/soc.h>
22 #include <sound/soc-dapm.h>
23 #include <sound/tlv.h>
24
25 #include "cs35l41.h"
26
27 static const char * const cs35l41_supplies[CS35L41_NUM_SUPPLIES] = {
28 "VA",
29 "VP",
30 };
31
32 struct cs35l41_pll_sysclk_config {
33 int freq;
34 int clk_cfg;
35 };
36
37 static const struct cs35l41_pll_sysclk_config cs35l41_pll_sysclk[] = {
38 { 32768, 0x00 },
39 { 8000, 0x01 },
40 { 11025, 0x02 },
41 { 12000, 0x03 },
42 { 16000, 0x04 },
43 { 22050, 0x05 },
44 { 24000, 0x06 },
45 { 32000, 0x07 },
46 { 44100, 0x08 },
47 { 48000, 0x09 },
48 { 88200, 0x0A },
49 { 96000, 0x0B },
50 { 128000, 0x0C },
51 { 176400, 0x0D },
52 { 192000, 0x0E },
53 { 256000, 0x0F },
54 { 352800, 0x10 },
55 { 384000, 0x11 },
56 { 512000, 0x12 },
57 { 705600, 0x13 },
58 { 750000, 0x14 },
59 { 768000, 0x15 },
60 { 1000000, 0x16 },
61 { 1024000, 0x17 },
62 { 1200000, 0x18 },
63 { 1411200, 0x19 },
64 { 1500000, 0x1A },
65 { 1536000, 0x1B },
66 { 2000000, 0x1C },
67 { 2048000, 0x1D },
68 { 2400000, 0x1E },
69 { 2822400, 0x1F },
70 { 3000000, 0x20 },
71 { 3072000, 0x21 },
72 { 3200000, 0x22 },
73 { 4000000, 0x23 },
74 { 4096000, 0x24 },
75 { 4800000, 0x25 },
76 { 5644800, 0x26 },
77 { 6000000, 0x27 },
78 { 6144000, 0x28 },
79 { 6250000, 0x29 },
80 { 6400000, 0x2A },
81 { 6500000, 0x2B },
82 { 6750000, 0x2C },
83 { 7526400, 0x2D },
84 { 8000000, 0x2E },
85 { 8192000, 0x2F },
86 { 9600000, 0x30 },
87 { 11289600, 0x31 },
88 { 12000000, 0x32 },
89 { 12288000, 0x33 },
90 { 12500000, 0x34 },
91 { 12800000, 0x35 },
92 { 13000000, 0x36 },
93 { 13500000, 0x37 },
94 { 19200000, 0x38 },
95 { 22579200, 0x39 },
96 { 24000000, 0x3A },
97 { 24576000, 0x3B },
98 { 25000000, 0x3C },
99 { 25600000, 0x3D },
100 { 26000000, 0x3E },
101 { 27000000, 0x3F },
102 };
103
104 struct cs35l41_fs_mon_config {
105 int freq;
106 unsigned int fs1;
107 unsigned int fs2;
108 };
109
110 static const struct cs35l41_fs_mon_config cs35l41_fs_mon[] = {
111 { 32768, 2254, 3754 },
112 { 8000, 9220, 15364 },
113 { 11025, 6148, 10244 },
114 { 12000, 6148, 10244 },
115 { 16000, 4612, 7684 },
116 { 22050, 3076, 5124 },
117 { 24000, 3076, 5124 },
118 { 32000, 2308, 3844 },
119 { 44100, 1540, 2564 },
120 { 48000, 1540, 2564 },
121 { 88200, 772, 1284 },
122 { 96000, 772, 1284 },
123 { 128000, 580, 964 },
124 { 176400, 388, 644 },
125 { 192000, 388, 644 },
126 { 256000, 292, 484 },
127 { 352800, 196, 324 },
128 { 384000, 196, 324 },
129 { 512000, 148, 244 },
130 { 705600, 100, 164 },
131 { 750000, 100, 164 },
132 { 768000, 100, 164 },
133 { 1000000, 76, 124 },
134 { 1024000, 76, 124 },
135 { 1200000, 64, 104 },
136 { 1411200, 52, 84 },
137 { 1500000, 52, 84 },
138 { 1536000, 52, 84 },
139 { 2000000, 40, 64 },
140 { 2048000, 40, 64 },
141 { 2400000, 34, 54 },
142 { 2822400, 28, 44 },
143 { 3000000, 28, 44 },
144 { 3072000, 28, 44 },
145 { 3200000, 27, 42 },
146 { 4000000, 22, 34 },
147 { 4096000, 22, 34 },
148 { 4800000, 19, 29 },
149 { 5644800, 16, 24 },
150 { 6000000, 16, 24 },
151 { 6144000, 16, 24 },
152 { 12288000, 0, 0 },
153 };
154
cs35l41_get_fs_mon_config_index(int freq)155 static int cs35l41_get_fs_mon_config_index(int freq)
156 {
157 int i;
158
159 for (i = 0; i < ARRAY_SIZE(cs35l41_fs_mon); i++) {
160 if (cs35l41_fs_mon[i].freq == freq)
161 return i;
162 }
163
164 return -EINVAL;
165 }
166
167 static const DECLARE_TLV_DB_RANGE(dig_vol_tlv,
168 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
169 1, 913, TLV_DB_MINMAX_ITEM(-10200, 1200));
170 static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 50, 100, 0);
171
172 static const struct snd_kcontrol_new dre_ctrl =
173 SOC_DAPM_SINGLE("Switch", CS35L41_PWR_CTRL3, 20, 1, 0);
174
175 static const char * const cs35l41_pcm_sftramp_text[] = {
176 "Off", ".5ms", "1ms", "2ms", "4ms", "8ms", "15ms", "30ms"
177 };
178
179 static SOC_ENUM_SINGLE_DECL(pcm_sft_ramp,
180 CS35L41_AMP_DIG_VOL_CTRL, 0,
181 cs35l41_pcm_sftramp_text);
182
cs35l41_dsp_preload_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)183 static int cs35l41_dsp_preload_ev(struct snd_soc_dapm_widget *w,
184 struct snd_kcontrol *kcontrol, int event)
185 {
186 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
187 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
188 int ret;
189
190 switch (event) {
191 case SND_SOC_DAPM_PRE_PMU:
192 if (cs35l41->dsp.cs_dsp.booted)
193 return 0;
194
195 return wm_adsp_early_event(w, kcontrol, event);
196 case SND_SOC_DAPM_PRE_PMD:
197 if (cs35l41->dsp.preloaded)
198 return 0;
199
200 if (cs35l41->dsp.cs_dsp.running) {
201 ret = wm_adsp_event(w, kcontrol, event);
202 if (ret)
203 return ret;
204 }
205
206 return wm_adsp_early_event(w, kcontrol, event);
207 default:
208 return 0;
209 }
210 }
211
cs35l41_dsp_audio_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)212 static int cs35l41_dsp_audio_ev(struct snd_soc_dapm_widget *w,
213 struct snd_kcontrol *kcontrol, int event)
214 {
215 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
216 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
217 unsigned int fw_status;
218 int ret;
219
220 switch (event) {
221 case SND_SOC_DAPM_POST_PMU:
222 if (!cs35l41->dsp.cs_dsp.running)
223 return wm_adsp_event(w, kcontrol, event);
224
225 ret = regmap_read(cs35l41->regmap, CS35L41_DSP_MBOX_2, &fw_status);
226 if (ret < 0) {
227 dev_err(cs35l41->dev,
228 "Failed to read firmware status: %d\n", ret);
229 return ret;
230 }
231
232 switch (fw_status) {
233 case CSPL_MBOX_STS_RUNNING:
234 case CSPL_MBOX_STS_PAUSED:
235 break;
236 default:
237 dev_err(cs35l41->dev, "Firmware status is invalid: %u\n",
238 fw_status);
239 return -EINVAL;
240 }
241
242 return cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap,
243 CSPL_MBOX_CMD_RESUME);
244 case SND_SOC_DAPM_PRE_PMD:
245 return cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap,
246 CSPL_MBOX_CMD_PAUSE);
247 default:
248 return 0;
249 }
250 }
251
252 static const char * const cs35l41_pcm_source_texts[] = {"ASP", "DSP"};
253 static const unsigned int cs35l41_pcm_source_values[] = {0x08, 0x32};
254 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_pcm_source_enum,
255 CS35L41_DAC_PCM1_SRC,
256 0, CS35L41_ASP_SOURCE_MASK,
257 cs35l41_pcm_source_texts,
258 cs35l41_pcm_source_values);
259
260 static const struct snd_kcontrol_new pcm_source_mux =
261 SOC_DAPM_ENUM("PCM Source", cs35l41_pcm_source_enum);
262
263 static const char * const cs35l41_tx_input_texts[] = {
264 "Zero", "ASPRX1", "ASPRX2", "VMON", "IMON",
265 "VPMON", "VBSTMON", "DSPTX1", "DSPTX2"
266 };
267
268 static const unsigned int cs35l41_tx_input_values[] = {
269 0x00, CS35L41_INPUT_SRC_ASPRX1, CS35L41_INPUT_SRC_ASPRX2,
270 CS35L41_INPUT_SRC_VMON, CS35L41_INPUT_SRC_IMON, CS35L41_INPUT_SRC_VPMON,
271 CS35L41_INPUT_SRC_VBSTMON, CS35L41_INPUT_DSP_TX1, CS35L41_INPUT_DSP_TX2
272 };
273
274 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx1_enum,
275 CS35L41_ASP_TX1_SRC,
276 0, CS35L41_ASP_SOURCE_MASK,
277 cs35l41_tx_input_texts,
278 cs35l41_tx_input_values);
279
280 static const struct snd_kcontrol_new asp_tx1_mux =
281 SOC_DAPM_ENUM("ASPTX1 SRC", cs35l41_asptx1_enum);
282
283 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx2_enum,
284 CS35L41_ASP_TX2_SRC,
285 0, CS35L41_ASP_SOURCE_MASK,
286 cs35l41_tx_input_texts,
287 cs35l41_tx_input_values);
288
289 static const struct snd_kcontrol_new asp_tx2_mux =
290 SOC_DAPM_ENUM("ASPTX2 SRC", cs35l41_asptx2_enum);
291
292 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx3_enum,
293 CS35L41_ASP_TX3_SRC,
294 0, CS35L41_ASP_SOURCE_MASK,
295 cs35l41_tx_input_texts,
296 cs35l41_tx_input_values);
297
298 static const struct snd_kcontrol_new asp_tx3_mux =
299 SOC_DAPM_ENUM("ASPTX3 SRC", cs35l41_asptx3_enum);
300
301 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx4_enum,
302 CS35L41_ASP_TX4_SRC,
303 0, CS35L41_ASP_SOURCE_MASK,
304 cs35l41_tx_input_texts,
305 cs35l41_tx_input_values);
306
307 static const struct snd_kcontrol_new asp_tx4_mux =
308 SOC_DAPM_ENUM("ASPTX4 SRC", cs35l41_asptx4_enum);
309
310 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx1_enum,
311 CS35L41_DSP1_RX1_SRC,
312 0, CS35L41_ASP_SOURCE_MASK,
313 cs35l41_tx_input_texts,
314 cs35l41_tx_input_values);
315
316 static const struct snd_kcontrol_new dsp_rx1_mux =
317 SOC_DAPM_ENUM("DSPRX1 SRC", cs35l41_dsprx1_enum);
318
319 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx2_enum,
320 CS35L41_DSP1_RX2_SRC,
321 0, CS35L41_ASP_SOURCE_MASK,
322 cs35l41_tx_input_texts,
323 cs35l41_tx_input_values);
324
325 static const struct snd_kcontrol_new dsp_rx2_mux =
326 SOC_DAPM_ENUM("DSPRX2 SRC", cs35l41_dsprx2_enum);
327
328 static const struct snd_kcontrol_new cs35l41_aud_controls[] = {
329 SOC_SINGLE_SX_TLV("Digital PCM Volume", CS35L41_AMP_DIG_VOL_CTRL,
330 3, 0x4CF, 0x391, dig_vol_tlv),
331 SOC_SINGLE_TLV("Analog PCM Volume", CS35L41_AMP_GAIN_CTRL, 5, 0x14, 0,
332 amp_gain_tlv),
333 SOC_ENUM("PCM Soft Ramp", pcm_sft_ramp),
334 SOC_SINGLE("HW Noise Gate Enable", CS35L41_NG_CFG, 8, 63, 0),
335 SOC_SINGLE("HW Noise Gate Delay", CS35L41_NG_CFG, 4, 7, 0),
336 SOC_SINGLE("HW Noise Gate Threshold", CS35L41_NG_CFG, 0, 7, 0),
337 SOC_SINGLE("Aux Noise Gate CH1 Switch",
338 CS35L41_MIXER_NGATE_CH1_CFG, 16, 1, 0),
339 SOC_SINGLE("Aux Noise Gate CH1 Entry Delay",
340 CS35L41_MIXER_NGATE_CH1_CFG, 8, 15, 0),
341 SOC_SINGLE("Aux Noise Gate CH1 Threshold",
342 CS35L41_MIXER_NGATE_CH1_CFG, 0, 7, 0),
343 SOC_SINGLE("Aux Noise Gate CH2 Entry Delay",
344 CS35L41_MIXER_NGATE_CH2_CFG, 8, 15, 0),
345 SOC_SINGLE("Aux Noise Gate CH2 Switch",
346 CS35L41_MIXER_NGATE_CH2_CFG, 16, 1, 0),
347 SOC_SINGLE("Aux Noise Gate CH2 Threshold",
348 CS35L41_MIXER_NGATE_CH2_CFG, 0, 7, 0),
349 SOC_SINGLE("SCLK Force Switch", CS35L41_SP_FORMAT, CS35L41_SCLK_FRC_SHIFT, 1, 0),
350 SOC_SINGLE("LRCLK Force Switch", CS35L41_SP_FORMAT, CS35L41_LRCLK_FRC_SHIFT, 1, 0),
351 SOC_SINGLE("Invert Class D Switch", CS35L41_AMP_DIG_VOL_CTRL,
352 CS35L41_AMP_INV_PCM_SHIFT, 1, 0),
353 SOC_SINGLE("Amp Gain ZC Switch", CS35L41_AMP_GAIN_CTRL,
354 CS35L41_AMP_GAIN_ZC_SHIFT, 1, 0),
355 WM_ADSP2_PRELOAD_SWITCH("DSP1", 1),
356 WM_ADSP_FW_CONTROL("DSP1", 0),
357 };
358
cs35l41_boost_enable(struct cs35l41_private * cs35l41,unsigned int enable)359 static void cs35l41_boost_enable(struct cs35l41_private *cs35l41, unsigned int enable)
360 {
361 switch (cs35l41->hw_cfg.bst_type) {
362 case CS35L41_INT_BOOST:
363 case CS35L41_SHD_BOOST_ACTV:
364 enable = enable ? CS35L41_BST_EN_DEFAULT : CS35L41_BST_DIS_FET_OFF;
365 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, CS35L41_BST_EN_MASK,
366 enable << CS35L41_BST_EN_SHIFT);
367 break;
368 default:
369 break;
370 }
371 }
372
373
cs35l41_error_release(struct cs35l41_private * cs35l41,unsigned int irq_err_bit,unsigned int rel_err_bit)374 static void cs35l41_error_release(struct cs35l41_private *cs35l41, unsigned int irq_err_bit,
375 unsigned int rel_err_bit)
376 {
377 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, irq_err_bit);
378 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0);
379 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, rel_err_bit, rel_err_bit);
380 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, rel_err_bit, 0);
381 }
382
cs35l41_irq(int irq,void * data)383 static irqreturn_t cs35l41_irq(int irq, void *data)
384 {
385 struct cs35l41_private *cs35l41 = data;
386 unsigned int status[4] = { 0, 0, 0, 0 };
387 unsigned int masks[4] = { 0, 0, 0, 0 };
388 unsigned int i;
389 int ret;
390
391 ret = pm_runtime_resume_and_get(cs35l41->dev);
392 if (ret < 0) {
393 dev_err(cs35l41->dev,
394 "pm_runtime_resume_and_get failed in %s: %d\n",
395 __func__, ret);
396 return IRQ_NONE;
397 }
398
399 ret = IRQ_NONE;
400
401 for (i = 0; i < ARRAY_SIZE(status); i++) {
402 regmap_read(cs35l41->regmap,
403 CS35L41_IRQ1_STATUS1 + (i * CS35L41_REGSTRIDE),
404 &status[i]);
405 regmap_read(cs35l41->regmap,
406 CS35L41_IRQ1_MASK1 + (i * CS35L41_REGSTRIDE),
407 &masks[i]);
408 }
409
410 /* Check to see if unmasked bits are active */
411 if (!(status[0] & ~masks[0]) && !(status[1] & ~masks[1]) &&
412 !(status[2] & ~masks[2]) && !(status[3] & ~masks[3]))
413 goto done;
414
415 if (status[3] & CS35L41_OTP_BOOT_DONE) {
416 regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK4,
417 CS35L41_OTP_BOOT_DONE, CS35L41_OTP_BOOT_DONE);
418 }
419
420 /*
421 * The following interrupts require a
422 * protection release cycle to get the
423 * speaker out of Safe-Mode.
424 */
425 if (status[0] & CS35L41_AMP_SHORT_ERR) {
426 dev_crit_ratelimited(cs35l41->dev, "Amp short error\n");
427 cs35l41_error_release(cs35l41, CS35L41_AMP_SHORT_ERR, CS35L41_AMP_SHORT_ERR_RLS);
428 ret = IRQ_HANDLED;
429 }
430
431 if (status[0] & CS35L41_TEMP_WARN) {
432 dev_crit_ratelimited(cs35l41->dev, "Over temperature warning\n");
433 cs35l41_error_release(cs35l41, CS35L41_TEMP_WARN, CS35L41_TEMP_WARN_ERR_RLS);
434 ret = IRQ_HANDLED;
435 }
436
437 if (status[0] & CS35L41_TEMP_ERR) {
438 dev_crit_ratelimited(cs35l41->dev, "Over temperature error\n");
439 cs35l41_error_release(cs35l41, CS35L41_TEMP_ERR, CS35L41_TEMP_ERR_RLS);
440 ret = IRQ_HANDLED;
441 }
442
443 if (status[0] & CS35L41_BST_OVP_ERR) {
444 dev_crit_ratelimited(cs35l41->dev, "VBST Over Voltage error\n");
445 cs35l41_boost_enable(cs35l41, 0);
446 cs35l41_error_release(cs35l41, CS35L41_BST_OVP_ERR, CS35L41_BST_OVP_ERR_RLS);
447 cs35l41_boost_enable(cs35l41, 1);
448 ret = IRQ_HANDLED;
449 }
450
451 if (status[0] & CS35L41_BST_DCM_UVP_ERR) {
452 dev_crit_ratelimited(cs35l41->dev, "DCM VBST Under Voltage Error\n");
453 cs35l41_boost_enable(cs35l41, 0);
454 cs35l41_error_release(cs35l41, CS35L41_BST_DCM_UVP_ERR, CS35L41_BST_UVP_ERR_RLS);
455 cs35l41_boost_enable(cs35l41, 1);
456 ret = IRQ_HANDLED;
457 }
458
459 if (status[0] & CS35L41_BST_SHORT_ERR) {
460 dev_crit_ratelimited(cs35l41->dev, "LBST error: powering off!\n");
461 cs35l41_boost_enable(cs35l41, 0);
462 cs35l41_error_release(cs35l41, CS35L41_BST_SHORT_ERR, CS35L41_BST_SHORT_ERR_RLS);
463 cs35l41_boost_enable(cs35l41, 1);
464 ret = IRQ_HANDLED;
465 }
466
467 if (status[2] & CS35L41_PLL_LOCK) {
468 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS3, CS35L41_PLL_LOCK);
469
470 if (cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_ACTV ||
471 cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_PASS) {
472 ret = cs35l41_mdsync_up(cs35l41->regmap);
473 if (ret)
474 dev_err(cs35l41->dev, "MDSYNC-up failed: %d\n", ret);
475 else
476 dev_dbg(cs35l41->dev, "MDSYNC-up done\n");
477
478 dev_dbg(cs35l41->dev, "PUP-done status: %d\n",
479 !!(status[0] & CS35L41_PUP_DONE_MASK));
480 }
481
482 ret = IRQ_HANDLED;
483 }
484
485 done:
486 pm_runtime_put_autosuspend(cs35l41->dev);
487
488 return ret;
489 }
490
491 static const struct reg_sequence cs35l41_pup_patch[] = {
492 { CS35L41_TEST_KEY_CTL, 0x00000055 },
493 { CS35L41_TEST_KEY_CTL, 0x000000AA },
494 { 0x00002084, 0x002F1AA0 },
495 { CS35L41_TEST_KEY_CTL, 0x000000CC },
496 { CS35L41_TEST_KEY_CTL, 0x00000033 },
497 };
498
499 static const struct reg_sequence cs35l41_pdn_patch[] = {
500 { CS35L41_TEST_KEY_CTL, 0x00000055 },
501 { CS35L41_TEST_KEY_CTL, 0x000000AA },
502 { 0x00002084, 0x002F1AA3 },
503 { CS35L41_TEST_KEY_CTL, 0x000000CC },
504 { CS35L41_TEST_KEY_CTL, 0x00000033 },
505 };
506
cs35l41_main_amp_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)507 static int cs35l41_main_amp_event(struct snd_soc_dapm_widget *w,
508 struct snd_kcontrol *kcontrol, int event)
509 {
510 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
511 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
512 int ret = 0;
513
514 switch (event) {
515 case SND_SOC_DAPM_PRE_PMU:
516 regmap_multi_reg_write_bypassed(cs35l41->regmap,
517 cs35l41_pup_patch,
518 ARRAY_SIZE(cs35l41_pup_patch));
519
520 ret = cs35l41_global_enable(cs35l41->dev, cs35l41->regmap, cs35l41->hw_cfg.bst_type,
521 1, &cs35l41->dsp.cs_dsp);
522 break;
523 case SND_SOC_DAPM_POST_PMD:
524 ret = cs35l41_global_enable(cs35l41->dev, cs35l41->regmap, cs35l41->hw_cfg.bst_type,
525 0, &cs35l41->dsp.cs_dsp);
526
527 regmap_multi_reg_write_bypassed(cs35l41->regmap,
528 cs35l41_pdn_patch,
529 ARRAY_SIZE(cs35l41_pdn_patch));
530 break;
531 default:
532 dev_err(cs35l41->dev, "Invalid event = 0x%x\n", event);
533 ret = -EINVAL;
534 }
535
536 return ret;
537 }
538
539 static const struct snd_soc_dapm_widget cs35l41_dapm_widgets[] = {
540 SND_SOC_DAPM_SPK("DSP1 Preload", NULL),
541 SND_SOC_DAPM_SUPPLY_S("DSP1 Preloader", 100, SND_SOC_NOPM, 0, 0,
542 cs35l41_dsp_preload_ev,
543 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
544 SND_SOC_DAPM_OUT_DRV_E("DSP1", SND_SOC_NOPM, 0, 0, NULL, 0,
545 cs35l41_dsp_audio_ev,
546 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
547
548 SND_SOC_DAPM_OUTPUT("SPK"),
549
550 SND_SOC_DAPM_AIF_IN("ASPRX1", NULL, 0, CS35L41_SP_ENABLES, 16, 0),
551 SND_SOC_DAPM_AIF_IN("ASPRX2", NULL, 0, CS35L41_SP_ENABLES, 17, 0),
552 SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0, CS35L41_SP_ENABLES, 0, 0),
553 SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 0, CS35L41_SP_ENABLES, 1, 0),
554 SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 0, CS35L41_SP_ENABLES, 2, 0),
555 SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 0, CS35L41_SP_ENABLES, 3, 0),
556
557 SND_SOC_DAPM_SIGGEN("VSENSE"),
558 SND_SOC_DAPM_SIGGEN("ISENSE"),
559 SND_SOC_DAPM_SIGGEN("VP"),
560 SND_SOC_DAPM_SIGGEN("VBST"),
561 SND_SOC_DAPM_SIGGEN("TEMP"),
562
563 SND_SOC_DAPM_SUPPLY("VMON", CS35L41_PWR_CTRL2, 12, 0, NULL, 0),
564 SND_SOC_DAPM_SUPPLY("IMON", CS35L41_PWR_CTRL2, 13, 0, NULL, 0),
565 SND_SOC_DAPM_SUPPLY("VPMON", CS35L41_PWR_CTRL2, 8, 0, NULL, 0),
566 SND_SOC_DAPM_SUPPLY("VBSTMON", CS35L41_PWR_CTRL2, 9, 0, NULL, 0),
567 SND_SOC_DAPM_SUPPLY("TEMPMON", CS35L41_PWR_CTRL2, 10, 0, NULL, 0),
568
569 SND_SOC_DAPM_ADC("VMON ADC", NULL, SND_SOC_NOPM, 0, 0),
570 SND_SOC_DAPM_ADC("IMON ADC", NULL, SND_SOC_NOPM, 0, 0),
571 SND_SOC_DAPM_ADC("VPMON ADC", NULL, SND_SOC_NOPM, 0, 0),
572 SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, SND_SOC_NOPM, 0, 0),
573 SND_SOC_DAPM_ADC("TEMPMON ADC", NULL, SND_SOC_NOPM, 0, 0),
574
575 SND_SOC_DAPM_ADC("CLASS H", NULL, CS35L41_PWR_CTRL3, 4, 0),
576
577 SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L41_PWR_CTRL2, 0, 0, NULL, 0,
578 cs35l41_main_amp_event,
579 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
580
581 SND_SOC_DAPM_MUX("ASP TX1 Source", SND_SOC_NOPM, 0, 0, &asp_tx1_mux),
582 SND_SOC_DAPM_MUX("ASP TX2 Source", SND_SOC_NOPM, 0, 0, &asp_tx2_mux),
583 SND_SOC_DAPM_MUX("ASP TX3 Source", SND_SOC_NOPM, 0, 0, &asp_tx3_mux),
584 SND_SOC_DAPM_MUX("ASP TX4 Source", SND_SOC_NOPM, 0, 0, &asp_tx4_mux),
585 SND_SOC_DAPM_MUX("DSP RX1 Source", SND_SOC_NOPM, 0, 0, &dsp_rx1_mux),
586 SND_SOC_DAPM_MUX("DSP RX2 Source", SND_SOC_NOPM, 0, 0, &dsp_rx2_mux),
587 SND_SOC_DAPM_MUX("PCM Source", SND_SOC_NOPM, 0, 0, &pcm_source_mux),
588 SND_SOC_DAPM_SWITCH("DRE", SND_SOC_NOPM, 0, 0, &dre_ctrl),
589 };
590
591 static const struct snd_soc_dapm_route cs35l41_audio_map[] = {
592 {"DSP RX1 Source", "ASPRX1", "ASPRX1"},
593 {"DSP RX1 Source", "ASPRX2", "ASPRX2"},
594 {"DSP RX2 Source", "ASPRX1", "ASPRX1"},
595 {"DSP RX2 Source", "ASPRX2", "ASPRX2"},
596
597 {"DSP1", NULL, "DSP RX1 Source"},
598 {"DSP1", NULL, "DSP RX2 Source"},
599
600 {"ASP TX1 Source", "VMON", "VMON ADC"},
601 {"ASP TX1 Source", "IMON", "IMON ADC"},
602 {"ASP TX1 Source", "VPMON", "VPMON ADC"},
603 {"ASP TX1 Source", "VBSTMON", "VBSTMON ADC"},
604 {"ASP TX1 Source", "DSPTX1", "DSP1"},
605 {"ASP TX1 Source", "DSPTX2", "DSP1"},
606 {"ASP TX1 Source", "ASPRX1", "ASPRX1" },
607 {"ASP TX1 Source", "ASPRX2", "ASPRX2" },
608 {"ASP TX2 Source", "VMON", "VMON ADC"},
609 {"ASP TX2 Source", "IMON", "IMON ADC"},
610 {"ASP TX2 Source", "VPMON", "VPMON ADC"},
611 {"ASP TX2 Source", "VBSTMON", "VBSTMON ADC"},
612 {"ASP TX2 Source", "DSPTX1", "DSP1"},
613 {"ASP TX2 Source", "DSPTX2", "DSP1"},
614 {"ASP TX2 Source", "ASPRX1", "ASPRX1" },
615 {"ASP TX2 Source", "ASPRX2", "ASPRX2" },
616 {"ASP TX3 Source", "VMON", "VMON ADC"},
617 {"ASP TX3 Source", "IMON", "IMON ADC"},
618 {"ASP TX3 Source", "VPMON", "VPMON ADC"},
619 {"ASP TX3 Source", "VBSTMON", "VBSTMON ADC"},
620 {"ASP TX3 Source", "DSPTX1", "DSP1"},
621 {"ASP TX3 Source", "DSPTX2", "DSP1"},
622 {"ASP TX3 Source", "ASPRX1", "ASPRX1" },
623 {"ASP TX3 Source", "ASPRX2", "ASPRX2" },
624 {"ASP TX4 Source", "VMON", "VMON ADC"},
625 {"ASP TX4 Source", "IMON", "IMON ADC"},
626 {"ASP TX4 Source", "VPMON", "VPMON ADC"},
627 {"ASP TX4 Source", "VBSTMON", "VBSTMON ADC"},
628 {"ASP TX4 Source", "DSPTX1", "DSP1"},
629 {"ASP TX4 Source", "DSPTX2", "DSP1"},
630 {"ASP TX4 Source", "ASPRX1", "ASPRX1" },
631 {"ASP TX4 Source", "ASPRX2", "ASPRX2" },
632 {"ASPTX1", NULL, "ASP TX1 Source"},
633 {"ASPTX2", NULL, "ASP TX2 Source"},
634 {"ASPTX3", NULL, "ASP TX3 Source"},
635 {"ASPTX4", NULL, "ASP TX4 Source"},
636 {"AMP Capture", NULL, "ASPTX1"},
637 {"AMP Capture", NULL, "ASPTX2"},
638 {"AMP Capture", NULL, "ASPTX3"},
639 {"AMP Capture", NULL, "ASPTX4"},
640
641 {"DSP1", NULL, "VMON"},
642 {"DSP1", NULL, "IMON"},
643 {"DSP1", NULL, "VPMON"},
644 {"DSP1", NULL, "VBSTMON"},
645 {"DSP1", NULL, "TEMPMON"},
646
647 {"VMON ADC", NULL, "VMON"},
648 {"IMON ADC", NULL, "IMON"},
649 {"VPMON ADC", NULL, "VPMON"},
650 {"VBSTMON ADC", NULL, "VBSTMON"},
651 {"TEMPMON ADC", NULL, "TEMPMON"},
652
653 {"VMON ADC", NULL, "VSENSE"},
654 {"IMON ADC", NULL, "ISENSE"},
655 {"VPMON ADC", NULL, "VP"},
656 {"VBSTMON ADC", NULL, "VBST"},
657 {"TEMPMON ADC", NULL, "TEMP"},
658
659 {"DSP1 Preload", NULL, "DSP1 Preloader"},
660 {"DSP1", NULL, "DSP1 Preloader"},
661
662 {"ASPRX1", NULL, "AMP Playback"},
663 {"ASPRX2", NULL, "AMP Playback"},
664 {"DRE", "Switch", "CLASS H"},
665 {"Main AMP", NULL, "CLASS H"},
666 {"Main AMP", NULL, "DRE"},
667 {"SPK", NULL, "Main AMP"},
668
669 {"PCM Source", "ASP", "ASPRX1"},
670 {"PCM Source", "DSP", "DSP1"},
671 {"CLASS H", NULL, "PCM Source"},
672 };
673
cs35l41_set_channel_map(struct snd_soc_dai * dai,unsigned int tx_n,const unsigned int * tx_slot,unsigned int rx_n,const unsigned int * rx_slot)674 static int cs35l41_set_channel_map(struct snd_soc_dai *dai, unsigned int tx_n,
675 const unsigned int *tx_slot,
676 unsigned int rx_n, const unsigned int *rx_slot)
677 {
678 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component);
679
680 return cs35l41_set_channels(cs35l41->dev, cs35l41->regmap, tx_n, tx_slot, rx_n, rx_slot);
681 }
682
cs35l41_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)683 static int cs35l41_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
684 {
685 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component);
686 unsigned int daifmt = 0;
687
688 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
689 case SND_SOC_DAIFMT_CBP_CFP:
690 daifmt |= CS35L41_SCLK_MSTR_MASK | CS35L41_LRCLK_MSTR_MASK;
691 break;
692 case SND_SOC_DAIFMT_CBC_CFC:
693 break;
694 default:
695 dev_warn(cs35l41->dev, "Mixed provider/consumer mode unsupported\n");
696 return -EINVAL;
697 }
698
699 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
700 case SND_SOC_DAIFMT_DSP_A:
701 break;
702 case SND_SOC_DAIFMT_I2S:
703 daifmt |= 2 << CS35L41_ASP_FMT_SHIFT;
704 break;
705 default:
706 dev_warn(cs35l41->dev, "Invalid or unsupported DAI format\n");
707 return -EINVAL;
708 }
709
710 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
711 case SND_SOC_DAIFMT_NB_IF:
712 daifmt |= CS35L41_LRCLK_INV_MASK;
713 break;
714 case SND_SOC_DAIFMT_IB_NF:
715 daifmt |= CS35L41_SCLK_INV_MASK;
716 break;
717 case SND_SOC_DAIFMT_IB_IF:
718 daifmt |= CS35L41_LRCLK_INV_MASK | CS35L41_SCLK_INV_MASK;
719 break;
720 case SND_SOC_DAIFMT_NB_NF:
721 break;
722 default:
723 dev_warn(cs35l41->dev, "Invalid DAI clock INV\n");
724 return -EINVAL;
725 }
726
727 return regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT,
728 CS35L41_SCLK_MSTR_MASK | CS35L41_LRCLK_MSTR_MASK |
729 CS35L41_ASP_FMT_MASK | CS35L41_LRCLK_INV_MASK |
730 CS35L41_SCLK_INV_MASK, daifmt);
731 }
732
733 struct cs35l41_global_fs_config {
734 int rate;
735 int fs_cfg;
736 };
737
738 static const struct cs35l41_global_fs_config cs35l41_fs_rates[] = {
739 { 12000, 0x01 },
740 { 24000, 0x02 },
741 { 48000, 0x03 },
742 { 96000, 0x04 },
743 { 192000, 0x05 },
744 { 11025, 0x09 },
745 { 22050, 0x0A },
746 { 44100, 0x0B },
747 { 88200, 0x0C },
748 { 176400, 0x0D },
749 { 8000, 0x11 },
750 { 16000, 0x12 },
751 { 32000, 0x13 },
752 };
753
cs35l41_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)754 static int cs35l41_pcm_hw_params(struct snd_pcm_substream *substream,
755 struct snd_pcm_hw_params *params,
756 struct snd_soc_dai *dai)
757 {
758 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component);
759 unsigned int rate = params_rate(params);
760 u8 asp_wl;
761 int i;
762
763 for (i = 0; i < ARRAY_SIZE(cs35l41_fs_rates); i++) {
764 if (rate == cs35l41_fs_rates[i].rate)
765 break;
766 }
767
768 if (i >= ARRAY_SIZE(cs35l41_fs_rates)) {
769 dev_err(cs35l41->dev, "Unsupported rate: %u\n", rate);
770 return -EINVAL;
771 }
772
773 asp_wl = params_width(params);
774
775 regmap_update_bits(cs35l41->regmap, CS35L41_GLOBAL_CLK_CTRL,
776 CS35L41_GLOBAL_FS_MASK,
777 cs35l41_fs_rates[i].fs_cfg << CS35L41_GLOBAL_FS_SHIFT);
778
779 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
780 regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT,
781 CS35L41_ASP_WIDTH_RX_MASK,
782 asp_wl << CS35L41_ASP_WIDTH_RX_SHIFT);
783 regmap_update_bits(cs35l41->regmap, CS35L41_SP_RX_WL,
784 CS35L41_ASP_RX_WL_MASK,
785 asp_wl << CS35L41_ASP_RX_WL_SHIFT);
786 } else {
787 regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT,
788 CS35L41_ASP_WIDTH_TX_MASK,
789 asp_wl << CS35L41_ASP_WIDTH_TX_SHIFT);
790 regmap_update_bits(cs35l41->regmap, CS35L41_SP_TX_WL,
791 CS35L41_ASP_TX_WL_MASK,
792 asp_wl << CS35L41_ASP_TX_WL_SHIFT);
793 }
794
795 return 0;
796 }
797
cs35l41_get_clk_config(int freq)798 static int cs35l41_get_clk_config(int freq)
799 {
800 int i;
801
802 for (i = 0; i < ARRAY_SIZE(cs35l41_pll_sysclk); i++) {
803 if (cs35l41_pll_sysclk[i].freq == freq)
804 return cs35l41_pll_sysclk[i].clk_cfg;
805 }
806
807 return -EINVAL;
808 }
809
cs35l41_component_set_sysclk(struct snd_soc_component * component,int clk_id,int source,unsigned int freq,int dir)810 static int cs35l41_component_set_sysclk(struct snd_soc_component *component,
811 int clk_id, int source,
812 unsigned int freq, int dir)
813 {
814 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
815 int extclk_cfg, clksrc;
816
817 switch (clk_id) {
818 case CS35L41_CLKID_SCLK:
819 clksrc = CS35L41_PLLSRC_SCLK;
820 break;
821 case CS35L41_CLKID_LRCLK:
822 clksrc = CS35L41_PLLSRC_LRCLK;
823 break;
824 case CS35L41_CLKID_MCLK:
825 clksrc = CS35L41_PLLSRC_MCLK;
826 break;
827 default:
828 dev_err(cs35l41->dev, "Invalid CLK Config\n");
829 return -EINVAL;
830 }
831
832 extclk_cfg = cs35l41_get_clk_config(freq);
833
834 if (extclk_cfg < 0) {
835 dev_err(cs35l41->dev, "Invalid CLK Config: %d, freq: %u\n",
836 extclk_cfg, freq);
837 return -EINVAL;
838 }
839
840 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
841 CS35L41_PLL_OPENLOOP_MASK,
842 1 << CS35L41_PLL_OPENLOOP_SHIFT);
843 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
844 CS35L41_REFCLK_FREQ_MASK,
845 extclk_cfg << CS35L41_REFCLK_FREQ_SHIFT);
846 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
847 CS35L41_PLL_CLK_EN_MASK,
848 0 << CS35L41_PLL_CLK_EN_SHIFT);
849 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
850 CS35L41_PLL_CLK_SEL_MASK, clksrc);
851 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
852 CS35L41_PLL_OPENLOOP_MASK,
853 0 << CS35L41_PLL_OPENLOOP_SHIFT);
854 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
855 CS35L41_PLL_CLK_EN_MASK,
856 1 << CS35L41_PLL_CLK_EN_SHIFT);
857
858 return 0;
859 }
860
cs35l41_dai_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)861 static int cs35l41_dai_set_sysclk(struct snd_soc_dai *dai,
862 int clk_id, unsigned int freq, int dir)
863 {
864 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component);
865 unsigned int fs1_val;
866 unsigned int fs2_val;
867 unsigned int val;
868 int fsindex;
869
870 fsindex = cs35l41_get_fs_mon_config_index(freq);
871 if (fsindex < 0) {
872 dev_err(cs35l41->dev, "Invalid CLK Config freq: %u\n", freq);
873 return -EINVAL;
874 }
875
876 dev_dbg(cs35l41->dev, "Set DAI sysclk %d\n", freq);
877
878 if (freq <= 6144000) {
879 /* Use the lookup table */
880 fs1_val = cs35l41_fs_mon[fsindex].fs1;
881 fs2_val = cs35l41_fs_mon[fsindex].fs2;
882 } else {
883 /* Use hard-coded values */
884 fs1_val = 0x10;
885 fs2_val = 0x24;
886 }
887
888 val = fs1_val;
889 val |= (fs2_val << CS35L41_FS2_WINDOW_SHIFT) & CS35L41_FS2_WINDOW_MASK;
890 regmap_write(cs35l41->regmap, CS35L41_TST_FS_MON0, val);
891
892 return 0;
893 }
894
cs35l41_set_pdata(struct cs35l41_private * cs35l41)895 static int cs35l41_set_pdata(struct cs35l41_private *cs35l41)
896 {
897 struct cs35l41_hw_cfg *hw_cfg = &cs35l41->hw_cfg;
898 int ret;
899
900 if (!hw_cfg->valid)
901 return -EINVAL;
902
903 if (hw_cfg->bst_type == CS35L41_EXT_BOOST_NO_VSPK_SWITCH)
904 return -EINVAL;
905
906 /* Required */
907 ret = cs35l41_init_boost(cs35l41->dev, cs35l41->regmap, hw_cfg);
908 if (ret)
909 return ret;
910
911 /* Optional */
912 if (hw_cfg->dout_hiz <= CS35L41_ASP_DOUT_HIZ_MASK && hw_cfg->dout_hiz >= 0)
913 regmap_update_bits(cs35l41->regmap, CS35L41_SP_HIZ_CTRL, CS35L41_ASP_DOUT_HIZ_MASK,
914 hw_cfg->dout_hiz);
915
916 return 0;
917 }
918
919 static const struct snd_soc_dapm_route cs35l41_ext_bst_routes[] = {
920 {"Main AMP", NULL, "VSPK"},
921 };
922
923 static const struct snd_soc_dapm_widget cs35l41_ext_bst_widget[] = {
924 SND_SOC_DAPM_SUPPLY("VSPK", CS35L41_GPIO1_CTRL1, CS35L41_GPIO_LVL_SHIFT, 0, NULL, 0),
925 };
926
cs35l41_component_probe(struct snd_soc_component * component)927 static int cs35l41_component_probe(struct snd_soc_component *component)
928 {
929 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
930 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
931 int ret;
932
933 if (cs35l41->hw_cfg.bst_type == CS35L41_EXT_BOOST) {
934 ret = snd_soc_dapm_new_controls(dapm, cs35l41_ext_bst_widget,
935 ARRAY_SIZE(cs35l41_ext_bst_widget));
936 if (ret)
937 return ret;
938
939 ret = snd_soc_dapm_add_routes(dapm, cs35l41_ext_bst_routes,
940 ARRAY_SIZE(cs35l41_ext_bst_routes));
941 if (ret)
942 return ret;
943 }
944
945 return wm_adsp2_component_probe(&cs35l41->dsp, component);
946 }
947
cs35l41_component_remove(struct snd_soc_component * component)948 static void cs35l41_component_remove(struct snd_soc_component *component)
949 {
950 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
951
952 wm_adsp2_component_remove(&cs35l41->dsp, component);
953 }
954
955 static const struct snd_soc_dai_ops cs35l41_ops = {
956 .set_fmt = cs35l41_set_dai_fmt,
957 .hw_params = cs35l41_pcm_hw_params,
958 .set_sysclk = cs35l41_dai_set_sysclk,
959 .set_channel_map = cs35l41_set_channel_map,
960 };
961
962 #define CS35L41_RATES ( \
963 SNDRV_PCM_RATE_8000_48000 | \
964 SNDRV_PCM_RATE_12000 | \
965 SNDRV_PCM_RATE_24000 | \
966 SNDRV_PCM_RATE_88200 | \
967 SNDRV_PCM_RATE_96000 | \
968 SNDRV_PCM_RATE_176400 | \
969 SNDRV_PCM_RATE_192000)
970
971 static struct snd_soc_dai_driver cs35l41_dai[] = {
972 {
973 .name = "cs35l41-pcm",
974 .id = 0,
975 .playback = {
976 .stream_name = "AMP Playback",
977 .channels_min = 1,
978 .channels_max = 2,
979 .rates = CS35L41_RATES,
980 .formats = CS35L41_RX_FORMATS,
981 },
982 .capture = {
983 .stream_name = "AMP Capture",
984 .channels_min = 1,
985 .channels_max = 4,
986 .rates = CS35L41_RATES,
987 .formats = CS35L41_TX_FORMATS,
988 },
989 .ops = &cs35l41_ops,
990 .symmetric_rate = 1,
991 },
992 };
993
994 static const struct snd_soc_component_driver soc_component_dev_cs35l41 = {
995 .name = "cs35l41-codec",
996 .probe = cs35l41_component_probe,
997 .remove = cs35l41_component_remove,
998
999 .dapm_widgets = cs35l41_dapm_widgets,
1000 .num_dapm_widgets = ARRAY_SIZE(cs35l41_dapm_widgets),
1001 .dapm_routes = cs35l41_audio_map,
1002 .num_dapm_routes = ARRAY_SIZE(cs35l41_audio_map),
1003
1004 .controls = cs35l41_aud_controls,
1005 .num_controls = ARRAY_SIZE(cs35l41_aud_controls),
1006 .set_sysclk = cs35l41_component_set_sysclk,
1007
1008 .endianness = 1,
1009 };
1010
cs35l41_handle_pdata(struct device * dev,struct cs35l41_hw_cfg * hw_cfg)1011 static int cs35l41_handle_pdata(struct device *dev, struct cs35l41_hw_cfg *hw_cfg)
1012 {
1013 struct cs35l41_gpio_cfg *gpio1 = &hw_cfg->gpio1;
1014 struct cs35l41_gpio_cfg *gpio2 = &hw_cfg->gpio2;
1015 unsigned int val;
1016 int ret;
1017
1018 /* Some ACPI systems received the Shared Boost feature before the upstream driver,
1019 * leaving those systems with deprecated _DSD properties.
1020 * To correctly configure those systems add shared-boost-active and shared-boost-passive
1021 * properties mapped to the correct value in boost-type.
1022 * These two are not DT properties and should not be used in new systems designs.
1023 */
1024 if (device_property_read_bool(dev, "cirrus,shared-boost-active")) {
1025 hw_cfg->bst_type = CS35L41_SHD_BOOST_ACTV;
1026 } else if (device_property_read_bool(dev, "cirrus,shared-boost-passive")) {
1027 hw_cfg->bst_type = CS35L41_SHD_BOOST_PASS;
1028 } else {
1029 ret = device_property_read_u32(dev, "cirrus,boost-type", &val);
1030 if (ret >= 0)
1031 hw_cfg->bst_type = val;
1032 }
1033
1034 ret = device_property_read_u32(dev, "cirrus,boost-peak-milliamp", &val);
1035 if (ret >= 0)
1036 hw_cfg->bst_ipk = val;
1037 else
1038 hw_cfg->bst_ipk = -1;
1039
1040 ret = device_property_read_u32(dev, "cirrus,boost-ind-nanohenry", &val);
1041 if (ret >= 0)
1042 hw_cfg->bst_ind = val;
1043 else
1044 hw_cfg->bst_ind = -1;
1045
1046 ret = device_property_read_u32(dev, "cirrus,boost-cap-microfarad", &val);
1047 if (ret >= 0)
1048 hw_cfg->bst_cap = val;
1049 else
1050 hw_cfg->bst_cap = -1;
1051
1052 ret = device_property_read_u32(dev, "cirrus,asp-sdout-hiz", &val);
1053 if (ret >= 0)
1054 hw_cfg->dout_hiz = val;
1055 else
1056 hw_cfg->dout_hiz = -1;
1057
1058 /* GPIO1 Pin Config */
1059 gpio1->pol_inv = device_property_read_bool(dev, "cirrus,gpio1-polarity-invert");
1060 gpio1->out_en = device_property_read_bool(dev, "cirrus,gpio1-output-enable");
1061 ret = device_property_read_u32(dev, "cirrus,gpio1-src-select", &val);
1062 if (ret >= 0) {
1063 gpio1->func = val;
1064 gpio1->valid = true;
1065 }
1066
1067 /* GPIO2 Pin Config */
1068 gpio2->pol_inv = device_property_read_bool(dev, "cirrus,gpio2-polarity-invert");
1069 gpio2->out_en = device_property_read_bool(dev, "cirrus,gpio2-output-enable");
1070 ret = device_property_read_u32(dev, "cirrus,gpio2-src-select", &val);
1071 if (ret >= 0) {
1072 gpio2->func = val;
1073 gpio2->valid = true;
1074 }
1075
1076 hw_cfg->valid = true;
1077
1078 return 0;
1079 }
1080
cs35l41_dsp_init(struct cs35l41_private * cs35l41)1081 static int cs35l41_dsp_init(struct cs35l41_private *cs35l41)
1082 {
1083 struct wm_adsp *dsp;
1084 uint32_t dsp1rx5_src;
1085 int ret;
1086
1087 dsp = &cs35l41->dsp;
1088 dsp->part = "cs35l41";
1089 dsp->fw = 9; /* 9 is WM_ADSP_FW_SPK_PROT in wm_adsp.c */
1090 dsp->toggle_preload = true;
1091
1092 cs35l41_configure_cs_dsp(cs35l41->dev, cs35l41->regmap, &dsp->cs_dsp);
1093
1094 ret = cs35l41_write_fs_errata(cs35l41->dev, cs35l41->regmap);
1095 if (ret < 0)
1096 return ret;
1097
1098 ret = wm_halo_init(dsp);
1099 if (ret) {
1100 dev_err(cs35l41->dev, "wm_halo_init failed: %d\n", ret);
1101 return ret;
1102 }
1103
1104 switch (cs35l41->hw_cfg.bst_type) {
1105 case CS35L41_INT_BOOST:
1106 case CS35L41_SHD_BOOST_ACTV:
1107 dsp1rx5_src = CS35L41_INPUT_SRC_VPMON;
1108 break;
1109 case CS35L41_EXT_BOOST:
1110 case CS35L41_SHD_BOOST_PASS:
1111 dsp1rx5_src = CS35L41_INPUT_SRC_VBSTMON;
1112 break;
1113 default:
1114 dev_err(cs35l41->dev, "wm_halo_init failed - Invalid Boost Type: %d\n",
1115 cs35l41->hw_cfg.bst_type);
1116 goto err_dsp;
1117 }
1118
1119 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX5_SRC, dsp1rx5_src);
1120 if (ret < 0) {
1121 dev_err(cs35l41->dev, "Write DSP1RX5_SRC: %d failed: %d\n", dsp1rx5_src, ret);
1122 goto err_dsp;
1123 }
1124 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX6_SRC, CS35L41_INPUT_SRC_VBSTMON);
1125 if (ret < 0) {
1126 dev_err(cs35l41->dev, "Write CS35L41_INPUT_SRC_VBSTMON failed: %d\n", ret);
1127 goto err_dsp;
1128 }
1129 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX7_SRC,
1130 CS35L41_INPUT_SRC_TEMPMON);
1131 if (ret < 0) {
1132 dev_err(cs35l41->dev, "Write INPUT_SRC_TEMPMON failed: %d\n", ret);
1133 goto err_dsp;
1134 }
1135 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX8_SRC,
1136 CS35L41_INPUT_SRC_RSVD);
1137 if (ret < 0) {
1138 dev_err(cs35l41->dev, "Write INPUT_SRC_RSVD failed: %d\n", ret);
1139 goto err_dsp;
1140 }
1141
1142 return 0;
1143
1144 err_dsp:
1145 wm_adsp2_remove(dsp);
1146
1147 return ret;
1148 }
1149
1150 #ifdef CONFIG_ACPI
cs35l41_acpi_get_name(struct cs35l41_private * cs35l41)1151 static int cs35l41_acpi_get_name(struct cs35l41_private *cs35l41)
1152 {
1153 struct acpi_device *adev = ACPI_COMPANION(cs35l41->dev);
1154 acpi_handle handle = acpi_device_handle(adev);
1155 const char *hid;
1156 const char *sub;
1157
1158 /* If there is no acpi_device, there is no ACPI for this system, return 0 */
1159 if (!adev)
1160 return 0;
1161
1162 sub = acpi_get_subsystem_id(handle);
1163 if (IS_ERR(sub)) {
1164 /* If no _SUB, fallback to _HID, otherwise fail */
1165 if (PTR_ERR(sub) == -ENODATA) {
1166 hid = acpi_device_hid(adev);
1167 /* If dummy hid, return 0 and fallback to legacy firmware path */
1168 if (!strcmp(hid, "device"))
1169 return 0;
1170 sub = kstrdup(hid, GFP_KERNEL);
1171 if (!sub)
1172 sub = ERR_PTR(-ENOMEM);
1173
1174 } else
1175 return PTR_ERR(sub);
1176 }
1177
1178 cs35l41->dsp.system_name = sub;
1179 dev_dbg(cs35l41->dev, "Subsystem ID: %s\n", cs35l41->dsp.system_name);
1180
1181 return 0;
1182 }
1183 #else
cs35l41_acpi_get_name(struct cs35l41_private * cs35l41)1184 static int cs35l41_acpi_get_name(struct cs35l41_private *cs35l41)
1185 {
1186 return 0;
1187 }
1188 #endif /* CONFIG_ACPI */
1189
cs35l41_probe(struct cs35l41_private * cs35l41,const struct cs35l41_hw_cfg * hw_cfg)1190 int cs35l41_probe(struct cs35l41_private *cs35l41, const struct cs35l41_hw_cfg *hw_cfg)
1191 {
1192 u32 regid, reg_revid, i, mtl_revid, int_status, chipid_match;
1193 int irq_pol = 0;
1194 int ret;
1195
1196 if (hw_cfg) {
1197 cs35l41->hw_cfg = *hw_cfg;
1198 } else {
1199 ret = cs35l41_handle_pdata(cs35l41->dev, &cs35l41->hw_cfg);
1200 if (ret != 0)
1201 return ret;
1202 }
1203
1204 for (i = 0; i < CS35L41_NUM_SUPPLIES; i++)
1205 cs35l41->supplies[i].supply = cs35l41_supplies[i];
1206
1207 ret = devm_regulator_bulk_get(cs35l41->dev, CS35L41_NUM_SUPPLIES,
1208 cs35l41->supplies);
1209 if (ret != 0)
1210 return dev_err_probe(cs35l41->dev, ret,
1211 "Failed to request core supplies\n");
1212
1213 ret = regulator_bulk_enable(CS35L41_NUM_SUPPLIES, cs35l41->supplies);
1214 if (ret != 0)
1215 return dev_err_probe(cs35l41->dev, ret,
1216 "Failed to enable core supplies\n");
1217
1218 /* returning NULL can be an option if in stereo mode */
1219 cs35l41->reset_gpio = devm_gpiod_get_optional(cs35l41->dev, "reset",
1220 GPIOD_OUT_LOW);
1221 if (IS_ERR(cs35l41->reset_gpio)) {
1222 ret = PTR_ERR(cs35l41->reset_gpio);
1223 cs35l41->reset_gpio = NULL;
1224 if (ret == -EBUSY) {
1225 dev_info(cs35l41->dev,
1226 "Reset line busy, assuming shared reset\n");
1227 } else {
1228 dev_err_probe(cs35l41->dev, ret,
1229 "Failed to get reset GPIO\n");
1230 goto err;
1231 }
1232 }
1233 if (cs35l41->reset_gpio) {
1234 /* satisfy minimum reset pulse width spec */
1235 usleep_range(2000, 2100);
1236 gpiod_set_value_cansleep(cs35l41->reset_gpio, 1);
1237 }
1238
1239 usleep_range(2000, 2100);
1240
1241 ret = regmap_read_poll_timeout(cs35l41->regmap, CS35L41_IRQ1_STATUS4,
1242 int_status, int_status & CS35L41_OTP_BOOT_DONE,
1243 1000, 100000);
1244 if (ret) {
1245 dev_err_probe(cs35l41->dev, ret,
1246 "Failed waiting for OTP_BOOT_DONE\n");
1247 goto err;
1248 }
1249
1250 regmap_read(cs35l41->regmap, CS35L41_IRQ1_STATUS3, &int_status);
1251 if (int_status & CS35L41_OTP_BOOT_ERR) {
1252 dev_err(cs35l41->dev, "OTP Boot error\n");
1253 ret = -EINVAL;
1254 goto err;
1255 }
1256
1257 ret = regmap_read(cs35l41->regmap, CS35L41_DEVID, ®id);
1258 if (ret < 0) {
1259 dev_err_probe(cs35l41->dev, ret, "Get Device ID failed\n");
1260 goto err;
1261 }
1262
1263 ret = regmap_read(cs35l41->regmap, CS35L41_REVID, ®_revid);
1264 if (ret < 0) {
1265 dev_err_probe(cs35l41->dev, ret, "Get Revision ID failed\n");
1266 goto err;
1267 }
1268
1269 mtl_revid = reg_revid & CS35L41_MTLREVID_MASK;
1270
1271 /* CS35L41 will have even MTLREVID
1272 * CS35L41R will have odd MTLREVID
1273 */
1274 chipid_match = (mtl_revid % 2) ? CS35L41R_CHIP_ID : CS35L41_CHIP_ID;
1275 if (regid != chipid_match) {
1276 dev_err(cs35l41->dev, "CS35L41 Device ID (%X). Expected ID %X\n",
1277 regid, chipid_match);
1278 ret = -ENODEV;
1279 goto err;
1280 }
1281
1282 cs35l41_test_key_unlock(cs35l41->dev, cs35l41->regmap);
1283
1284 ret = cs35l41_register_errata_patch(cs35l41->dev, cs35l41->regmap, reg_revid);
1285 if (ret)
1286 goto err;
1287
1288 ret = cs35l41_otp_unpack(cs35l41->dev, cs35l41->regmap);
1289 if (ret < 0) {
1290 dev_err_probe(cs35l41->dev, ret, "OTP Unpack failed\n");
1291 goto err;
1292 }
1293
1294 cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap);
1295
1296 irq_pol = cs35l41_gpio_config(cs35l41->regmap, &cs35l41->hw_cfg);
1297
1298 /* Set interrupt masks for critical errors */
1299 regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1,
1300 CS35L41_INT1_MASK_DEFAULT);
1301 if (cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_PASS ||
1302 cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_ACTV)
1303 regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK3, CS35L41_INT3_PLL_LOCK_MASK,
1304 0 << CS35L41_INT3_PLL_LOCK_SHIFT);
1305
1306 ret = devm_request_threaded_irq(cs35l41->dev, cs35l41->irq, NULL, cs35l41_irq,
1307 IRQF_ONESHOT | IRQF_SHARED | irq_pol,
1308 "cs35l41", cs35l41);
1309 if (ret != 0) {
1310 dev_err_probe(cs35l41->dev, ret, "Failed to request IRQ\n");
1311 goto err;
1312 }
1313
1314 ret = cs35l41_set_pdata(cs35l41);
1315 if (ret < 0) {
1316 dev_err_probe(cs35l41->dev, ret, "Set pdata failed\n");
1317 goto err;
1318 }
1319
1320 ret = cs35l41_acpi_get_name(cs35l41);
1321 if (ret < 0)
1322 goto err;
1323
1324 ret = cs35l41_dsp_init(cs35l41);
1325 if (ret < 0)
1326 goto err;
1327
1328 pm_runtime_set_autosuspend_delay(cs35l41->dev, 3000);
1329 pm_runtime_use_autosuspend(cs35l41->dev);
1330 pm_runtime_set_active(cs35l41->dev);
1331 pm_runtime_get_noresume(cs35l41->dev);
1332 pm_runtime_enable(cs35l41->dev);
1333
1334 ret = devm_snd_soc_register_component(cs35l41->dev,
1335 &soc_component_dev_cs35l41,
1336 cs35l41_dai, ARRAY_SIZE(cs35l41_dai));
1337 if (ret < 0) {
1338 dev_err_probe(cs35l41->dev, ret, "Register codec failed\n");
1339 goto err_pm;
1340 }
1341
1342 pm_runtime_put_autosuspend(cs35l41->dev);
1343
1344 dev_info(cs35l41->dev, "Cirrus Logic CS35L41 (%x), Revision: %02X\n",
1345 regid, reg_revid);
1346
1347 return 0;
1348
1349 err_pm:
1350 pm_runtime_dont_use_autosuspend(cs35l41->dev);
1351 pm_runtime_disable(cs35l41->dev);
1352 pm_runtime_put_noidle(cs35l41->dev);
1353
1354 wm_adsp2_remove(&cs35l41->dsp);
1355 err:
1356 cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type);
1357 regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies);
1358 gpiod_set_value_cansleep(cs35l41->reset_gpio, 0);
1359
1360 return ret;
1361 }
1362 EXPORT_SYMBOL_GPL(cs35l41_probe);
1363
cs35l41_remove(struct cs35l41_private * cs35l41)1364 void cs35l41_remove(struct cs35l41_private *cs35l41)
1365 {
1366 pm_runtime_get_sync(cs35l41->dev);
1367 pm_runtime_dont_use_autosuspend(cs35l41->dev);
1368 pm_runtime_disable(cs35l41->dev);
1369
1370 regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 0xFFFFFFFF);
1371 if (cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_PASS ||
1372 cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_ACTV)
1373 regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK3, CS35L41_INT3_PLL_LOCK_MASK,
1374 1 << CS35L41_INT3_PLL_LOCK_SHIFT);
1375 kfree(cs35l41->dsp.system_name);
1376 wm_adsp2_remove(&cs35l41->dsp);
1377 cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type);
1378
1379 pm_runtime_put_noidle(cs35l41->dev);
1380
1381 regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies);
1382 gpiod_set_value_cansleep(cs35l41->reset_gpio, 0);
1383 }
1384 EXPORT_SYMBOL_GPL(cs35l41_remove);
1385
cs35l41_runtime_suspend(struct device * dev)1386 static int cs35l41_runtime_suspend(struct device *dev)
1387 {
1388 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
1389
1390 dev_dbg(cs35l41->dev, "Runtime suspend\n");
1391
1392 if (!cs35l41->dsp.preloaded || !cs35l41->dsp.cs_dsp.running)
1393 return 0;
1394
1395 cs35l41_enter_hibernate(dev, cs35l41->regmap, cs35l41->hw_cfg.bst_type);
1396
1397 regcache_cache_only(cs35l41->regmap, true);
1398 regcache_mark_dirty(cs35l41->regmap);
1399
1400 return 0;
1401 }
1402
cs35l41_runtime_resume(struct device * dev)1403 static int cs35l41_runtime_resume(struct device *dev)
1404 {
1405 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
1406 int ret;
1407
1408 dev_dbg(cs35l41->dev, "Runtime resume\n");
1409
1410 if (!cs35l41->dsp.preloaded || !cs35l41->dsp.cs_dsp.running)
1411 return 0;
1412
1413 regcache_cache_only(cs35l41->regmap, false);
1414
1415 ret = cs35l41_exit_hibernate(cs35l41->dev, cs35l41->regmap);
1416 if (ret)
1417 return ret;
1418
1419 /* Test key needs to be unlocked to allow the OTP settings to re-apply */
1420 cs35l41_test_key_unlock(cs35l41->dev, cs35l41->regmap);
1421 ret = regcache_sync(cs35l41->regmap);
1422 cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap);
1423 if (ret) {
1424 dev_err(cs35l41->dev, "Failed to restore register cache: %d\n", ret);
1425 return ret;
1426 }
1427 cs35l41_init_boost(cs35l41->dev, cs35l41->regmap, &cs35l41->hw_cfg);
1428
1429 return 0;
1430 }
1431
cs35l41_sys_suspend(struct device * dev)1432 static int cs35l41_sys_suspend(struct device *dev)
1433 {
1434 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
1435
1436 dev_dbg(cs35l41->dev, "System suspend, disabling IRQ\n");
1437 disable_irq(cs35l41->irq);
1438
1439 return 0;
1440 }
1441
cs35l41_sys_suspend_noirq(struct device * dev)1442 static int cs35l41_sys_suspend_noirq(struct device *dev)
1443 {
1444 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
1445
1446 dev_dbg(cs35l41->dev, "Late system suspend, reenabling IRQ\n");
1447 enable_irq(cs35l41->irq);
1448
1449 return 0;
1450 }
1451
cs35l41_sys_resume_noirq(struct device * dev)1452 static int cs35l41_sys_resume_noirq(struct device *dev)
1453 {
1454 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
1455
1456 dev_dbg(cs35l41->dev, "Early system resume, disabling IRQ\n");
1457 disable_irq(cs35l41->irq);
1458
1459 return 0;
1460 }
1461
cs35l41_sys_resume(struct device * dev)1462 static int cs35l41_sys_resume(struct device *dev)
1463 {
1464 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
1465
1466 dev_dbg(cs35l41->dev, "System resume, reenabling IRQ\n");
1467 enable_irq(cs35l41->irq);
1468
1469 return 0;
1470 }
1471
1472 EXPORT_GPL_DEV_PM_OPS(cs35l41_pm_ops) = {
1473 RUNTIME_PM_OPS(cs35l41_runtime_suspend, cs35l41_runtime_resume, NULL)
1474
1475 SYSTEM_SLEEP_PM_OPS(cs35l41_sys_suspend, cs35l41_sys_resume)
1476 NOIRQ_SYSTEM_SLEEP_PM_OPS(cs35l41_sys_suspend_noirq, cs35l41_sys_resume_noirq)
1477 };
1478
1479 MODULE_DESCRIPTION("ASoC CS35L41 driver");
1480 MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <david.rhodes@cirrus.com>");
1481 MODULE_LICENSE("GPL");
1482