1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) Huawei Technologies Co., Ltd. 2025. All rights reserved.
3
4 #include <linux/bitfield.h>
5 #include <linux/device.h>
6 #include <linux/io.h>
7
8 #include "hinic3_common.h"
9 #include "hinic3_csr.h"
10 #include "hinic3_hwdev.h"
11 #include "hinic3_hwif.h"
12
13 #define HINIC3_HWIF_READY_TIMEOUT 10000
14 #define HINIC3_DB_AND_OUTBOUND_EN_TIMEOUT 60000
15 #define HINIC3_PCIE_LINK_DOWN 0xFFFFFFFF
16
17 /* config BAR4/5 4MB, DB & DWQE both 2MB */
18 #define HINIC3_DB_DWQE_SIZE 0x00400000
19
20 /* db/dwqe page size: 4K */
21 #define HINIC3_DB_PAGE_SIZE 0x00001000
22 #define HINIC3_DWQE_OFFSET 0x00000800
23 #define HINIC3_DB_MAX_AREAS (HINIC3_DB_DWQE_SIZE / HINIC3_DB_PAGE_SIZE)
24
25 #define HINIC3_MAX_MSIX_ENTRY 2048
26
27 #define HINIC3_AF0_FUNC_GLOBAL_IDX_MASK GENMASK(11, 0)
28 #define HINIC3_AF0_P2P_IDX_MASK GENMASK(16, 12)
29 #define HINIC3_AF0_PCI_INTF_IDX_MASK GENMASK(19, 17)
30 #define HINIC3_AF0_FUNC_TYPE_MASK BIT(28)
31 #define HINIC3_AF0_GET(val, member) \
32 FIELD_GET(HINIC3_AF0_##member##_MASK, val)
33
34 #define HINIC3_AF1_PPF_IDX_MASK GENMASK(5, 0)
35 #define HINIC3_AF1_AEQS_PER_FUNC_MASK GENMASK(9, 8)
36 #define HINIC3_AF1_MGMT_INIT_STATUS_MASK BIT(30)
37 #define HINIC3_AF1_GET(val, member) \
38 FIELD_GET(HINIC3_AF1_##member##_MASK, val)
39
40 #define HINIC3_AF2_CEQS_PER_FUNC_MASK GENMASK(8, 0)
41 #define HINIC3_AF2_IRQS_PER_FUNC_MASK GENMASK(26, 16)
42 #define HINIC3_AF2_GET(val, member) \
43 FIELD_GET(HINIC3_AF2_##member##_MASK, val)
44
45 #define HINIC3_AF3_GLOBAL_VF_ID_OF_PF_MASK GENMASK(27, 16)
46 #define HINIC3_AF3_GET(val, member) \
47 FIELD_GET(HINIC3_AF3_##member##_MASK, val)
48
49 #define HINIC3_AF4_DOORBELL_CTRL_MASK BIT(0)
50 #define HINIC3_AF4_GET(val, member) \
51 FIELD_GET(HINIC3_AF4_##member##_MASK, val)
52 #define HINIC3_AF4_SET(val, member) \
53 FIELD_PREP(HINIC3_AF4_##member##_MASK, val)
54
55 #define HINIC3_AF5_OUTBOUND_CTRL_MASK BIT(0)
56 #define HINIC3_AF5_GET(val, member) \
57 FIELD_GET(HINIC3_AF5_##member##_MASK, val)
58
59 #define HINIC3_AF6_PF_STATUS_MASK GENMASK(15, 0)
60 #define HINIC3_AF6_FUNC_MAX_SQ_MASK GENMASK(31, 23)
61 #define HINIC3_AF6_MSIX_FLEX_EN_MASK BIT(22)
62 #define HINIC3_AF6_SET(val, member) \
63 FIELD_PREP(HINIC3_AF6_##member##_MASK, val)
64 #define HINIC3_AF6_GET(val, member) \
65 FIELD_GET(HINIC3_AF6_##member##_MASK, val)
66
67 #define HINIC3_PPF_ELECTION_IDX_MASK GENMASK(5, 0)
68 #define HINIC3_PPF_ELECTION_SET(val, member) \
69 FIELD_PREP(HINIC3_PPF_ELECTION_##member##_MASK, val)
70 #define HINIC3_PPF_ELECTION_GET(val, member) \
71 FIELD_GET(HINIC3_PPF_ELECTION_##member##_MASK, val)
72
73 #define HINIC3_GET_REG_ADDR(reg) ((reg) & (HINIC3_REGS_FLAG_MASK))
74
hinic3_reg_addr(struct hinic3_hwif * hwif,u32 reg)75 static void __iomem *hinic3_reg_addr(struct hinic3_hwif *hwif, u32 reg)
76 {
77 return hwif->cfg_regs_base + HINIC3_GET_REG_ADDR(reg);
78 }
79
hinic3_hwif_read_reg(struct hinic3_hwif * hwif,u32 reg)80 u32 hinic3_hwif_read_reg(struct hinic3_hwif *hwif, u32 reg)
81 {
82 void __iomem *addr = hinic3_reg_addr(hwif, reg);
83
84 return ioread32be(addr);
85 }
86
hinic3_hwif_write_reg(struct hinic3_hwif * hwif,u32 reg,u32 val)87 void hinic3_hwif_write_reg(struct hinic3_hwif *hwif, u32 reg, u32 val)
88 {
89 void __iomem *addr = hinic3_reg_addr(hwif, reg);
90
91 iowrite32be(val, addr);
92 }
93
check_hwif_ready_handler(void * priv_data)94 static enum hinic3_wait_return check_hwif_ready_handler(void *priv_data)
95 {
96 struct hinic3_hwdev *hwdev = priv_data;
97 u32 attr1;
98
99 attr1 = hinic3_hwif_read_reg(hwdev->hwif, HINIC3_CSR_FUNC_ATTR1_ADDR);
100
101 return HINIC3_AF1_GET(attr1, MGMT_INIT_STATUS) ?
102 HINIC3_WAIT_PROCESS_CPL : HINIC3_WAIT_PROCESS_WAITING;
103 }
104
wait_hwif_ready(struct hinic3_hwdev * hwdev)105 static int wait_hwif_ready(struct hinic3_hwdev *hwdev)
106 {
107 return hinic3_wait_for_timeout(hwdev, check_hwif_ready_handler,
108 HINIC3_HWIF_READY_TIMEOUT,
109 USEC_PER_MSEC);
110 }
111
112 /* Set attr struct from HW attr values. */
set_hwif_attr(struct hinic3_func_attr * attr,u32 attr0,u32 attr1,u32 attr2,u32 attr3,u32 attr6)113 static void set_hwif_attr(struct hinic3_func_attr *attr, u32 attr0, u32 attr1,
114 u32 attr2, u32 attr3, u32 attr6)
115 {
116 attr->func_global_idx = HINIC3_AF0_GET(attr0, FUNC_GLOBAL_IDX);
117 attr->port_to_port_idx = HINIC3_AF0_GET(attr0, P2P_IDX);
118 attr->pci_intf_idx = HINIC3_AF0_GET(attr0, PCI_INTF_IDX);
119 attr->func_type = HINIC3_AF0_GET(attr0, FUNC_TYPE);
120
121 attr->ppf_idx = HINIC3_AF1_GET(attr1, PPF_IDX);
122 attr->num_aeqs = BIT(HINIC3_AF1_GET(attr1, AEQS_PER_FUNC));
123 attr->num_ceqs = HINIC3_AF2_GET(attr2, CEQS_PER_FUNC);
124 attr->num_irqs = HINIC3_AF2_GET(attr2, IRQS_PER_FUNC);
125 if (attr->num_irqs > HINIC3_MAX_MSIX_ENTRY)
126 attr->num_irqs = HINIC3_MAX_MSIX_ENTRY;
127
128 attr->global_vf_id_of_pf = HINIC3_AF3_GET(attr3, GLOBAL_VF_ID_OF_PF);
129
130 attr->num_sq = HINIC3_AF6_GET(attr6, FUNC_MAX_SQ);
131 attr->msix_flex_en = HINIC3_AF6_GET(attr6, MSIX_FLEX_EN);
132 }
133
134 /* Read attributes from HW and set attribute struct. */
init_hwif_attr(struct hinic3_hwdev * hwdev)135 static int init_hwif_attr(struct hinic3_hwdev *hwdev)
136 {
137 u32 attr0, attr1, attr2, attr3, attr6;
138 struct hinic3_hwif *hwif;
139
140 hwif = hwdev->hwif;
141 attr0 = hinic3_hwif_read_reg(hwif, HINIC3_CSR_FUNC_ATTR0_ADDR);
142 if (attr0 == HINIC3_PCIE_LINK_DOWN)
143 return -EFAULT;
144
145 attr1 = hinic3_hwif_read_reg(hwif, HINIC3_CSR_FUNC_ATTR1_ADDR);
146 if (attr1 == HINIC3_PCIE_LINK_DOWN)
147 return -EFAULT;
148
149 attr2 = hinic3_hwif_read_reg(hwif, HINIC3_CSR_FUNC_ATTR2_ADDR);
150 if (attr2 == HINIC3_PCIE_LINK_DOWN)
151 return -EFAULT;
152
153 attr3 = hinic3_hwif_read_reg(hwif, HINIC3_CSR_FUNC_ATTR3_ADDR);
154 if (attr3 == HINIC3_PCIE_LINK_DOWN)
155 return -EFAULT;
156
157 attr6 = hinic3_hwif_read_reg(hwif, HINIC3_CSR_FUNC_ATTR6_ADDR);
158 if (attr6 == HINIC3_PCIE_LINK_DOWN)
159 return -EFAULT;
160
161 set_hwif_attr(&hwif->attr, attr0, attr1, attr2, attr3, attr6);
162
163 if (!hwif->attr.num_ceqs) {
164 dev_err(hwdev->dev, "Ceq num cfg in fw is zero\n");
165 return -EFAULT;
166 }
167
168 if (!hwif->attr.num_irqs) {
169 dev_err(hwdev->dev,
170 "Irq num cfg in fw is zero, msix_flex_en %d\n",
171 hwif->attr.msix_flex_en);
172 return -EFAULT;
173 }
174
175 return 0;
176 }
177
hinic3_get_doorbell_ctrl_status(struct hinic3_hwif * hwif)178 static enum hinic3_doorbell_ctrl hinic3_get_doorbell_ctrl_status(struct hinic3_hwif *hwif)
179 {
180 u32 attr4 = hinic3_hwif_read_reg(hwif, HINIC3_CSR_FUNC_ATTR4_ADDR);
181
182 return HINIC3_AF4_GET(attr4, DOORBELL_CTRL);
183 }
184
hinic3_get_outbound_ctrl_status(struct hinic3_hwif * hwif)185 static enum hinic3_outbound_ctrl hinic3_get_outbound_ctrl_status(struct hinic3_hwif *hwif)
186 {
187 u32 attr5 = hinic3_hwif_read_reg(hwif, HINIC3_CSR_FUNC_ATTR5_ADDR);
188
189 return HINIC3_AF5_GET(attr5, OUTBOUND_CTRL);
190 }
191
hinic3_toggle_doorbell(struct hinic3_hwif * hwif,enum hinic3_doorbell_ctrl flag)192 void hinic3_toggle_doorbell(struct hinic3_hwif *hwif,
193 enum hinic3_doorbell_ctrl flag)
194 {
195 u32 addr, attr4;
196
197 addr = HINIC3_CSR_FUNC_ATTR4_ADDR;
198 attr4 = hinic3_hwif_read_reg(hwif, addr);
199
200 attr4 &= ~HINIC3_AF4_DOORBELL_CTRL_MASK;
201 attr4 |= HINIC3_AF4_SET(flag, DOORBELL_CTRL);
202
203 hinic3_hwif_write_reg(hwif, addr, attr4);
204 }
205
hinic3_set_ppf(struct hinic3_hwdev * hwdev)206 static void hinic3_set_ppf(struct hinic3_hwdev *hwdev)
207 {
208 struct hinic3_hwif *hwif = hwdev->hwif;
209 struct hinic3_func_attr *attr;
210 u32 addr, val;
211
212 if (HINIC3_IS_VF(hwdev))
213 return;
214
215 /* Read Modify Write */
216 attr = &hwif->attr;
217 addr = HINIC3_CSR_PPF_ELECTION_ADDR;
218 val = hinic3_hwif_read_reg(hwif, addr);
219 val &= ~HINIC3_PPF_ELECTION_IDX_MASK;
220 val |= HINIC3_PPF_ELECTION_SET(attr->func_global_idx, IDX);
221 hinic3_hwif_write_reg(hwif, addr, val);
222
223 /* Check PPF index */
224 val = hinic3_hwif_read_reg(hwif, addr);
225 attr->ppf_idx = HINIC3_PPF_ELECTION_GET(val, IDX);
226 }
227
db_area_idx_init(struct hinic3_hwif * hwif,u64 db_base_phy,u8 __iomem * db_base,u64 db_dwqe_len)228 static int db_area_idx_init(struct hinic3_hwif *hwif, u64 db_base_phy,
229 u8 __iomem *db_base, u64 db_dwqe_len)
230 {
231 struct hinic3_db_area *db_area = &hwif->db_area;
232 u32 db_max_areas;
233
234 hwif->db_base_phy = db_base_phy;
235 hwif->db_base = db_base;
236 hwif->db_dwqe_len = db_dwqe_len;
237
238 db_max_areas = db_dwqe_len > HINIC3_DB_DWQE_SIZE ?
239 HINIC3_DB_MAX_AREAS : db_dwqe_len / HINIC3_DB_PAGE_SIZE;
240 db_area->db_bitmap_array = bitmap_zalloc(db_max_areas, GFP_KERNEL);
241 if (!db_area->db_bitmap_array)
242 return -ENOMEM;
243
244 db_area->db_max_areas = db_max_areas;
245 spin_lock_init(&db_area->idx_lock);
246
247 return 0;
248 }
249
db_area_idx_free(struct hinic3_db_area * db_area)250 static void db_area_idx_free(struct hinic3_db_area *db_area)
251 {
252 bitmap_free(db_area->db_bitmap_array);
253 }
254
get_db_idx(struct hinic3_hwif * hwif,u32 * idx)255 static int get_db_idx(struct hinic3_hwif *hwif, u32 *idx)
256 {
257 struct hinic3_db_area *db_area = &hwif->db_area;
258 u32 pg_idx;
259
260 spin_lock(&db_area->idx_lock);
261 pg_idx = find_first_zero_bit(db_area->db_bitmap_array,
262 db_area->db_max_areas);
263 if (pg_idx == db_area->db_max_areas) {
264 spin_unlock(&db_area->idx_lock);
265 return -ENOMEM;
266 }
267 set_bit(pg_idx, db_area->db_bitmap_array);
268 spin_unlock(&db_area->idx_lock);
269
270 *idx = pg_idx;
271
272 return 0;
273 }
274
free_db_idx(struct hinic3_hwif * hwif,u32 idx)275 static void free_db_idx(struct hinic3_hwif *hwif, u32 idx)
276 {
277 struct hinic3_db_area *db_area = &hwif->db_area;
278
279 spin_lock(&db_area->idx_lock);
280 clear_bit(idx, db_area->db_bitmap_array);
281 spin_unlock(&db_area->idx_lock);
282 }
283
hinic3_free_db_addr(struct hinic3_hwdev * hwdev,const u8 __iomem * db_base)284 void hinic3_free_db_addr(struct hinic3_hwdev *hwdev, const u8 __iomem *db_base)
285 {
286 struct hinic3_hwif *hwif;
287 uintptr_t distance;
288 u32 idx;
289
290 hwif = hwdev->hwif;
291 distance = db_base - hwif->db_base;
292 idx = distance / HINIC3_DB_PAGE_SIZE;
293
294 free_db_idx(hwif, idx);
295 }
296
hinic3_alloc_db_addr(struct hinic3_hwdev * hwdev,void __iomem ** db_base,void __iomem ** dwqe_base)297 int hinic3_alloc_db_addr(struct hinic3_hwdev *hwdev, void __iomem **db_base,
298 void __iomem **dwqe_base)
299 {
300 struct hinic3_hwif *hwif;
301 u8 __iomem *addr;
302 u32 idx;
303 int err;
304
305 hwif = hwdev->hwif;
306
307 err = get_db_idx(hwif, &idx);
308 if (err)
309 return err;
310
311 addr = hwif->db_base + idx * HINIC3_DB_PAGE_SIZE;
312 *db_base = addr;
313
314 if (dwqe_base)
315 *dwqe_base = addr + HINIC3_DWQE_OFFSET;
316
317 return 0;
318 }
319
hinic3_set_msix_state(struct hinic3_hwdev * hwdev,u16 msix_idx,enum hinic3_msix_state flag)320 void hinic3_set_msix_state(struct hinic3_hwdev *hwdev, u16 msix_idx,
321 enum hinic3_msix_state flag)
322 {
323 struct hinic3_hwif *hwif;
324 u8 int_msk = 1;
325 u32 mask_bits;
326 u32 addr;
327
328 hwif = hwdev->hwif;
329
330 if (flag)
331 mask_bits = HINIC3_MSI_CLR_INDIR_SET(int_msk, INT_MSK_SET);
332 else
333 mask_bits = HINIC3_MSI_CLR_INDIR_SET(int_msk, INT_MSK_CLR);
334 mask_bits = mask_bits |
335 HINIC3_MSI_CLR_INDIR_SET(msix_idx, SIMPLE_INDIR_IDX);
336
337 addr = HINIC3_CSR_FUNC_MSI_CLR_WR_ADDR;
338 hinic3_hwif_write_reg(hwif, addr, mask_bits);
339 }
340
disable_all_msix(struct hinic3_hwdev * hwdev)341 static void disable_all_msix(struct hinic3_hwdev *hwdev)
342 {
343 u16 num_irqs = hwdev->hwif->attr.num_irqs;
344 u16 i;
345
346 for (i = 0; i < num_irqs; i++)
347 hinic3_set_msix_state(hwdev, i, HINIC3_MSIX_DISABLE);
348 }
349
hinic3_msix_intr_clear_resend_bit(struct hinic3_hwdev * hwdev,u16 msix_idx,u8 clear_resend_en)350 void hinic3_msix_intr_clear_resend_bit(struct hinic3_hwdev *hwdev, u16 msix_idx,
351 u8 clear_resend_en)
352 {
353 struct hinic3_hwif *hwif;
354 u32 msix_ctrl, addr;
355
356 hwif = hwdev->hwif;
357
358 msix_ctrl = HINIC3_MSI_CLR_INDIR_SET(msix_idx, SIMPLE_INDIR_IDX) |
359 HINIC3_MSI_CLR_INDIR_SET(clear_resend_en, RESEND_TIMER_CLR);
360
361 addr = HINIC3_CSR_FUNC_MSI_CLR_WR_ADDR;
362 hinic3_hwif_write_reg(hwif, addr, msix_ctrl);
363 }
364
hinic3_set_msix_auto_mask_state(struct hinic3_hwdev * hwdev,u16 msix_idx,enum hinic3_msix_auto_mask flag)365 void hinic3_set_msix_auto_mask_state(struct hinic3_hwdev *hwdev, u16 msix_idx,
366 enum hinic3_msix_auto_mask flag)
367 {
368 struct hinic3_hwif *hwif;
369 u32 mask_bits;
370 u32 addr;
371
372 hwif = hwdev->hwif;
373
374 if (flag)
375 mask_bits = HINIC3_MSI_CLR_INDIR_SET(1, AUTO_MSK_SET);
376 else
377 mask_bits = HINIC3_MSI_CLR_INDIR_SET(1, AUTO_MSK_CLR);
378
379 mask_bits = mask_bits |
380 HINIC3_MSI_CLR_INDIR_SET(msix_idx, SIMPLE_INDIR_IDX);
381
382 addr = HINIC3_CSR_FUNC_MSI_CLR_WR_ADDR;
383 hinic3_hwif_write_reg(hwif, addr, mask_bits);
384 }
385
check_db_outbound_enable_handler(void * priv_data)386 static enum hinic3_wait_return check_db_outbound_enable_handler(void *priv_data)
387 {
388 enum hinic3_outbound_ctrl outbound_ctrl;
389 struct hinic3_hwif *hwif = priv_data;
390 enum hinic3_doorbell_ctrl db_ctrl;
391
392 db_ctrl = hinic3_get_doorbell_ctrl_status(hwif);
393 outbound_ctrl = hinic3_get_outbound_ctrl_status(hwif);
394 if (outbound_ctrl == ENABLE_OUTBOUND && db_ctrl == ENABLE_DOORBELL)
395 return HINIC3_WAIT_PROCESS_CPL;
396
397 return HINIC3_WAIT_PROCESS_WAITING;
398 }
399
wait_until_doorbell_and_outbound_enabled(struct hinic3_hwif * hwif)400 static int wait_until_doorbell_and_outbound_enabled(struct hinic3_hwif *hwif)
401 {
402 return hinic3_wait_for_timeout(hwif, check_db_outbound_enable_handler,
403 HINIC3_DB_AND_OUTBOUND_EN_TIMEOUT,
404 USEC_PER_MSEC);
405 }
406
hinic3_set_pf_status(struct hinic3_hwif * hwif,enum hinic3_pf_status status)407 void hinic3_set_pf_status(struct hinic3_hwif *hwif,
408 enum hinic3_pf_status status)
409 {
410 u32 attr6 = hinic3_hwif_read_reg(hwif, HINIC3_CSR_FUNC_ATTR6_ADDR);
411
412 attr6 &= ~HINIC3_AF6_PF_STATUS_MASK;
413 attr6 |= HINIC3_AF6_SET(status, PF_STATUS);
414
415 if (hwif->attr.func_type == HINIC3_FUNC_TYPE_VF)
416 return;
417
418 hinic3_hwif_write_reg(hwif, HINIC3_CSR_FUNC_ATTR6_ADDR, attr6);
419 }
420
hinic3_get_pf_status(struct hinic3_hwif * hwif)421 enum hinic3_pf_status hinic3_get_pf_status(struct hinic3_hwif *hwif)
422 {
423 u32 attr6 = hinic3_hwif_read_reg(hwif, HINIC3_CSR_FUNC_ATTR6_ADDR);
424
425 return HINIC3_AF6_GET(attr6, PF_STATUS);
426 }
427
hinic3_init_hwif(struct hinic3_hwdev * hwdev)428 int hinic3_init_hwif(struct hinic3_hwdev *hwdev)
429 {
430 struct hinic3_pcidev *pci_adapter = hwdev->adapter;
431 struct hinic3_hwif *hwif;
432 u32 attr1, attr4, attr5;
433 int err;
434
435 hwif = kzalloc_obj(*hwif);
436 if (!hwif)
437 return -ENOMEM;
438
439 hwdev->hwif = hwif;
440 /* if function is VF, mgmt_regs_base will be NULL */
441 hwif->cfg_regs_base = pci_adapter->mgmt_reg_base ?
442 pci_adapter->cfg_reg_base :
443 (u8 __iomem *)pci_adapter->cfg_reg_base +
444 HINIC3_VF_CFG_REG_OFFSET;
445
446 hwif->intr_regs_base = pci_adapter->intr_reg_base;
447 hwif->mgmt_regs_base = pci_adapter->mgmt_reg_base;
448
449 err = db_area_idx_init(hwif, pci_adapter->db_base_phy,
450 pci_adapter->db_base,
451 pci_adapter->db_dwqe_len);
452 if (err) {
453 dev_err(hwdev->dev, "Failed to init db area.\n");
454 goto err_free_hwif;
455 }
456
457 err = wait_hwif_ready(hwdev);
458 if (err) {
459 attr1 = hinic3_hwif_read_reg(hwif, HINIC3_CSR_FUNC_ATTR1_ADDR);
460 dev_err(hwdev->dev, "Chip status is not ready, attr1:0x%x\n",
461 attr1);
462 goto err_free_db_area_idx;
463 }
464
465 err = init_hwif_attr(hwdev);
466 if (err) {
467 dev_err(hwdev->dev, "Init hwif attr failed\n");
468 goto err_free_db_area_idx;
469 }
470
471 err = wait_until_doorbell_and_outbound_enabled(hwif);
472 if (err) {
473 attr4 = hinic3_hwif_read_reg(hwif, HINIC3_CSR_FUNC_ATTR4_ADDR);
474 attr5 = hinic3_hwif_read_reg(hwif, HINIC3_CSR_FUNC_ATTR5_ADDR);
475 dev_err(hwdev->dev, "HW doorbell/outbound is disabled, attr4 0x%x attr5 0x%x\n",
476 attr4, attr5);
477 goto err_free_db_area_idx;
478 }
479
480 hinic3_set_ppf(hwdev);
481
482 disable_all_msix(hwdev);
483 /* disable mgmt cpu from reporting any event */
484 hinic3_set_pf_status(hwdev->hwif, HINIC3_PF_STATUS_INIT);
485
486 dev_dbg(hwdev->dev, "global_func_idx: %u, func_type: %d, host_id: %u, ppf: %u\n",
487 hwif->attr.func_global_idx, hwif->attr.func_type,
488 hwif->attr.pci_intf_idx, hwif->attr.ppf_idx);
489
490 return 0;
491
492 err_free_db_area_idx:
493 db_area_idx_free(&hwif->db_area);
494 err_free_hwif:
495 kfree(hwif);
496
497 return err;
498 }
499
hinic3_free_hwif(struct hinic3_hwdev * hwdev)500 void hinic3_free_hwif(struct hinic3_hwdev *hwdev)
501 {
502 db_area_idx_free(&hwdev->hwif->db_area);
503 kfree(hwdev->hwif);
504 }
505
hinic3_global_func_id(struct hinic3_hwdev * hwdev)506 u16 hinic3_global_func_id(struct hinic3_hwdev *hwdev)
507 {
508 return hwdev->hwif->attr.func_global_idx;
509 }
510
hinic3_pf_id_of_vf(struct hinic3_hwdev * hwdev)511 u8 hinic3_pf_id_of_vf(struct hinic3_hwdev *hwdev)
512 {
513 return hwdev->hwif->attr.port_to_port_idx;
514 }
515
hinic3_glb_pf_vf_offset(struct hinic3_hwdev * hwdev)516 u16 hinic3_glb_pf_vf_offset(struct hinic3_hwdev *hwdev)
517 {
518 return hwdev->hwif->attr.global_vf_id_of_pf;
519 }
520
hinic3_ppf_idx(struct hinic3_hwdev * hwdev)521 u8 hinic3_ppf_idx(struct hinic3_hwdev *hwdev)
522 {
523 return hwdev->hwif->attr.ppf_idx;
524 }
525