| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/ |
| H A D | dcn10_dpp_cm.c | 92 struct dcn10_dpp *dpp, in program_gamut_remap() 164 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_set_gamut_remap() local 184 static void read_gamut_remap(struct dcn10_dpp *dpp, in read_gamut_remap() 236 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_get_gamut_remap() local 253 struct dcn10_dpp *dpp, in dpp1_cm_program_color_matrix() 311 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_set_output_csc_default() local 325 struct dcn10_dpp *dpp, in dpp1_cm_get_reg_field() 352 struct dcn10_dpp *dpp, in dpp1_cm_get_degamma_reg_field() 381 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_set_output_csc_adjustment() local 389 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_power_on_regamma_lut() local [all …]
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| H A D | dcn10_dpp_dscl.c | 161 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_power_on_dscl() local 180 struct dcn10_dpp *dpp, in dpp1_dscl_set_lb() 241 struct dcn10_dpp *dpp, in dpp1_dscl_set_scaler_filter() 279 struct dcn10_dpp *dpp, in dpp1_dscl_set_scl_filter() 459 static enum lb_memory_config dpp1_dscl_find_lb_memory_config(struct dcn10_dpp *dpp, in dpp1_dscl_find_lb_memory_config() 511 struct dcn10_dpp *dpp, const struct scaler_data *data) in dpp1_dscl_set_manual_ratio_init() 587 static void dpp1_dscl_set_recout(struct dcn10_dpp *dpp, in dpp1_dscl_set_recout() 617 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_dscl_set_scaler_manual_scale() local
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/ |
| H A D | dcn20_dpp_cm.c | 53 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_enable_cm_block() local 70 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_degamma_ram_inuse() local 93 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_program_degamma_lut() local 138 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_set_degamma() local 162 struct dcn20_dpp *dpp, in program_gamut_remap() 217 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_cm_set_gamut_remap() local 237 static void read_gamut_remap(struct dcn20_dpp *dpp, in read_gamut_remap() 276 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_cm_get_gamut_remap() local 298 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_program_input_csc() local 369 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp20_power_on_blnd_lut() local [all …]
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| H A D | dcn20_dpp.c | 54 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp20_read_state() local 81 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_power_on_obuf() local 105 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_cnv_setup() local 320 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_cnv_set_alpha_keyer() local 344 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_set_cursor_attributes() local 369 struct dpp *dpp, in oppn20_dummy_program_regamma_pwl() 407 struct dcn20_dpp *dpp, in dpp2_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/ |
| H A D | dcn30_dpp.c | 46 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp30_read_state() local 89 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp30_read_reg_state() local 110 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_program_post_csc() local 180 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_set_pre_degam() local 228 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_cnv_setup() local 405 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_set_cursor_attributes() local 439 struct dpp *dpp, in dpp3_get_optimal_number_of_taps() 543 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_deferred_update() local 591 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_power_on_blnd_lut() local 608 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_power_on_hdr3dlut() local [all …]
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| H A D | dcn30_dpp_cm.c | 46 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_enable_cm_block() local 62 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp30_get_gamcor_current() local 84 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_program_gammcor_lut() local 130 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_power_on_gamcor_lut() local 149 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_program_cm_dealpha() local 160 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_program_cm_bias() local 169 struct dcn3_dpp *dpp, in dpp3_gamcor_reg_field() 205 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_configure_gamcor_lut() local 220 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_program_gamcor_lut() local 308 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_set_hdr_multiplier() local [all …]
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| H A D | dcn30_dpp.h | 30 #define TO_DCN30_DPP(dpp)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/ |
| H A D | dcn201_dpp.c | 52 struct dcn201_dpp *dpp = TO_DCN201_DPP(dpp_base); in dpp201_cnv_setup() local 191 struct dpp *dpp, in dpp201_get_optimal_number_of_taps() 298 struct dcn201_dpp *dpp, in dpp201_construct()
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| H A D | dcn201_dpp.h | 30 #define TO_DCN201_DPP(dpp)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn401/ |
| H A D | dcn401_dpp.c | 47 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp401_read_state() local 63 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); in dpp401_dpp_setup() local 263 struct dcn401_dpp *dpp, in dpp401_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| H A D | dcn201_hwseq.c | 291 struct dpp *dpp = res_pool->dpps[i]; in dcn201_init_hw() local 311 struct dpp *dpp = res_pool->dpps[i]; in dcn201_init_hw() local
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/ |
| H A D | dcn35_hwseq.c | 695 struct dpp *dpp = dc->res_pool->dpps[i]; in dcn35_init_pipes() local 819 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn35_enable_plane() local 859 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn35_plane_atomic_disable() local 1677 const struct dpp *dpp = pipe->plane_res.dpp; in dcn35_update_cursor_offload_pipe() local
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| H A D | dcn10_hwseq.c | 464 struct dpp *dpp = pool->dpps[i]; in dcn10_log_color_state() local 1489 struct dpp *dpp, in dcn10_plane_atomic_power_down() 1525 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn10_plane_atomic_disable() local 1643 struct dpp *dpp = dc->res_pool->dpps[i]; in dcn10_init_pipes() local 2113 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn10_set_output_transfer_func() local 2858 static void dcn10_update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state) in dcn10_update_dpp() 2984 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn10_update_dchubp_dpp() local 3650 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn10_set_cursor_position() local
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_hw_sequencer.c | 1740 struct dpp *dpp, uint32_t hw_mult) in hwss_add_dpp_set_hdr_multiplier() 1948 struct dpp *dpp = pipe_ctx->plane_res.dpp; in hwss_setup_dpp() local 1968 struct dpp *dpp = pipe_ctx->plane_res.dpp; in hwss_program_bias_and_scale() local 2407 struct dpp *dpp = params->dpp_set_hdr_multiplier_params.dpp; in hwss_dpp_set_hdr_multiplier() local 2820 struct dpp *dpp = params->dpp_dppclk_control_params.dpp; in hwss_dpp_dppclk_control() local 2915 struct dpp *dpp = params->dpp_reset_params.dpp; in hwss_dpp_reset() local 3013 struct dpp *dpp = params->dpp_set_cursor_matrix_params.dpp; in hwss_dpp_set_cursor_matrix() local 3067 struct dpp *dpp = params->dpp_set_scaler_params.dpp; in hwss_dpp_set_scaler() local 3594 struct dpp *dpp, in hwss_add_dpp_dppclk_control() 3732 struct dpp *dpp) in hwss_add_dpp_reset() [all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.c | 90 struct dpp *dpp = pool->dpps[i]; in dcn20_log_color_state() local 699 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn20_plane_atomic_disable() local 1671 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn20_update_dchubp_dpp() local 3167 struct dpp *dpp = res_pool->dpps[i]; in dcn20_fpga_init_hw() local 3187 struct dpp *dpp = dc->res_pool->dpps[i]; in dcn20_fpga_init_hw() local
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| H A D | dcn30_hwseq.c | 91 struct dpp *dpp = pool->dpps[i]; in dcn30_log_color_state() local 1250 struct dpp *dpp = dc->res_pool->dpps[i]; in dcn30_get_underflow_debug_data() local
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| /linux/arch/sparc/vdso/ |
| H A D | vma.c | 251 struct page *dp, **dpp = NULL; in init_vdso_image() local
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| /linux/fs/xfs/scrub/ |
| H A D | parent.c | 414 struct xfs_inode **dpp) in xchk_parent_iget()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/ |
| H A D | hw_sequencer.h | 311 struct dpp *dpp; member 568 struct dpp *dpp; member 594 struct dpp *dpp; member 673 struct dpp *dpp; member 684 struct dpp *dpp; member
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_dmub_srv.c | 1068 const struct hubp *hubp, const struct dpp *dpp) in dc_build_cursor_position_update_payload0() 1083 const struct hubp *hubp, const struct dpp *dpp) in dc_build_cursor_attribute_update_payload1()
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| H A D | dc.h | 274 struct dpp_color_caps dpp; member 807 bool dpp: 1; member 827 bool dpp : 1; /* Display pipes and planes */ member 2997 } dpp[MAX_PIPES]; member
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| H A D | dcn401_resource.c | 942 static void dcn401_dpp_destroy(struct dpp **dpp) in dcn401_dpp_destroy()
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| /linux/fs/nfsd/ |
| H A D | vfs.c | 125 nfsd_cross_mnt(struct svc_rqst *rqstp, struct dentry **dpp, in nfsd_cross_mnt()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | core_types.h | 383 struct dpp *dpp; member
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