1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Rockchip USBDP Combo PHY with Samsung IP block driver
4 *
5 * Copyright (C) 2021-2024 Rockchip Electronics Co., Ltd
6 * Copyright (C) 2024 Collabora Ltd
7 */
8
9 #include <dt-bindings/phy/phy.h>
10 #include <linux/bitfield.h>
11 #include <linux/bits.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/module.h>
17 #include <linux/mutex.h>
18 #include <linux/phy/phy.h>
19 #include <linux/platform_device.h>
20 #include <linux/property.h>
21 #include <linux/regmap.h>
22 #include <linux/reset.h>
23 #include <linux/usb/ch9.h>
24 #include <linux/usb/typec_dp.h>
25 #include <linux/usb/typec_mux.h>
26
27 /* USBDP PHY Register Definitions */
28 #define UDPHY_PCS 0x4000
29 #define UDPHY_PMA 0x8000
30
31 /* VO0 GRF Registers */
32 #define DP_SINK_HPD_CFG BIT(11)
33 #define DP_SINK_HPD_SEL BIT(10)
34 #define DP_AUX_DIN_SEL BIT(9)
35 #define DP_AUX_DOUT_SEL BIT(8)
36 #define DP_LANE_SEL_N(n) GENMASK(2 * (n) + 1, 2 * (n))
37 #define DP_LANE_SEL_ALL GENMASK(7, 0)
38
39 /* PMA CMN Registers */
40 #define CMN_LANE_MUX_AND_EN_OFFSET 0x0288 /* cmn_reg00A2 */
41 #define CMN_DP_LANE_MUX_N(n) BIT((n) + 4)
42 #define CMN_DP_LANE_EN_N(n) BIT(n)
43 #define CMN_DP_LANE_MUX_ALL GENMASK(7, 4)
44 #define CMN_DP_LANE_EN_ALL GENMASK(3, 0)
45
46 #define CMN_DP_LINK_OFFSET 0x28c /* cmn_reg00A3 */
47 #define CMN_DP_TX_LINK_BW GENMASK(6, 5)
48 #define CMN_DP_TX_LANE_SWAP_EN BIT(2)
49
50 #define CMN_SSC_EN_OFFSET 0x2d0 /* cmn_reg00B4 */
51 #define CMN_ROPLL_SSC_EN BIT(1)
52 #define CMN_LCPLL_SSC_EN BIT(0)
53
54 #define CMN_ANA_LCPLL_DONE_OFFSET 0x0350 /* cmn_reg00D4 */
55 #define CMN_ANA_LCPLL_LOCK_DONE BIT(7)
56 #define CMN_ANA_LCPLL_AFC_DONE BIT(6)
57
58 #define CMN_ANA_ROPLL_DONE_OFFSET 0x0354 /* cmn_reg00D5 */
59 #define CMN_ANA_ROPLL_LOCK_DONE BIT(1)
60 #define CMN_ANA_ROPLL_AFC_DONE BIT(0)
61
62 #define CMN_DP_RSTN_OFFSET 0x038c /* cmn_reg00E3 */
63 #define CMN_DP_INIT_RSTN BIT(3)
64 #define CMN_DP_CMN_RSTN BIT(2)
65 #define CMN_CDR_WTCHDG_EN BIT(1)
66 #define CMN_CDR_WTCHDG_MSK_CDR_EN BIT(0)
67
68 #define TRSV_ANA_TX_CLK_OFFSET_N(n) (0x854 + (n) * 0x800) /* trsv_reg0215 */
69 #define LN_ANA_TX_SER_TXCLK_INV BIT(1)
70
71 #define TRSV_LN0_MON_RX_CDR_DONE_OFFSET 0x0b84 /* trsv_reg02E1 */
72 #define TRSV_LN0_MON_RX_CDR_LOCK_DONE BIT(0)
73
74 #define TRSV_LN2_MON_RX_CDR_DONE_OFFSET 0x1b84 /* trsv_reg06E1 */
75 #define TRSV_LN2_MON_RX_CDR_LOCK_DONE BIT(0)
76
77 #define BIT_WRITEABLE_SHIFT 16
78 #define PHY_AUX_DP_DATA_POL_NORMAL 0
79 #define PHY_AUX_DP_DATA_POL_INVERT 1
80 #define PHY_LANE_MUX_USB 0
81 #define PHY_LANE_MUX_DP 1
82
83 enum {
84 DP_BW_RBR,
85 DP_BW_HBR,
86 DP_BW_HBR2,
87 DP_BW_HBR3,
88 };
89
90 enum {
91 UDPHY_MODE_NONE = 0,
92 UDPHY_MODE_USB = BIT(0),
93 UDPHY_MODE_DP = BIT(1),
94 UDPHY_MODE_DP_USB = BIT(1) | BIT(0),
95 };
96
97 struct rk_udphy_grf_reg {
98 unsigned int offset;
99 unsigned int disable;
100 unsigned int enable;
101 };
102
103 #define _RK_UDPHY_GEN_GRF_REG(offset, mask, disable, enable) \
104 {\
105 offset, \
106 FIELD_PREP_CONST(mask, disable) | (mask << BIT_WRITEABLE_SHIFT), \
107 FIELD_PREP_CONST(mask, enable) | (mask << BIT_WRITEABLE_SHIFT), \
108 }
109
110 #define RK_UDPHY_GEN_GRF_REG(offset, bitend, bitstart, disable, enable) \
111 _RK_UDPHY_GEN_GRF_REG(offset, GENMASK(bitend, bitstart), disable, enable)
112
113 struct rk_udphy_grf_cfg {
114 /* u2phy-grf */
115 struct rk_udphy_grf_reg bvalid_phy_con;
116 struct rk_udphy_grf_reg bvalid_grf_con;
117
118 /* usb-grf */
119 struct rk_udphy_grf_reg usb3otg0_cfg;
120 struct rk_udphy_grf_reg usb3otg1_cfg;
121
122 /* usbdpphy-grf */
123 struct rk_udphy_grf_reg low_pwrn;
124 struct rk_udphy_grf_reg rx_lfps;
125 };
126
127 struct rk_udphy_vogrf_cfg {
128 /* vo-grf */
129 struct rk_udphy_grf_reg hpd_trigger;
130 u32 dp_lane_reg;
131 };
132
133 struct rk_udphy_dp_tx_drv_ctrl {
134 u32 trsv_reg0204;
135 u32 trsv_reg0205;
136 u32 trsv_reg0206;
137 u32 trsv_reg0207;
138 };
139
140 struct rk_udphy_cfg {
141 unsigned int num_phys;
142 unsigned int phy_ids[2];
143 /* resets to be requested */
144 const char * const *rst_list;
145 int num_rsts;
146
147 struct rk_udphy_grf_cfg grfcfg;
148 struct rk_udphy_vogrf_cfg vogrfcfg[2];
149 const struct rk_udphy_dp_tx_drv_ctrl (*dp_tx_ctrl_cfg[4])[4];
150 const struct rk_udphy_dp_tx_drv_ctrl (*dp_tx_ctrl_cfg_typec[4])[4];
151 };
152
153 struct rk_udphy {
154 struct device *dev;
155 struct regmap *pma_regmap;
156 struct regmap *u2phygrf;
157 struct regmap *udphygrf;
158 struct regmap *usbgrf;
159 struct regmap *vogrf;
160 struct typec_switch_dev *sw;
161 struct typec_mux_dev *mux;
162 struct mutex mutex; /* mutex to protect access to individual PHYs */
163
164 /* clocks and rests */
165 int num_clks;
166 struct clk_bulk_data *clks;
167 struct clk *refclk;
168 int num_rsts;
169 struct reset_control_bulk_data *rsts;
170
171 /* PHY status management */
172 bool flip;
173 bool mode_change;
174 u8 mode;
175 u8 status;
176
177 /* utilized for USB */
178 bool hs; /* flag for high-speed */
179
180 /* utilized for DP */
181 struct gpio_desc *sbu1_dc_gpio;
182 struct gpio_desc *sbu2_dc_gpio;
183 u32 lane_mux_sel[4];
184 u32 dp_lane_sel[4];
185 u32 dp_aux_dout_sel;
186 u32 dp_aux_din_sel;
187 bool dp_sink_hpd_sel;
188 bool dp_sink_hpd_cfg;
189 unsigned int link_rate;
190 unsigned int lanes;
191 u8 bw;
192 int id;
193
194 bool dp_in_use;
195
196 /* PHY const config */
197 const struct rk_udphy_cfg *cfgs;
198
199 /* PHY devices */
200 struct phy *phy_dp;
201 struct phy *phy_u3;
202 };
203
204 static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr[4][4] = {
205 /* voltage swing 0, pre-emphasis 0->3 */
206 {
207 { 0x20, 0x10, 0x42, 0xe5 },
208 { 0x26, 0x14, 0x42, 0xe5 },
209 { 0x29, 0x18, 0x42, 0xe5 },
210 { 0x2b, 0x1c, 0x43, 0xe7 },
211 },
212
213 /* voltage swing 1, pre-emphasis 0->2 */
214 {
215 { 0x23, 0x10, 0x42, 0xe7 },
216 { 0x2a, 0x17, 0x43, 0xe7 },
217 { 0x2b, 0x1a, 0x43, 0xe7 },
218 },
219
220 /* voltage swing 2, pre-emphasis 0->1 */
221 {
222 { 0x27, 0x10, 0x42, 0xe7 },
223 { 0x2b, 0x17, 0x43, 0xe7 },
224 },
225
226 /* voltage swing 3, pre-emphasis 0 */
227 {
228 { 0x29, 0x10, 0x43, 0xe7 },
229 },
230 };
231
232 static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr_typec[4][4] = {
233 /* voltage swing 0, pre-emphasis 0->3 */
234 {
235 { 0x20, 0x10, 0x42, 0xe5 },
236 { 0x26, 0x14, 0x42, 0xe5 },
237 { 0x29, 0x18, 0x42, 0xe5 },
238 { 0x2b, 0x1c, 0x43, 0xe7 },
239 },
240
241 /* voltage swing 1, pre-emphasis 0->2 */
242 {
243 { 0x23, 0x10, 0x42, 0xe7 },
244 { 0x2a, 0x17, 0x43, 0xe7 },
245 { 0x2b, 0x1a, 0x43, 0xe7 },
246 },
247
248 /* voltage swing 2, pre-emphasis 0->1 */
249 {
250 { 0x27, 0x10, 0x43, 0x67 },
251 { 0x2b, 0x17, 0x43, 0xe7 },
252 },
253
254 /* voltage swing 3, pre-emphasis 0 */
255 {
256 { 0x29, 0x10, 0x43, 0xe7 },
257 },
258 };
259
260 static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr2[4][4] = {
261 /* voltage swing 0, pre-emphasis 0->3 */
262 {
263 { 0x21, 0x10, 0x42, 0xe5 },
264 { 0x26, 0x14, 0x42, 0xe5 },
265 { 0x26, 0x16, 0x43, 0xe5 },
266 { 0x2a, 0x19, 0x43, 0xe7 },
267 },
268
269 /* voltage swing 1, pre-emphasis 0->2 */
270 {
271 { 0x24, 0x10, 0x42, 0xe7 },
272 { 0x2a, 0x17, 0x43, 0xe7 },
273 { 0x2b, 0x1a, 0x43, 0xe7 },
274 },
275
276 /* voltage swing 2, pre-emphasis 0->1 */
277 {
278 { 0x28, 0x10, 0x42, 0xe7 },
279 { 0x2b, 0x17, 0x43, 0xe7 },
280 },
281
282 /* voltage swing 3, pre-emphasis 0 */
283 {
284 { 0x28, 0x10, 0x43, 0xe7 },
285 },
286 };
287
288 static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr3[4][4] = {
289 /* voltage swing 0, pre-emphasis 0->3 */
290 {
291 { 0x21, 0x10, 0x42, 0xe5 },
292 { 0x26, 0x14, 0x42, 0xe5 },
293 { 0x26, 0x16, 0x43, 0xe5 },
294 { 0x29, 0x18, 0x43, 0xe7 },
295 },
296
297 /* voltage swing 1, pre-emphasis 0->2 */
298 {
299 { 0x24, 0x10, 0x42, 0xe7 },
300 { 0x2a, 0x18, 0x43, 0xe7 },
301 { 0x2b, 0x1b, 0x43, 0xe7 }
302 },
303
304 /* voltage swing 2, pre-emphasis 0->1 */
305 {
306 { 0x27, 0x10, 0x42, 0xe7 },
307 { 0x2b, 0x18, 0x43, 0xe7 }
308 },
309
310 /* voltage swing 3, pre-emphasis 0 */
311 {
312 { 0x28, 0x10, 0x43, 0xe7 },
313 },
314 };
315
316 static const struct reg_sequence rk_udphy_24m_refclk_cfg[] = {
317 {0x0090, 0x68}, {0x0094, 0x68},
318 {0x0128, 0x24}, {0x012c, 0x44},
319 {0x0130, 0x3f}, {0x0134, 0x44},
320 {0x015c, 0xa9}, {0x0160, 0x71},
321 {0x0164, 0x71}, {0x0168, 0xa9},
322 {0x0174, 0xa9}, {0x0178, 0x71},
323 {0x017c, 0x71}, {0x0180, 0xa9},
324 {0x018c, 0x41}, {0x0190, 0x00},
325 {0x0194, 0x05}, {0x01ac, 0x2a},
326 {0x01b0, 0x17}, {0x01b4, 0x17},
327 {0x01b8, 0x2a}, {0x01c8, 0x04},
328 {0x01cc, 0x08}, {0x01d0, 0x08},
329 {0x01d4, 0x04}, {0x01d8, 0x20},
330 {0x01dc, 0x01}, {0x01e0, 0x09},
331 {0x01e4, 0x03}, {0x01f0, 0x29},
332 {0x01f4, 0x02}, {0x01f8, 0x02},
333 {0x01fc, 0x29}, {0x0208, 0x2a},
334 {0x020c, 0x17}, {0x0210, 0x17},
335 {0x0214, 0x2a}, {0x0224, 0x20},
336 {0x03f0, 0x0a}, {0x03f4, 0x07},
337 {0x03f8, 0x07}, {0x03fc, 0x0c},
338 {0x0404, 0x12}, {0x0408, 0x1a},
339 {0x040c, 0x1a}, {0x0410, 0x3f},
340 {0x0ce0, 0x68}, {0x0ce8, 0xd0},
341 {0x0cf0, 0x87}, {0x0cf8, 0x70},
342 {0x0d00, 0x70}, {0x0d08, 0xa9},
343 {0x1ce0, 0x68}, {0x1ce8, 0xd0},
344 {0x1cf0, 0x87}, {0x1cf8, 0x70},
345 {0x1d00, 0x70}, {0x1d08, 0xa9},
346 {0x0a3c, 0xd0}, {0x0a44, 0xd0},
347 {0x0a48, 0x01}, {0x0a4c, 0x0d},
348 {0x0a54, 0xe0}, {0x0a5c, 0xe0},
349 {0x0a64, 0xa8}, {0x1a3c, 0xd0},
350 {0x1a44, 0xd0}, {0x1a48, 0x01},
351 {0x1a4c, 0x0d}, {0x1a54, 0xe0},
352 {0x1a5c, 0xe0}, {0x1a64, 0xa8}
353 };
354
355 static const struct reg_sequence rk_udphy_26m_refclk_cfg[] = {
356 {0x0830, 0x07}, {0x085c, 0x80},
357 {0x1030, 0x07}, {0x105c, 0x80},
358 {0x1830, 0x07}, {0x185c, 0x80},
359 {0x2030, 0x07}, {0x205c, 0x80},
360 {0x0228, 0x38}, {0x0104, 0x44},
361 {0x0248, 0x44}, {0x038c, 0x02},
362 {0x0878, 0x04}, {0x1878, 0x04},
363 {0x0898, 0x77}, {0x1898, 0x77},
364 {0x0054, 0x01}, {0x00e0, 0x38},
365 {0x0060, 0x24}, {0x0064, 0x77},
366 {0x0070, 0x76}, {0x0234, 0xe8},
367 {0x0af4, 0x15}, {0x1af4, 0x15},
368 {0x081c, 0xe5}, {0x181c, 0xe5},
369 {0x099c, 0x48}, {0x199c, 0x48},
370 {0x09a4, 0x07}, {0x09a8, 0x22},
371 {0x19a4, 0x07}, {0x19a8, 0x22},
372 {0x09b8, 0x3e}, {0x19b8, 0x3e},
373 {0x09e4, 0x02}, {0x19e4, 0x02},
374 {0x0a34, 0x1e}, {0x1a34, 0x1e},
375 {0x0a98, 0x2f}, {0x1a98, 0x2f},
376 {0x0c30, 0x0e}, {0x0c48, 0x06},
377 {0x1c30, 0x0e}, {0x1c48, 0x06},
378 {0x028c, 0x18}, {0x0af0, 0x00},
379 {0x1af0, 0x00}
380 };
381
382 static const struct reg_sequence rk_udphy_init_sequence[] = {
383 {0x0104, 0x44}, {0x0234, 0xe8},
384 {0x0248, 0x44}, {0x028c, 0x18},
385 {0x081c, 0xe5}, {0x0878, 0x00},
386 {0x0994, 0x1c}, {0x0af0, 0x00},
387 {0x181c, 0xe5}, {0x1878, 0x00},
388 {0x1994, 0x1c}, {0x1af0, 0x00},
389 {0x0428, 0x60}, {0x0d58, 0x33},
390 {0x1d58, 0x33}, {0x0990, 0x74},
391 {0x0d64, 0x17}, {0x08c8, 0x13},
392 {0x1990, 0x74}, {0x1d64, 0x17},
393 {0x18c8, 0x13}, {0x0d90, 0x40},
394 {0x0da8, 0x40}, {0x0dc0, 0x40},
395 {0x0dd8, 0x40}, {0x1d90, 0x40},
396 {0x1da8, 0x40}, {0x1dc0, 0x40},
397 {0x1dd8, 0x40}, {0x03c0, 0x30},
398 {0x03c4, 0x06}, {0x0e10, 0x00},
399 {0x1e10, 0x00}, {0x043c, 0x0f},
400 {0x0d2c, 0xff}, {0x1d2c, 0xff},
401 {0x0d34, 0x0f}, {0x1d34, 0x0f},
402 {0x08fc, 0x2a}, {0x0914, 0x28},
403 {0x0a30, 0x03}, {0x0e38, 0x03},
404 {0x0ecc, 0x27}, {0x0ed0, 0x22},
405 {0x0ed4, 0x26}, {0x18fc, 0x2a},
406 {0x1914, 0x28}, {0x1a30, 0x03},
407 {0x1e38, 0x03}, {0x1ecc, 0x27},
408 {0x1ed0, 0x22}, {0x1ed4, 0x26},
409 {0x0048, 0x0f}, {0x0060, 0x3c},
410 {0x0064, 0xf7}, {0x006c, 0x20},
411 {0x0070, 0x7d}, {0x0074, 0x68},
412 {0x0af4, 0x1a}, {0x1af4, 0x1a},
413 {0x0440, 0x3f}, {0x10d4, 0x08},
414 {0x20d4, 0x08}, {0x00d4, 0x30},
415 {0x0024, 0x6e},
416 };
417
rk_udphy_grfreg_write(struct regmap * base,const struct rk_udphy_grf_reg * reg,bool en)418 static inline int rk_udphy_grfreg_write(struct regmap *base,
419 const struct rk_udphy_grf_reg *reg, bool en)
420 {
421 return regmap_write(base, reg->offset, en ? reg->enable : reg->disable);
422 }
423
rk_udphy_clk_init(struct rk_udphy * udphy,struct device * dev)424 static int rk_udphy_clk_init(struct rk_udphy *udphy, struct device *dev)
425 {
426 int i;
427
428 udphy->num_clks = devm_clk_bulk_get_all(dev, &udphy->clks);
429 if (udphy->num_clks < 1)
430 return -ENODEV;
431
432 /* used for configure phy reference clock frequency */
433 for (i = 0; i < udphy->num_clks; i++) {
434 if (!strncmp(udphy->clks[i].id, "refclk", 6)) {
435 udphy->refclk = udphy->clks[i].clk;
436 break;
437 }
438 }
439
440 if (!udphy->refclk)
441 return dev_err_probe(udphy->dev, -EINVAL, "no refclk found\n");
442
443 return 0;
444 }
445
rk_udphy_reset_assert_all(struct rk_udphy * udphy)446 static int rk_udphy_reset_assert_all(struct rk_udphy *udphy)
447 {
448 return reset_control_bulk_assert(udphy->num_rsts, udphy->rsts);
449 }
450
rk_udphy_reset_deassert_all(struct rk_udphy * udphy)451 static int rk_udphy_reset_deassert_all(struct rk_udphy *udphy)
452 {
453 return reset_control_bulk_deassert(udphy->num_rsts, udphy->rsts);
454 }
455
rk_udphy_reset_deassert(struct rk_udphy * udphy,char * name)456 static int rk_udphy_reset_deassert(struct rk_udphy *udphy, char *name)
457 {
458 struct reset_control_bulk_data *list = udphy->rsts;
459 int idx;
460
461 for (idx = 0; idx < udphy->num_rsts; idx++) {
462 if (!strcmp(list[idx].id, name))
463 return reset_control_deassert(list[idx].rstc);
464 }
465
466 return -EINVAL;
467 }
468
rk_udphy_reset_init(struct rk_udphy * udphy,struct device * dev)469 static int rk_udphy_reset_init(struct rk_udphy *udphy, struct device *dev)
470 {
471 const struct rk_udphy_cfg *cfg = udphy->cfgs;
472 int idx;
473
474 udphy->num_rsts = cfg->num_rsts;
475 udphy->rsts = devm_kcalloc(dev, udphy->num_rsts,
476 sizeof(*udphy->rsts), GFP_KERNEL);
477 if (!udphy->rsts)
478 return -ENOMEM;
479
480 for (idx = 0; idx < cfg->num_rsts; idx++)
481 udphy->rsts[idx].id = cfg->rst_list[idx];
482
483 return devm_reset_control_bulk_get_exclusive(dev, cfg->num_rsts,
484 udphy->rsts);
485 }
486
rk_udphy_u3_port_disable(struct rk_udphy * udphy,u8 disable)487 static void rk_udphy_u3_port_disable(struct rk_udphy *udphy, u8 disable)
488 {
489 const struct rk_udphy_cfg *cfg = udphy->cfgs;
490 const struct rk_udphy_grf_reg *preg;
491
492 preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg;
493 rk_udphy_grfreg_write(udphy->usbgrf, preg, disable);
494 }
495
rk_udphy_usb_bvalid_enable(struct rk_udphy * udphy,u8 enable)496 static void rk_udphy_usb_bvalid_enable(struct rk_udphy *udphy, u8 enable)
497 {
498 const struct rk_udphy_cfg *cfg = udphy->cfgs;
499
500 rk_udphy_grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable);
501 rk_udphy_grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable);
502 }
503
504 /*
505 * In usb/dp combo phy driver, here are 2 ways to mapping lanes.
506 *
507 * 1 Type-C Mapping table (DP_Alt_Mode V1.0b remove ABF pin mapping)
508 * ---------------------------------------------------------------------------
509 * Type-C Pin B11-B10 A2-A3 A11-A10 B2-B3
510 * PHY Pad ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
511 * C/E(Normal) dpln3 dpln2 dpln0 dpln1
512 * C/E(Flip ) dpln0 dpln1 dpln3 dpln2
513 * D/F(Normal) usbrx usbtx dpln0 dpln1
514 * D/F(Flip ) dpln0 dpln1 usbrx usbtx
515 * A(Normal ) dpln3 dpln1 dpln2 dpln0
516 * A(Flip ) dpln2 dpln0 dpln3 dpln1
517 * B(Normal ) usbrx usbtx dpln1 dpln0
518 * B(Flip ) dpln1 dpln0 usbrx usbtx
519 * ---------------------------------------------------------------------------
520 *
521 * 2 Mapping the lanes in dtsi
522 * if all 4 lane assignment for dp function, define rockchip,dp-lane-mux = <x x x x>;
523 * sample as follow:
524 * ---------------------------------------------------------------------------
525 * B11-B10 A2-A3 A11-A10 B2-B3
526 * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
527 * <0 1 2 3> dpln0 dpln1 dpln2 dpln3
528 * <2 3 0 1> dpln2 dpln3 dpln0 dpln1
529 * ---------------------------------------------------------------------------
530 * if 2 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = <x x>;
531 * sample as follow:
532 * ---------------------------------------------------------------------------
533 * B11-B10 A2-A3 A11-A10 B2-B3
534 * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
535 * <0 1> dpln0 dpln1 usbrx usbtx
536 * <2 3> usbrx usbtx dpln0 dpln1
537 * ---------------------------------------------------------------------------
538 */
539
rk_udphy_dplane_select(struct rk_udphy * udphy)540 static void rk_udphy_dplane_select(struct rk_udphy *udphy)
541 {
542 const struct rk_udphy_cfg *cfg = udphy->cfgs;
543 u32 value = 0;
544
545 switch (udphy->mode) {
546 case UDPHY_MODE_DP:
547 value |= 2 << udphy->dp_lane_sel[2] * 2;
548 value |= 3 << udphy->dp_lane_sel[3] * 2;
549 fallthrough;
550
551 case UDPHY_MODE_DP_USB:
552 value |= 0 << udphy->dp_lane_sel[0] * 2;
553 value |= 1 << udphy->dp_lane_sel[1] * 2;
554 break;
555
556 case UDPHY_MODE_USB:
557 break;
558
559 default:
560 break;
561 }
562
563 regmap_write(udphy->vogrf, cfg->vogrfcfg[udphy->id].dp_lane_reg,
564 ((DP_AUX_DIN_SEL | DP_AUX_DOUT_SEL | DP_LANE_SEL_ALL) << 16) |
565 FIELD_PREP(DP_AUX_DIN_SEL, udphy->dp_aux_din_sel) |
566 FIELD_PREP(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel) | value);
567 }
568
rk_udphy_dplane_get(struct rk_udphy * udphy)569 static int rk_udphy_dplane_get(struct rk_udphy *udphy)
570 {
571 int dp_lanes;
572
573 switch (udphy->mode) {
574 case UDPHY_MODE_DP:
575 dp_lanes = 4;
576 break;
577
578 case UDPHY_MODE_DP_USB:
579 dp_lanes = 2;
580 break;
581
582 case UDPHY_MODE_USB:
583 default:
584 dp_lanes = 0;
585 break;
586 }
587
588 return dp_lanes;
589 }
590
rk_udphy_dplane_enable(struct rk_udphy * udphy,int dp_lanes)591 static void rk_udphy_dplane_enable(struct rk_udphy *udphy, int dp_lanes)
592 {
593 u32 val = 0;
594 int i;
595
596 for (i = 0; i < dp_lanes; i++)
597 val |= BIT(udphy->dp_lane_sel[i]);
598
599 regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, CMN_DP_LANE_EN_ALL,
600 FIELD_PREP(CMN_DP_LANE_EN_ALL, val));
601
602 if (!dp_lanes)
603 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
604 CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0));
605 }
606
rk_udphy_dp_hpd_event_trigger(struct rk_udphy * udphy,bool hpd)607 static void rk_udphy_dp_hpd_event_trigger(struct rk_udphy *udphy, bool hpd)
608 {
609 const struct rk_udphy_cfg *cfg = udphy->cfgs;
610
611 udphy->dp_sink_hpd_sel = true;
612 udphy->dp_sink_hpd_cfg = hpd;
613
614 if (!udphy->dp_in_use)
615 return;
616
617 rk_udphy_grfreg_write(udphy->vogrf, &cfg->vogrfcfg[udphy->id].hpd_trigger, hpd);
618 }
619
rk_udphy_set_typec_default_mapping(struct rk_udphy * udphy)620 static void rk_udphy_set_typec_default_mapping(struct rk_udphy *udphy)
621 {
622 if (udphy->flip) {
623 udphy->dp_lane_sel[0] = 0;
624 udphy->dp_lane_sel[1] = 1;
625 udphy->dp_lane_sel[2] = 3;
626 udphy->dp_lane_sel[3] = 2;
627 udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
628 udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
629 udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB;
630 udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB;
631 udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_INVERT;
632 udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_INVERT;
633 gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 1);
634 gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0);
635 } else {
636 udphy->dp_lane_sel[0] = 2;
637 udphy->dp_lane_sel[1] = 3;
638 udphy->dp_lane_sel[2] = 1;
639 udphy->dp_lane_sel[3] = 0;
640 udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB;
641 udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB;
642 udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
643 udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
644 udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_NORMAL;
645 udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_NORMAL;
646 gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0);
647 gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 1);
648 }
649
650 udphy->mode = UDPHY_MODE_DP_USB;
651 }
652
rk_udphy_orien_sw_set(struct typec_switch_dev * sw,enum typec_orientation orien)653 static int rk_udphy_orien_sw_set(struct typec_switch_dev *sw,
654 enum typec_orientation orien)
655 {
656 struct rk_udphy *udphy = typec_switch_get_drvdata(sw);
657
658 mutex_lock(&udphy->mutex);
659
660 if (orien == TYPEC_ORIENTATION_NONE) {
661 gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0);
662 gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0);
663 /* unattached */
664 rk_udphy_usb_bvalid_enable(udphy, false);
665 goto unlock_ret;
666 }
667
668 udphy->flip = orien == TYPEC_ORIENTATION_REVERSE;
669 rk_udphy_set_typec_default_mapping(udphy);
670 rk_udphy_usb_bvalid_enable(udphy, true);
671
672 unlock_ret:
673 mutex_unlock(&udphy->mutex);
674 return 0;
675 }
676
rk_udphy_orien_switch_unregister(void * data)677 static void rk_udphy_orien_switch_unregister(void *data)
678 {
679 struct rk_udphy *udphy = data;
680
681 typec_switch_unregister(udphy->sw);
682 }
683
rk_udphy_setup_orien_switch(struct rk_udphy * udphy)684 static int rk_udphy_setup_orien_switch(struct rk_udphy *udphy)
685 {
686 struct typec_switch_desc sw_desc = { };
687
688 sw_desc.drvdata = udphy;
689 sw_desc.fwnode = dev_fwnode(udphy->dev);
690 sw_desc.set = rk_udphy_orien_sw_set;
691
692 udphy->sw = typec_switch_register(udphy->dev, &sw_desc);
693 if (IS_ERR(udphy->sw)) {
694 dev_err(udphy->dev, "Error register typec orientation switch: %ld\n",
695 PTR_ERR(udphy->sw));
696 return PTR_ERR(udphy->sw);
697 }
698
699 return devm_add_action_or_reset(udphy->dev,
700 rk_udphy_orien_switch_unregister, udphy);
701 }
702
rk_udphy_refclk_set(struct rk_udphy * udphy)703 static int rk_udphy_refclk_set(struct rk_udphy *udphy)
704 {
705 unsigned long rate;
706 int ret;
707
708 /* configure phy reference clock */
709 rate = clk_get_rate(udphy->refclk);
710 dev_dbg(udphy->dev, "refclk freq %ld\n", rate);
711
712 switch (rate) {
713 case 24000000:
714 ret = regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_24m_refclk_cfg,
715 ARRAY_SIZE(rk_udphy_24m_refclk_cfg));
716 if (ret)
717 return ret;
718 break;
719
720 case 26000000:
721 /* register default is 26MHz */
722 ret = regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_26m_refclk_cfg,
723 ARRAY_SIZE(rk_udphy_26m_refclk_cfg));
724 if (ret)
725 return ret;
726 break;
727
728 default:
729 dev_err(udphy->dev, "unsupported refclk freq %ld\n", rate);
730 return -EINVAL;
731 }
732
733 return 0;
734 }
735
rk_udphy_status_check(struct rk_udphy * udphy)736 static int rk_udphy_status_check(struct rk_udphy *udphy)
737 {
738 unsigned int val;
739 int ret;
740
741 /* LCPLL check */
742 if (udphy->mode & UDPHY_MODE_USB) {
743 ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_LCPLL_DONE_OFFSET,
744 val, (val & CMN_ANA_LCPLL_AFC_DONE) &&
745 (val & CMN_ANA_LCPLL_LOCK_DONE), 200, 100000);
746 if (ret) {
747 dev_err(udphy->dev, "cmn ana lcpll lock timeout\n");
748 /*
749 * If earlier software (U-Boot) enabled USB once already
750 * the PLL may have problems locking on the first try.
751 * It will be successful on the second try, so for the
752 * time being a -EPROBE_DEFER will solve the issue.
753 *
754 * This requires further investigation to understand the
755 * root cause, especially considering that the driver is
756 * asserting all reset lines at probe time.
757 */
758 return -EPROBE_DEFER;
759 }
760
761 if (!udphy->flip) {
762 ret = regmap_read_poll_timeout(udphy->pma_regmap,
763 TRSV_LN0_MON_RX_CDR_DONE_OFFSET, val,
764 val & TRSV_LN0_MON_RX_CDR_LOCK_DONE,
765 200, 100000);
766 if (ret)
767 dev_err(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n");
768 } else {
769 ret = regmap_read_poll_timeout(udphy->pma_regmap,
770 TRSV_LN2_MON_RX_CDR_DONE_OFFSET, val,
771 val & TRSV_LN2_MON_RX_CDR_LOCK_DONE,
772 200, 100000);
773 if (ret)
774 dev_err(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n");
775 }
776 }
777
778 return 0;
779 }
780
rk_udphy_init(struct rk_udphy * udphy)781 static int rk_udphy_init(struct rk_udphy *udphy)
782 {
783 const struct rk_udphy_cfg *cfg = udphy->cfgs;
784 int ret;
785
786 rk_udphy_reset_assert_all(udphy);
787 usleep_range(10000, 11000);
788
789 /* enable rx lfps for usb */
790 if (udphy->mode & UDPHY_MODE_USB)
791 rk_udphy_grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true);
792
793 /* Step 1: power on pma and deassert apb rstn */
794 rk_udphy_grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true);
795
796 rk_udphy_reset_deassert(udphy, "pma_apb");
797 rk_udphy_reset_deassert(udphy, "pcs_apb");
798
799 /* Step 2: set init sequence and phy refclk */
800 ret = regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_init_sequence,
801 ARRAY_SIZE(rk_udphy_init_sequence));
802 if (ret) {
803 dev_err(udphy->dev, "init sequence set error %d\n", ret);
804 goto assert_resets;
805 }
806
807 ret = rk_udphy_refclk_set(udphy);
808 if (ret) {
809 dev_err(udphy->dev, "refclk set error %d\n", ret);
810 goto assert_resets;
811 }
812
813 /* Step 3: configure lane mux */
814 regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET,
815 CMN_DP_LANE_MUX_ALL | CMN_DP_LANE_EN_ALL,
816 FIELD_PREP(CMN_DP_LANE_MUX_N(3), udphy->lane_mux_sel[3]) |
817 FIELD_PREP(CMN_DP_LANE_MUX_N(2), udphy->lane_mux_sel[2]) |
818 FIELD_PREP(CMN_DP_LANE_MUX_N(1), udphy->lane_mux_sel[1]) |
819 FIELD_PREP(CMN_DP_LANE_MUX_N(0), udphy->lane_mux_sel[0]) |
820 FIELD_PREP(CMN_DP_LANE_EN_ALL, 0));
821
822 /* Step 4: deassert init rstn and wait for 200ns from datasheet */
823 if (udphy->mode & UDPHY_MODE_USB)
824 rk_udphy_reset_deassert(udphy, "init");
825
826 if (udphy->mode & UDPHY_MODE_DP) {
827 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
828 CMN_DP_INIT_RSTN,
829 FIELD_PREP(CMN_DP_INIT_RSTN, 0x1));
830 }
831
832 udelay(1);
833
834 /* Step 5: deassert cmn/lane rstn */
835 if (udphy->mode & UDPHY_MODE_USB) {
836 rk_udphy_reset_deassert(udphy, "cmn");
837 rk_udphy_reset_deassert(udphy, "lane");
838 }
839
840 /* Step 6: wait for lock done of pll */
841 ret = rk_udphy_status_check(udphy);
842 if (ret)
843 goto assert_resets;
844
845 return 0;
846
847 assert_resets:
848 rk_udphy_reset_assert_all(udphy);
849 return ret;
850 }
851
rk_udphy_setup(struct rk_udphy * udphy)852 static int rk_udphy_setup(struct rk_udphy *udphy)
853 {
854 int ret;
855
856 ret = clk_bulk_prepare_enable(udphy->num_clks, udphy->clks);
857 if (ret) {
858 dev_err(udphy->dev, "failed to enable clk\n");
859 return ret;
860 }
861
862 ret = rk_udphy_init(udphy);
863 if (ret) {
864 dev_err(udphy->dev, "failed to init combophy\n");
865 clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks);
866 return ret;
867 }
868
869 return 0;
870 }
871
rk_udphy_disable(struct rk_udphy * udphy)872 static void rk_udphy_disable(struct rk_udphy *udphy)
873 {
874 clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks);
875 rk_udphy_reset_assert_all(udphy);
876 }
877
rk_udphy_parse_lane_mux_data(struct rk_udphy * udphy)878 static int rk_udphy_parse_lane_mux_data(struct rk_udphy *udphy)
879 {
880 int ret, i, num_lanes;
881
882 num_lanes = device_property_count_u32(udphy->dev, "rockchip,dp-lane-mux");
883 if (num_lanes < 0) {
884 dev_dbg(udphy->dev, "no dp-lane-mux, following dp alt mode\n");
885 udphy->mode = UDPHY_MODE_USB;
886 return 0;
887 }
888
889 if (num_lanes != 2 && num_lanes != 4)
890 return dev_err_probe(udphy->dev, -EINVAL,
891 "invalid number of lane mux\n");
892
893 ret = device_property_read_u32_array(udphy->dev, "rockchip,dp-lane-mux",
894 udphy->dp_lane_sel, num_lanes);
895 if (ret)
896 return dev_err_probe(udphy->dev, ret, "get dp lane mux failed\n");
897
898 for (i = 0; i < num_lanes; i++) {
899 int j;
900
901 if (udphy->dp_lane_sel[i] > 3)
902 return dev_err_probe(udphy->dev, -EINVAL,
903 "lane mux between 0 and 3, exceeding the range\n");
904
905 udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP;
906
907 for (j = i + 1; j < num_lanes; j++) {
908 if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j])
909 return dev_err_probe(udphy->dev, -EINVAL,
910 "set repeat lane mux value\n");
911 }
912 }
913
914 udphy->mode = UDPHY_MODE_DP;
915 if (num_lanes == 2) {
916 udphy->mode |= UDPHY_MODE_USB;
917 udphy->flip = (udphy->lane_mux_sel[0] == PHY_LANE_MUX_DP);
918 }
919
920 return 0;
921 }
922
rk_udphy_get_initial_status(struct rk_udphy * udphy)923 static int rk_udphy_get_initial_status(struct rk_udphy *udphy)
924 {
925 int ret;
926 u32 value;
927
928 ret = clk_bulk_prepare_enable(udphy->num_clks, udphy->clks);
929 if (ret) {
930 dev_err(udphy->dev, "failed to enable clk\n");
931 return ret;
932 }
933
934 rk_udphy_reset_deassert_all(udphy);
935
936 regmap_read(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, &value);
937 if (FIELD_GET(CMN_DP_LANE_MUX_ALL, value) && FIELD_GET(CMN_DP_LANE_EN_ALL, value))
938 udphy->status = UDPHY_MODE_DP;
939 else
940 rk_udphy_disable(udphy);
941
942 return 0;
943 }
944
rk_udphy_parse_dt(struct rk_udphy * udphy)945 static int rk_udphy_parse_dt(struct rk_udphy *udphy)
946 {
947 struct device *dev = udphy->dev;
948 struct device_node *np = dev_of_node(dev);
949 enum usb_device_speed maximum_speed;
950 int ret;
951
952 udphy->u2phygrf = syscon_regmap_lookup_by_phandle(np, "rockchip,u2phy-grf");
953 if (IS_ERR(udphy->u2phygrf))
954 return dev_err_probe(dev, PTR_ERR(udphy->u2phygrf), "failed to get u2phy-grf\n");
955
956 udphy->udphygrf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbdpphy-grf");
957 if (IS_ERR(udphy->udphygrf))
958 return dev_err_probe(dev, PTR_ERR(udphy->udphygrf), "failed to get usbdpphy-grf\n");
959
960 udphy->usbgrf = syscon_regmap_lookup_by_phandle(np, "rockchip,usb-grf");
961 if (IS_ERR(udphy->usbgrf))
962 return dev_err_probe(dev, PTR_ERR(udphy->usbgrf), "failed to get usb-grf\n");
963
964 udphy->vogrf = syscon_regmap_lookup_by_phandle(np, "rockchip,vo-grf");
965 if (IS_ERR(udphy->vogrf))
966 return dev_err_probe(dev, PTR_ERR(udphy->vogrf), "failed to get vo-grf\n");
967
968 ret = rk_udphy_parse_lane_mux_data(udphy);
969 if (ret)
970 return ret;
971
972 udphy->sbu1_dc_gpio = devm_gpiod_get_optional(dev, "sbu1-dc", GPIOD_OUT_LOW);
973 if (IS_ERR(udphy->sbu1_dc_gpio))
974 return PTR_ERR(udphy->sbu1_dc_gpio);
975
976 udphy->sbu2_dc_gpio = devm_gpiod_get_optional(dev, "sbu2-dc", GPIOD_OUT_LOW);
977 if (IS_ERR(udphy->sbu2_dc_gpio))
978 return PTR_ERR(udphy->sbu2_dc_gpio);
979
980 if (device_property_present(dev, "maximum-speed")) {
981 maximum_speed = usb_get_maximum_speed(dev);
982 udphy->hs = maximum_speed <= USB_SPEED_HIGH;
983 }
984
985 ret = rk_udphy_clk_init(udphy, dev);
986 if (ret)
987 return ret;
988
989 return rk_udphy_reset_init(udphy, dev);
990 }
991
rk_udphy_power_on(struct rk_udphy * udphy,u8 mode)992 static int rk_udphy_power_on(struct rk_udphy *udphy, u8 mode)
993 {
994 int ret;
995
996 if (!(udphy->mode & mode)) {
997 dev_info(udphy->dev, "mode 0x%02x is not support\n", mode);
998 return 0;
999 }
1000
1001 if (udphy->status == UDPHY_MODE_NONE) {
1002 udphy->mode_change = false;
1003 ret = rk_udphy_setup(udphy);
1004 if (ret)
1005 return ret;
1006
1007 if (udphy->mode & UDPHY_MODE_USB)
1008 rk_udphy_u3_port_disable(udphy, false);
1009 } else if (udphy->mode_change) {
1010 udphy->mode_change = false;
1011 udphy->status = UDPHY_MODE_NONE;
1012 if (udphy->mode == UDPHY_MODE_DP)
1013 rk_udphy_u3_port_disable(udphy, true);
1014
1015 rk_udphy_disable(udphy);
1016 ret = rk_udphy_setup(udphy);
1017 if (ret)
1018 return ret;
1019 }
1020
1021 udphy->status |= mode;
1022
1023 return 0;
1024 }
1025
rk_udphy_power_off(struct rk_udphy * udphy,u8 mode)1026 static void rk_udphy_power_off(struct rk_udphy *udphy, u8 mode)
1027 {
1028 if (!(udphy->mode & mode)) {
1029 dev_info(udphy->dev, "mode 0x%02x is not support\n", mode);
1030 return;
1031 }
1032
1033 if (!udphy->status)
1034 return;
1035
1036 udphy->status &= ~mode;
1037
1038 if (udphy->status == UDPHY_MODE_NONE)
1039 rk_udphy_disable(udphy);
1040 }
1041
rk_udphy_dp_phy_init(struct phy * phy)1042 static int rk_udphy_dp_phy_init(struct phy *phy)
1043 {
1044 struct rk_udphy *udphy = phy_get_drvdata(phy);
1045
1046 mutex_lock(&udphy->mutex);
1047
1048 udphy->dp_in_use = true;
1049
1050 mutex_unlock(&udphy->mutex);
1051
1052 return 0;
1053 }
1054
rk_udphy_dp_phy_exit(struct phy * phy)1055 static int rk_udphy_dp_phy_exit(struct phy *phy)
1056 {
1057 struct rk_udphy *udphy = phy_get_drvdata(phy);
1058
1059 mutex_lock(&udphy->mutex);
1060 udphy->dp_in_use = false;
1061 mutex_unlock(&udphy->mutex);
1062 return 0;
1063 }
1064
rk_udphy_dp_phy_power_on(struct phy * phy)1065 static int rk_udphy_dp_phy_power_on(struct phy *phy)
1066 {
1067 struct rk_udphy *udphy = phy_get_drvdata(phy);
1068 int ret, dp_lanes;
1069
1070 mutex_lock(&udphy->mutex);
1071
1072 dp_lanes = rk_udphy_dplane_get(udphy);
1073 phy_set_bus_width(phy, dp_lanes);
1074
1075 ret = rk_udphy_power_on(udphy, UDPHY_MODE_DP);
1076 if (ret)
1077 goto unlock;
1078
1079 rk_udphy_dplane_enable(udphy, dp_lanes);
1080
1081 rk_udphy_dplane_select(udphy);
1082
1083 unlock:
1084 mutex_unlock(&udphy->mutex);
1085 /*
1086 * If data send by aux channel too fast after phy power on,
1087 * the aux may be not ready which will cause aux error. Adding
1088 * delay to avoid this issue.
1089 */
1090 usleep_range(10000, 11000);
1091 return ret;
1092 }
1093
rk_udphy_dp_phy_power_off(struct phy * phy)1094 static int rk_udphy_dp_phy_power_off(struct phy *phy)
1095 {
1096 struct rk_udphy *udphy = phy_get_drvdata(phy);
1097
1098 mutex_lock(&udphy->mutex);
1099 rk_udphy_dplane_enable(udphy, 0);
1100 rk_udphy_power_off(udphy, UDPHY_MODE_DP);
1101 mutex_unlock(&udphy->mutex);
1102
1103 return 0;
1104 }
1105
1106 /*
1107 * Verify link rate
1108 */
rk_udphy_dp_phy_verify_link_rate(struct rk_udphy * udphy,struct phy_configure_opts_dp * dp)1109 static int rk_udphy_dp_phy_verify_link_rate(struct rk_udphy *udphy,
1110 struct phy_configure_opts_dp *dp)
1111 {
1112 switch (dp->link_rate) {
1113 case 1620:
1114 case 2700:
1115 case 5400:
1116 case 8100:
1117 udphy->link_rate = dp->link_rate;
1118 break;
1119 default:
1120 return -EINVAL;
1121 }
1122
1123 return 0;
1124 }
1125
rk_udphy_dp_phy_verify_lanes(struct rk_udphy * udphy,struct phy_configure_opts_dp * dp)1126 static int rk_udphy_dp_phy_verify_lanes(struct rk_udphy *udphy,
1127 struct phy_configure_opts_dp *dp)
1128 {
1129 switch (dp->lanes) {
1130 case 1:
1131 case 2:
1132 case 4:
1133 /* valid lane count. */
1134 udphy->lanes = dp->lanes;
1135 break;
1136
1137 default:
1138 return -EINVAL;
1139 }
1140
1141 return 0;
1142 }
1143
1144 /*
1145 * If changing voltages is required, check swing and pre-emphasis
1146 * levels, per-lane.
1147 */
rk_udphy_dp_phy_verify_voltages(struct rk_udphy * udphy,struct phy_configure_opts_dp * dp)1148 static int rk_udphy_dp_phy_verify_voltages(struct rk_udphy *udphy,
1149 struct phy_configure_opts_dp *dp)
1150 {
1151 int i;
1152
1153 /* Lane count verified previously. */
1154 for (i = 0; i < udphy->lanes; i++) {
1155 if (dp->voltage[i] > 3 || dp->pre[i] > 3)
1156 return -EINVAL;
1157
1158 /*
1159 * Sum of voltage swing and pre-emphasis levels cannot
1160 * exceed 3.
1161 */
1162 if (dp->voltage[i] + dp->pre[i] > 3)
1163 return -EINVAL;
1164 }
1165
1166 return 0;
1167 }
1168
rk_udphy_dp_set_voltage(struct rk_udphy * udphy,u8 bw,u32 voltage,u32 pre,u32 lane)1169 static void rk_udphy_dp_set_voltage(struct rk_udphy *udphy, u8 bw,
1170 u32 voltage, u32 pre, u32 lane)
1171 {
1172 const struct rk_udphy_cfg *cfg = udphy->cfgs;
1173 const struct rk_udphy_dp_tx_drv_ctrl (*dp_ctrl)[4];
1174 u32 offset = 0x800 * lane;
1175 u32 val;
1176
1177 if (udphy->mux)
1178 dp_ctrl = cfg->dp_tx_ctrl_cfg_typec[bw];
1179 else
1180 dp_ctrl = cfg->dp_tx_ctrl_cfg[bw];
1181
1182 val = dp_ctrl[voltage][pre].trsv_reg0204;
1183 regmap_write(udphy->pma_regmap, 0x0810 + offset, val);
1184
1185 val = dp_ctrl[voltage][pre].trsv_reg0205;
1186 regmap_write(udphy->pma_regmap, 0x0814 + offset, val);
1187
1188 val = dp_ctrl[voltage][pre].trsv_reg0206;
1189 regmap_write(udphy->pma_regmap, 0x0818 + offset, val);
1190
1191 val = dp_ctrl[voltage][pre].trsv_reg0207;
1192 regmap_write(udphy->pma_regmap, 0x081c + offset, val);
1193 }
1194
rk_udphy_dp_phy_configure(struct phy * phy,union phy_configure_opts * opts)1195 static int rk_udphy_dp_phy_configure(struct phy *phy,
1196 union phy_configure_opts *opts)
1197 {
1198 struct rk_udphy *udphy = phy_get_drvdata(phy);
1199 struct phy_configure_opts_dp *dp = &opts->dp;
1200 u32 i, val, lane;
1201 int ret;
1202
1203 if (dp->set_rate) {
1204 ret = rk_udphy_dp_phy_verify_link_rate(udphy, dp);
1205 if (ret)
1206 return ret;
1207 }
1208
1209 if (dp->set_lanes) {
1210 ret = rk_udphy_dp_phy_verify_lanes(udphy, dp);
1211 if (ret)
1212 return ret;
1213 }
1214
1215 if (dp->set_voltages) {
1216 ret = rk_udphy_dp_phy_verify_voltages(udphy, dp);
1217 if (ret)
1218 return ret;
1219 }
1220
1221 if (dp->set_rate) {
1222 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
1223 CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0));
1224
1225 switch (dp->link_rate) {
1226 case 1620:
1227 udphy->bw = DP_BW_RBR;
1228 break;
1229
1230 case 2700:
1231 udphy->bw = DP_BW_HBR;
1232 break;
1233
1234 case 5400:
1235 udphy->bw = DP_BW_HBR2;
1236 break;
1237
1238 case 8100:
1239 udphy->bw = DP_BW_HBR3;
1240 break;
1241
1242 default:
1243 return -EINVAL;
1244 }
1245
1246 regmap_update_bits(udphy->pma_regmap, CMN_DP_LINK_OFFSET, CMN_DP_TX_LINK_BW,
1247 FIELD_PREP(CMN_DP_TX_LINK_BW, udphy->bw));
1248 regmap_update_bits(udphy->pma_regmap, CMN_SSC_EN_OFFSET, CMN_ROPLL_SSC_EN,
1249 FIELD_PREP(CMN_ROPLL_SSC_EN, dp->ssc));
1250 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, CMN_DP_CMN_RSTN,
1251 FIELD_PREP(CMN_DP_CMN_RSTN, 0x1));
1252
1253 ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_ROPLL_DONE_OFFSET, val,
1254 FIELD_GET(CMN_ANA_ROPLL_LOCK_DONE, val) &&
1255 FIELD_GET(CMN_ANA_ROPLL_AFC_DONE, val),
1256 0, 1000);
1257 if (ret) {
1258 dev_err(udphy->dev, "ROPLL is not lock, set_rate failed\n");
1259 return ret;
1260 }
1261 }
1262
1263 if (dp->set_voltages) {
1264 for (i = 0; i < udphy->lanes; i++) {
1265 lane = udphy->dp_lane_sel[i];
1266 switch (udphy->link_rate) {
1267 case 1620:
1268 case 2700:
1269 regmap_update_bits(udphy->pma_regmap,
1270 TRSV_ANA_TX_CLK_OFFSET_N(lane),
1271 LN_ANA_TX_SER_TXCLK_INV,
1272 FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV,
1273 udphy->lane_mux_sel[lane]));
1274 break;
1275
1276 case 5400:
1277 case 8100:
1278 regmap_update_bits(udphy->pma_regmap,
1279 TRSV_ANA_TX_CLK_OFFSET_N(lane),
1280 LN_ANA_TX_SER_TXCLK_INV,
1281 FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, 0x0));
1282 break;
1283 }
1284
1285 rk_udphy_dp_set_voltage(udphy, udphy->bw, dp->voltage[i],
1286 dp->pre[i], lane);
1287 }
1288 }
1289
1290 return 0;
1291 }
1292
1293 static const struct phy_ops rk_udphy_dp_phy_ops = {
1294 .init = rk_udphy_dp_phy_init,
1295 .exit = rk_udphy_dp_phy_exit,
1296 .power_on = rk_udphy_dp_phy_power_on,
1297 .power_off = rk_udphy_dp_phy_power_off,
1298 .configure = rk_udphy_dp_phy_configure,
1299 .owner = THIS_MODULE,
1300 };
1301
rk_udphy_usb3_phy_init(struct phy * phy)1302 static int rk_udphy_usb3_phy_init(struct phy *phy)
1303 {
1304 struct rk_udphy *udphy = phy_get_drvdata(phy);
1305 int ret = 0;
1306
1307 mutex_lock(&udphy->mutex);
1308 /* DP only or high-speed, disable U3 port */
1309 if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {
1310 rk_udphy_u3_port_disable(udphy, true);
1311 goto unlock;
1312 }
1313
1314 ret = rk_udphy_power_on(udphy, UDPHY_MODE_USB);
1315
1316 unlock:
1317 mutex_unlock(&udphy->mutex);
1318 return ret;
1319 }
1320
rk_udphy_usb3_phy_exit(struct phy * phy)1321 static int rk_udphy_usb3_phy_exit(struct phy *phy)
1322 {
1323 struct rk_udphy *udphy = phy_get_drvdata(phy);
1324
1325 mutex_lock(&udphy->mutex);
1326 /* DP only or high-speed */
1327 if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs)
1328 goto unlock;
1329
1330 rk_udphy_power_off(udphy, UDPHY_MODE_USB);
1331
1332 unlock:
1333 mutex_unlock(&udphy->mutex);
1334 return 0;
1335 }
1336
1337 static const struct phy_ops rk_udphy_usb3_phy_ops = {
1338 .init = rk_udphy_usb3_phy_init,
1339 .exit = rk_udphy_usb3_phy_exit,
1340 .owner = THIS_MODULE,
1341 };
1342
rk_udphy_typec_mux_set(struct typec_mux_dev * mux,struct typec_mux_state * state)1343 static int rk_udphy_typec_mux_set(struct typec_mux_dev *mux,
1344 struct typec_mux_state *state)
1345 {
1346 struct rk_udphy *udphy = typec_mux_get_drvdata(mux);
1347 u8 mode;
1348
1349 mutex_lock(&udphy->mutex);
1350
1351 switch (state->mode) {
1352 case TYPEC_DP_STATE_C:
1353 case TYPEC_DP_STATE_E:
1354 udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
1355 udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
1356 udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
1357 udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
1358 mode = UDPHY_MODE_DP;
1359 break;
1360
1361 case TYPEC_DP_STATE_D:
1362 default:
1363 if (udphy->flip) {
1364 udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
1365 udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
1366 udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB;
1367 udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB;
1368 } else {
1369 udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB;
1370 udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB;
1371 udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
1372 udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
1373 }
1374 mode = UDPHY_MODE_DP_USB;
1375 break;
1376 }
1377
1378 if (state->alt && state->alt->svid == USB_TYPEC_DP_SID) {
1379 struct typec_displayport_data *data = state->data;
1380
1381 if (!data) {
1382 rk_udphy_dp_hpd_event_trigger(udphy, false);
1383 } else if (data->status & DP_STATUS_IRQ_HPD) {
1384 rk_udphy_dp_hpd_event_trigger(udphy, false);
1385 usleep_range(750, 800);
1386 rk_udphy_dp_hpd_event_trigger(udphy, true);
1387 } else if (data->status & DP_STATUS_HPD_STATE) {
1388 if (udphy->mode != mode) {
1389 udphy->mode = mode;
1390 udphy->mode_change = true;
1391 }
1392 rk_udphy_dp_hpd_event_trigger(udphy, true);
1393 } else {
1394 rk_udphy_dp_hpd_event_trigger(udphy, false);
1395 }
1396 }
1397
1398 mutex_unlock(&udphy->mutex);
1399 return 0;
1400 }
1401
rk_udphy_typec_mux_unregister(void * data)1402 static void rk_udphy_typec_mux_unregister(void *data)
1403 {
1404 struct rk_udphy *udphy = data;
1405
1406 typec_mux_unregister(udphy->mux);
1407 }
1408
rk_udphy_setup_typec_mux(struct rk_udphy * udphy)1409 static int rk_udphy_setup_typec_mux(struct rk_udphy *udphy)
1410 {
1411 struct typec_mux_desc mux_desc = {};
1412
1413 mux_desc.drvdata = udphy;
1414 mux_desc.fwnode = dev_fwnode(udphy->dev);
1415 mux_desc.set = rk_udphy_typec_mux_set;
1416
1417 udphy->mux = typec_mux_register(udphy->dev, &mux_desc);
1418 if (IS_ERR(udphy->mux)) {
1419 dev_err(udphy->dev, "Error register typec mux: %ld\n",
1420 PTR_ERR(udphy->mux));
1421 return PTR_ERR(udphy->mux);
1422 }
1423
1424 return devm_add_action_or_reset(udphy->dev, rk_udphy_typec_mux_unregister,
1425 udphy);
1426 }
1427
1428 static const struct regmap_config rk_udphy_pma_regmap_cfg = {
1429 .reg_bits = 32,
1430 .reg_stride = 4,
1431 .val_bits = 32,
1432 .max_register = 0x20dc,
1433 };
1434
rk_udphy_phy_xlate(struct device * dev,const struct of_phandle_args * args)1435 static struct phy *rk_udphy_phy_xlate(struct device *dev, const struct of_phandle_args *args)
1436 {
1437 struct rk_udphy *udphy = dev_get_drvdata(dev);
1438
1439 if (args->args_count == 0)
1440 return ERR_PTR(-EINVAL);
1441
1442 switch (args->args[0]) {
1443 case PHY_TYPE_USB3:
1444 return udphy->phy_u3;
1445 case PHY_TYPE_DP:
1446 return udphy->phy_dp;
1447 }
1448
1449 return ERR_PTR(-EINVAL);
1450 }
1451
rk_udphy_probe(struct platform_device * pdev)1452 static int rk_udphy_probe(struct platform_device *pdev)
1453 {
1454 struct device *dev = &pdev->dev;
1455 struct phy_provider *phy_provider;
1456 struct resource *res;
1457 struct rk_udphy *udphy;
1458 void __iomem *base;
1459 int id, ret;
1460
1461 udphy = devm_kzalloc(dev, sizeof(*udphy), GFP_KERNEL);
1462 if (!udphy)
1463 return -ENOMEM;
1464
1465 udphy->cfgs = device_get_match_data(dev);
1466 if (!udphy->cfgs)
1467 return dev_err_probe(dev, -EINVAL, "missing match data\n");
1468
1469 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1470 if (IS_ERR(base))
1471 return PTR_ERR(base);
1472
1473 /* find the phy-id from the io address */
1474 udphy->id = -ENODEV;
1475 for (id = 0; id < udphy->cfgs->num_phys; id++) {
1476 if (res->start == udphy->cfgs->phy_ids[id]) {
1477 udphy->id = id;
1478 break;
1479 }
1480 }
1481
1482 if (udphy->id < 0)
1483 return dev_err_probe(dev, -ENODEV, "no matching device found\n");
1484
1485 udphy->pma_regmap = devm_regmap_init_mmio(dev, base + UDPHY_PMA,
1486 &rk_udphy_pma_regmap_cfg);
1487 if (IS_ERR(udphy->pma_regmap))
1488 return PTR_ERR(udphy->pma_regmap);
1489
1490 udphy->dev = dev;
1491 ret = rk_udphy_parse_dt(udphy);
1492 if (ret)
1493 return ret;
1494
1495 ret = rk_udphy_get_initial_status(udphy);
1496 if (ret)
1497 return ret;
1498
1499 mutex_init(&udphy->mutex);
1500 platform_set_drvdata(pdev, udphy);
1501
1502 if (device_property_present(dev, "orientation-switch")) {
1503 ret = rk_udphy_setup_orien_switch(udphy);
1504 if (ret)
1505 return ret;
1506 }
1507
1508 if (device_property_present(dev, "mode-switch")) {
1509 ret = rk_udphy_setup_typec_mux(udphy);
1510 if (ret)
1511 return ret;
1512 }
1513
1514 udphy->phy_u3 = devm_phy_create(dev, dev->of_node, &rk_udphy_usb3_phy_ops);
1515 if (IS_ERR(udphy->phy_u3)) {
1516 ret = PTR_ERR(udphy->phy_u3);
1517 return dev_err_probe(dev, ret, "failed to create USB3 phy\n");
1518 }
1519 phy_set_drvdata(udphy->phy_u3, udphy);
1520
1521 udphy->phy_dp = devm_phy_create(dev, dev->of_node, &rk_udphy_dp_phy_ops);
1522 if (IS_ERR(udphy->phy_dp)) {
1523 ret = PTR_ERR(udphy->phy_dp);
1524 return dev_err_probe(dev, ret, "failed to create DP phy\n");
1525 }
1526 phy_set_bus_width(udphy->phy_dp, rk_udphy_dplane_get(udphy));
1527 udphy->phy_dp->attrs.max_link_rate = 8100;
1528 phy_set_drvdata(udphy->phy_dp, udphy);
1529
1530 phy_provider = devm_of_phy_provider_register(dev, rk_udphy_phy_xlate);
1531 if (IS_ERR(phy_provider)) {
1532 ret = PTR_ERR(phy_provider);
1533 return dev_err_probe(dev, ret, "failed to register phy provider\n");
1534 }
1535
1536 return 0;
1537 }
1538
rk_udphy_resume(struct device * dev)1539 static int __maybe_unused rk_udphy_resume(struct device *dev)
1540 {
1541 struct rk_udphy *udphy = dev_get_drvdata(dev);
1542
1543 if (udphy->dp_sink_hpd_sel)
1544 rk_udphy_dp_hpd_event_trigger(udphy, udphy->dp_sink_hpd_cfg);
1545
1546 return 0;
1547 }
1548
1549 static const struct dev_pm_ops rk_udphy_pm_ops = {
1550 SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, rk_udphy_resume)
1551 };
1552
1553 static const char * const rk_udphy_rst_list[] = {
1554 "init", "cmn", "lane", "pcs_apb", "pma_apb"
1555 };
1556
1557 static const struct rk_udphy_cfg rk3576_udphy_cfgs = {
1558 .num_phys = 1,
1559 .phy_ids = { 0x2b010000 },
1560 .num_rsts = ARRAY_SIZE(rk_udphy_rst_list),
1561 .rst_list = rk_udphy_rst_list,
1562 .grfcfg = {
1563 /* u2phy-grf */
1564 .bvalid_phy_con = RK_UDPHY_GEN_GRF_REG(0x0010, 1, 0, 0x2, 0x3),
1565 .bvalid_grf_con = RK_UDPHY_GEN_GRF_REG(0x0000, 15, 14, 0x1, 0x3),
1566
1567 /* usb-grf */
1568 .usb3otg0_cfg = RK_UDPHY_GEN_GRF_REG(0x0030, 15, 0, 0x1100, 0x0188),
1569
1570 /* usbdpphy-grf */
1571 .low_pwrn = RK_UDPHY_GEN_GRF_REG(0x0004, 13, 13, 0, 1),
1572 .rx_lfps = RK_UDPHY_GEN_GRF_REG(0x0004, 14, 14, 0, 1),
1573 },
1574 .vogrfcfg = {
1575 {
1576 .hpd_trigger = RK_UDPHY_GEN_GRF_REG(0x0000, 11, 10, 1, 3),
1577 .dp_lane_reg = 0x0000,
1578 },
1579 },
1580 .dp_tx_ctrl_cfg = {
1581 rk3588_dp_tx_drv_ctrl_rbr_hbr_typec,
1582 rk3588_dp_tx_drv_ctrl_rbr_hbr_typec,
1583 rk3588_dp_tx_drv_ctrl_hbr2,
1584 rk3588_dp_tx_drv_ctrl_hbr3,
1585 },
1586 .dp_tx_ctrl_cfg_typec = {
1587 rk3588_dp_tx_drv_ctrl_rbr_hbr_typec,
1588 rk3588_dp_tx_drv_ctrl_rbr_hbr_typec,
1589 rk3588_dp_tx_drv_ctrl_hbr2,
1590 rk3588_dp_tx_drv_ctrl_hbr3,
1591 },
1592 };
1593
1594 static const struct rk_udphy_cfg rk3588_udphy_cfgs = {
1595 .num_phys = 2,
1596 .phy_ids = {
1597 0xfed80000,
1598 0xfed90000,
1599 },
1600 .num_rsts = ARRAY_SIZE(rk_udphy_rst_list),
1601 .rst_list = rk_udphy_rst_list,
1602 .grfcfg = {
1603 /* u2phy-grf */
1604 .bvalid_phy_con = RK_UDPHY_GEN_GRF_REG(0x0008, 1, 0, 0x2, 0x3),
1605 .bvalid_grf_con = RK_UDPHY_GEN_GRF_REG(0x0010, 3, 2, 0x2, 0x3),
1606
1607 /* usb-grf */
1608 .usb3otg0_cfg = RK_UDPHY_GEN_GRF_REG(0x001c, 15, 0, 0x1100, 0x0188),
1609 .usb3otg1_cfg = RK_UDPHY_GEN_GRF_REG(0x0034, 15, 0, 0x1100, 0x0188),
1610
1611 /* usbdpphy-grf */
1612 .low_pwrn = RK_UDPHY_GEN_GRF_REG(0x0004, 13, 13, 0, 1),
1613 .rx_lfps = RK_UDPHY_GEN_GRF_REG(0x0004, 14, 14, 0, 1),
1614 },
1615 .vogrfcfg = {
1616 {
1617 .hpd_trigger = RK_UDPHY_GEN_GRF_REG(0x0000, 11, 10, 1, 3),
1618 .dp_lane_reg = 0x0000,
1619 },
1620 {
1621 .hpd_trigger = RK_UDPHY_GEN_GRF_REG(0x0008, 11, 10, 1, 3),
1622 .dp_lane_reg = 0x0008,
1623 },
1624 },
1625 .dp_tx_ctrl_cfg = {
1626 rk3588_dp_tx_drv_ctrl_rbr_hbr,
1627 rk3588_dp_tx_drv_ctrl_rbr_hbr,
1628 rk3588_dp_tx_drv_ctrl_hbr2,
1629 rk3588_dp_tx_drv_ctrl_hbr3,
1630 },
1631 .dp_tx_ctrl_cfg_typec = {
1632 rk3588_dp_tx_drv_ctrl_rbr_hbr_typec,
1633 rk3588_dp_tx_drv_ctrl_rbr_hbr_typec,
1634 rk3588_dp_tx_drv_ctrl_hbr2,
1635 rk3588_dp_tx_drv_ctrl_hbr3,
1636 },
1637 };
1638
1639 static const struct of_device_id rk_udphy_dt_match[] = {
1640 {
1641 .compatible = "rockchip,rk3576-usbdp-phy",
1642 .data = &rk3576_udphy_cfgs
1643 },
1644 {
1645 .compatible = "rockchip,rk3588-usbdp-phy",
1646 .data = &rk3588_udphy_cfgs
1647 },
1648 { /* sentinel */ }
1649 };
1650 MODULE_DEVICE_TABLE(of, rk_udphy_dt_match);
1651
1652 static struct platform_driver rk_udphy_driver = {
1653 .probe = rk_udphy_probe,
1654 .driver = {
1655 .name = "rockchip-usbdp-phy",
1656 .of_match_table = rk_udphy_dt_match,
1657 .pm = &rk_udphy_pm_ops,
1658 },
1659 };
1660 module_platform_driver(rk_udphy_driver);
1661
1662 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
1663 MODULE_AUTHOR("Zhang Yubing <yubing.zhang@rock-chips.com>");
1664 MODULE_DESCRIPTION("Rockchip USBDP Combo PHY driver");
1665 MODULE_LICENSE("GPL");
1666