1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2/* 3 * Copyright (c) 2024 TQ-Systems GmbH <linux@ew.tq-group.com>, 4 * D-82229 Seefeld, Germany. 5 * Author: Alexander Stein 6 */ 7 8/dts-v1/; 9 10#include <dt-bindings/net/ti-dp83867.h> 11#include <dt-bindings/phy/phy-imx8-pcie.h> 12#include <dt-bindings/usb/pd.h> 13#include "imx95.dtsi" 14 15/ { 16 aliases { 17 ethernet0 = &enetc_port0; 18 ethernet1 = &enetc_port1; 19 }; 20 21 memory@80000000 { 22 device_type = "memory"; 23 /* 24 * DRAM base addr, size : 2048 MiB DRAM 25 * should be corrected by bootloader 26 */ 27 reg = <0 0x80000000 0 0x80000000>; 28 }; 29 30 reserved-memory { 31 #address-cells = <2>; 32 #size-cells = <2>; 33 ranges; 34 35 linux_cma: linux,cma { 36 compatible = "shared-dma-pool"; 37 reusable; 38 size = <0 0x28000000>; 39 alloc-ranges = <0 0x80000000 0 0x80000000>; 40 linux,cma-default; 41 }; 42 43 vpu_boot: vpu_boot@a0000000 { 44 reg = <0 0xa0000000 0 0x100000>; 45 no-map; 46 }; 47 }; 48 49 clk_dp: clk-dp { 50 compatible = "fixed-clock"; 51 #clock-cells = <0>; 52 clock-frequency = <26000000>; 53 }; 54 55 clk_xtal25: clk-xtal25 { 56 compatible = "fixed-clock"; 57 #clock-cells = <0>; 58 clock-frequency = <25000000>; 59 }; 60 61 reg_1v8: regulator-1v8 { 62 compatible = "regulator-fixed"; 63 regulator-name = "V_1V8"; 64 regulator-min-microvolt = <1800000>; 65 regulator-max-microvolt = <1800000>; 66 regulator-always-on; 67 }; 68 69 reg_3v3: regulator-3v3 { 70 compatible = "regulator-fixed"; 71 regulator-name = "V_3V3"; 72 regulator-min-microvolt = <3300000>; 73 regulator-max-microvolt = <3300000>; 74 regulator-always-on; 75 }; 76 77 /* Controlled by system manager */ 78 reg_sdvmmc: regulator-sdvmmc { 79 compatible = "regulator-fixed"; 80 pinctrl-names = "default"; 81 pinctrl-0 = <&pinctrl_sdvmmc>; 82 regulator-name = "SDIO_PWR_EN"; 83 regulator-min-microvolt = <3300000>; 84 regulator-max-microvolt = <3300000>; 85 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 86 enable-active-high; 87 status = "disabled"; 88 }; 89}; 90 91&enetc_port0 { 92 pinctrl-names = "default"; 93 pinctrl-0 = <&pinctrl_enetc0>; 94 phy-handle = <ðphy0>; 95 phy-mode = "rgmii-id"; 96}; 97 98&enetc_port1 { 99 pinctrl-names = "default"; 100 pinctrl-0 = <&pinctrl_enetc1>; 101 phy-handle = <ðphy3>; 102 phy-mode = "rgmii-id"; 103}; 104 105&netc_timer { 106 status = "okay"; 107}; 108 109&flexcan1 { 110 pinctrl-names = "default"; 111 pinctrl-0 = <&pinctrl_flexcan1>; 112}; 113 114&flexcan3 { 115 pinctrl-names = "default"; 116 pinctrl-0 = <&pinctrl_flexcan3>; 117}; 118 119&flexspi1 { 120 pinctrl-names = "default"; 121 pinctrl-0 = <&pinctrl_flexspi1>; 122 status = "okay"; 123 124 flash0: flash@0 { 125 compatible = "jedec,spi-nor"; 126 reg = <0>; 127 spi-max-frequency = <66000000>; 128 spi-tx-bus-width = <4>; 129 spi-rx-bus-width = <4>; 130 vcc-supply = <®_1v8>; 131 132 partitions { 133 compatible = "fixed-partitions"; 134 #address-cells = <1>; 135 #size-cells = <1>; 136 }; 137 }; 138}; 139 140&gpio1 { 141 pinctrl-names = "default"; 142 pinctrl-0 = <&pinctrl_gpio1>; 143 gpio-line-names = "", "", "", "", 144 "", "", "", "", 145 "", "", "GPIO7", "GPIO8", 146 "", "GPIO9", "", "", 147 "", "", "", "", 148 "", "", "", "", 149 "", "", "", "", 150 "", "", "", ""; 151}; 152 153&gpio2 { 154 pinctrl-names = "default"; 155 pinctrl-0 = <&pinctrl_gpio2>; 156 gpio-line-names = "", "", "", "", 157 "", "", "", "", 158 "", "", "", "", 159 "", "", "", "", 160 "", "", "SLEEP", "GPIO5", 161 "", "", "GPIO6", "", 162 "", "", "", "", 163 "", "", "", ""; 164}; 165 166&lpi2c1 { 167 clock-frequency = <400000>; 168 pinctrl-names = "default"; 169 pinctrl-0 = <&pinctrl_lpi2c1>; 170 status = "okay"; 171 172 tmp1075: temperature-sensor@4a { 173 compatible = "ti,tmp1075"; 174 reg = <0x4a>; 175 vs-supply = <®_1v8>; 176 }; 177 178 eeprom_smarc: eeprom@50 { 179 compatible = "atmel,24c64"; 180 reg = <0x50>; 181 pagesize = <32>; 182 vcc-supply = <®_1v8>; 183 }; 184 185 pcf85063: rtc@51 { 186 compatible = "nxp,pcf85063a"; 187 reg = <0x51>; 188 quartz-load-femtofarads = <7000>; 189 pinctrl-names = "default"; 190 pinctrl-0 = <&pinctrl_pcf85063>; 191 interrupt-parent = <&gpio2>; 192 interrupts = <27 IRQ_TYPE_EDGE_FALLING>; 193 }; 194 195 m24c64: eeprom@54 { 196 compatible = "atmel,24c64"; 197 reg = <0x54>; 198 pagesize = <32>; 199 vcc-supply = <®_1v8>; 200 }; 201 202 /* protectable identification memory (part of M24C64-D @50) */ 203 eeprom@58 { 204 compatible = "atmel,24c64d-wl"; 205 reg = <0x58>; 206 pagesize = <32>; 207 vcc-supply = <®_1v8>; 208 }; 209 210 /* protectable identification memory (part of M24C64-D @54) */ 211 eeprom@5c { 212 compatible = "atmel,24c64d-wl"; 213 reg = <0x5c>; 214 pagesize = <32>; 215 vcc-supply = <®_1v8>; 216 }; 217 218 pcieclk: clock-generator@6a { 219 compatible = "renesas,9fgv0441"; 220 reg = <0x6a>; 221 clocks = <&clk_xtal25>; 222 #clock-cells = <1>; 223 }; 224 225 imu@6b { 226 compatible = "st,ism330dhcx"; 227 reg = <0x6b>; 228 vdd-supply = <®_3v3>; 229 vddio-supply = <®_3v3>; 230 }; 231 232 /* D23 */ 233 expander2: gpio@74 { 234 compatible = "ti,tca9539"; 235 reg = <0x74>; 236 vcc-supply = <®_1v8>; 237 gpio-controller; 238 #gpio-cells = <2>; 239 gpio-line-names = "GPIO4", "LCD0_BLKT_EN", "LCD0_VDD_EN", "LCD1_BLKT_EN", 240 "LCD1_VDD_EN", "ENET1_RESET#", "ENET2_RESET#", "GBE0_SDP_DIR", 241 "GBE1_SDP_DIR", "PCIE1_RST#", "PCIE2_RST#", "DP_BRIDGE_EN", 242 "HUB_RST#", "QSPI_RESET#", "PCIE1_CLK_EN", "PCIE2_CLK_EN"; 243 }; 244 245 /* D21 */ 246 expander1: gpio@75 { 247 compatible = "ti,tca9539"; 248 reg = <0x75>; 249 vcc-supply = <®_1v8>; 250 pinctrl-names = "default"; 251 pinctrl-0 = <&pinctrl_expander1>; 252 gpio-controller; 253 #gpio-cells = <2>; 254 interrupt-controller; 255 #interrupt-cells = <2>; 256 interrupt-parent = <&gpio3>; 257 interrupts = <27 IRQ_TYPE_EDGE_FALLING>; 258 gpio-line-names = "GPIO10", "GPIO11", "GPIO12", "GPIO13", 259 "CHG_PRSNT#", "CHARGING", "LID", "BATLOW#", 260 "TEMP_EVENT#", "PGOOD_ARM", "PGOOD_SOC", "PCIE_WAKE#_1V8", 261 "GPIO0", "GPIO1", "GPIO2", "GPIO3"; 262 }; 263}; 264 265/* I2C_CAM0 */ 266&lpi2c3 { 267 clock-frequency = <400000>; 268 pinctrl-names = "default", "gpio"; 269 pinctrl-0 = <&pinctrl_lpi2c3>; 270 pinctrl-1 = <&pinctrl_lpi2c3_gpio>; 271 sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 272 scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 273 status = "okay"; 274 275 dp_bridge: dp-bridge@f { 276 compatible = "toshiba,tc9595", "toshiba,tc358767"; 277 reg = <0x0f>; 278 pinctrl-names = "default"; 279 pinctrl-0 = <&pinctrl_tc9595>; 280 clock-names = "ref"; 281 clocks = <&clk_dp>; 282 reset-gpios = <&expander2 11 GPIO_ACTIVE_HIGH>; 283 interrupt-parent = <&gpio2>; 284 interrupts = <25 IRQ_TYPE_EDGE_RISING>; 285 toshiba,hpd-pin = <0>; 286 status = "disabled"; 287 288 ports { 289 #address-cells = <1>; 290 #size-cells = <0>; 291 292 port@0 { 293 reg = <0>; 294 295 dp_dsi_in: endpoint { 296 /* TODO: DSI out */ 297 data-lanes = <1 2 3 4>; 298 }; 299 }; 300 }; 301 }; 302}; 303 304/* I2C_CAM1 */ 305&lpi2c4 { 306 clock-frequency = <400000>; 307 pinctrl-names = "default", "gpio"; 308 pinctrl-0 = <&pinctrl_lpi2c4>; 309 pinctrl-1 = <&pinctrl_lpi2c4_gpio>; 310 sda-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 311 scl-gpios = <&gpio2 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 312 status = "okay"; 313}; 314 315/* I2C_LCD */ 316&lpi2c6 { 317 clock-frequency = <400000>; 318 pinctrl-names = "default", "gpio"; 319 pinctrl-0 = <&pinctrl_lpi2c6>; 320 pinctrl-1 = <&pinctrl_lpi2c6_gpio>; 321 sda-gpios = <&gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 322 scl-gpios = <&gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 323 status = "okay"; 324}; 325 326&lpspi3 { 327 pinctrl-names = "default"; 328 pinctrl-0 = <&pinctrl_lpspi3>; 329 cs-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>, <&gpio2 7 GPIO_ACTIVE_LOW>; 330}; 331 332/* SER0 */ 333&lpuart1 { 334 pinctrl-names = "default"; 335 pinctrl-0 = <&pinctrl_lpuart1>; 336}; 337 338/* SER3 */ 339&lpuart5 { 340 pinctrl-names = "default"; 341 pinctrl-0 = <&pinctrl_lpuart5>; 342}; 343 344/* SER1 */ 345&lpuart7 { 346 pinctrl-names = "default"; 347 pinctrl-0 = <&pinctrl_lpuart7>; 348}; 349 350/* SER2 */ 351&lpuart8 { 352 pinctrl-names = "default"; 353 pinctrl-0 = <&pinctrl_lpuart8>; 354}; 355 356&netc_blk_ctrl { 357 status = "okay"; 358}; 359 360&netc_emdio { 361 pinctrl-names = "default"; 362 pinctrl-0 = <&pinctrl_mdio>; 363 status = "okay"; 364 365 ethphy0: ethernet-phy@0 { 366 compatible = "ethernet-phy-ieee802.3-c22"; 367 reg = <0>; 368 pinctrl-names = "default"; 369 pinctrl-0 = <&pinctrl_ethphy0>; 370 reset-gpios = <&expander2 5 GPIO_ACTIVE_LOW>; 371 reset-assert-us = <500000>; 372 reset-deassert-us = <50000>; 373 interrupt-parent = <&gpio5>; 374 interrupts = <13 IRQ_TYPE_LEVEL_LOW>; 375 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; 376 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; 377 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 378 ti,dp83867-rxctrl-strap-quirk; 379 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 380 }; 381 382 ethphy3: ethernet-phy@3 { 383 compatible = "ethernet-phy-ieee802.3-c22"; 384 reg = <3>; 385 pinctrl-names = "default"; 386 pinctrl-0 = <&pinctrl_ethphy3>; 387 reset-gpios = <&expander2 6 GPIO_ACTIVE_LOW>; 388 reset-assert-us = <500000>; 389 reset-deassert-us = <50000>; 390 interrupt-parent = <&gpio5>; 391 interrupts = <14 IRQ_TYPE_LEVEL_LOW>; 392 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; 393 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; 394 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 395 ti,dp83867-rxctrl-strap-quirk; 396 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 397 }; 398}; 399 400&pcie0 { 401 pinctrl-0 = <&pinctrl_pcie0>; 402 pinctrl-names = "default"; 403 clocks = <&scmi_clk IMX95_CLK_HSIO>, 404 <&scmi_clk IMX95_CLK_HSIOPLL>, 405 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 406 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, 407 <&pcieclk 1>; 408 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; 409 reset-gpios = <&expander2 9 GPIO_ACTIVE_LOW>; 410}; 411 412&pcie1 { 413 pinctrl-0 = <&pinctrl_pcie1>; 414 pinctrl-names = "default"; 415 clocks = <&scmi_clk IMX95_CLK_HSIO>, 416 <&scmi_clk IMX95_CLK_HSIOPLL>, 417 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 418 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, 419 <&pcieclk 0>; 420 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; 421 reset-gpios = <&expander2 10 GPIO_ACTIVE_LOW>; 422}; 423 424&sai3 { 425 #sound-dai-cells = <0>; 426 pinctrl-names = "default"; 427 pinctrl-0 = <&pinctrl_sai3>; 428 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 429 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 430 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 431 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 432 <&scmi_clk IMX95_CLK_SAI3>; 433 assigned-clock-parents = <0>, <0>, <0>, <0>, 434 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 435 assigned-clock-rates = <3932160000>, 436 <3612672000>, <393216000>, 437 <361267200>, <12288000>; 438 fsl,sai-mclk-direction-output; 439}; 440 441&sai5 { 442 #sound-dai-cells = <0>; 443 pinctrl-names = "default"; 444 pinctrl-0 = <&pinctrl_sai5>; 445 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 446 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 447 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 448 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 449 <&scmi_clk IMX95_CLK_SAI5>; 450 assigned-clock-parents = <0>, <0>, <0>, <0>, 451 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 452 assigned-clock-rates = <3932160000>, 453 <3612672000>, <393216000>, 454 <361267200>, <12288000>; 455}; 456 457&scmi_bbm { 458 linux,code = <KEY_POWER>; 459}; 460 461&tpm3 { 462 pinctrl-names = "default"; 463 pinctrl-0 = <&pinctrl_tpm3>; 464}; 465 466&tpm4 { 467 pinctrl-names = "default"; 468 pinctrl-0 = <&pinctrl_tpm4>; 469}; 470 471&tpm5 { 472 pinctrl-names = "default"; 473 pinctrl-0 = <&pinctrl_tpm5>; 474}; 475 476&usb3 { 477 status = "okay"; 478}; 479 480&usb3_dwc3 { 481 dr_mode = "host"; 482 #address-cells = <1>; 483 #size-cells = <0>; 484 485 hub_2_0: hub@1 { 486 compatible = "usb451,8142"; 487 reg = <1>; 488 peer-hub = <&hub_3_0>; 489 reset-gpios = <&expander2 12 GPIO_ACTIVE_LOW>; 490 vdd-supply = <®_3v3>; 491 }; 492 493 hub_3_0: hub@2 { 494 compatible = "usb451,8140"; 495 reg = <2>; 496 peer-hub = <&hub_2_0>; 497 reset-gpios = <&expander2 12 GPIO_ACTIVE_LOW>; 498 vdd-supply = <®_3v3>; 499 }; 500}; 501 502&usb3_phy { 503 status = "okay"; 504}; 505 506&usdhc1 { 507 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 508 pinctrl-0 = <&pinctrl_usdhc1>; 509 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 510 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 511 bus-width = <8>; 512 non-removable; 513 no-sdio; 514 no-sd; 515 status = "okay"; 516}; 517 518&usdhc2 { 519 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 520 pinctrl-0 = <&pinctrl_usdhc2>; 521 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 522 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 523 vmmc-supply = <®_sdvmmc>; 524 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 525 no-1-8-v; 526 disable-wp; 527 bus-width = <4>; 528}; 529 530&wdog3 { 531 status = "okay"; 532}; 533 534&scmi_iomuxc { 535 pinctrl_ethphy0: ethphy0grp { 536 fsl,pins = <IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x1100>; 537 }; 538 539 pinctrl_ethphy3: ethphy3grp { 540 fsl,pins = <IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x1100>; 541 }; 542 543 pinctrl_enetc0: enetc0grp { 544 fsl,pins = <IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x1100>, 545 <IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x1100>, 546 <IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x1100>, 547 <IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x1100>, 548 <IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x1100>, 549 <IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x1100>, 550 <IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x11e>, 551 <IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x11e>, 552 <IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x11e>, 553 <IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x11e>, 554 <IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x11e>, 555 <IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x11e>, 556 <IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23 0x51e>; 557 }; 558 559 pinctrl_enetc1: enetc1grp { 560 fsl,pins = <IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x1100>, 561 <IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x1100>, 562 <IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x1100>, 563 <IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x1100>, 564 <IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x1100>, 565 <IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x1100>, 566 <IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x11e>, 567 <IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x11e>, 568 <IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x11e>, 569 <IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x11e>, 570 <IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x11e>, 571 <IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x11e>, 572 <IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24 0x51e>; 573 }; 574 575 pinctrl_expander1: expander1grp { 576 fsl,pins = <IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x1100>; 577 }; 578 579 pinctrl_flexcan1: flexcan1grp { 580 fsl,pins = <IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x1300>, 581 <IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x31e>; 582 }; 583 584 pinctrl_flexcan3: flexcan3grp { 585 fsl,pins = <IMX95_PAD_CCM_CLKO3__CAN3_TX 0x31e>, 586 <IMX95_PAD_CCM_CLKO4__CAN3_RX 0x1300>; 587 }; 588 589 pinctrl_flexspi1: flexspi1grp { 590 fsl,pins = <IMX95_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x19e>, 591 <IMX95_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x19e>, 592 <IMX95_PAD_SD3_DATA0__FLEXSPI1_A_DATA_BIT0 0x19e>, 593 <IMX95_PAD_SD3_DATA1__FLEXSPI1_A_DATA_BIT1 0x19e>, 594 <IMX95_PAD_SD3_DATA2__FLEXSPI1_A_DATA_BIT2 0x19e>, 595 <IMX95_PAD_SD3_DATA3__FLEXSPI1_A_DATA_BIT3 0x19e>; 596 }; 597 598 pinctrl_gpio1: gpio1grp { 599 fsl,pins = <IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_BIT10 0x111e>, 600 <IMX95_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_BIT13 0x111e>, 601 <IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11 0x111e>; 602 }; 603 604 pinctrl_gpio2: gpio2grp { 605 fsl,pins = <IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x1100>, 606 <IMX95_PAD_GPIO_IO19__GPIO2_IO_BIT19 0x111e>, 607 <IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22 0x111e>; 608 }; 609 610 pinctrl_lpi2c1: lpi2c1grp { 611 fsl,pins = <IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x4000191e>, 612 <IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x4000191e>; 613 }; 614 615 pinctrl_lpi2c3: lpi2c3grp { 616 fsl,pins = <IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x4000191e>, 617 <IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x4000191e>; 618 }; 619 620 pinctrl_lpi2c3_gpio: lpi2c3-gpiogrp { 621 fsl,pins = <IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x4000191e>, 622 <IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x4000191e>; 623 }; 624 625 pinctrl_lpi2c4: lpi2c4grp { 626 fsl,pins = <IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x4000191e>, 627 <IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x4000191e>; 628 }; 629 630 pinctrl_lpi2c4_gpio: lpi2c4-gpiogrp { 631 fsl,pins = <IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30 0x4000191e>, 632 <IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31 0x4000191e>; 633 }; 634 635 pinctrl_lpi2c6: lpi2c6grp { 636 fsl,pins = <IMX95_PAD_GPIO_IO02__LPI2C6_SDA 0x4000191e>, 637 <IMX95_PAD_GPIO_IO03__LPI2C6_SCL 0x4000191e>; 638 }; 639 640 pinctrl_lpi2c6_gpio: lpi2c6-gpiogrp { 641 fsl,pins = <IMX95_PAD_GPIO_IO02__GPIO2_IO_BIT2 0x4000191e>, 642 <IMX95_PAD_GPIO_IO03__GPIO2_IO_BIT3 0x4000191e>; 643 }; 644 645 pinctrl_lpspi3: lpspi3grp { 646 fsl,pins = <IMX95_PAD_GPIO_IO07__GPIO2_IO_BIT7 0x51e>, 647 <IMX95_PAD_GPIO_IO08__GPIO2_IO_BIT8 0x51e>, 648 <IMX95_PAD_GPIO_IO09__LPSPI3_SIN 0x51e>, 649 <IMX95_PAD_GPIO_IO10__LPSPI3_SOUT 0x51e>, 650 <IMX95_PAD_GPIO_IO11__LPSPI3_SCK 0x51e>; 651 }; 652 653 pinctrl_lpuart1: lpuart1grp { 654 fsl,pins = <IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x1300>, 655 <IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e>, 656 <IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART1_RTS_B 0x1300>, 657 <IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART1_CTS_B 0x31e>; 658 }; 659 660 pinctrl_lpuart5: lpuart5grp { 661 fsl,pins = <IMX95_PAD_GPIO_IO00__LPUART5_TX 0x31e>, 662 <IMX95_PAD_GPIO_IO01__LPUART5_RX 0x1300>; 663 }; 664 665 pinctrl_lpuart7: lpuart7grp { 666 fsl,pins = <IMX95_PAD_GPIO_IO36__LPUART7_TX 0x31e>, 667 <IMX95_PAD_GPIO_IO37__LPUART7_RX 0x1300>; 668 }; 669 670 pinctrl_lpuart8: lpuart8grp { 671 fsl,pins = <IMX95_PAD_GPIO_IO12__LPUART8_TX 0x31e>, 672 <IMX95_PAD_GPIO_IO13__LPUART8_RX 0x1300>, 673 <IMX95_PAD_GPIO_IO14__LPUART8_CTS_B 0x31e>, 674 <IMX95_PAD_GPIO_IO15__LPUART8_RTS_B 0x1300>; 675 }; 676 677 pinctrl_mdio: mdiogrp { 678 fsl,pins = <IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x51e>, 679 <IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x51e>; 680 }; 681 682 pinctrl_pcf85063: pcf85063grp { 683 fsl,pins = <IMX95_PAD_GPIO_IO27__GPIO2_IO_BIT27 0x1100>; 684 }; 685 686 pinctrl_pcie0: pcie0grp { 687 fsl,pins = <IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x111e>; 688 }; 689 690 pinctrl_pcie1: pcie1grp { 691 fsl,pins = <IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x111e>; 692 }; 693 694 pinctrl_sai3: sai3grp { 695 fsl,pins = <IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x51e>, 696 <IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x51e>, 697 <IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x1300>, 698 <IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x51e>, 699 <IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x51e>; 700 }; 701 702 pinctrl_sai5: sai5grp { 703 fsl,pins = <IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0 0x51e>, 704 <IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC 0x51e>, 705 <IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK 0x51e>, 706 <IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0 0x1300>; 707 }; 708 709 pinctrl_sdvmmc: sdvmmcgrp { 710 fsl,pins = <IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x11e>; 711 }; 712 713 pinctrl_tc9595: tc9595grp { 714 fsl,pins = <IMX95_PAD_GPIO_IO25__GPIO2_IO_BIT25 0x1500>; 715 }; 716 717 pinctrl_tpm3: tpm3grp { 718 fsl,pins = <IMX95_PAD_GPIO_IO04__TPM3_CH0 0x51e>; 719 }; 720 721 pinctrl_tpm4: tpm4grp { 722 fsl,pins = <IMX95_PAD_GPIO_IO05__TPM4_CH0 0x51e>; 723 }; 724 725 pinctrl_tpm5: tpm5grp { 726 fsl,pins = <IMX95_PAD_GPIO_IO06__TPM5_CH0 0x51e>; 727 }; 728 729 pinctrl_usdhc1: usdhc1grp { 730 fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e>, 731 <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e>, 732 <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e>, 733 <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e>, 734 <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e>, 735 <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e>, 736 <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e>, 737 <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e>, 738 <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e>, 739 <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e>, 740 <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e>; 741 }; 742 743 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 744 fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e>, 745 <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e>, 746 <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e>, 747 <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e>, 748 <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e>, 749 <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e>, 750 <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e>, 751 <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e>, 752 <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e>, 753 <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e>, 754 <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e>; 755 }; 756 757 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 758 fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe>, 759 <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe>, 760 <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe>, 761 <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe>, 762 <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe>, 763 <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe>, 764 <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe>, 765 <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe>, 766 <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe>, 767 <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe>, 768 <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe>; 769 }; 770 771 pinctrl_usdhc2: usdhc2grp { 772 fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x1100>, 773 <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x51e>, 774 <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x31e>, 775 <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x131e>, 776 <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x131e>, 777 <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x131e>, 778 <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x131e>, 779 <IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e>; 780 }; 781 782 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 783 fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x1100>, 784 <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e>, 785 <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e>, 786 <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e>, 787 <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e>, 788 <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e>, 789 <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e>, 790 <IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e>; 791 }; 792 793 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 794 fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x1100>, 795 <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe>, 796 <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe>, 797 <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe>, 798 <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe>, 799 <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe>, 800 <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe>, 801 <IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e>; 802 }; 803}; 804