1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * https://beagleboard.org/ai-64 4 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 5 * Copyright (C) 2022-2024 Jason Kridner, BeagleBoard.org Foundation 6 * Copyright (C) 2022-2024 Robert Nelson, BeagleBoard.org Foundation 7 */ 8 9/dts-v1/; 10 11#include "k3-j721e.dtsi" 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/input/input.h> 14#include <dt-bindings/leds/common.h> 15#include <dt-bindings/net/ti-dp83867.h> 16#include <dt-bindings/phy/phy-cadence.h> 17 18/ { 19 compatible = "beagle,j721e-beagleboneai64", "ti,j721e"; 20 model = "BeagleBoard.org BeagleBone AI-64"; 21 22 aliases { 23 serial0 = &wkup_uart0; 24 serial2 = &main_uart0; 25 mmc0 = &main_sdhci0; 26 mmc1 = &main_sdhci1; 27 i2c0 = &wkup_i2c0; 28 i2c1 = &main_i2c6; 29 i2c2 = &main_i2c2; 30 i2c3 = &main_i2c4; 31 }; 32 33 chosen { 34 stdout-path = "serial2:115200n8"; 35 }; 36 37 memory@80000000 { 38 device_type = "memory"; 39 /* 4G RAM */ 40 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 41 <0x00000008 0x80000000 0x00000000 0x80000000>; 42 }; 43 44 reserved_memory: reserved-memory { 45 #address-cells = <2>; 46 #size-cells = <2>; 47 ranges; 48 49 secure_ddr: optee@9e800000 { 50 reg = <0x00 0x9e800000 0x00 0x01800000>; 51 no-map; 52 }; 53 54 mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { 55 compatible = "shared-dma-pool"; 56 reg = <0x00 0xa0000000 0x00 0x100000>; 57 no-map; 58 }; 59 60 mcu_r5fss0_core0_memory_region: memory@a0100000 { 61 compatible = "shared-dma-pool"; 62 reg = <0x00 0xa0100000 0x00 0xf00000>; 63 no-map; 64 }; 65 }; 66 67 gpio_keys: gpio-keys { 68 compatible = "gpio-keys"; 69 pinctrl-names = "default"; 70 pinctrl-0 = <&sw_pwr_pins_default>; 71 72 button-1 { 73 label = "BOOT"; 74 linux,code = <BTN_0>; 75 gpios = <&wkup_gpio0 0 GPIO_ACTIVE_LOW>; 76 }; 77 78 button-2 { 79 label = "POWER"; 80 linux,code = <KEY_POWER>; 81 gpios = <&wkup_gpio0 4 GPIO_ACTIVE_LOW>; 82 }; 83 }; 84 85 leds { 86 compatible = "gpio-leds"; 87 pinctrl-names = "default"; 88 pinctrl-0 = <&led_pins_default>; 89 90 led-0 { 91 gpios = <&main_gpio0 96 GPIO_ACTIVE_HIGH>; 92 function = LED_FUNCTION_HEARTBEAT; 93 linux,default-trigger = "heartbeat"; 94 }; 95 96 led-1 { 97 gpios = <&main_gpio0 95 GPIO_ACTIVE_HIGH>; 98 function = LED_FUNCTION_DISK_ACTIVITY; 99 linux,default-trigger = "mmc0"; 100 }; 101 102 led-2 { 103 gpios = <&main_gpio0 97 GPIO_ACTIVE_HIGH>; 104 function = LED_FUNCTION_CPU; 105 linux,default-trigger = "cpu"; 106 }; 107 108 led-3 { 109 gpios = <&main_gpio0 110 GPIO_ACTIVE_HIGH>; 110 function = LED_FUNCTION_DISK_ACTIVITY; 111 linux,default-trigger = "mmc1"; 112 }; 113 114 led-4 { 115 gpios = <&main_gpio0 109 GPIO_ACTIVE_HIGH>; 116 function = LED_FUNCTION_WLAN; 117 default-state = "off"; 118 }; 119 }; 120 121 evm_12v0: regulator-0 { 122 /* main supply */ 123 compatible = "regulator-fixed"; 124 regulator-name = "evm_12v0"; 125 regulator-min-microvolt = <12000000>; 126 regulator-max-microvolt = <12000000>; 127 regulator-always-on; 128 regulator-boot-on; 129 }; 130 131 vsys_3v3: regulator-1 { 132 /* Output of LMS140 */ 133 compatible = "regulator-fixed"; 134 regulator-name = "vsys_3v3"; 135 regulator-min-microvolt = <3300000>; 136 regulator-max-microvolt = <3300000>; 137 vin-supply = <&evm_12v0>; 138 regulator-always-on; 139 regulator-boot-on; 140 }; 141 142 vsys_5v0: regulator-2 { 143 /* Output of LM5140 */ 144 compatible = "regulator-fixed"; 145 regulator-name = "vsys_5v0"; 146 regulator-min-microvolt = <5000000>; 147 regulator-max-microvolt = <5000000>; 148 vin-supply = <&evm_12v0>; 149 regulator-always-on; 150 regulator-boot-on; 151 }; 152 153 vdd_mmc1: regulator-3 { 154 compatible = "regulator-fixed"; 155 pinctrl-names = "default"; 156 pinctrl-0 = <&sd_pwr_en_pins_default>; 157 regulator-name = "vdd_mmc1"; 158 regulator-min-microvolt = <3300000>; 159 regulator-max-microvolt = <3300000>; 160 regulator-boot-on; 161 enable-active-high; 162 vin-supply = <&vsys_3v3>; 163 gpio = <&main_gpio0 82 GPIO_ACTIVE_HIGH>; 164 }; 165 166 vdd_sd_dv_alt: regulator-4 { 167 compatible = "regulator-gpio"; 168 pinctrl-names = "default"; 169 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; 170 regulator-name = "tlv71033"; 171 regulator-min-microvolt = <1800000>; 172 regulator-max-microvolt = <3300000>; 173 regulator-boot-on; 174 vin-supply = <&vsys_5v0>; 175 gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>; 176 states = <1800000 0x0>, 177 <3300000 0x1>; 178 }; 179 180 dp_pwr_3v3: regulator-5 { 181 compatible = "regulator-fixed"; 182 pinctrl-names = "default"; 183 pinctrl-0 = <&dp0_3v3_en_pins_default>; 184 regulator-name = "dp-pwr"; 185 regulator-min-microvolt = <3300000>; 186 regulator-max-microvolt = <3300000>; 187 gpio = <&main_gpio0 49 GPIO_ACTIVE_HIGH>; /* DP0_PWR_SW_EN */ 188 enable-active-high; 189 }; 190 191 dp0: connector { 192 compatible = "dp-connector"; 193 label = "DP0"; 194 type = "full-size"; 195 dp-pwr-supply = <&dp_pwr_3v3>; 196 197 port { 198 dp_connector_in: endpoint { 199 remote-endpoint = <&dp0_out>; 200 }; 201 }; 202 }; 203}; 204 205&main_pmx0 { 206 led_pins_default: led-default-pins { 207 pinctrl-single,pins = < 208 J721E_IOPAD(0x184, PIN_INPUT, 7) /* (T23) RGMII5_RD0.GPIO0_96 */ 209 J721E_IOPAD(0x180, PIN_INPUT, 7) /* (R23) RGMII5_RD1.GPIO0_95 */ 210 J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */ 211 J721E_IOPAD(0x1bc, PIN_INPUT, 7) /* (V24) MDIO0_MDC.GPIO0_110 */ 212 J721E_IOPAD(0x1b8, PIN_INPUT, 7) /* (V26) MDIO0_MDIO.GPIO0_109 */ 213 >; 214 }; 215 216 main_mmc1_pins_default: main-mmc1-default-pins { 217 pinctrl-single,pins = < 218 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ 219 J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ 220 J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ 221 J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ 222 J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ 223 J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ 224 J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ 225 J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ 226 >; 227 }; 228 229 main_uart0_pins_default: main-uart0-default-pins { 230 pinctrl-single,pins = < 231 J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ 232 J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ 233 >; 234 }; 235 236 sd_pwr_en_pins_default: sd-pwr-en-default-pins { 237 pinctrl-single,pins = < 238 J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ 239 >; 240 }; 241 242 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { 243 pinctrl-single,pins = < 244 J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */ 245 >; 246 }; 247 248 main_usbss0_pins_default: main-usbss0-default-pins { 249 pinctrl-single,pins = < 250 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 - USBC_DIR */ 251 >; 252 }; 253 254 main_usbss1_pins_default: main-usbss1-default-pins { 255 pinctrl-single,pins = < 256 J721E_IOPAD(0x290, INPUT_DISABLE, 1) /* (U6) USB0_DRVVBUS.USB1_DRVVBUS */ 257 >; 258 }; 259 260 dp0_3v3_en_pins_default:dp0-3v3-en-default-pins { 261 pinctrl-single,pins = < 262 J721E_IOPAD(0xc8, PIN_INPUT, 7) /* (AE26) PRG0_PRU0_GPO6.GPIO0_49 */ 263 >; 264 }; 265 266 dp0_pins_default: dp0-default-pins { 267 pinctrl-single,pins = < 268 J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* (Y4) SPI0_CS1.DP0_HPD */ 269 >; 270 }; 271 272 main_i2c0_pins_default: main-i2c0-default-pins { 273 pinctrl-single,pins = < 274 J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ 275 J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ 276 >; 277 }; 278 279 main_i2c1_pins_default: main-i2c1-default-pins { 280 pinctrl-single,pins = < 281 J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ 282 J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ 283 >; 284 }; 285 286 main_i2c2_pins_default: main-i2c2-default-pins { 287 pinctrl-single,pins = < 288 J721E_IOPAD(0x208, PIN_INPUT_PULLUP, 4) /* (W5) MCAN0_RX.I2C2_SCL */ 289 J721E_IOPAD(0x20c, PIN_INPUT_PULLUP, 4) /* (W6) MCAN0_TX.I2C2_SDA */ 290 J721E_IOPAD(0x138, PIN_INPUT, 7) /* (AE25) PRG0_PRU1_GPO14.GPIO0_77 */ 291 J721E_IOPAD(0x13c, PIN_INPUT, 7) /* (AF29) PRG0_PRU1_GPO15.GPIO0_78 */ 292 >; 293 }; 294 295 main_i2c3_pins_default: main-i2c3-default-pins { 296 pinctrl-single,pins = < 297 J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ 298 J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ 299 >; 300 }; 301 302 main_i2c4_pins_default: main-i2c4-default-pins { 303 pinctrl-single,pins = < 304 J721E_IOPAD(0x1e0, PIN_INPUT_PULLUP, 2) /* (Y5) SPI1_D0.I2C4_SCL */ 305 J721E_IOPAD(0x1dc, PIN_INPUT_PULLUP, 2) /* (Y1) SPI1_CLK.I2C4_SDA */ 306 J721E_IOPAD(0x30, PIN_INPUT, 7) /* (AF24) PRG1_PRU0_GPO11.GPIO0_12 */ 307 J721E_IOPAD(0x34, PIN_INPUT, 7) /* (AJ24) PRG1_PRU0_GPO12.GPIO0_13 */ 308 >; 309 }; 310 311 main_i2c5_pins_default: main-i2c5-default-pins { 312 pinctrl-single,pins = < 313 J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ 314 J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ 315 >; 316 }; 317 318 main_i2c6_pins_default: main-i2c6-default-pins { 319 pinctrl-single,pins = < 320 J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */ 321 J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */ 322 J721E_IOPAD(0x74, PIN_INPUT, 7) /* (AC21) PRG1_PRU1_GPO7.GPIO0_28 */ 323 J721E_IOPAD(0xa4, PIN_INPUT, 7) /* (AH22) PRG1_PRU1_GPO19.GPIO0_40 */ 324 >; 325 }; 326 327 csi0_gpio_pins_default: csi0-gpio-default-pins { 328 pinctrl-single,pins = < 329 J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ 330 J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ 331 >; 332 }; 333 334 csi1_gpio_pins_default: csi1-gpio-default-pins { 335 pinctrl-single,pins = < 336 J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ 337 J721E_IOPAD(0x1b0, PIN_INPUT_PULLDOWN, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ 338 >; 339 }; 340 341 pcie1_rst_pins_default: pcie1-rst-default-pins { 342 pinctrl-single,pins = < 343 J721E_IOPAD(0x5c, PIN_INPUT, 7) /* (AG23) PRG1_PRU1_GPO1.GPIO0_22 */ 344 >; 345 }; 346}; 347 348&wkup_pmx0 { 349 eeprom_wp_pins_default: eeprom-wp-default-pins { 350 pinctrl-single,pins = < 351 J721E_WKUP_IOPAD(0xc4, PIN_OUTPUT_PULLUP, 7) /* (G24) WKUP_GPIO0_5 */ 352 >; 353 }; 354 355 mcu_adc0_pins_default: mcu-adc0-default-pins { 356 pinctrl-single,pins = < 357 J721E_WKUP_IOPAD(0x130, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN0 */ 358 J721E_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (K26) MCU_ADC0_AIN1 */ 359 J721E_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (K28) MCU_ADC0_AIN2 */ 360 J721E_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (L28) MCU_ADC0_AIN3 */ 361 J721E_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN4 */ 362 J721E_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (K27) MCU_ADC0_AIN5 */ 363 J721E_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (K29) MCU_ADC0_AIN6 */ 364 >; 365 }; 366 367 mcu_adc1_pins_default: mcu-adc1-default-pins { 368 pinctrl-single,pins = < 369 J721E_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (N23) MCU_ADC1_AIN0 */ 370 >; 371 }; 372 373 mikro_bus_pins_default: mikro-bus-default-pins { 374 pinctrl-single,pins = < 375 J721E_WKUP_IOPAD(0x108, PIN_INPUT, 7) /* SDAPULLEN (E26) PMIC_POWER_EN0.WKUP_GPIO0_66 */ 376 J721E_WKUP_IOPAD(0xd4, PIN_INPUT, 7) /* SDA (G26) WKUP_GPIO0_9.MCU_I2C1_SDA */ 377 J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 7) /* SDA (D25) MCU_I3C0_SDA.WKUP_GPIO0_61 */ 378 J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* SCL (G27) WKUP_GPIO0_8.MCU_I2C1_SCL */ 379 J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 7) /* SCL (D26) MCU_I3C0_SCL.WKUP_GPIO0_60 */ 380 381 J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* MOSI (F28) WKUP_GPIO0_2.MCU_SPI1_D1 */ 382 J721E_WKUP_IOPAD(0xb4, PIN_INPUT, 7) /* MISO (F25) WKUP_GPIO0_1.MCU_SPI1_D0 */ 383 J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* CLK (F26) WKUP_GPIO0_0.MCU_SPI1_CLK */ 384 J721E_WKUP_IOPAD(0xbc, PIN_INPUT, 7) /* CS (F27) WKUP_GPIO0_3.MCU_SPI1_CS0 */ 385 386 J721E_WKUP_IOPAD(0x44, PIN_INPUT, 7) /* RX (G22) MCU_OSPI1_D1.WKUP_GPIO0_33 */ 387 J721E_WKUP_IOPAD(0x48, PIN_INPUT, 7) /* TX (D23) MCU_OSPI1_D2.WKUP_GPIO0_34 */ 388 389 J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 7) /* INT (C23) MCU_OSPI1_D3.WKUP_GPIO0_35 */ 390 J721E_WKUP_IOPAD(0x54, PIN_INPUT, 7) /* RST (E22) MCU_OSPI1_CSn1.WKUP_GPIO0_37 */ 391 J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* PWM (H27) WKUP_GPIO0_11 */ 392 J721E_WKUP_IOPAD(0xac, PIN_INPUT, 7) /* AN (C29) MCU_MCAN0_RX.WKUP_GPIO0_59 */ 393 >; 394 }; 395 396 mcu_cpsw_pins_default: mcu-cpsw-default-pins { 397 pinctrl-single,pins = < 398 J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */ 399 J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */ 400 J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */ 401 J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */ 402 J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */ 403 J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */ 404 J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */ 405 J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */ 406 J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */ 407 J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */ 408 J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */ 409 J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */ 410 >; 411 }; 412 413 mcu_mdio_pins_default: mcu-mdio1-default-pins { 414 pinctrl-single,pins = < 415 J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */ 416 J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */ 417 >; 418 }; 419 420 sw_pwr_pins_default: sw-pwr-default-pins { 421 pinctrl-single,pins = < 422 J721E_WKUP_IOPAD(0xc0, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_4 */ 423 >; 424 }; 425 426 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 427 pinctrl-single,pins = < 428 J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ 429 J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ 430 >; 431 }; 432 433 wkup_uart0_pins_default: wkup-uart0-default-pins { 434 pinctrl-single,pins = < 435 J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ 436 J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ 437 >; 438 }; 439 440 mcu_usbss1_pins_default: mcu-usbss1-default-pins { 441 pinctrl-single,pins = < 442 J721E_WKUP_IOPAD(0x3c, PIN_OUTPUT_PULLUP, 5) /* (A23) MCU_OSPI1_LBCLKO.WKUP_GPIO0_30 */ 443 >; 444 }; 445}; 446 447&wkup_uart0 { 448 /* Wakeup UART is used by TIFS firmware. */ 449 status = "reserved"; 450 pinctrl-names = "default"; 451 pinctrl-0 = <&wkup_uart0_pins_default>; 452}; 453 454&main_uart0 { 455 status = "okay"; 456 pinctrl-names = "default"; 457 pinctrl-0 = <&main_uart0_pins_default>; 458 /* Shared with ATF on this platform */ 459 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 460}; 461 462&main_sdhci0 { 463 /* eMMC */ 464 status = "okay"; 465 non-removable; 466 ti,driver-strength-ohm = <50>; 467 disable-wp; 468}; 469 470&main_sdhci1 { 471 /* SD Card */ 472 status = "okay"; 473 vmmc-supply = <&vdd_mmc1>; 474 vqmmc-supply = <&vdd_sd_dv_alt>; 475 pinctrl-names = "default"; 476 pinctrl-0 = <&main_mmc1_pins_default>; 477 ti,driver-strength-ohm = <50>; 478 disable-wp; 479}; 480 481&main_i2c0 { 482 status = "okay"; 483 pinctrl-names = "default"; 484 pinctrl-0 = <&main_i2c0_pins_default>; 485 clock-frequency = <400000>; 486}; 487 488&main_i2c1 { 489 status = "okay"; 490 pinctrl-names = "default"; 491 pinctrl-0 = <&main_i2c1_pins_default>; 492 clock-frequency = <400000>; 493}; 494 495&main_i2c2 { 496 /* BBB Header: P9.19 and P9.20 */ 497 status = "okay"; 498 pinctrl-names = "default"; 499 pinctrl-0 = <&main_i2c2_pins_default>; 500 clock-frequency = <100000>; 501}; 502 503&main_i2c3 { 504 status = "okay"; 505 pinctrl-names = "default"; 506 pinctrl-0 = <&main_i2c3_pins_default>; 507 clock-frequency = <400000>; 508}; 509 510&main_i2c4 { 511 /* BBB Header: P9.24 and P9.26 */ 512 status = "okay"; 513 pinctrl-names = "default"; 514 pinctrl-0 = <&main_i2c4_pins_default>; 515 clock-frequency = <100000>; 516}; 517 518&main_i2c5 { 519 status = "okay"; 520 pinctrl-names = "default"; 521 pinctrl-0 = <&main_i2c5_pins_default>; 522 clock-frequency = <400000>; 523}; 524 525&main_i2c6 { 526 /* BBB Header: P9.17 and P9.18 */ 527 status = "okay"; 528 pinctrl-names = "default"; 529 pinctrl-0 = <&main_i2c6_pins_default>; 530 clock-frequency = <100000>; 531 status = "okay"; 532}; 533 534&wkup_i2c0 { 535 status = "okay"; 536 pinctrl-names = "default"; 537 pinctrl-0 = <&wkup_i2c0_pins_default>; 538 clock-frequency = <400000>; 539 540 eeprom@50 { 541 compatible = "atmel,24c04"; 542 reg = <0x50>; 543 pinctrl-names = "default"; 544 pinctrl-0 = <&eeprom_wp_pins_default>; 545 }; 546}; 547 548&wkup_gpio0 { 549 status = "okay"; 550 pinctrl-names = "default"; 551 pinctrl-0 = <&mcu_adc0_pins_default>, <&mcu_adc1_pins_default>, 552 <&mikro_bus_pins_default>; 553}; 554 555&main_gpio0 { 556 status = "okay"; 557 pinctrl-names = "default"; 558 pinctrl-0 = <&csi1_gpio_pins_default>, <&csi0_gpio_pins_default>; 559}; 560 561&main_gpio1 { 562 status = "okay"; 563}; 564 565&usb_serdes_mux { 566 idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ 567}; 568 569&serdes_ln_ctrl { 570 idle-states = <J721E_SERDES0_LANE0_IP4_UNUSED>, <J721E_SERDES0_LANE1_IP4_UNUSED>, 571 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 572 <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>, 573 <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, 574 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 575 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 576}; 577 578&serdes_wiz3 { 579 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_LOW>; 580 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ 581}; 582 583&serdes3 { 584 serdes3_usb_link: phy@0 { 585 reg = <0>; 586 cdns,num-lanes = <2>; 587 #phy-cells = <0>; 588 cdns,phy-type = <PHY_TYPE_USB3>; 589 resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; 590 }; 591}; 592 593&serdes4 { 594 torrent_phy_dp: phy@0 { 595 reg = <0>; 596 resets = <&serdes_wiz4 1>; 597 cdns,phy-type = <PHY_TYPE_DP>; 598 cdns,num-lanes = <4>; 599 cdns,max-bit-rate = <5400>; 600 #phy-cells = <0>; 601 }; 602}; 603 604&mhdp { 605 phys = <&torrent_phy_dp>; 606 phy-names = "dpphy"; 607 pinctrl-names = "default"; 608 pinctrl-0 = <&dp0_pins_default>; 609}; 610 611&usbss0 { 612 pinctrl-names = "default"; 613 pinctrl-0 = <&main_usbss0_pins_default>; 614 ti,vbus-divider; 615}; 616 617&usb0 { 618 dr_mode = "peripheral"; 619 maximum-speed = "super-speed"; 620 phys = <&serdes3_usb_link>; 621 phy-names = "cdns3,usb3-phy"; 622}; 623 624&serdes2 { 625 serdes2_usb_link: phy@1 { 626 reg = <1>; 627 cdns,num-lanes = <1>; 628 #phy-cells = <0>; 629 cdns,phy-type = <PHY_TYPE_USB3>; 630 resets = <&serdes_wiz2 2>; 631 }; 632}; 633 634&usbss1 { 635 pinctrl-names = "default"; 636 pinctrl-0 = <&main_usbss1_pins_default>, <&mcu_usbss1_pins_default>; 637 ti,vbus-divider; 638}; 639 640&usb1 { 641 dr_mode = "host"; 642 maximum-speed = "super-speed"; 643 phys = <&serdes2_usb_link>; 644 phy-names = "cdns3,usb3-phy"; 645}; 646 647&tscadc0 { 648 status = "okay"; 649 /* BBB Header: P9.39, P9.40, P9.37, P9.38, P9.33, P9.36, P9.35 */ 650 adc { 651 ti,adc-channels = <0 1 2 3 4 5 6>; 652 }; 653}; 654 655&tscadc1 { 656 status = "okay"; 657 /* MCU mikroBUS Header J10.1 - MCU_ADC1_AIN0 */ 658 adc { 659 ti,adc-channels = <0>; 660 }; 661}; 662 663&mcu_cpsw { 664 pinctrl-names = "default"; 665 pinctrl-0 = <&mcu_cpsw_pins_default>; 666 status = "okay"; 667}; 668 669&davinci_mdio { 670 pinctrl-names = "default"; 671 pinctrl-0 = <&mcu_mdio_pins_default>; 672 673 phy0: ethernet-phy@0 { 674 reg = <0>; 675 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 676 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 677 }; 678}; 679 680&cpsw_port1 { 681 phy-mode = "rgmii-id"; 682 phy-handle = <&phy0>; 683}; 684 685&dss { 686 /* 687 * These clock assignments are chosen to enable the following outputs: 688 * 689 * VP0 - DisplayPort SST 690 * VP1 - DPI0 691 * VP2 - DSI 692 * VP3 - DPI1 693 */ 694 695 assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */ 696 <&k3_clks 152 4>, /* VP 2 pixel clock */ 697 <&k3_clks 152 9>, /* VP 3 pixel clock */ 698 <&k3_clks 152 13>; /* VP 4 pixel clock */ 699 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ 700 <&k3_clks 152 6>, /* PLL19_HSDIV0 */ 701 <&k3_clks 152 11>, /* PLL18_HSDIV0 */ 702 <&k3_clks 152 18>; /* PLL23_HSDIV0 */ 703}; 704 705&dss_ports { 706 port { 707 dpi0_out: endpoint { 708 remote-endpoint = <&dp0_in>; 709 }; 710 }; 711}; 712 713&dp0_ports { 714 #address-cells = <1>; 715 #size-cells = <0>; 716 717 port@0 { 718 reg = <0>; 719 dp0_in: endpoint { 720 remote-endpoint = <&dpi0_out>; 721 }; 722 }; 723 724 port@4 { 725 reg = <4>; 726 dp0_out: endpoint { 727 remote-endpoint = <&dp_connector_in>; 728 }; 729 }; 730}; 731 732&serdes0 { 733 serdes0_pcie_link: phy@0 { 734 reg = <0>; 735 cdns,num-lanes = <1>; 736 #phy-cells = <0>; 737 cdns,phy-type = <PHY_TYPE_PCIE>; 738 resets = <&serdes_wiz0 1>; 739 }; 740}; 741 742&serdes1 { 743 serdes1_pcie_link: phy@0 { 744 reg = <0>; 745 cdns,num-lanes = <2>; 746 #phy-cells = <0>; 747 cdns,phy-type = <PHY_TYPE_PCIE>; 748 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; 749 }; 750}; 751 752&pcie1_rc { 753 status = "okay"; 754 pinctrl-names = "default"; 755 pinctrl-0 = <&pcie1_rst_pins_default>; 756 phys = <&serdes1_pcie_link>; 757 phy-names = "pcie-phy"; 758 num-lanes = <2>; 759 max-link-speed = <3>; 760 reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>; 761}; 762 763&ufs_wrapper { 764 status = "disabled"; 765}; 766 767#include "k3-j721e-ti-ipc-firmware.dtsi" 768