1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * omap-mcpdm.c -- OMAP ALSA SoC DAI driver using McPDM port
4 *
5 * Copyright (C) 2009 - 2011 Texas Instruments
6 *
7 * Author: Misael Lopez Cruz <misael.lopez@ti.com>
8 * Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
9 * Margarita Olaya <magi.olaya@ti.com>
10 * Peter Ujfalusi <peter.ujfalusi@ti.com>
11 */
12
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/interrupt.h>
17 #include <linux/err.h>
18 #include <linux/io.h>
19 #include <linux/irq.h>
20 #include <linux/slab.h>
21 #include <linux/pm_runtime.h>
22
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
27 #include <sound/dmaengine_pcm.h>
28
29 #include "omap-mcpdm.h"
30 #include "sdma-pcm.h"
31
32 struct mcpdm_link_config {
33 u32 link_mask; /* channel mask for the direction */
34 u32 threshold; /* FIFO threshold */
35 };
36
37 struct omap_mcpdm {
38 struct device *dev;
39 unsigned long phys_base;
40 void __iomem *io_base;
41 int irq;
42 struct pm_qos_request pm_qos_req;
43 int latency[2];
44
45 struct mutex mutex;
46
47 /* Playback/Capture configuration */
48 struct mcpdm_link_config config[2];
49
50 /* McPDM dn offsets for rx1, and 2 channels */
51 u32 dn_rx_offset;
52
53 /* McPDM needs to be restarted due to runtime reconfiguration */
54 bool restart;
55
56 /* pm state for suspend/resume handling */
57 int pm_active_count;
58
59 struct snd_dmaengine_dai_dma_data dma_data[2];
60 };
61
62 /*
63 * Stream DMA parameters
64 */
65
omap_mcpdm_write(struct omap_mcpdm * mcpdm,u16 reg,u32 val)66 static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
67 {
68 writel_relaxed(val, mcpdm->io_base + reg);
69 }
70
omap_mcpdm_read(struct omap_mcpdm * mcpdm,u16 reg)71 static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
72 {
73 return readl_relaxed(mcpdm->io_base + reg);
74 }
75
76 #ifdef DEBUG
omap_mcpdm_reg_dump(struct omap_mcpdm * mcpdm)77 static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
78 {
79 dev_dbg(mcpdm->dev, "***********************\n");
80 dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n",
81 omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
82 dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n",
83 omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
84 dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n",
85 omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
86 dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n",
87 omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
88 dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
89 omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
90 dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
91 omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
92 dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n",
93 omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
94 dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n",
95 omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
96 dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n",
97 omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
98 dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n",
99 omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
100 dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
101 omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
102 dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
103 omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
104 dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n",
105 omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
106 dev_dbg(mcpdm->dev, "***********************\n");
107 }
108 #else
omap_mcpdm_reg_dump(struct omap_mcpdm * mcpdm)109 static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
110 #endif
111
112 /*
113 * Enables the transfer through the PDM interface to/from the Phoenix
114 * codec by enabling the corresponding UP or DN channels.
115 */
omap_mcpdm_start(struct omap_mcpdm * mcpdm)116 static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
117 {
118 u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
119 u32 link_mask = mcpdm->config[0].link_mask | mcpdm->config[1].link_mask;
120
121 ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
122 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
123
124 ctrl |= link_mask;
125 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
126
127 ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
128 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
129 }
130
131 /*
132 * Disables the transfer through the PDM interface to/from the Phoenix
133 * codec by disabling the corresponding UP or DN channels.
134 */
omap_mcpdm_stop(struct omap_mcpdm * mcpdm)135 static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
136 {
137 u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
138 u32 link_mask = MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK;
139
140 ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
141 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
142
143 ctrl &= ~(link_mask);
144 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
145
146 ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
147 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
148
149 }
150
151 /*
152 * Is the physical McPDM interface active.
153 */
omap_mcpdm_active(struct omap_mcpdm * mcpdm)154 static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
155 {
156 return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
157 (MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK);
158 }
159
160 /*
161 * Configures McPDM uplink, and downlink for audio.
162 * This function should be called before omap_mcpdm_start.
163 */
omap_mcpdm_open_streams(struct omap_mcpdm * mcpdm)164 static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
165 {
166 u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
167
168 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl | MCPDM_WD_EN);
169
170 omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
171 MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL |
172 MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
173
174 /* Enable DN RX1/2 offset cancellation feature, if configured */
175 if (mcpdm->dn_rx_offset) {
176 u32 dn_offset = mcpdm->dn_rx_offset;
177
178 omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
179 dn_offset |= (MCPDM_DN_OFST_RX1_EN | MCPDM_DN_OFST_RX2_EN);
180 omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
181 }
182
183 omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN,
184 mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold);
185 omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP,
186 mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold);
187
188 omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
189 MCPDM_DMA_DN_ENABLE | MCPDM_DMA_UP_ENABLE);
190 }
191
192 /*
193 * Cleans McPDM uplink, and downlink configuration.
194 * This function should be called when the stream is closed.
195 */
omap_mcpdm_close_streams(struct omap_mcpdm * mcpdm)196 static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
197 {
198 /* Disable irq request generation for downlink */
199 omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
200 MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL);
201
202 /* Disable DMA request generation for downlink */
203 omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);
204
205 /* Disable irq request generation for uplink */
206 omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
207 MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
208
209 /* Disable DMA request generation for uplink */
210 omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);
211
212 /* Disable RX1/2 offset cancellation */
213 if (mcpdm->dn_rx_offset)
214 omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
215 }
216
omap_mcpdm_irq_handler(int irq,void * dev_id)217 static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
218 {
219 struct omap_mcpdm *mcpdm = dev_id;
220 int irq_status;
221
222 irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);
223
224 /* Acknowledge irq event */
225 omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);
226
227 if (irq_status & MCPDM_DN_IRQ_FULL)
228 dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");
229
230 if (irq_status & MCPDM_DN_IRQ_EMPTY)
231 dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");
232
233 if (irq_status & MCPDM_DN_IRQ)
234 dev_dbg(mcpdm->dev, "DN (playback) write request\n");
235
236 if (irq_status & MCPDM_UP_IRQ_FULL)
237 dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");
238
239 if (irq_status & MCPDM_UP_IRQ_EMPTY)
240 dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");
241
242 if (irq_status & MCPDM_UP_IRQ)
243 dev_dbg(mcpdm->dev, "UP (capture) write request\n");
244
245 return IRQ_HANDLED;
246 }
247
omap_mcpdm_dai_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)248 static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
249 struct snd_soc_dai *dai)
250 {
251 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
252
253 guard(mutex)(&mcpdm->mutex);
254
255 if (!snd_soc_dai_active(dai))
256 omap_mcpdm_open_streams(mcpdm);
257
258 return 0;
259 }
260
omap_mcpdm_dai_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)261 static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
262 struct snd_soc_dai *dai)
263 {
264 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
265 int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
266 int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE;
267 int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK;
268
269 guard(mutex)(&mcpdm->mutex);
270
271 if (!snd_soc_dai_active(dai)) {
272 if (omap_mcpdm_active(mcpdm)) {
273 omap_mcpdm_stop(mcpdm);
274 omap_mcpdm_close_streams(mcpdm);
275 mcpdm->config[0].link_mask = 0;
276 mcpdm->config[1].link_mask = 0;
277 }
278 }
279
280 if (mcpdm->latency[stream2])
281 cpu_latency_qos_update_request(&mcpdm->pm_qos_req,
282 mcpdm->latency[stream2]);
283 else if (mcpdm->latency[stream1])
284 cpu_latency_qos_remove_request(&mcpdm->pm_qos_req);
285
286 mcpdm->latency[stream1] = 0;
287 }
288
omap_mcpdm_dai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)289 static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
290 struct snd_pcm_hw_params *params,
291 struct snd_soc_dai *dai)
292 {
293 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
294 int stream = substream->stream;
295 struct snd_dmaengine_dai_dma_data *dma_data;
296 u32 threshold;
297 int channels, latency;
298 int link_mask = 0;
299
300 channels = params_channels(params);
301 switch (channels) {
302 case 5:
303 if (stream == SNDRV_PCM_STREAM_CAPTURE)
304 /* up to 3 channels for capture */
305 return -EINVAL;
306 link_mask |= 1 << 4;
307 fallthrough;
308 case 4:
309 if (stream == SNDRV_PCM_STREAM_CAPTURE)
310 /* up to 3 channels for capture */
311 return -EINVAL;
312 link_mask |= 1 << 3;
313 fallthrough;
314 case 3:
315 link_mask |= 1 << 2;
316 fallthrough;
317 case 2:
318 link_mask |= 1 << 1;
319 fallthrough;
320 case 1:
321 link_mask |= 1 << 0;
322 break;
323 default:
324 /* unsupported number of channels */
325 return -EINVAL;
326 }
327
328 dma_data = snd_soc_dai_get_dma_data(dai, substream);
329
330 threshold = mcpdm->config[stream].threshold;
331 /* Configure McPDM channels, and DMA packet size */
332 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
333 link_mask <<= 3;
334
335 /* If capture is not running assume a stereo stream to come */
336 if (!mcpdm->config[!stream].link_mask)
337 mcpdm->config[!stream].link_mask = 0x3;
338
339 dma_data->maxburst =
340 (MCPDM_DN_THRES_MAX - threshold) * channels;
341 latency = threshold;
342 } else {
343 /* If playback is not running assume a stereo stream to come */
344 if (!mcpdm->config[!stream].link_mask)
345 mcpdm->config[!stream].link_mask = (0x3 << 3);
346
347 dma_data->maxburst = threshold * channels;
348 latency = (MCPDM_DN_THRES_MAX - threshold);
349 }
350
351 /*
352 * The DMA must act to a DMA request within latency time (usec) to avoid
353 * under/overflow
354 */
355 mcpdm->latency[stream] = latency * USEC_PER_SEC / params_rate(params);
356
357 if (!mcpdm->latency[stream])
358 mcpdm->latency[stream] = 10;
359
360 /* Check if we need to restart McPDM with this stream */
361 if (mcpdm->config[stream].link_mask &&
362 mcpdm->config[stream].link_mask != link_mask)
363 mcpdm->restart = true;
364
365 mcpdm->config[stream].link_mask = link_mask;
366
367 return 0;
368 }
369
omap_mcpdm_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)370 static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
371 struct snd_soc_dai *dai)
372 {
373 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
374 struct pm_qos_request *pm_qos_req = &mcpdm->pm_qos_req;
375 int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
376 int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE;
377 int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK;
378 int latency = mcpdm->latency[stream2];
379
380 /* Prevent omap hardware from hitting off between FIFO fills */
381 if (!latency || mcpdm->latency[stream1] < latency)
382 latency = mcpdm->latency[stream1];
383
384 if (cpu_latency_qos_request_active(pm_qos_req))
385 cpu_latency_qos_update_request(pm_qos_req, latency);
386 else if (latency)
387 cpu_latency_qos_add_request(pm_qos_req, latency);
388
389 if (!omap_mcpdm_active(mcpdm)) {
390 omap_mcpdm_start(mcpdm);
391 omap_mcpdm_reg_dump(mcpdm);
392 } else if (mcpdm->restart) {
393 omap_mcpdm_stop(mcpdm);
394 omap_mcpdm_start(mcpdm);
395 mcpdm->restart = false;
396 omap_mcpdm_reg_dump(mcpdm);
397 }
398
399 return 0;
400 }
401
omap_mcpdm_probe(struct snd_soc_dai * dai)402 static int omap_mcpdm_probe(struct snd_soc_dai *dai)
403 {
404 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
405 int ret;
406
407 pm_runtime_enable(mcpdm->dev);
408
409 /* Disable lines while request is ongoing */
410 pm_runtime_get_sync(mcpdm->dev);
411 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);
412
413 ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler, 0, "McPDM",
414 (void *)mcpdm);
415
416 pm_runtime_put_sync(mcpdm->dev);
417
418 if (ret) {
419 dev_err(mcpdm->dev, "Request for IRQ failed\n");
420 pm_runtime_disable(mcpdm->dev);
421 }
422
423 /* Configure McPDM threshold values */
424 mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold = 2;
425 mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold =
426 MCPDM_UP_THRES_MAX - 3;
427
428 snd_soc_dai_init_dma_data(dai,
429 &mcpdm->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
430 &mcpdm->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
431
432 return ret;
433 }
434
omap_mcpdm_remove(struct snd_soc_dai * dai)435 static int omap_mcpdm_remove(struct snd_soc_dai *dai)
436 {
437 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
438
439 free_irq(mcpdm->irq, (void *)mcpdm);
440 pm_runtime_disable(mcpdm->dev);
441
442 if (cpu_latency_qos_request_active(&mcpdm->pm_qos_req))
443 cpu_latency_qos_remove_request(&mcpdm->pm_qos_req);
444
445 return 0;
446 }
447
448 static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
449 .probe = omap_mcpdm_probe,
450 .remove = omap_mcpdm_remove,
451 .startup = omap_mcpdm_dai_startup,
452 .shutdown = omap_mcpdm_dai_shutdown,
453 .hw_params = omap_mcpdm_dai_hw_params,
454 .prepare = omap_mcpdm_prepare,
455 .probe_order = SND_SOC_COMP_ORDER_LATE,
456 .remove_order = SND_SOC_COMP_ORDER_EARLY,
457 };
458
459 #ifdef CONFIG_PM_SLEEP
omap_mcpdm_suspend(struct snd_soc_component * component)460 static int omap_mcpdm_suspend(struct snd_soc_component *component)
461 {
462 struct omap_mcpdm *mcpdm = snd_soc_component_get_drvdata(component);
463
464 if (snd_soc_component_active(component)) {
465 omap_mcpdm_stop(mcpdm);
466 omap_mcpdm_close_streams(mcpdm);
467 }
468
469 mcpdm->pm_active_count = 0;
470 while (pm_runtime_active(mcpdm->dev)) {
471 pm_runtime_put_sync(mcpdm->dev);
472 mcpdm->pm_active_count++;
473 }
474
475 return 0;
476 }
477
omap_mcpdm_resume(struct snd_soc_component * component)478 static int omap_mcpdm_resume(struct snd_soc_component *component)
479 {
480 struct omap_mcpdm *mcpdm = snd_soc_component_get_drvdata(component);
481
482 if (mcpdm->pm_active_count) {
483 while (mcpdm->pm_active_count--)
484 pm_runtime_get_sync(mcpdm->dev);
485
486 if (snd_soc_component_active(component)) {
487 omap_mcpdm_open_streams(mcpdm);
488 omap_mcpdm_start(mcpdm);
489 }
490 }
491
492
493 return 0;
494 }
495 #else
496 #define omap_mcpdm_suspend NULL
497 #define omap_mcpdm_resume NULL
498 #endif
499
500 #define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
501 #define OMAP_MCPDM_FORMATS SNDRV_PCM_FMTBIT_S32_LE
502
503 static struct snd_soc_dai_driver omap_mcpdm_dai = {
504 .playback = {
505 .channels_min = 1,
506 .channels_max = 5,
507 .rates = OMAP_MCPDM_RATES,
508 .formats = OMAP_MCPDM_FORMATS,
509 .sig_bits = 24,
510 },
511 .capture = {
512 .channels_min = 1,
513 .channels_max = 3,
514 .rates = OMAP_MCPDM_RATES,
515 .formats = OMAP_MCPDM_FORMATS,
516 .sig_bits = 24,
517 },
518 .ops = &omap_mcpdm_dai_ops,
519 };
520
521 static const struct snd_soc_component_driver omap_mcpdm_component = {
522 .name = "omap-mcpdm",
523 .suspend = omap_mcpdm_suspend,
524 .resume = omap_mcpdm_resume,
525 .legacy_dai_naming = 1,
526 };
527
omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime * rtd,u8 rx1,u8 rx2)528 void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
529 u8 rx1, u8 rx2)
530 {
531 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(snd_soc_rtd_to_cpu(rtd, 0));
532
533 mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) | MCPDM_DNOFST_RX2(rx2);
534 }
535 EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);
536
asoc_mcpdm_probe(struct platform_device * pdev)537 static int asoc_mcpdm_probe(struct platform_device *pdev)
538 {
539 struct omap_mcpdm *mcpdm;
540 struct resource *res;
541 int ret;
542
543 mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL);
544 if (!mcpdm)
545 return -ENOMEM;
546
547 platform_set_drvdata(pdev, mcpdm);
548
549 mutex_init(&mcpdm->mutex);
550
551 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
552 if (res == NULL)
553 return -ENOMEM;
554
555 mcpdm->dma_data[0].addr = res->start + MCPDM_REG_DN_DATA;
556 mcpdm->dma_data[1].addr = res->start + MCPDM_REG_UP_DATA;
557
558 mcpdm->dma_data[0].filter_data = "dn_link";
559 mcpdm->dma_data[1].filter_data = "up_link";
560
561 mcpdm->io_base = devm_platform_ioremap_resource_byname(pdev, "mpu");
562 if (IS_ERR(mcpdm->io_base))
563 return PTR_ERR(mcpdm->io_base);
564
565 mcpdm->irq = platform_get_irq(pdev, 0);
566 if (mcpdm->irq < 0)
567 return mcpdm->irq;
568
569 mcpdm->dev = &pdev->dev;
570
571 ret = devm_snd_soc_register_component(&pdev->dev,
572 &omap_mcpdm_component,
573 &omap_mcpdm_dai, 1);
574 if (ret)
575 return ret;
576
577 return sdma_pcm_platform_register(&pdev->dev, "dn_link", "up_link");
578 }
579
580 static const struct of_device_id omap_mcpdm_of_match[] = {
581 { .compatible = "ti,omap4-mcpdm", },
582 { }
583 };
584 MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match);
585
586 static struct platform_driver asoc_mcpdm_driver = {
587 .driver = {
588 .name = "omap-mcpdm",
589 .of_match_table = omap_mcpdm_of_match,
590 },
591
592 .probe = asoc_mcpdm_probe,
593 };
594
595 module_platform_driver(asoc_mcpdm_driver);
596
597 MODULE_ALIAS("platform:omap-mcpdm");
598 MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
599 MODULE_DESCRIPTION("OMAP PDM SoC Interface");
600 MODULE_LICENSE("GPL");
601