1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 *
4 * Copyright (C) STMicroelectronics SA 2017
5 * Author(s): M'boumba Cedric Madianga <cedric.madianga@gmail.com>
6 * Pierre-Yves Mordret <pierre-yves.mordret@st.com>
7 *
8 * DMA Router driver for STM32 DMA MUX
9 *
10 * Based on TI DMA Crossbar driver
11 */
12
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/err.h>
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/of_dma.h>
20 #include <linux/of_platform.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/reset.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26
27 #define STM32_DMAMUX_CCR(x) (0x4 * (x))
28 #define STM32_DMAMUX_MAX_DMA_REQUESTS 32
29 #define STM32_DMAMUX_MAX_REQUESTS 255
30
31 struct stm32_dmamux {
32 u32 master;
33 u32 request;
34 u32 chan_id;
35 };
36
37 struct stm32_dmamux_data {
38 struct dma_router dmarouter;
39 struct clk *clk;
40 void __iomem *iomem;
41 u32 dma_requests; /* Number of DMA requests connected to DMAMUX */
42 u32 dmamux_requests; /* Number of DMA requests routed toward DMAs */
43 spinlock_t lock; /* Protects register access */
44 DECLARE_BITMAP(dma_inuse, STM32_DMAMUX_MAX_DMA_REQUESTS); /* Used DMA channel */
45 u32 ccr[STM32_DMAMUX_MAX_DMA_REQUESTS]; /* Used to backup CCR register
46 * in suspend
47 */
48 u32 dma_reqs[]; /* Number of DMA Request per DMA masters.
49 * [0] holds number of DMA Masters.
50 * To be kept at very end of this structure
51 */
52 };
53
stm32_dmamux_read(void __iomem * iomem,u32 reg)54 static inline u32 stm32_dmamux_read(void __iomem *iomem, u32 reg)
55 {
56 return readl_relaxed(iomem + reg);
57 }
58
stm32_dmamux_write(void __iomem * iomem,u32 reg,u32 val)59 static inline void stm32_dmamux_write(void __iomem *iomem, u32 reg, u32 val)
60 {
61 writel_relaxed(val, iomem + reg);
62 }
63
stm32_dmamux_free(struct device * dev,void * route_data)64 static void stm32_dmamux_free(struct device *dev, void *route_data)
65 {
66 struct stm32_dmamux_data *dmamux = dev_get_drvdata(dev);
67 struct stm32_dmamux *mux = route_data;
68 unsigned long flags;
69
70 /* Clear dma request */
71 spin_lock_irqsave(&dmamux->lock, flags);
72
73 stm32_dmamux_write(dmamux->iomem, STM32_DMAMUX_CCR(mux->chan_id), 0);
74 clear_bit(mux->chan_id, dmamux->dma_inuse);
75
76 pm_runtime_put_sync(dev);
77
78 spin_unlock_irqrestore(&dmamux->lock, flags);
79
80 dev_dbg(dev, "Unmapping DMAMUX(%u) to DMA%u(%u)\n",
81 mux->request, mux->master, mux->chan_id);
82
83 kfree(mux);
84 }
85
stm32_dmamux_route_allocate(struct of_phandle_args * dma_spec,struct of_dma * ofdma)86 static void *stm32_dmamux_route_allocate(struct of_phandle_args *dma_spec,
87 struct of_dma *ofdma)
88 {
89 struct platform_device *pdev = of_find_device_by_node(ofdma->of_node);
90 struct stm32_dmamux_data *dmamux = platform_get_drvdata(pdev);
91 struct stm32_dmamux *mux;
92 u32 i, min, max;
93 int ret = -EINVAL;
94 unsigned long flags;
95
96 if (dma_spec->args_count != 3) {
97 dev_err(&pdev->dev, "invalid number of dma mux args\n");
98 goto err_put_pdev;
99 }
100
101 if (dma_spec->args[0] > dmamux->dmamux_requests) {
102 dev_err(&pdev->dev, "invalid mux request number: %d\n",
103 dma_spec->args[0]);
104 goto err_put_pdev;
105 }
106
107 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
108 if (!mux) {
109 ret = -ENOMEM;
110 goto err_put_pdev;
111 }
112
113 spin_lock_irqsave(&dmamux->lock, flags);
114 mux->chan_id = find_first_zero_bit(dmamux->dma_inuse,
115 dmamux->dma_requests);
116
117 if (mux->chan_id == dmamux->dma_requests) {
118 spin_unlock_irqrestore(&dmamux->lock, flags);
119 dev_err(&pdev->dev, "Run out of free DMA requests\n");
120 ret = -ENOMEM;
121 goto err_free_mux;
122 }
123 set_bit(mux->chan_id, dmamux->dma_inuse);
124 spin_unlock_irqrestore(&dmamux->lock, flags);
125
126 /* Look for DMA Master */
127 for (i = 1, min = 0, max = dmamux->dma_reqs[i];
128 i <= dmamux->dma_reqs[0];
129 min += dmamux->dma_reqs[i], max += dmamux->dma_reqs[++i])
130 if (mux->chan_id < max)
131 break;
132 mux->master = i - 1;
133
134 /* The of_node_put() will be done in of_dma_router_xlate function */
135 dma_spec->np = of_parse_phandle(ofdma->of_node, "dma-masters", i - 1);
136 if (!dma_spec->np) {
137 dev_err(&pdev->dev, "can't get dma master\n");
138 goto err_clear_inuse;
139 }
140
141 /* Set dma request */
142 spin_lock_irqsave(&dmamux->lock, flags);
143 ret = pm_runtime_resume_and_get(&pdev->dev);
144 if (ret < 0) {
145 spin_unlock_irqrestore(&dmamux->lock, flags);
146 goto err_put_dma_spec_np;
147 }
148 spin_unlock_irqrestore(&dmamux->lock, flags);
149
150 mux->request = dma_spec->args[0];
151
152 /* craft DMA spec */
153 dma_spec->args[3] = dma_spec->args[2] | mux->chan_id << 16;
154 dma_spec->args[2] = dma_spec->args[1];
155 dma_spec->args[1] = 0;
156 dma_spec->args[0] = mux->chan_id - min;
157 dma_spec->args_count = 4;
158
159 stm32_dmamux_write(dmamux->iomem, STM32_DMAMUX_CCR(mux->chan_id),
160 mux->request);
161 dev_dbg(&pdev->dev, "Mapping DMAMUX(%u) to DMA%u(%u)\n",
162 mux->request, mux->master, mux->chan_id);
163
164 put_device(&pdev->dev);
165
166 return mux;
167
168 err_put_dma_spec_np:
169 of_node_put(dma_spec->np);
170 err_clear_inuse:
171 clear_bit(mux->chan_id, dmamux->dma_inuse);
172 err_free_mux:
173 kfree(mux);
174 err_put_pdev:
175 put_device(&pdev->dev);
176
177 return ERR_PTR(ret);
178 }
179
180 static const struct of_device_id stm32_stm32dma_master_match[] __maybe_unused = {
181 { .compatible = "st,stm32-dma", },
182 {},
183 };
184
stm32_dmamux_probe(struct platform_device * pdev)185 static int stm32_dmamux_probe(struct platform_device *pdev)
186 {
187 struct device_node *node = pdev->dev.of_node;
188 const struct of_device_id *match;
189 struct device_node *dma_node;
190 struct stm32_dmamux_data *stm32_dmamux;
191 void __iomem *iomem;
192 struct reset_control *rst;
193 int i, count, ret;
194 u32 dma_req;
195
196 if (!node)
197 return -ENODEV;
198
199 count = device_property_count_u32(&pdev->dev, "dma-masters");
200 if (count < 0) {
201 dev_err(&pdev->dev, "Can't get DMA master(s) node\n");
202 return -ENODEV;
203 }
204
205 stm32_dmamux = devm_kzalloc(&pdev->dev, sizeof(*stm32_dmamux) +
206 sizeof(u32) * (count + 1), GFP_KERNEL);
207 if (!stm32_dmamux)
208 return -ENOMEM;
209
210 dma_req = 0;
211 for (i = 1; i <= count; i++) {
212 dma_node = of_parse_phandle(node, "dma-masters", i - 1);
213
214 match = of_match_node(stm32_stm32dma_master_match, dma_node);
215 if (!match) {
216 dev_err(&pdev->dev, "DMA master is not supported\n");
217 of_node_put(dma_node);
218 return -EINVAL;
219 }
220
221 if (of_property_read_u32(dma_node, "dma-requests",
222 &stm32_dmamux->dma_reqs[i])) {
223 dev_info(&pdev->dev,
224 "Missing MUX output information, using %u.\n",
225 STM32_DMAMUX_MAX_DMA_REQUESTS);
226 stm32_dmamux->dma_reqs[i] =
227 STM32_DMAMUX_MAX_DMA_REQUESTS;
228 }
229 dma_req += stm32_dmamux->dma_reqs[i];
230 of_node_put(dma_node);
231 }
232
233 if (dma_req > STM32_DMAMUX_MAX_DMA_REQUESTS) {
234 dev_err(&pdev->dev, "Too many DMA Master Requests to manage\n");
235 return -ENODEV;
236 }
237
238 stm32_dmamux->dma_requests = dma_req;
239 stm32_dmamux->dma_reqs[0] = count;
240
241 if (device_property_read_u32(&pdev->dev, "dma-requests",
242 &stm32_dmamux->dmamux_requests)) {
243 stm32_dmamux->dmamux_requests = STM32_DMAMUX_MAX_REQUESTS;
244 dev_warn(&pdev->dev, "DMAMUX defaulting on %u requests\n",
245 stm32_dmamux->dmamux_requests);
246 }
247 pm_runtime_get_noresume(&pdev->dev);
248
249 iomem = devm_platform_ioremap_resource(pdev, 0);
250 if (IS_ERR(iomem))
251 return PTR_ERR(iomem);
252
253 spin_lock_init(&stm32_dmamux->lock);
254
255 stm32_dmamux->clk = devm_clk_get(&pdev->dev, NULL);
256 if (IS_ERR(stm32_dmamux->clk))
257 return dev_err_probe(&pdev->dev, PTR_ERR(stm32_dmamux->clk),
258 "Missing clock controller\n");
259
260 ret = clk_prepare_enable(stm32_dmamux->clk);
261 if (ret < 0) {
262 dev_err(&pdev->dev, "clk_prep_enable error: %d\n", ret);
263 return ret;
264 }
265
266 rst = devm_reset_control_get(&pdev->dev, NULL);
267 if (IS_ERR(rst)) {
268 ret = PTR_ERR(rst);
269 if (ret == -EPROBE_DEFER)
270 goto err_clk;
271 } else if (count > 1) { /* Don't reset if there is only one dma-master */
272 reset_control_assert(rst);
273 udelay(2);
274 reset_control_deassert(rst);
275 }
276
277 stm32_dmamux->iomem = iomem;
278 stm32_dmamux->dmarouter.dev = &pdev->dev;
279 stm32_dmamux->dmarouter.route_free = stm32_dmamux_free;
280
281 platform_set_drvdata(pdev, stm32_dmamux);
282 pm_runtime_set_active(&pdev->dev);
283 pm_runtime_enable(&pdev->dev);
284
285 pm_runtime_get_noresume(&pdev->dev);
286
287 /* Reset the dmamux */
288 for (i = 0; i < stm32_dmamux->dma_requests; i++)
289 stm32_dmamux_write(stm32_dmamux->iomem, STM32_DMAMUX_CCR(i), 0);
290
291 pm_runtime_put(&pdev->dev);
292
293 ret = of_dma_router_register(node, stm32_dmamux_route_allocate,
294 &stm32_dmamux->dmarouter);
295 if (ret)
296 goto pm_disable;
297
298 return 0;
299
300 pm_disable:
301 pm_runtime_disable(&pdev->dev);
302 err_clk:
303 clk_disable_unprepare(stm32_dmamux->clk);
304
305 return ret;
306 }
307
308 #ifdef CONFIG_PM
stm32_dmamux_runtime_suspend(struct device * dev)309 static int stm32_dmamux_runtime_suspend(struct device *dev)
310 {
311 struct platform_device *pdev = to_platform_device(dev);
312 struct stm32_dmamux_data *stm32_dmamux = platform_get_drvdata(pdev);
313
314 clk_disable_unprepare(stm32_dmamux->clk);
315
316 return 0;
317 }
318
stm32_dmamux_runtime_resume(struct device * dev)319 static int stm32_dmamux_runtime_resume(struct device *dev)
320 {
321 struct platform_device *pdev = to_platform_device(dev);
322 struct stm32_dmamux_data *stm32_dmamux = platform_get_drvdata(pdev);
323 int ret;
324
325 ret = clk_prepare_enable(stm32_dmamux->clk);
326 if (ret) {
327 dev_err(&pdev->dev, "failed to prepare_enable clock\n");
328 return ret;
329 }
330
331 return 0;
332 }
333 #endif
334
335 #ifdef CONFIG_PM_SLEEP
stm32_dmamux_suspend(struct device * dev)336 static int stm32_dmamux_suspend(struct device *dev)
337 {
338 struct platform_device *pdev = to_platform_device(dev);
339 struct stm32_dmamux_data *stm32_dmamux = platform_get_drvdata(pdev);
340 int i, ret;
341
342 ret = pm_runtime_resume_and_get(dev);
343 if (ret < 0)
344 return ret;
345
346 for (i = 0; i < stm32_dmamux->dma_requests; i++)
347 stm32_dmamux->ccr[i] = stm32_dmamux_read(stm32_dmamux->iomem,
348 STM32_DMAMUX_CCR(i));
349
350 pm_runtime_put_sync(dev);
351
352 pm_runtime_force_suspend(dev);
353
354 return 0;
355 }
356
stm32_dmamux_resume(struct device * dev)357 static int stm32_dmamux_resume(struct device *dev)
358 {
359 struct platform_device *pdev = to_platform_device(dev);
360 struct stm32_dmamux_data *stm32_dmamux = platform_get_drvdata(pdev);
361 int i, ret;
362
363 ret = pm_runtime_force_resume(dev);
364 if (ret < 0)
365 return ret;
366
367 ret = pm_runtime_resume_and_get(dev);
368 if (ret < 0)
369 return ret;
370
371 for (i = 0; i < stm32_dmamux->dma_requests; i++)
372 stm32_dmamux_write(stm32_dmamux->iomem, STM32_DMAMUX_CCR(i),
373 stm32_dmamux->ccr[i]);
374
375 pm_runtime_put_sync(dev);
376
377 return 0;
378 }
379 #endif
380
381 static const struct dev_pm_ops stm32_dmamux_pm_ops = {
382 SET_SYSTEM_SLEEP_PM_OPS(stm32_dmamux_suspend, stm32_dmamux_resume)
383 SET_RUNTIME_PM_OPS(stm32_dmamux_runtime_suspend,
384 stm32_dmamux_runtime_resume, NULL)
385 };
386
387 static const struct of_device_id stm32_dmamux_match[] = {
388 { .compatible = "st,stm32h7-dmamux" },
389 {},
390 };
391
392 static struct platform_driver stm32_dmamux_driver = {
393 .probe = stm32_dmamux_probe,
394 .driver = {
395 .name = "stm32-dmamux",
396 .of_match_table = stm32_dmamux_match,
397 .pm = &stm32_dmamux_pm_ops,
398 },
399 };
400
stm32_dmamux_init(void)401 static int __init stm32_dmamux_init(void)
402 {
403 return platform_driver_register(&stm32_dmamux_driver);
404 }
405 arch_initcall(stm32_dmamux_init);
406
407 MODULE_DESCRIPTION("DMA Router driver for STM32 DMA MUX");
408 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
409 MODULE_AUTHOR("Pierre-Yves Mordret <pierre-yves.mordret@st.com>");
410