1 // SPDX-License-Identifier: ISC
2 /*
3 * Copyright (c) 2014 Broadcom Corporation
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/firmware.h>
9 #include <linux/pci.h>
10 #include <linux/vmalloc.h>
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13 #include <linux/bcma/bcma.h>
14 #include <linux/sched.h>
15 #include <linux/sched/signal.h>
16 #include <linux/kthread.h>
17 #include <linux/io.h>
18 #include <linux/random.h>
19 #include <linux/unaligned.h>
20
21 #include <soc.h>
22 #include <chipcommon.h>
23 #include <brcmu_utils.h>
24 #include <brcmu_wifi.h>
25 #include <brcm_hw_ids.h>
26
27 /* Custom brcmf_err() that takes bus arg and passes it further */
28 #define brcmf_err(bus, fmt, ...) \
29 do { \
30 if (IS_ENABLED(CONFIG_BRCMDBG) || \
31 IS_ENABLED(CONFIG_BRCM_TRACING) || \
32 net_ratelimit()) \
33 __brcmf_err(bus, __func__, fmt, ##__VA_ARGS__); \
34 } while (0)
35
36 #include "debug.h"
37 #include "bus.h"
38 #include "commonring.h"
39 #include "msgbuf.h"
40 #include "pcie.h"
41 #include "firmware.h"
42 #include "chip.h"
43 #include "core.h"
44 #include "common.h"
45
46
47 enum brcmf_pcie_state {
48 BRCMFMAC_PCIE_STATE_DOWN,
49 BRCMFMAC_PCIE_STATE_UP
50 };
51
52 BRCMF_FW_DEF(43602, "brcmfmac43602-pcie");
53 BRCMF_FW_DEF(4350, "brcmfmac4350-pcie");
54 BRCMF_FW_DEF(4350C, "brcmfmac4350c2-pcie");
55 BRCMF_FW_CLM_DEF(4355, "brcmfmac4355-pcie");
56 BRCMF_FW_CLM_DEF(4355C1, "brcmfmac4355c1-pcie");
57 BRCMF_FW_CLM_DEF(4356, "brcmfmac4356-pcie");
58 BRCMF_FW_CLM_DEF(43570, "brcmfmac43570-pcie");
59 BRCMF_FW_DEF(4358, "brcmfmac4358-pcie");
60 BRCMF_FW_DEF(4359, "brcmfmac4359-pcie");
61 BRCMF_FW_DEF(4359C, "brcmfmac4359c-pcie");
62 BRCMF_FW_CLM_DEF(4364B2, "brcmfmac4364b2-pcie");
63 BRCMF_FW_CLM_DEF(4364B3, "brcmfmac4364b3-pcie");
64 BRCMF_FW_DEF(4365B, "brcmfmac4365b-pcie");
65 BRCMF_FW_DEF(4365C, "brcmfmac4365c-pcie");
66 BRCMF_FW_DEF(4366B, "brcmfmac4366b-pcie");
67 BRCMF_FW_DEF(4366C, "brcmfmac4366c-pcie");
68 BRCMF_FW_DEF(4371, "brcmfmac4371-pcie");
69 BRCMF_FW_CLM_DEF(43752, "brcmfmac43752-pcie");
70 BRCMF_FW_CLM_DEF(4377B3, "brcmfmac4377b3-pcie");
71 BRCMF_FW_CLM_DEF(4378B1, "brcmfmac4378b1-pcie");
72 BRCMF_FW_CLM_DEF(4378B3, "brcmfmac4378b3-pcie");
73 BRCMF_FW_CLM_DEF(4387C2, "brcmfmac4387c2-pcie");
74
75 /* firmware config files */
76 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.txt");
77 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.txt");
78
79 /* per-board firmware binaries */
80 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.bin");
81 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.clm_blob");
82 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.txcap_blob");
83
84 static const struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = {
85 BRCMF_FW_ENTRY(BRCM_CC_43602_CHIP_ID, 0xFFFFFFFF, 43602),
86 BRCMF_FW_ENTRY(BRCM_CC_43465_CHIP_ID, 0xFFFFFFF0, 4366C),
87 BRCMF_FW_ENTRY(BRCM_CC_4350_CHIP_ID, 0x000000FF, 4350C),
88 BRCMF_FW_ENTRY(BRCM_CC_4350_CHIP_ID, 0xFFFFFF00, 4350),
89 BRCMF_FW_ENTRY(BRCM_CC_43525_CHIP_ID, 0xFFFFFFF0, 4365C),
90 BRCMF_FW_ENTRY(BRCM_CC_4355_CHIP_ID, 0x000007FF, 4355),
91 BRCMF_FW_ENTRY(BRCM_CC_4355_CHIP_ID, 0xFFFFF800, 4355C1), /* rev ID 12/C2 seen */
92 BRCMF_FW_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356),
93 BRCMF_FW_ENTRY(BRCM_CC_43567_CHIP_ID, 0xFFFFFFFF, 43570),
94 BRCMF_FW_ENTRY(BRCM_CC_43569_CHIP_ID, 0xFFFFFFFF, 43570),
95 BRCMF_FW_ENTRY(BRCM_CC_43570_CHIP_ID, 0xFFFFFFFF, 43570),
96 BRCMF_FW_ENTRY(BRCM_CC_4358_CHIP_ID, 0xFFFFFFFF, 4358),
97 BRCMF_FW_ENTRY(BRCM_CC_4359_CHIP_ID, 0x000001FF, 4359),
98 BRCMF_FW_ENTRY(BRCM_CC_4359_CHIP_ID, 0xFFFFFE00, 4359C),
99 BRCMF_FW_ENTRY(BRCM_CC_4364_CHIP_ID, 0x0000000F, 4364B2), /* 3 */
100 BRCMF_FW_ENTRY(BRCM_CC_4364_CHIP_ID, 0xFFFFFFF0, 4364B3), /* 4 */
101 BRCMF_FW_ENTRY(BRCM_CC_4365_CHIP_ID, 0x0000000F, 4365B),
102 BRCMF_FW_ENTRY(BRCM_CC_4365_CHIP_ID, 0xFFFFFFF0, 4365C),
103 BRCMF_FW_ENTRY(BRCM_CC_4366_CHIP_ID, 0x0000000F, 4366B),
104 BRCMF_FW_ENTRY(BRCM_CC_4366_CHIP_ID, 0xFFFFFFF0, 4366C),
105 BRCMF_FW_ENTRY(BRCM_CC_43664_CHIP_ID, 0xFFFFFFF0, 4366C),
106 BRCMF_FW_ENTRY(BRCM_CC_43666_CHIP_ID, 0xFFFFFFF0, 4366C),
107 BRCMF_FW_ENTRY(BRCM_CC_4371_CHIP_ID, 0xFFFFFFFF, 4371),
108 BRCMF_FW_ENTRY(BRCM_CC_43752_CHIP_ID, 0xFFFFFFFF, 43752),
109 BRCMF_FW_ENTRY(BRCM_CC_4377_CHIP_ID, 0xFFFFFFFF, 4377B3), /* revision ID 4 */
110 BRCMF_FW_ENTRY(BRCM_CC_4378_CHIP_ID, 0x0000000F, 4378B1), /* revision ID 3 */
111 BRCMF_FW_ENTRY(BRCM_CC_4378_CHIP_ID, 0xFFFFFFE0, 4378B3), /* revision ID 5 */
112 BRCMF_FW_ENTRY(BRCM_CC_4387_CHIP_ID, 0xFFFFFFFF, 4387C2), /* revision ID 7 */
113 };
114
115 #define BRCMF_PCIE_FW_UP_TIMEOUT 5000 /* msec */
116
117 #define BRCMF_PCIE_REG_MAP_SIZE (32 * 1024)
118
119 /* backplane addres space accessed by BAR0 */
120 #define BRCMF_PCIE_BAR0_WINDOW 0x80
121 #define BRCMF_PCIE_BAR0_REG_SIZE 0x1000
122 #define BRCMF_PCIE_BAR0_WRAPPERBASE 0x70
123
124 #define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET 0x1000
125 #define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET 0x2000
126
127 #define BRCMF_PCIE_ARMCR4REG_BANKIDX 0x40
128 #define BRCMF_PCIE_ARMCR4REG_BANKPDA 0x4C
129
130 #define BRCMF_PCIE_REG_INTSTATUS 0x90
131 #define BRCMF_PCIE_REG_INTMASK 0x94
132 #define BRCMF_PCIE_REG_SBMBX 0x98
133
134 #define BRCMF_PCIE_REG_LINK_STATUS_CTRL 0xBC
135
136 #define BRCMF_PCIE_PCIE2REG_INTMASK 0x24
137 #define BRCMF_PCIE_PCIE2REG_MAILBOXINT 0x48
138 #define BRCMF_PCIE_PCIE2REG_MAILBOXMASK 0x4C
139 #define BRCMF_PCIE_PCIE2REG_CONFIGADDR 0x120
140 #define BRCMF_PCIE_PCIE2REG_CONFIGDATA 0x124
141 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0 0x140
142 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1 0x144
143
144 #define BRCMF_PCIE_64_PCIE2REG_INTMASK 0xC14
145 #define BRCMF_PCIE_64_PCIE2REG_MAILBOXINT 0xC30
146 #define BRCMF_PCIE_64_PCIE2REG_MAILBOXMASK 0xC34
147 #define BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_0 0xA20
148 #define BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_1 0xA24
149
150 #define BRCMF_PCIE2_INTA 0x01
151 #define BRCMF_PCIE2_INTB 0x02
152
153 #define BRCMF_PCIE_INT_0 0x01
154 #define BRCMF_PCIE_INT_1 0x02
155 #define BRCMF_PCIE_INT_DEF (BRCMF_PCIE_INT_0 | \
156 BRCMF_PCIE_INT_1)
157
158 #define BRCMF_PCIE_MB_INT_FN0_0 0x0100
159 #define BRCMF_PCIE_MB_INT_FN0_1 0x0200
160 #define BRCMF_PCIE_MB_INT_D2H0_DB0 0x10000
161 #define BRCMF_PCIE_MB_INT_D2H0_DB1 0x20000
162 #define BRCMF_PCIE_MB_INT_D2H1_DB0 0x40000
163 #define BRCMF_PCIE_MB_INT_D2H1_DB1 0x80000
164 #define BRCMF_PCIE_MB_INT_D2H2_DB0 0x100000
165 #define BRCMF_PCIE_MB_INT_D2H2_DB1 0x200000
166 #define BRCMF_PCIE_MB_INT_D2H3_DB0 0x400000
167 #define BRCMF_PCIE_MB_INT_D2H3_DB1 0x800000
168
169 #define BRCMF_PCIE_MB_INT_FN0 (BRCMF_PCIE_MB_INT_FN0_0 | \
170 BRCMF_PCIE_MB_INT_FN0_1)
171 #define BRCMF_PCIE_MB_INT_D2H_DB (BRCMF_PCIE_MB_INT_D2H0_DB0 | \
172 BRCMF_PCIE_MB_INT_D2H0_DB1 | \
173 BRCMF_PCIE_MB_INT_D2H1_DB0 | \
174 BRCMF_PCIE_MB_INT_D2H1_DB1 | \
175 BRCMF_PCIE_MB_INT_D2H2_DB0 | \
176 BRCMF_PCIE_MB_INT_D2H2_DB1 | \
177 BRCMF_PCIE_MB_INT_D2H3_DB0 | \
178 BRCMF_PCIE_MB_INT_D2H3_DB1)
179
180 #define BRCMF_PCIE_64_MB_INT_D2H0_DB0 0x1
181 #define BRCMF_PCIE_64_MB_INT_D2H0_DB1 0x2
182 #define BRCMF_PCIE_64_MB_INT_D2H1_DB0 0x4
183 #define BRCMF_PCIE_64_MB_INT_D2H1_DB1 0x8
184 #define BRCMF_PCIE_64_MB_INT_D2H2_DB0 0x10
185 #define BRCMF_PCIE_64_MB_INT_D2H2_DB1 0x20
186 #define BRCMF_PCIE_64_MB_INT_D2H3_DB0 0x40
187 #define BRCMF_PCIE_64_MB_INT_D2H3_DB1 0x80
188 #define BRCMF_PCIE_64_MB_INT_D2H4_DB0 0x100
189 #define BRCMF_PCIE_64_MB_INT_D2H4_DB1 0x200
190 #define BRCMF_PCIE_64_MB_INT_D2H5_DB0 0x400
191 #define BRCMF_PCIE_64_MB_INT_D2H5_DB1 0x800
192 #define BRCMF_PCIE_64_MB_INT_D2H6_DB0 0x1000
193 #define BRCMF_PCIE_64_MB_INT_D2H6_DB1 0x2000
194 #define BRCMF_PCIE_64_MB_INT_D2H7_DB0 0x4000
195 #define BRCMF_PCIE_64_MB_INT_D2H7_DB1 0x8000
196
197 #define BRCMF_PCIE_64_MB_INT_D2H_DB (BRCMF_PCIE_64_MB_INT_D2H0_DB0 | \
198 BRCMF_PCIE_64_MB_INT_D2H0_DB1 | \
199 BRCMF_PCIE_64_MB_INT_D2H1_DB0 | \
200 BRCMF_PCIE_64_MB_INT_D2H1_DB1 | \
201 BRCMF_PCIE_64_MB_INT_D2H2_DB0 | \
202 BRCMF_PCIE_64_MB_INT_D2H2_DB1 | \
203 BRCMF_PCIE_64_MB_INT_D2H3_DB0 | \
204 BRCMF_PCIE_64_MB_INT_D2H3_DB1 | \
205 BRCMF_PCIE_64_MB_INT_D2H4_DB0 | \
206 BRCMF_PCIE_64_MB_INT_D2H4_DB1 | \
207 BRCMF_PCIE_64_MB_INT_D2H5_DB0 | \
208 BRCMF_PCIE_64_MB_INT_D2H5_DB1 | \
209 BRCMF_PCIE_64_MB_INT_D2H6_DB0 | \
210 BRCMF_PCIE_64_MB_INT_D2H6_DB1 | \
211 BRCMF_PCIE_64_MB_INT_D2H7_DB0 | \
212 BRCMF_PCIE_64_MB_INT_D2H7_DB1)
213
214 #define BRCMF_PCIE_SHARED_VERSION_7 7
215 #define BRCMF_PCIE_MIN_SHARED_VERSION 5
216 #define BRCMF_PCIE_MAX_SHARED_VERSION BRCMF_PCIE_SHARED_VERSION_7
217 #define BRCMF_PCIE_SHARED_VERSION_MASK 0x00FF
218 #define BRCMF_PCIE_SHARED_DMA_INDEX 0x10000
219 #define BRCMF_PCIE_SHARED_DMA_2B_IDX 0x100000
220 #define BRCMF_PCIE_SHARED_HOSTRDY_DB1 0x10000000
221
222 #define BRCMF_PCIE_FLAGS_HTOD_SPLIT 0x4000
223 #define BRCMF_PCIE_FLAGS_DTOH_SPLIT 0x8000
224
225 #define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET 34
226 #define BRCMF_SHARED_RING_BASE_OFFSET 52
227 #define BRCMF_SHARED_RX_DATAOFFSET_OFFSET 36
228 #define BRCMF_SHARED_CONSOLE_ADDR_OFFSET 20
229 #define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET 40
230 #define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET 44
231 #define BRCMF_SHARED_RING_INFO_ADDR_OFFSET 48
232 #define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET 52
233 #define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET 56
234 #define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET 64
235 #define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET 68
236
237 #define BRCMF_RING_H2D_RING_COUNT_OFFSET 0
238 #define BRCMF_RING_D2H_RING_COUNT_OFFSET 1
239 #define BRCMF_RING_H2D_RING_MEM_OFFSET 4
240 #define BRCMF_RING_H2D_RING_STATE_OFFSET 8
241
242 #define BRCMF_RING_MEM_BASE_ADDR_OFFSET 8
243 #define BRCMF_RING_MAX_ITEM_OFFSET 4
244 #define BRCMF_RING_LEN_ITEMS_OFFSET 6
245 #define BRCMF_RING_MEM_SZ 16
246 #define BRCMF_RING_STATE_SZ 8
247
248 #define BRCMF_DEF_MAX_RXBUFPOST 255
249
250 #define BRCMF_CONSOLE_BUFADDR_OFFSET 8
251 #define BRCMF_CONSOLE_BUFSIZE_OFFSET 12
252 #define BRCMF_CONSOLE_WRITEIDX_OFFSET 16
253
254 #define BRCMF_DMA_D2H_SCRATCH_BUF_LEN 8
255 #define BRCMF_DMA_D2H_RINGUPD_BUF_LEN 1024
256
257 #define BRCMF_D2H_DEV_D3_ACK 0x00000001
258 #define BRCMF_D2H_DEV_DS_ENTER_REQ 0x00000002
259 #define BRCMF_D2H_DEV_DS_EXIT_NOTE 0x00000004
260 #define BRCMF_D2H_DEV_FWHALT 0x10000000
261
262 #define BRCMF_H2D_HOST_D3_INFORM 0x00000001
263 #define BRCMF_H2D_HOST_DS_ACK 0x00000002
264 #define BRCMF_H2D_HOST_D0_INFORM_IN_USE 0x00000008
265 #define BRCMF_H2D_HOST_D0_INFORM 0x00000010
266
267 #define BRCMF_PCIE_MBDATA_TIMEOUT msecs_to_jiffies(2000)
268
269 #define BRCMF_PCIE_CFGREG_STATUS_CMD 0x4
270 #define BRCMF_PCIE_CFGREG_PM_CSR 0x4C
271 #define BRCMF_PCIE_CFGREG_MSI_CAP 0x58
272 #define BRCMF_PCIE_CFGREG_MSI_ADDR_L 0x5C
273 #define BRCMF_PCIE_CFGREG_MSI_ADDR_H 0x60
274 #define BRCMF_PCIE_CFGREG_MSI_DATA 0x64
275 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL 0xBC
276 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2 0xDC
277 #define BRCMF_PCIE_CFGREG_RBAR_CTRL 0x228
278 #define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1 0x248
279 #define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG 0x4E0
280 #define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG 0x4F4
281 #define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB 3
282
283 /* Magic number at a magic location to find RAM size */
284 #define BRCMF_RAMSIZE_MAGIC 0x534d4152 /* SMAR */
285 #define BRCMF_RAMSIZE_OFFSET 0x6c
286
287
288 struct brcmf_pcie_console {
289 u32 base_addr;
290 u32 buf_addr;
291 u32 bufsize;
292 u32 read_idx;
293 u8 log_str[256];
294 u8 log_idx;
295 };
296
297 struct brcmf_pcie_shared_info {
298 u32 tcm_base_address;
299 u32 flags;
300 struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS];
301 struct brcmf_pcie_ringbuf *flowrings;
302 u16 max_rxbufpost;
303 u16 max_flowrings;
304 u16 max_submissionrings;
305 u16 max_completionrings;
306 u32 rx_dataoffset;
307 u32 htod_mb_data_addr;
308 u32 dtoh_mb_data_addr;
309 u32 ring_info_addr;
310 struct brcmf_pcie_console console;
311 void *scratch;
312 dma_addr_t scratch_dmahandle;
313 void *ringupd;
314 dma_addr_t ringupd_dmahandle;
315 u8 version;
316 };
317
318 #define BRCMF_OTP_MAX_PARAM_LEN 16
319
320 struct brcmf_otp_params {
321 char module[BRCMF_OTP_MAX_PARAM_LEN];
322 char vendor[BRCMF_OTP_MAX_PARAM_LEN];
323 char version[BRCMF_OTP_MAX_PARAM_LEN];
324 bool valid;
325 };
326
327 struct brcmf_pciedev_info {
328 enum brcmf_pcie_state state;
329 bool in_irq;
330 struct pci_dev *pdev;
331 char fw_name[BRCMF_FW_NAME_LEN];
332 char nvram_name[BRCMF_FW_NAME_LEN];
333 char clm_name[BRCMF_FW_NAME_LEN];
334 char txcap_name[BRCMF_FW_NAME_LEN];
335 const struct firmware *clm_fw;
336 const struct firmware *txcap_fw;
337 const struct brcmf_pcie_reginfo *reginfo;
338 void __iomem *regs;
339 void __iomem *tcm;
340 u32 ram_base;
341 u32 ram_size;
342 struct brcmf_chip *ci;
343 u32 coreid;
344 struct brcmf_pcie_shared_info shared;
345 wait_queue_head_t mbdata_resp_wait;
346 bool mbdata_completed;
347 bool irq_allocated;
348 bool wowl_enabled;
349 u8 dma_idx_sz;
350 void *idxbuf;
351 u32 idxbuf_sz;
352 dma_addr_t idxbuf_dmahandle;
353 u16 (*read_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset);
354 void (*write_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
355 u16 value);
356 struct brcmf_mp_device *settings;
357 struct brcmf_otp_params otp;
358 bool fwseed;
359 #ifdef DEBUG
360 u32 console_interval;
361 bool console_active;
362 struct timer_list timer;
363 #endif
364 };
365
366 struct brcmf_pcie_ringbuf {
367 struct brcmf_commonring commonring;
368 dma_addr_t dma_handle;
369 u32 w_idx_addr;
370 u32 r_idx_addr;
371 struct brcmf_pciedev_info *devinfo;
372 u8 id;
373 };
374
375 /**
376 * struct brcmf_pcie_dhi_ringinfo - dongle/host interface shared ring info
377 *
378 * @ringmem: dongle memory pointer to ring memory location
379 * @h2d_w_idx_ptr: h2d ring write indices dongle memory pointers
380 * @h2d_r_idx_ptr: h2d ring read indices dongle memory pointers
381 * @d2h_w_idx_ptr: d2h ring write indices dongle memory pointers
382 * @d2h_r_idx_ptr: d2h ring read indices dongle memory pointers
383 * @h2d_w_idx_hostaddr: h2d ring write indices host memory pointers
384 * @h2d_r_idx_hostaddr: h2d ring read indices host memory pointers
385 * @d2h_w_idx_hostaddr: d2h ring write indices host memory pointers
386 * @d2h_r_idx_hostaddr: d2h ring reaD indices host memory pointers
387 * @max_flowrings: maximum number of tx flow rings supported.
388 * @max_submissionrings: maximum number of submission rings(h2d) supported.
389 * @max_completionrings: maximum number of completion rings(d2h) supported.
390 */
391 struct brcmf_pcie_dhi_ringinfo {
392 __le32 ringmem;
393 __le32 h2d_w_idx_ptr;
394 __le32 h2d_r_idx_ptr;
395 __le32 d2h_w_idx_ptr;
396 __le32 d2h_r_idx_ptr;
397 struct msgbuf_buf_addr h2d_w_idx_hostaddr;
398 struct msgbuf_buf_addr h2d_r_idx_hostaddr;
399 struct msgbuf_buf_addr d2h_w_idx_hostaddr;
400 struct msgbuf_buf_addr d2h_r_idx_hostaddr;
401 __le16 max_flowrings;
402 __le16 max_submissionrings;
403 __le16 max_completionrings;
404 };
405
406 static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = {
407 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM,
408 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM,
409 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM,
410 BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM,
411 BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM
412 };
413
414 static const u32 brcmf_ring_itemsize_pre_v7[BRCMF_NROF_COMMON_MSGRINGS] = {
415 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
416 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
417 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
418 BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE_PRE_V7,
419 BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE_PRE_V7
420 };
421
422 static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = {
423 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
424 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
425 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
426 BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE,
427 BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE
428 };
429
430 struct brcmf_pcie_reginfo {
431 u32 intmask;
432 u32 mailboxint;
433 u32 mailboxmask;
434 u32 h2d_mailbox_0;
435 u32 h2d_mailbox_1;
436 u32 int_d2h_db;
437 u32 int_fn0;
438 };
439
440 static const struct brcmf_pcie_reginfo brcmf_reginfo_default = {
441 .intmask = BRCMF_PCIE_PCIE2REG_INTMASK,
442 .mailboxint = BRCMF_PCIE_PCIE2REG_MAILBOXINT,
443 .mailboxmask = BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
444 .h2d_mailbox_0 = BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0,
445 .h2d_mailbox_1 = BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1,
446 .int_d2h_db = BRCMF_PCIE_MB_INT_D2H_DB,
447 .int_fn0 = BRCMF_PCIE_MB_INT_FN0,
448 };
449
450 static const struct brcmf_pcie_reginfo brcmf_reginfo_64 = {
451 .intmask = BRCMF_PCIE_64_PCIE2REG_INTMASK,
452 .mailboxint = BRCMF_PCIE_64_PCIE2REG_MAILBOXINT,
453 .mailboxmask = BRCMF_PCIE_64_PCIE2REG_MAILBOXMASK,
454 .h2d_mailbox_0 = BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_0,
455 .h2d_mailbox_1 = BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_1,
456 .int_d2h_db = BRCMF_PCIE_64_MB_INT_D2H_DB,
457 .int_fn0 = 0,
458 };
459
460 static void brcmf_pcie_setup(struct device *dev, int ret,
461 struct brcmf_fw_request *fwreq);
462 static struct brcmf_fw_request *
463 brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info *devinfo);
464 static void
465 brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info *devinfo, bool active);
466 static void brcmf_pcie_debugfs_create(struct device *dev);
467
468 static u16
brcmf_pcie_read_reg16(struct brcmf_pciedev_info * devinfo,u32 reg_offset)469 brcmf_pcie_read_reg16(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
470 {
471 void __iomem *address = devinfo->regs + reg_offset;
472
473 return ioread16(address);
474 }
475
476 static u32
brcmf_pcie_read_reg32(struct brcmf_pciedev_info * devinfo,u32 reg_offset)477 brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
478 {
479 void __iomem *address = devinfo->regs + reg_offset;
480
481 return (ioread32(address));
482 }
483
484
485 static void
brcmf_pcie_write_reg32(struct brcmf_pciedev_info * devinfo,u32 reg_offset,u32 value)486 brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset,
487 u32 value)
488 {
489 void __iomem *address = devinfo->regs + reg_offset;
490
491 iowrite32(value, address);
492 }
493
494
495 static u8
brcmf_pcie_read_tcm8(struct brcmf_pciedev_info * devinfo,u32 mem_offset)496 brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
497 {
498 void __iomem *address = devinfo->tcm + mem_offset;
499
500 return (ioread8(address));
501 }
502
503
504 static u16
brcmf_pcie_read_tcm16(struct brcmf_pciedev_info * devinfo,u32 mem_offset)505 brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
506 {
507 void __iomem *address = devinfo->tcm + mem_offset;
508
509 return (ioread16(address));
510 }
511
512
513 static void
brcmf_pcie_write_tcm16(struct brcmf_pciedev_info * devinfo,u32 mem_offset,u16 value)514 brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
515 u16 value)
516 {
517 void __iomem *address = devinfo->tcm + mem_offset;
518
519 iowrite16(value, address);
520 }
521
522
523 static u16
brcmf_pcie_read_idx(struct brcmf_pciedev_info * devinfo,u32 mem_offset)524 brcmf_pcie_read_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
525 {
526 u16 *address = devinfo->idxbuf + mem_offset;
527
528 return (*(address));
529 }
530
531
532 static void
brcmf_pcie_write_idx(struct brcmf_pciedev_info * devinfo,u32 mem_offset,u16 value)533 brcmf_pcie_write_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
534 u16 value)
535 {
536 u16 *address = devinfo->idxbuf + mem_offset;
537
538 *(address) = value;
539 }
540
541
542 static u32
brcmf_pcie_read_tcm32(struct brcmf_pciedev_info * devinfo,u32 mem_offset)543 brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
544 {
545 void __iomem *address = devinfo->tcm + mem_offset;
546
547 return (ioread32(address));
548 }
549
550
551 static void
brcmf_pcie_write_tcm32(struct brcmf_pciedev_info * devinfo,u32 mem_offset,u32 value)552 brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
553 u32 value)
554 {
555 void __iomem *address = devinfo->tcm + mem_offset;
556
557 iowrite32(value, address);
558 }
559
560
561 static u32
brcmf_pcie_read_ram32(struct brcmf_pciedev_info * devinfo,u32 mem_offset)562 brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
563 {
564 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
565
566 return (ioread32(addr));
567 }
568
569
570 static void
brcmf_pcie_write_ram32(struct brcmf_pciedev_info * devinfo,u32 mem_offset,u32 value)571 brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
572 u32 value)
573 {
574 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
575
576 iowrite32(value, addr);
577 }
578
579
580 static void
brcmf_pcie_copy_dev_tomem(struct brcmf_pciedev_info * devinfo,u32 mem_offset,void * dstaddr,u32 len)581 brcmf_pcie_copy_dev_tomem(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
582 void *dstaddr, u32 len)
583 {
584 void __iomem *address = devinfo->tcm + mem_offset;
585 __le32 *dst32;
586 __le16 *dst16;
587 u8 *dst8;
588
589 if (((ulong)address & 4) || ((ulong)dstaddr & 4) || (len & 4)) {
590 if (((ulong)address & 2) || ((ulong)dstaddr & 2) || (len & 2)) {
591 dst8 = (u8 *)dstaddr;
592 while (len) {
593 *dst8 = ioread8(address);
594 address++;
595 dst8++;
596 len--;
597 }
598 } else {
599 len = len / 2;
600 dst16 = (__le16 *)dstaddr;
601 while (len) {
602 *dst16 = cpu_to_le16(ioread16(address));
603 address += 2;
604 dst16++;
605 len--;
606 }
607 }
608 } else {
609 len = len / 4;
610 dst32 = (__le32 *)dstaddr;
611 while (len) {
612 *dst32 = cpu_to_le32(ioread32(address));
613 address += 4;
614 dst32++;
615 len--;
616 }
617 }
618 }
619
620
621 #define READCC32(devinfo, reg) brcmf_pcie_read_reg32(devinfo, \
622 CHIPCREGOFFS(reg))
623 #define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \
624 CHIPCREGOFFS(reg), value)
625
626
627 static void
brcmf_pcie_select_core(struct brcmf_pciedev_info * devinfo,u16 coreid)628 brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid)
629 {
630 const struct pci_dev *pdev = devinfo->pdev;
631 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
632 struct brcmf_core *core;
633 u32 bar0_win;
634
635 core = brcmf_chip_get_core(devinfo->ci, coreid);
636 if (core) {
637 bar0_win = core->base;
638 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win);
639 if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW,
640 &bar0_win) == 0) {
641 if (bar0_win != core->base) {
642 bar0_win = core->base;
643 pci_write_config_dword(pdev,
644 BRCMF_PCIE_BAR0_WINDOW,
645 bar0_win);
646 }
647 }
648 } else {
649 brcmf_err(bus, "Unsupported core selected %x\n", coreid);
650 }
651 }
652
653
brcmf_pcie_reset_device(struct brcmf_pciedev_info * devinfo)654 static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo)
655 {
656 struct brcmf_core *core;
657 u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD,
658 BRCMF_PCIE_CFGREG_PM_CSR,
659 BRCMF_PCIE_CFGREG_MSI_CAP,
660 BRCMF_PCIE_CFGREG_MSI_ADDR_L,
661 BRCMF_PCIE_CFGREG_MSI_ADDR_H,
662 BRCMF_PCIE_CFGREG_MSI_DATA,
663 BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2,
664 BRCMF_PCIE_CFGREG_RBAR_CTRL,
665 BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1,
666 BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG,
667 BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG };
668 u32 i;
669 u32 val;
670 u32 lsc;
671
672 if (!devinfo->ci)
673 return;
674
675 /* Disable ASPM */
676 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
677 pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
678 &lsc);
679 val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB);
680 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
681 val);
682
683 /* Watchdog reset */
684 brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON);
685 WRITECC32(devinfo, watchdog, 4);
686 msleep(100);
687
688 /* Restore ASPM */
689 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
690 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
691 lsc);
692
693 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2);
694 if (core->rev <= 13) {
695 for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) {
696 brcmf_pcie_write_reg32(devinfo,
697 BRCMF_PCIE_PCIE2REG_CONFIGADDR,
698 cfg_offset[i]);
699 val = brcmf_pcie_read_reg32(devinfo,
700 BRCMF_PCIE_PCIE2REG_CONFIGDATA);
701 brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n",
702 cfg_offset[i], val);
703 brcmf_pcie_write_reg32(devinfo,
704 BRCMF_PCIE_PCIE2REG_CONFIGDATA,
705 val);
706 }
707 }
708 }
709
710
brcmf_pcie_attach(struct brcmf_pciedev_info * devinfo)711 static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo)
712 {
713 u32 config;
714
715 /* BAR1 window may not be sized properly */
716 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
717 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0);
718 config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
719 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config);
720
721 device_wakeup_enable(&devinfo->pdev->dev);
722 }
723
724
brcmf_pcie_enter_download_state(struct brcmf_pciedev_info * devinfo)725 static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo)
726 {
727 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
728 brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4);
729 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
730 5);
731 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
732 0);
733 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
734 7);
735 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
736 0);
737 }
738 return 0;
739 }
740
741
brcmf_pcie_exit_download_state(struct brcmf_pciedev_info * devinfo,u32 resetintr)742 static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo,
743 u32 resetintr)
744 {
745 struct brcmf_core *core;
746
747 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
748 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM);
749 brcmf_chip_resetcore(core, 0, 0, 0);
750 }
751
752 if (!brcmf_chip_set_active(devinfo->ci, resetintr))
753 return -EIO;
754 return 0;
755 }
756
757
758 static int
brcmf_pcie_send_mb_data(struct brcmf_pciedev_info * devinfo,u32 htod_mb_data)759 brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data)
760 {
761 struct brcmf_pcie_shared_info *shared;
762 struct brcmf_core *core;
763 u32 addr;
764 u32 cur_htod_mb_data;
765 u32 i;
766
767 shared = &devinfo->shared;
768 addr = shared->htod_mb_data_addr;
769 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
770
771 if (cur_htod_mb_data != 0)
772 brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n",
773 cur_htod_mb_data);
774
775 i = 0;
776 while (cur_htod_mb_data != 0) {
777 msleep(10);
778 i++;
779 if (i > 100)
780 return -EIO;
781 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
782 }
783
784 brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data);
785 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
786
787 /* Send mailbox interrupt twice as a hardware workaround */
788 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2);
789 if (core->rev <= 13)
790 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
791
792 return 0;
793 }
794
795
brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info * devinfo)796 static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo)
797 {
798 struct brcmf_pcie_shared_info *shared;
799 u32 addr;
800 u32 dtoh_mb_data;
801
802 shared = &devinfo->shared;
803 addr = shared->dtoh_mb_data_addr;
804 dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
805
806 if (!dtoh_mb_data)
807 return;
808
809 brcmf_pcie_write_tcm32(devinfo, addr, 0);
810
811 brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data);
812 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ) {
813 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n");
814 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK);
815 brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n");
816 }
817 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE)
818 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n");
819 if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) {
820 brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n");
821 devinfo->mbdata_completed = true;
822 wake_up(&devinfo->mbdata_resp_wait);
823 }
824 if (dtoh_mb_data & BRCMF_D2H_DEV_FWHALT) {
825 brcmf_dbg(PCIE, "D2H_MB_DATA: FW HALT\n");
826 brcmf_fw_crashed(&devinfo->pdev->dev);
827 }
828 }
829
830
brcmf_pcie_bus_console_init(struct brcmf_pciedev_info * devinfo)831 static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo)
832 {
833 struct brcmf_pcie_shared_info *shared;
834 struct brcmf_pcie_console *console;
835 u32 addr;
836
837 shared = &devinfo->shared;
838 console = &shared->console;
839 addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET;
840 console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr);
841
842 addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET;
843 console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr);
844 addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET;
845 console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr);
846
847 brcmf_dbg(FWCON, "Console: base %x, buf %x, size %d\n",
848 console->base_addr, console->buf_addr, console->bufsize);
849 }
850
851 /**
852 * brcmf_pcie_bus_console_read - reads firmware messages
853 *
854 * @devinfo: pointer to the device data structure
855 * @error: specifies if error has occurred (prints messages unconditionally)
856 */
brcmf_pcie_bus_console_read(struct brcmf_pciedev_info * devinfo,bool error)857 static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo,
858 bool error)
859 {
860 struct pci_dev *pdev = devinfo->pdev;
861 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
862 struct brcmf_pcie_console *console;
863 u32 addr;
864 u8 ch;
865 u32 newidx;
866
867 if (!error && !BRCMF_FWCON_ON())
868 return;
869
870 console = &devinfo->shared.console;
871 if (!console->base_addr)
872 return;
873 addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET;
874 newidx = brcmf_pcie_read_tcm32(devinfo, addr);
875 while (newidx != console->read_idx) {
876 addr = console->buf_addr + console->read_idx;
877 ch = brcmf_pcie_read_tcm8(devinfo, addr);
878 console->read_idx++;
879 if (console->read_idx == console->bufsize)
880 console->read_idx = 0;
881 if (ch == '\r')
882 continue;
883 console->log_str[console->log_idx] = ch;
884 console->log_idx++;
885 if ((ch != '\n') &&
886 (console->log_idx == (sizeof(console->log_str) - 2))) {
887 ch = '\n';
888 console->log_str[console->log_idx] = ch;
889 console->log_idx++;
890 }
891 if (ch == '\n') {
892 console->log_str[console->log_idx] = 0;
893 if (error)
894 __brcmf_err(bus, __func__, "CONSOLE: %s",
895 console->log_str);
896 else
897 pr_debug("CONSOLE: %s", console->log_str);
898 console->log_idx = 0;
899 }
900 }
901 }
902
903
brcmf_pcie_intr_disable(struct brcmf_pciedev_info * devinfo)904 static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo)
905 {
906 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxmask, 0);
907 }
908
909
brcmf_pcie_intr_enable(struct brcmf_pciedev_info * devinfo)910 static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo)
911 {
912 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxmask,
913 devinfo->reginfo->int_d2h_db |
914 devinfo->reginfo->int_fn0);
915 }
916
brcmf_pcie_hostready(struct brcmf_pciedev_info * devinfo)917 static void brcmf_pcie_hostready(struct brcmf_pciedev_info *devinfo)
918 {
919 if (devinfo->shared.flags & BRCMF_PCIE_SHARED_HOSTRDY_DB1)
920 brcmf_pcie_write_reg32(devinfo,
921 devinfo->reginfo->h2d_mailbox_1, 1);
922 }
923
brcmf_pcie_quick_check_isr(int irq,void * arg)924 static irqreturn_t brcmf_pcie_quick_check_isr(int irq, void *arg)
925 {
926 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
927
928 if (brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->mailboxint)) {
929 brcmf_pcie_intr_disable(devinfo);
930 brcmf_dbg(PCIE, "Enter\n");
931 return IRQ_WAKE_THREAD;
932 }
933 return IRQ_NONE;
934 }
935
936
brcmf_pcie_isr_thread(int irq,void * arg)937 static irqreturn_t brcmf_pcie_isr_thread(int irq, void *arg)
938 {
939 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
940 u32 status;
941
942 devinfo->in_irq = true;
943 status = brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->mailboxint);
944 brcmf_dbg(PCIE, "Enter %x\n", status);
945 if (status) {
946 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxint,
947 status);
948 if (status & devinfo->reginfo->int_fn0)
949 brcmf_pcie_handle_mb_data(devinfo);
950 if (status & devinfo->reginfo->int_d2h_db) {
951 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
952 brcmf_proto_msgbuf_rx_trigger(
953 &devinfo->pdev->dev);
954 }
955 }
956 brcmf_pcie_bus_console_read(devinfo, false);
957 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
958 brcmf_pcie_intr_enable(devinfo);
959 devinfo->in_irq = false;
960 return IRQ_HANDLED;
961 }
962
963
brcmf_pcie_request_irq(struct brcmf_pciedev_info * devinfo)964 static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo)
965 {
966 struct pci_dev *pdev = devinfo->pdev;
967 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
968
969 brcmf_pcie_intr_disable(devinfo);
970
971 brcmf_dbg(PCIE, "Enter\n");
972
973 pci_enable_msi(pdev);
974 if (request_threaded_irq(pdev->irq, brcmf_pcie_quick_check_isr,
975 brcmf_pcie_isr_thread, IRQF_SHARED,
976 "brcmf_pcie_intr", devinfo)) {
977 pci_disable_msi(pdev);
978 brcmf_err(bus, "Failed to request IRQ %d\n", pdev->irq);
979 return -EIO;
980 }
981 devinfo->irq_allocated = true;
982 return 0;
983 }
984
985
brcmf_pcie_release_irq(struct brcmf_pciedev_info * devinfo)986 static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo)
987 {
988 struct pci_dev *pdev = devinfo->pdev;
989 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
990 u32 status;
991 u32 count;
992
993 if (!devinfo->irq_allocated)
994 return;
995
996 brcmf_pcie_intr_disable(devinfo);
997 free_irq(pdev->irq, devinfo);
998 pci_disable_msi(pdev);
999
1000 msleep(50);
1001 count = 0;
1002 while ((devinfo->in_irq) && (count < 20)) {
1003 msleep(50);
1004 count++;
1005 }
1006 if (devinfo->in_irq)
1007 brcmf_err(bus, "Still in IRQ (processing) !!!\n");
1008
1009 status = brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->mailboxint);
1010 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxint, status);
1011
1012 devinfo->irq_allocated = false;
1013 }
1014
1015
brcmf_pcie_ring_mb_write_rptr(void * ctx)1016 static int brcmf_pcie_ring_mb_write_rptr(void *ctx)
1017 {
1018 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
1019 struct brcmf_pciedev_info *devinfo = ring->devinfo;
1020 struct brcmf_commonring *commonring = &ring->commonring;
1021
1022 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1023 return -EIO;
1024
1025 brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr,
1026 commonring->w_ptr, ring->id);
1027
1028 devinfo->write_ptr(devinfo, ring->r_idx_addr, commonring->r_ptr);
1029
1030 return 0;
1031 }
1032
1033
brcmf_pcie_ring_mb_write_wptr(void * ctx)1034 static int brcmf_pcie_ring_mb_write_wptr(void *ctx)
1035 {
1036 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
1037 struct brcmf_pciedev_info *devinfo = ring->devinfo;
1038 struct brcmf_commonring *commonring = &ring->commonring;
1039
1040 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1041 return -EIO;
1042
1043 brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr,
1044 commonring->r_ptr, ring->id);
1045
1046 devinfo->write_ptr(devinfo, ring->w_idx_addr, commonring->w_ptr);
1047
1048 return 0;
1049 }
1050
1051
brcmf_pcie_ring_mb_ring_bell(void * ctx)1052 static int brcmf_pcie_ring_mb_ring_bell(void *ctx)
1053 {
1054 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
1055 struct brcmf_pciedev_info *devinfo = ring->devinfo;
1056
1057 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1058 return -EIO;
1059
1060 brcmf_dbg(PCIE, "RING !\n");
1061 /* Any arbitrary value will do, lets use 1 */
1062 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->h2d_mailbox_0, 1);
1063
1064 return 0;
1065 }
1066
1067
brcmf_pcie_ring_mb_update_rptr(void * ctx)1068 static int brcmf_pcie_ring_mb_update_rptr(void *ctx)
1069 {
1070 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
1071 struct brcmf_pciedev_info *devinfo = ring->devinfo;
1072 struct brcmf_commonring *commonring = &ring->commonring;
1073
1074 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1075 return -EIO;
1076
1077 commonring->r_ptr = devinfo->read_ptr(devinfo, ring->r_idx_addr);
1078
1079 brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr,
1080 commonring->w_ptr, ring->id);
1081
1082 return 0;
1083 }
1084
1085
brcmf_pcie_ring_mb_update_wptr(void * ctx)1086 static int brcmf_pcie_ring_mb_update_wptr(void *ctx)
1087 {
1088 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
1089 struct brcmf_pciedev_info *devinfo = ring->devinfo;
1090 struct brcmf_commonring *commonring = &ring->commonring;
1091
1092 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1093 return -EIO;
1094
1095 commonring->w_ptr = devinfo->read_ptr(devinfo, ring->w_idx_addr);
1096
1097 brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr,
1098 commonring->r_ptr, ring->id);
1099
1100 return 0;
1101 }
1102
1103
1104 static void *
brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info * devinfo,u32 size,u32 tcm_dma_phys_addr,dma_addr_t * dma_handle)1105 brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo,
1106 u32 size, u32 tcm_dma_phys_addr,
1107 dma_addr_t *dma_handle)
1108 {
1109 void *ring;
1110 u64 address;
1111
1112 ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle,
1113 GFP_KERNEL);
1114 if (!ring)
1115 return NULL;
1116
1117 address = (u64)*dma_handle;
1118 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr,
1119 address & 0xffffffff);
1120 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32);
1121
1122 return (ring);
1123 }
1124
1125
1126 static struct brcmf_pcie_ringbuf *
brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info * devinfo,u32 ring_id,u32 tcm_ring_phys_addr)1127 brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id,
1128 u32 tcm_ring_phys_addr)
1129 {
1130 void *dma_buf;
1131 dma_addr_t dma_handle;
1132 struct brcmf_pcie_ringbuf *ring;
1133 u32 size;
1134 u32 addr;
1135 const u32 *ring_itemsize_array;
1136
1137 if (devinfo->shared.version < BRCMF_PCIE_SHARED_VERSION_7)
1138 ring_itemsize_array = brcmf_ring_itemsize_pre_v7;
1139 else
1140 ring_itemsize_array = brcmf_ring_itemsize;
1141
1142 size = brcmf_ring_max_item[ring_id] * ring_itemsize_array[ring_id];
1143 dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size,
1144 tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET,
1145 &dma_handle);
1146 if (!dma_buf)
1147 return NULL;
1148
1149 addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET;
1150 brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]);
1151 addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET;
1152 brcmf_pcie_write_tcm16(devinfo, addr, ring_itemsize_array[ring_id]);
1153
1154 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1155 if (!ring) {
1156 dma_free_coherent(&devinfo->pdev->dev, size, dma_buf,
1157 dma_handle);
1158 return NULL;
1159 }
1160 brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id],
1161 ring_itemsize_array[ring_id], dma_buf);
1162 ring->dma_handle = dma_handle;
1163 ring->devinfo = devinfo;
1164 brcmf_commonring_register_cb(&ring->commonring,
1165 brcmf_pcie_ring_mb_ring_bell,
1166 brcmf_pcie_ring_mb_update_rptr,
1167 brcmf_pcie_ring_mb_update_wptr,
1168 brcmf_pcie_ring_mb_write_rptr,
1169 brcmf_pcie_ring_mb_write_wptr, ring);
1170
1171 return (ring);
1172 }
1173
1174
brcmf_pcie_release_ringbuffer(struct device * dev,struct brcmf_pcie_ringbuf * ring)1175 static void brcmf_pcie_release_ringbuffer(struct device *dev,
1176 struct brcmf_pcie_ringbuf *ring)
1177 {
1178 void *dma_buf;
1179 u32 size;
1180
1181 if (!ring)
1182 return;
1183
1184 dma_buf = ring->commonring.buf_addr;
1185 if (dma_buf) {
1186 size = ring->commonring.depth * ring->commonring.item_len;
1187 dma_free_coherent(dev, size, dma_buf, ring->dma_handle);
1188 }
1189 kfree(ring);
1190 }
1191
1192
brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info * devinfo)1193 static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo)
1194 {
1195 u32 i;
1196
1197 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1198 brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev,
1199 devinfo->shared.commonrings[i]);
1200 devinfo->shared.commonrings[i] = NULL;
1201 }
1202 kfree(devinfo->shared.flowrings);
1203 devinfo->shared.flowrings = NULL;
1204 if (devinfo->idxbuf) {
1205 dma_free_coherent(&devinfo->pdev->dev,
1206 devinfo->idxbuf_sz,
1207 devinfo->idxbuf,
1208 devinfo->idxbuf_dmahandle);
1209 devinfo->idxbuf = NULL;
1210 }
1211 }
1212
1213
brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info * devinfo)1214 static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo)
1215 {
1216 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev);
1217 struct brcmf_pcie_ringbuf *ring;
1218 struct brcmf_pcie_ringbuf *rings;
1219 u32 d2h_w_idx_ptr;
1220 u32 d2h_r_idx_ptr;
1221 u32 h2d_w_idx_ptr;
1222 u32 h2d_r_idx_ptr;
1223 u32 ring_mem_ptr;
1224 u32 i;
1225 u64 address;
1226 u32 bufsz;
1227 u8 idx_offset;
1228 struct brcmf_pcie_dhi_ringinfo ringinfo;
1229 u16 max_flowrings;
1230 u16 max_submissionrings;
1231 u16 max_completionrings;
1232
1233 memcpy_fromio(&ringinfo, devinfo->tcm + devinfo->shared.ring_info_addr,
1234 sizeof(ringinfo));
1235 if (devinfo->shared.version >= 6) {
1236 max_submissionrings = le16_to_cpu(ringinfo.max_submissionrings);
1237 max_flowrings = le16_to_cpu(ringinfo.max_flowrings);
1238 max_completionrings = le16_to_cpu(ringinfo.max_completionrings);
1239 } else {
1240 max_submissionrings = le16_to_cpu(ringinfo.max_flowrings);
1241 max_flowrings = max_submissionrings -
1242 BRCMF_NROF_H2D_COMMON_MSGRINGS;
1243 max_completionrings = BRCMF_NROF_D2H_COMMON_MSGRINGS;
1244 }
1245 if (max_flowrings > 512) {
1246 brcmf_err(bus, "invalid max_flowrings(%d)\n", max_flowrings);
1247 return -EIO;
1248 }
1249
1250 if (devinfo->dma_idx_sz != 0) {
1251 bufsz = (max_submissionrings + max_completionrings) *
1252 devinfo->dma_idx_sz * 2;
1253 devinfo->idxbuf = dma_alloc_coherent(&devinfo->pdev->dev, bufsz,
1254 &devinfo->idxbuf_dmahandle,
1255 GFP_KERNEL);
1256 if (!devinfo->idxbuf)
1257 devinfo->dma_idx_sz = 0;
1258 }
1259
1260 if (devinfo->dma_idx_sz == 0) {
1261 d2h_w_idx_ptr = le32_to_cpu(ringinfo.d2h_w_idx_ptr);
1262 d2h_r_idx_ptr = le32_to_cpu(ringinfo.d2h_r_idx_ptr);
1263 h2d_w_idx_ptr = le32_to_cpu(ringinfo.h2d_w_idx_ptr);
1264 h2d_r_idx_ptr = le32_to_cpu(ringinfo.h2d_r_idx_ptr);
1265 idx_offset = sizeof(u32);
1266 devinfo->write_ptr = brcmf_pcie_write_tcm16;
1267 devinfo->read_ptr = brcmf_pcie_read_tcm16;
1268 brcmf_dbg(PCIE, "Using TCM indices\n");
1269 } else {
1270 memset(devinfo->idxbuf, 0, bufsz);
1271 devinfo->idxbuf_sz = bufsz;
1272 idx_offset = devinfo->dma_idx_sz;
1273 devinfo->write_ptr = brcmf_pcie_write_idx;
1274 devinfo->read_ptr = brcmf_pcie_read_idx;
1275
1276 h2d_w_idx_ptr = 0;
1277 address = (u64)devinfo->idxbuf_dmahandle;
1278 ringinfo.h2d_w_idx_hostaddr.low_addr =
1279 cpu_to_le32(address & 0xffffffff);
1280 ringinfo.h2d_w_idx_hostaddr.high_addr =
1281 cpu_to_le32(address >> 32);
1282
1283 h2d_r_idx_ptr = h2d_w_idx_ptr +
1284 max_submissionrings * idx_offset;
1285 address += max_submissionrings * idx_offset;
1286 ringinfo.h2d_r_idx_hostaddr.low_addr =
1287 cpu_to_le32(address & 0xffffffff);
1288 ringinfo.h2d_r_idx_hostaddr.high_addr =
1289 cpu_to_le32(address >> 32);
1290
1291 d2h_w_idx_ptr = h2d_r_idx_ptr +
1292 max_submissionrings * idx_offset;
1293 address += max_submissionrings * idx_offset;
1294 ringinfo.d2h_w_idx_hostaddr.low_addr =
1295 cpu_to_le32(address & 0xffffffff);
1296 ringinfo.d2h_w_idx_hostaddr.high_addr =
1297 cpu_to_le32(address >> 32);
1298
1299 d2h_r_idx_ptr = d2h_w_idx_ptr +
1300 max_completionrings * idx_offset;
1301 address += max_completionrings * idx_offset;
1302 ringinfo.d2h_r_idx_hostaddr.low_addr =
1303 cpu_to_le32(address & 0xffffffff);
1304 ringinfo.d2h_r_idx_hostaddr.high_addr =
1305 cpu_to_le32(address >> 32);
1306
1307 memcpy_toio(devinfo->tcm + devinfo->shared.ring_info_addr,
1308 &ringinfo, sizeof(ringinfo));
1309 brcmf_dbg(PCIE, "Using host memory indices\n");
1310 }
1311
1312 ring_mem_ptr = le32_to_cpu(ringinfo.ringmem);
1313
1314 for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) {
1315 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1316 if (!ring)
1317 goto fail;
1318 ring->w_idx_addr = h2d_w_idx_ptr;
1319 ring->r_idx_addr = h2d_r_idx_ptr;
1320 ring->id = i;
1321 devinfo->shared.commonrings[i] = ring;
1322
1323 h2d_w_idx_ptr += idx_offset;
1324 h2d_r_idx_ptr += idx_offset;
1325 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1326 }
1327
1328 for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS;
1329 i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1330 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1331 if (!ring)
1332 goto fail;
1333 ring->w_idx_addr = d2h_w_idx_ptr;
1334 ring->r_idx_addr = d2h_r_idx_ptr;
1335 ring->id = i;
1336 devinfo->shared.commonrings[i] = ring;
1337
1338 d2h_w_idx_ptr += idx_offset;
1339 d2h_r_idx_ptr += idx_offset;
1340 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1341 }
1342
1343 devinfo->shared.max_flowrings = max_flowrings;
1344 devinfo->shared.max_submissionrings = max_submissionrings;
1345 devinfo->shared.max_completionrings = max_completionrings;
1346 rings = kcalloc(max_flowrings, sizeof(*ring), GFP_KERNEL);
1347 if (!rings)
1348 goto fail;
1349
1350 brcmf_dbg(PCIE, "Nr of flowrings is %d\n", max_flowrings);
1351
1352 for (i = 0; i < max_flowrings; i++) {
1353 ring = &rings[i];
1354 ring->devinfo = devinfo;
1355 ring->id = i + BRCMF_H2D_MSGRING_FLOWRING_IDSTART;
1356 brcmf_commonring_register_cb(&ring->commonring,
1357 brcmf_pcie_ring_mb_ring_bell,
1358 brcmf_pcie_ring_mb_update_rptr,
1359 brcmf_pcie_ring_mb_update_wptr,
1360 brcmf_pcie_ring_mb_write_rptr,
1361 brcmf_pcie_ring_mb_write_wptr,
1362 ring);
1363 ring->w_idx_addr = h2d_w_idx_ptr;
1364 ring->r_idx_addr = h2d_r_idx_ptr;
1365 h2d_w_idx_ptr += idx_offset;
1366 h2d_r_idx_ptr += idx_offset;
1367 }
1368 devinfo->shared.flowrings = rings;
1369
1370 return 0;
1371
1372 fail:
1373 brcmf_err(bus, "Allocating ring buffers failed\n");
1374 brcmf_pcie_release_ringbuffers(devinfo);
1375 return -ENOMEM;
1376 }
1377
1378
1379 static void
brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info * devinfo)1380 brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1381 {
1382 if (devinfo->shared.scratch)
1383 dma_free_coherent(&devinfo->pdev->dev,
1384 BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1385 devinfo->shared.scratch,
1386 devinfo->shared.scratch_dmahandle);
1387 if (devinfo->shared.ringupd)
1388 dma_free_coherent(&devinfo->pdev->dev,
1389 BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1390 devinfo->shared.ringupd,
1391 devinfo->shared.ringupd_dmahandle);
1392 }
1393
brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info * devinfo)1394 static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1395 {
1396 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev);
1397 u64 address;
1398 u32 addr;
1399
1400 devinfo->shared.scratch =
1401 dma_alloc_coherent(&devinfo->pdev->dev,
1402 BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1403 &devinfo->shared.scratch_dmahandle,
1404 GFP_KERNEL);
1405 if (!devinfo->shared.scratch)
1406 goto fail;
1407
1408 addr = devinfo->shared.tcm_base_address +
1409 BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET;
1410 address = (u64)devinfo->shared.scratch_dmahandle;
1411 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1412 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1413 addr = devinfo->shared.tcm_base_address +
1414 BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET;
1415 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1416
1417 devinfo->shared.ringupd =
1418 dma_alloc_coherent(&devinfo->pdev->dev,
1419 BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1420 &devinfo->shared.ringupd_dmahandle,
1421 GFP_KERNEL);
1422 if (!devinfo->shared.ringupd)
1423 goto fail;
1424
1425 addr = devinfo->shared.tcm_base_address +
1426 BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET;
1427 address = (u64)devinfo->shared.ringupd_dmahandle;
1428 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1429 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1430 addr = devinfo->shared.tcm_base_address +
1431 BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET;
1432 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1433 return 0;
1434
1435 fail:
1436 brcmf_err(bus, "Allocating scratch buffers failed\n");
1437 brcmf_pcie_release_scratchbuffers(devinfo);
1438 return -ENOMEM;
1439 }
1440
1441
brcmf_pcie_down(struct device * dev)1442 static void brcmf_pcie_down(struct device *dev)
1443 {
1444 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1445 struct brcmf_pciedev *pcie_bus_dev = bus_if->bus_priv.pcie;
1446 struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo;
1447
1448 brcmf_pcie_fwcon_timer(devinfo, false);
1449 }
1450
brcmf_pcie_preinit(struct device * dev)1451 static int brcmf_pcie_preinit(struct device *dev)
1452 {
1453 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1454 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1455
1456 brcmf_dbg(PCIE, "Enter\n");
1457
1458 brcmf_pcie_intr_enable(buspub->devinfo);
1459 brcmf_pcie_hostready(buspub->devinfo);
1460
1461 return 0;
1462 }
1463
brcmf_pcie_tx(struct device * dev,struct sk_buff * skb)1464 static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb)
1465 {
1466 return 0;
1467 }
1468
1469
brcmf_pcie_tx_ctlpkt(struct device * dev,unsigned char * msg,uint len)1470 static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg,
1471 uint len)
1472 {
1473 return 0;
1474 }
1475
1476
brcmf_pcie_rx_ctlpkt(struct device * dev,unsigned char * msg,uint len)1477 static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg,
1478 uint len)
1479 {
1480 return 0;
1481 }
1482
1483
brcmf_pcie_wowl_config(struct device * dev,bool enabled)1484 static void brcmf_pcie_wowl_config(struct device *dev, bool enabled)
1485 {
1486 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1487 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1488 struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1489
1490 brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled);
1491 devinfo->wowl_enabled = enabled;
1492 }
1493
1494
brcmf_pcie_get_ramsize(struct device * dev)1495 static size_t brcmf_pcie_get_ramsize(struct device *dev)
1496 {
1497 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1498 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1499 struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1500
1501 return devinfo->ci->ramsize - devinfo->ci->srsize;
1502 }
1503
1504
brcmf_pcie_get_memdump(struct device * dev,void * data,size_t len)1505 static int brcmf_pcie_get_memdump(struct device *dev, void *data, size_t len)
1506 {
1507 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1508 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1509 struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1510
1511 brcmf_dbg(PCIE, "dump at 0x%08X: len=%zu\n", devinfo->ci->rambase, len);
1512 brcmf_pcie_copy_dev_tomem(devinfo, devinfo->ci->rambase, data, len);
1513 return 0;
1514 }
1515
brcmf_pcie_get_blob(struct device * dev,const struct firmware ** fw,enum brcmf_blob_type type)1516 static int brcmf_pcie_get_blob(struct device *dev, const struct firmware **fw,
1517 enum brcmf_blob_type type)
1518 {
1519 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1520 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1521 struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1522
1523 switch (type) {
1524 case BRCMF_BLOB_CLM:
1525 *fw = devinfo->clm_fw;
1526 devinfo->clm_fw = NULL;
1527 break;
1528 case BRCMF_BLOB_TXCAP:
1529 *fw = devinfo->txcap_fw;
1530 devinfo->txcap_fw = NULL;
1531 break;
1532 default:
1533 return -ENOENT;
1534 }
1535
1536 if (!*fw)
1537 return -ENOENT;
1538
1539 return 0;
1540 }
1541
brcmf_pcie_reset(struct device * dev)1542 static int brcmf_pcie_reset(struct device *dev)
1543 {
1544 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1545 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1546 struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1547 struct brcmf_fw_request *fwreq;
1548 int err;
1549
1550 brcmf_pcie_intr_disable(devinfo);
1551
1552 brcmf_pcie_bus_console_read(devinfo, true);
1553
1554 brcmf_detach(dev);
1555
1556 brcmf_pcie_release_irq(devinfo);
1557 brcmf_pcie_release_scratchbuffers(devinfo);
1558 brcmf_pcie_release_ringbuffers(devinfo);
1559 brcmf_pcie_reset_device(devinfo);
1560
1561 fwreq = brcmf_pcie_prepare_fw_request(devinfo);
1562 if (!fwreq) {
1563 dev_err(dev, "Failed to prepare FW request\n");
1564 return -ENOMEM;
1565 }
1566
1567 err = brcmf_fw_get_firmwares(dev, fwreq, brcmf_pcie_setup);
1568 if (err) {
1569 dev_err(dev, "Failed to prepare FW request\n");
1570 kfree(fwreq);
1571 }
1572
1573 return err;
1574 }
1575
1576 static const struct brcmf_bus_ops brcmf_pcie_bus_ops = {
1577 .preinit = brcmf_pcie_preinit,
1578 .txdata = brcmf_pcie_tx,
1579 .stop = brcmf_pcie_down,
1580 .txctl = brcmf_pcie_tx_ctlpkt,
1581 .rxctl = brcmf_pcie_rx_ctlpkt,
1582 .wowl_config = brcmf_pcie_wowl_config,
1583 .get_ramsize = brcmf_pcie_get_ramsize,
1584 .get_memdump = brcmf_pcie_get_memdump,
1585 .get_blob = brcmf_pcie_get_blob,
1586 .reset = brcmf_pcie_reset,
1587 .debugfs_create = brcmf_pcie_debugfs_create,
1588 };
1589
1590
1591 static void
brcmf_pcie_adjust_ramsize(struct brcmf_pciedev_info * devinfo,u8 * data,u32 data_len)1592 brcmf_pcie_adjust_ramsize(struct brcmf_pciedev_info *devinfo, u8 *data,
1593 u32 data_len)
1594 {
1595 __le32 *field;
1596 u32 newsize;
1597
1598 if (data_len < BRCMF_RAMSIZE_OFFSET + 8)
1599 return;
1600
1601 field = (__le32 *)&data[BRCMF_RAMSIZE_OFFSET];
1602 if (le32_to_cpup(field) != BRCMF_RAMSIZE_MAGIC)
1603 return;
1604 field++;
1605 newsize = le32_to_cpup(field);
1606
1607 brcmf_dbg(PCIE, "Found ramsize info in FW, adjusting to 0x%x\n",
1608 newsize);
1609 devinfo->ci->ramsize = newsize;
1610 }
1611
1612
1613 static int
brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info * devinfo,u32 sharedram_addr)1614 brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo,
1615 u32 sharedram_addr)
1616 {
1617 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev);
1618 struct brcmf_pcie_shared_info *shared;
1619 u32 addr;
1620
1621 shared = &devinfo->shared;
1622 shared->tcm_base_address = sharedram_addr;
1623
1624 shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr);
1625 shared->version = (u8)(shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK);
1626 brcmf_dbg(PCIE, "PCIe protocol version %d\n", shared->version);
1627 if ((shared->version > BRCMF_PCIE_MAX_SHARED_VERSION) ||
1628 (shared->version < BRCMF_PCIE_MIN_SHARED_VERSION)) {
1629 brcmf_err(bus, "Unsupported PCIE version %d\n",
1630 shared->version);
1631 return -EINVAL;
1632 }
1633
1634 /* check firmware support dma indicies */
1635 if (shared->flags & BRCMF_PCIE_SHARED_DMA_INDEX) {
1636 if (shared->flags & BRCMF_PCIE_SHARED_DMA_2B_IDX)
1637 devinfo->dma_idx_sz = sizeof(u16);
1638 else
1639 devinfo->dma_idx_sz = sizeof(u32);
1640 }
1641
1642 addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET;
1643 shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr);
1644 if (shared->max_rxbufpost == 0)
1645 shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST;
1646
1647 addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET;
1648 shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr);
1649
1650 addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET;
1651 shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1652
1653 addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET;
1654 shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1655
1656 addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET;
1657 shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1658
1659 brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n",
1660 shared->max_rxbufpost, shared->rx_dataoffset);
1661
1662 brcmf_pcie_bus_console_init(devinfo);
1663 brcmf_pcie_bus_console_read(devinfo, false);
1664
1665 return 0;
1666 }
1667
1668 struct brcmf_random_seed_footer {
1669 __le32 length;
1670 __le32 magic;
1671 };
1672
1673 #define BRCMF_RANDOM_SEED_MAGIC 0xfeedc0de
1674 #define BRCMF_RANDOM_SEED_LENGTH 0x100
1675
1676 static noinline_for_stack void
brcmf_pcie_provide_random_bytes(struct brcmf_pciedev_info * devinfo,u32 address)1677 brcmf_pcie_provide_random_bytes(struct brcmf_pciedev_info *devinfo, u32 address)
1678 {
1679 u8 randbuf[BRCMF_RANDOM_SEED_LENGTH];
1680
1681 get_random_bytes(randbuf, BRCMF_RANDOM_SEED_LENGTH);
1682 memcpy_toio(devinfo->tcm + address, randbuf, BRCMF_RANDOM_SEED_LENGTH);
1683 }
1684
brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info * devinfo,const struct firmware * fw,void * nvram,u32 nvram_len)1685 static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo,
1686 const struct firmware *fw, void *nvram,
1687 u32 nvram_len)
1688 {
1689 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev);
1690 u32 sharedram_addr;
1691 u32 sharedram_addr_written;
1692 u32 loop_counter;
1693 int err;
1694 u32 address;
1695 u32 resetintr;
1696
1697 brcmf_dbg(PCIE, "Halt ARM.\n");
1698 err = brcmf_pcie_enter_download_state(devinfo);
1699 if (err)
1700 return err;
1701
1702 brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name);
1703 memcpy_toio(devinfo->tcm + devinfo->ci->rambase,
1704 (void *)fw->data, fw->size);
1705
1706 resetintr = get_unaligned_le32(fw->data);
1707 release_firmware(fw);
1708
1709 /* reset last 4 bytes of RAM address. to be used for shared
1710 * area. This identifies when FW is running
1711 */
1712 brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0);
1713
1714 if (nvram) {
1715 brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name);
1716 address = devinfo->ci->rambase + devinfo->ci->ramsize -
1717 nvram_len;
1718 memcpy_toio(devinfo->tcm + address, nvram, nvram_len);
1719 brcmf_fw_nvram_free(nvram);
1720
1721 if (devinfo->fwseed) {
1722 size_t rand_len = BRCMF_RANDOM_SEED_LENGTH;
1723 struct brcmf_random_seed_footer footer = {
1724 .length = cpu_to_le32(rand_len),
1725 .magic = cpu_to_le32(BRCMF_RANDOM_SEED_MAGIC),
1726 };
1727
1728 /* Some chips/firmwares expect a buffer of random
1729 * data to be present before NVRAM
1730 */
1731 brcmf_dbg(PCIE, "Download random seed\n");
1732
1733 address -= sizeof(footer);
1734 memcpy_toio(devinfo->tcm + address, &footer,
1735 sizeof(footer));
1736
1737 address -= rand_len;
1738 brcmf_pcie_provide_random_bytes(devinfo, address);
1739 }
1740 } else {
1741 brcmf_dbg(PCIE, "No matching NVRAM file found %s\n",
1742 devinfo->nvram_name);
1743 }
1744
1745 sharedram_addr_written = brcmf_pcie_read_ram32(devinfo,
1746 devinfo->ci->ramsize -
1747 4);
1748 brcmf_dbg(PCIE, "Bring ARM in running state\n");
1749 err = brcmf_pcie_exit_download_state(devinfo, resetintr);
1750 if (err)
1751 return err;
1752
1753 brcmf_dbg(PCIE, "Wait for FW init\n");
1754 sharedram_addr = sharedram_addr_written;
1755 loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50;
1756 while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) {
1757 msleep(50);
1758 sharedram_addr = brcmf_pcie_read_ram32(devinfo,
1759 devinfo->ci->ramsize -
1760 4);
1761 loop_counter--;
1762 }
1763 if (sharedram_addr == sharedram_addr_written) {
1764 brcmf_err(bus, "FW failed to initialize\n");
1765 return -ENODEV;
1766 }
1767 if (sharedram_addr < devinfo->ci->rambase ||
1768 sharedram_addr >= devinfo->ci->rambase + devinfo->ci->ramsize) {
1769 brcmf_err(bus, "Invalid shared RAM address 0x%08x\n",
1770 sharedram_addr);
1771 return -ENODEV;
1772 }
1773 brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr);
1774
1775 return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr));
1776 }
1777
1778
brcmf_pcie_get_resource(struct brcmf_pciedev_info * devinfo)1779 static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo)
1780 {
1781 struct pci_dev *pdev = devinfo->pdev;
1782 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
1783 int err;
1784 phys_addr_t bar0_addr, bar1_addr;
1785 ulong bar1_size;
1786
1787 err = pci_enable_device(pdev);
1788 if (err) {
1789 brcmf_err(bus, "pci_enable_device failed err=%d\n", err);
1790 return err;
1791 }
1792
1793 pci_set_master(pdev);
1794
1795 /* Bar-0 mapped address */
1796 bar0_addr = pci_resource_start(pdev, 0);
1797 /* Bar-1 mapped address */
1798 bar1_addr = pci_resource_start(pdev, 2);
1799 /* read Bar-1 mapped memory range */
1800 bar1_size = pci_resource_len(pdev, 2);
1801 if ((bar1_size == 0) || (bar1_addr == 0)) {
1802 brcmf_err(bus, "BAR1 Not enabled, device size=%ld, addr=%#016llx\n",
1803 bar1_size, (unsigned long long)bar1_addr);
1804 return -EINVAL;
1805 }
1806
1807 devinfo->regs = ioremap(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE);
1808 devinfo->tcm = ioremap(bar1_addr, bar1_size);
1809
1810 if (!devinfo->regs || !devinfo->tcm) {
1811 brcmf_err(bus, "ioremap() failed (%p,%p)\n", devinfo->regs,
1812 devinfo->tcm);
1813 return -EINVAL;
1814 }
1815 brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n",
1816 devinfo->regs, (unsigned long long)bar0_addr);
1817 brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx size 0x%x\n",
1818 devinfo->tcm, (unsigned long long)bar1_addr,
1819 (unsigned int)bar1_size);
1820
1821 return 0;
1822 }
1823
1824
brcmf_pcie_release_resource(struct brcmf_pciedev_info * devinfo)1825 static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo)
1826 {
1827 if (devinfo->tcm)
1828 iounmap(devinfo->tcm);
1829 if (devinfo->regs)
1830 iounmap(devinfo->regs);
1831
1832 pci_disable_device(devinfo->pdev);
1833 }
1834
1835
brcmf_pcie_buscore_prep_addr(const struct pci_dev * pdev,u32 addr)1836 static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr)
1837 {
1838 u32 ret_addr;
1839
1840 ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1);
1841 addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1);
1842 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr);
1843
1844 return ret_addr;
1845 }
1846
1847
brcmf_pcie_buscore_read32(void * ctx,u32 addr)1848 static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr)
1849 {
1850 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1851
1852 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1853 return brcmf_pcie_read_reg32(devinfo, addr);
1854 }
1855
1856
brcmf_pcie_buscore_write32(void * ctx,u32 addr,u32 value)1857 static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value)
1858 {
1859 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1860
1861 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1862 brcmf_pcie_write_reg32(devinfo, addr, value);
1863 }
1864
1865
brcmf_pcie_buscoreprep(void * ctx)1866 static int brcmf_pcie_buscoreprep(void *ctx)
1867 {
1868 return brcmf_pcie_get_resource(ctx);
1869 }
1870
1871
brcmf_pcie_buscore_reset(void * ctx,struct brcmf_chip * chip)1872 static int brcmf_pcie_buscore_reset(void *ctx, struct brcmf_chip *chip)
1873 {
1874 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1875 struct brcmf_core *core;
1876 u32 val, reg;
1877
1878 devinfo->ci = chip;
1879 brcmf_pcie_reset_device(devinfo);
1880
1881 /* reginfo is not ready yet */
1882 core = brcmf_chip_get_core(chip, BCMA_CORE_PCIE2);
1883 if (core->rev >= 64)
1884 reg = BRCMF_PCIE_64_PCIE2REG_MAILBOXINT;
1885 else
1886 reg = BRCMF_PCIE_PCIE2REG_MAILBOXINT;
1887
1888 val = brcmf_pcie_read_reg32(devinfo, reg);
1889 if (val != 0xffffffff)
1890 brcmf_pcie_write_reg32(devinfo, reg, val);
1891
1892 return 0;
1893 }
1894
1895
brcmf_pcie_buscore_activate(void * ctx,struct brcmf_chip * chip,u32 rstvec)1896 static void brcmf_pcie_buscore_activate(void *ctx, struct brcmf_chip *chip,
1897 u32 rstvec)
1898 {
1899 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1900
1901 brcmf_pcie_write_tcm32(devinfo, 0, rstvec);
1902 }
1903
1904
1905 static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = {
1906 .prepare = brcmf_pcie_buscoreprep,
1907 .reset = brcmf_pcie_buscore_reset,
1908 .activate = brcmf_pcie_buscore_activate,
1909 .read32 = brcmf_pcie_buscore_read32,
1910 .write32 = brcmf_pcie_buscore_write32,
1911 };
1912
1913 #define BRCMF_OTP_SYS_VENDOR 0x15
1914 #define BRCMF_OTP_BRCM_CIS 0x80
1915
1916 #define BRCMF_OTP_VENDOR_HDR 0x00000008
1917
1918 static int
brcmf_pcie_parse_otp_sys_vendor(struct brcmf_pciedev_info * devinfo,u8 * data,size_t size)1919 brcmf_pcie_parse_otp_sys_vendor(struct brcmf_pciedev_info *devinfo,
1920 u8 *data, size_t size)
1921 {
1922 int idx = 4;
1923 const char *chip_params;
1924 const char *board_params;
1925 const char *p;
1926
1927 /* 4-byte header and two empty strings */
1928 if (size < 6)
1929 return -EINVAL;
1930
1931 if (get_unaligned_le32(data) != BRCMF_OTP_VENDOR_HDR)
1932 return -EINVAL;
1933
1934 chip_params = &data[idx];
1935
1936 /* Skip first string, including terminator */
1937 idx += strnlen(chip_params, size - idx) + 1;
1938 if (idx >= size)
1939 return -EINVAL;
1940
1941 board_params = &data[idx];
1942
1943 /* Skip to terminator of second string */
1944 idx += strnlen(board_params, size - idx);
1945 if (idx >= size)
1946 return -EINVAL;
1947
1948 /* At this point both strings are guaranteed NUL-terminated */
1949 brcmf_dbg(PCIE, "OTP: chip_params='%s' board_params='%s'\n",
1950 chip_params, board_params);
1951
1952 p = skip_spaces(board_params);
1953 while (*p) {
1954 char tag = *p++;
1955 const char *end;
1956 size_t len;
1957
1958 if (*p++ != '=') /* implicit NUL check */
1959 return -EINVAL;
1960
1961 /* *p might be NUL here, if so end == p and len == 0 */
1962 end = strchrnul(p, ' ');
1963 len = end - p;
1964
1965 /* leave 1 byte for NUL in destination string */
1966 if (len > (BRCMF_OTP_MAX_PARAM_LEN - 1))
1967 return -EINVAL;
1968
1969 /* Copy len characters plus a NUL terminator */
1970 switch (tag) {
1971 case 'M':
1972 strscpy(devinfo->otp.module, p, len + 1);
1973 break;
1974 case 'V':
1975 strscpy(devinfo->otp.vendor, p, len + 1);
1976 break;
1977 case 'm':
1978 strscpy(devinfo->otp.version, p, len + 1);
1979 break;
1980 }
1981
1982 /* Skip to next arg, if any */
1983 p = skip_spaces(end);
1984 }
1985
1986 brcmf_dbg(PCIE, "OTP: module=%s vendor=%s version=%s\n",
1987 devinfo->otp.module, devinfo->otp.vendor,
1988 devinfo->otp.version);
1989
1990 if (!devinfo->otp.module[0] ||
1991 !devinfo->otp.vendor[0] ||
1992 !devinfo->otp.version[0])
1993 return -EINVAL;
1994
1995 devinfo->otp.valid = true;
1996 return 0;
1997 }
1998
1999 static int
brcmf_pcie_parse_otp(struct brcmf_pciedev_info * devinfo,u8 * otp,size_t size)2000 brcmf_pcie_parse_otp(struct brcmf_pciedev_info *devinfo, u8 *otp, size_t size)
2001 {
2002 int p = 0;
2003 int ret = -EINVAL;
2004
2005 brcmf_dbg(PCIE, "parse_otp size=%zd\n", size);
2006
2007 while (p < (size - 1)) {
2008 u8 type = otp[p];
2009 u8 length = otp[p + 1];
2010
2011 if (type == 0)
2012 break;
2013
2014 if ((p + 2 + length) > size)
2015 break;
2016
2017 switch (type) {
2018 case BRCMF_OTP_SYS_VENDOR:
2019 brcmf_dbg(PCIE, "OTP @ 0x%x (%d): SYS_VENDOR\n",
2020 p, length);
2021 ret = brcmf_pcie_parse_otp_sys_vendor(devinfo,
2022 &otp[p + 2],
2023 length);
2024 break;
2025 case BRCMF_OTP_BRCM_CIS:
2026 brcmf_dbg(PCIE, "OTP @ 0x%x (%d): BRCM_CIS\n",
2027 p, length);
2028 break;
2029 default:
2030 brcmf_dbg(PCIE, "OTP @ 0x%x (%d): Unknown type 0x%x\n",
2031 p, length, type);
2032 break;
2033 }
2034
2035 p += 2 + length;
2036 }
2037
2038 return ret;
2039 }
2040
brcmf_pcie_read_otp(struct brcmf_pciedev_info * devinfo)2041 static int brcmf_pcie_read_otp(struct brcmf_pciedev_info *devinfo)
2042 {
2043 const struct pci_dev *pdev = devinfo->pdev;
2044 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
2045 u32 coreid, base, words, idx, sromctl;
2046 u16 *otp;
2047 struct brcmf_core *core;
2048 int ret;
2049
2050 switch (devinfo->ci->chip) {
2051 case BRCM_CC_4355_CHIP_ID:
2052 coreid = BCMA_CORE_CHIPCOMMON;
2053 base = 0x8c0;
2054 words = 0xb2;
2055 break;
2056 case BRCM_CC_4364_CHIP_ID:
2057 coreid = BCMA_CORE_CHIPCOMMON;
2058 base = 0x8c0;
2059 words = 0x1a0;
2060 break;
2061 case BRCM_CC_4377_CHIP_ID:
2062 case BRCM_CC_4378_CHIP_ID:
2063 coreid = BCMA_CORE_GCI;
2064 base = 0x1120;
2065 words = 0x170;
2066 break;
2067 case BRCM_CC_4387_CHIP_ID:
2068 coreid = BCMA_CORE_GCI;
2069 base = 0x113c;
2070 words = 0x170;
2071 break;
2072 default:
2073 /* OTP not supported on this chip */
2074 return 0;
2075 }
2076
2077 core = brcmf_chip_get_core(devinfo->ci, coreid);
2078 if (!core) {
2079 brcmf_err(bus, "No OTP core\n");
2080 return -ENODEV;
2081 }
2082
2083 if (coreid == BCMA_CORE_CHIPCOMMON) {
2084 /* Chips with OTP accessed via ChipCommon need additional
2085 * handling to access the OTP
2086 */
2087 brcmf_pcie_select_core(devinfo, coreid);
2088 sromctl = READCC32(devinfo, sromcontrol);
2089
2090 if (!(sromctl & BCMA_CC_SROM_CONTROL_OTP_PRESENT)) {
2091 /* Chip lacks OTP, try without it... */
2092 brcmf_err(bus,
2093 "OTP unavailable, using default firmware\n");
2094 return 0;
2095 }
2096
2097 /* Map OTP to shadow area */
2098 WRITECC32(devinfo, sromcontrol,
2099 sromctl | BCMA_CC_SROM_CONTROL_OTPSEL);
2100 }
2101
2102 otp = kcalloc(words, sizeof(u16), GFP_KERNEL);
2103 if (!otp)
2104 return -ENOMEM;
2105
2106 /* Map bus window to SROM/OTP shadow area in core */
2107 base = brcmf_pcie_buscore_prep_addr(devinfo->pdev, base + core->base);
2108
2109 brcmf_dbg(PCIE, "OTP data:\n");
2110 for (idx = 0; idx < words; idx++) {
2111 otp[idx] = brcmf_pcie_read_reg16(devinfo, base + 2 * idx);
2112 brcmf_dbg(PCIE, "[%8x] 0x%04x\n", base + 2 * idx, otp[idx]);
2113 }
2114
2115 if (coreid == BCMA_CORE_CHIPCOMMON) {
2116 brcmf_pcie_select_core(devinfo, coreid);
2117 WRITECC32(devinfo, sromcontrol, sromctl);
2118 }
2119
2120 ret = brcmf_pcie_parse_otp(devinfo, (u8 *)otp, 2 * words);
2121 kfree(otp);
2122
2123 return ret;
2124 }
2125
2126 #define BRCMF_PCIE_FW_CODE 0
2127 #define BRCMF_PCIE_FW_NVRAM 1
2128 #define BRCMF_PCIE_FW_CLM 2
2129 #define BRCMF_PCIE_FW_TXCAP 3
2130
brcmf_pcie_setup(struct device * dev,int ret,struct brcmf_fw_request * fwreq)2131 static void brcmf_pcie_setup(struct device *dev, int ret,
2132 struct brcmf_fw_request *fwreq)
2133 {
2134 const struct firmware *fw;
2135 void *nvram;
2136 struct brcmf_bus *bus;
2137 struct brcmf_pciedev *pcie_bus_dev;
2138 struct brcmf_pciedev_info *devinfo;
2139 struct brcmf_commonring **flowrings;
2140 u32 i, nvram_len;
2141
2142 bus = dev_get_drvdata(dev);
2143 pcie_bus_dev = bus->bus_priv.pcie;
2144 devinfo = pcie_bus_dev->devinfo;
2145
2146 /* check firmware loading result */
2147 if (ret)
2148 goto fail;
2149
2150 brcmf_pcie_attach(devinfo);
2151
2152 fw = fwreq->items[BRCMF_PCIE_FW_CODE].binary;
2153 nvram = fwreq->items[BRCMF_PCIE_FW_NVRAM].nv_data.data;
2154 nvram_len = fwreq->items[BRCMF_PCIE_FW_NVRAM].nv_data.len;
2155 devinfo->clm_fw = fwreq->items[BRCMF_PCIE_FW_CLM].binary;
2156 devinfo->txcap_fw = fwreq->items[BRCMF_PCIE_FW_TXCAP].binary;
2157 kfree(fwreq);
2158
2159 ret = brcmf_chip_get_raminfo(devinfo->ci);
2160 if (ret) {
2161 brcmf_err(bus, "Failed to get RAM info\n");
2162 release_firmware(fw);
2163 brcmf_fw_nvram_free(nvram);
2164 goto fail;
2165 }
2166
2167 /* Some of the firmwares have the size of the memory of the device
2168 * defined inside the firmware. This is because part of the memory in
2169 * the device is shared and the devision is determined by FW. Parse
2170 * the firmware and adjust the chip memory size now.
2171 */
2172 brcmf_pcie_adjust_ramsize(devinfo, (u8 *)fw->data, fw->size);
2173
2174 ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len);
2175 if (ret)
2176 goto fail;
2177
2178 devinfo->state = BRCMFMAC_PCIE_STATE_UP;
2179
2180 ret = brcmf_pcie_init_ringbuffers(devinfo);
2181 if (ret)
2182 goto fail;
2183
2184 ret = brcmf_pcie_init_scratchbuffers(devinfo);
2185 if (ret)
2186 goto fail;
2187
2188 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
2189 ret = brcmf_pcie_request_irq(devinfo);
2190 if (ret)
2191 goto fail;
2192
2193 /* hook the commonrings in the bus structure. */
2194 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++)
2195 bus->msgbuf->commonrings[i] =
2196 &devinfo->shared.commonrings[i]->commonring;
2197
2198 flowrings = kcalloc(devinfo->shared.max_flowrings, sizeof(*flowrings),
2199 GFP_KERNEL);
2200 if (!flowrings)
2201 goto fail;
2202
2203 for (i = 0; i < devinfo->shared.max_flowrings; i++)
2204 flowrings[i] = &devinfo->shared.flowrings[i].commonring;
2205 bus->msgbuf->flowrings = flowrings;
2206
2207 bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset;
2208 bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost;
2209 bus->msgbuf->max_flowrings = devinfo->shared.max_flowrings;
2210
2211 init_waitqueue_head(&devinfo->mbdata_resp_wait);
2212
2213 ret = brcmf_attach(&devinfo->pdev->dev);
2214 if (ret)
2215 goto fail;
2216
2217 brcmf_pcie_bus_console_read(devinfo, false);
2218
2219 brcmf_pcie_fwcon_timer(devinfo, true);
2220
2221 return;
2222
2223 fail:
2224 brcmf_err(bus, "Dongle setup failed\n");
2225 brcmf_pcie_bus_console_read(devinfo, true);
2226 brcmf_fw_crashed(dev);
2227 device_release_driver(dev);
2228 }
2229
2230 static struct brcmf_fw_request *
brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info * devinfo)2231 brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info *devinfo)
2232 {
2233 struct brcmf_fw_request *fwreq;
2234 struct brcmf_fw_name fwnames[] = {
2235 { ".bin", devinfo->fw_name },
2236 { ".txt", devinfo->nvram_name },
2237 { ".clm_blob", devinfo->clm_name },
2238 { ".txcap_blob", devinfo->txcap_name },
2239 };
2240
2241 fwreq = brcmf_fw_alloc_request(devinfo->ci->chip, devinfo->ci->chiprev,
2242 brcmf_pcie_fwnames,
2243 ARRAY_SIZE(brcmf_pcie_fwnames),
2244 fwnames, ARRAY_SIZE(fwnames));
2245 if (!fwreq)
2246 return NULL;
2247
2248 fwreq->items[BRCMF_PCIE_FW_CODE].type = BRCMF_FW_TYPE_BINARY;
2249 fwreq->items[BRCMF_PCIE_FW_NVRAM].type = BRCMF_FW_TYPE_NVRAM;
2250 fwreq->items[BRCMF_PCIE_FW_NVRAM].flags = BRCMF_FW_REQF_OPTIONAL;
2251 fwreq->items[BRCMF_PCIE_FW_CLM].type = BRCMF_FW_TYPE_BINARY;
2252 fwreq->items[BRCMF_PCIE_FW_CLM].flags = BRCMF_FW_REQF_OPTIONAL;
2253 fwreq->items[BRCMF_PCIE_FW_TXCAP].type = BRCMF_FW_TYPE_BINARY;
2254 fwreq->items[BRCMF_PCIE_FW_TXCAP].flags = BRCMF_FW_REQF_OPTIONAL;
2255 /* NVRAM reserves PCI domain 0 for Broadcom's SDK faked bus */
2256 fwreq->domain_nr = pci_domain_nr(devinfo->pdev->bus) + 1;
2257 fwreq->bus_nr = devinfo->pdev->bus->number;
2258
2259 /* Apple platforms with fancy firmware/NVRAM selection */
2260 if (devinfo->settings->board_type &&
2261 devinfo->settings->antenna_sku &&
2262 devinfo->otp.valid) {
2263 const struct brcmf_otp_params *otp = &devinfo->otp;
2264 struct device *dev = &devinfo->pdev->dev;
2265 const char **bt = fwreq->board_types;
2266
2267 brcmf_dbg(PCIE, "Apple board: %s\n",
2268 devinfo->settings->board_type);
2269
2270 /* Example: apple,shikoku-RASP-m-6.11-X3 */
2271 bt[0] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s-%s-%s-%s",
2272 devinfo->settings->board_type,
2273 otp->module, otp->vendor, otp->version,
2274 devinfo->settings->antenna_sku);
2275 bt[1] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s-%s-%s",
2276 devinfo->settings->board_type,
2277 otp->module, otp->vendor, otp->version);
2278 bt[2] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s-%s",
2279 devinfo->settings->board_type,
2280 otp->module, otp->vendor);
2281 bt[3] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s",
2282 devinfo->settings->board_type,
2283 otp->module);
2284 bt[4] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s",
2285 devinfo->settings->board_type,
2286 devinfo->settings->antenna_sku);
2287 bt[5] = devinfo->settings->board_type;
2288
2289 if (!bt[0] || !bt[1] || !bt[2] || !bt[3] || !bt[4]) {
2290 kfree(fwreq);
2291 return NULL;
2292 }
2293 } else {
2294 brcmf_dbg(PCIE, "Board: %s\n", devinfo->settings->board_type);
2295 fwreq->board_types[0] = devinfo->settings->board_type;
2296 }
2297
2298 return fwreq;
2299 }
2300
2301 #ifdef DEBUG
2302 static void
brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info * devinfo,bool active)2303 brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info *devinfo, bool active)
2304 {
2305 if (!active) {
2306 if (devinfo->console_active) {
2307 del_timer_sync(&devinfo->timer);
2308 devinfo->console_active = false;
2309 }
2310 return;
2311 }
2312
2313 /* don't start the timer */
2314 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP ||
2315 !devinfo->console_interval || !BRCMF_FWCON_ON())
2316 return;
2317
2318 if (!devinfo->console_active) {
2319 devinfo->timer.expires = jiffies + devinfo->console_interval;
2320 add_timer(&devinfo->timer);
2321 devinfo->console_active = true;
2322 } else {
2323 /* Reschedule the timer */
2324 mod_timer(&devinfo->timer, jiffies + devinfo->console_interval);
2325 }
2326 }
2327
2328 static void
brcmf_pcie_fwcon(struct timer_list * t)2329 brcmf_pcie_fwcon(struct timer_list *t)
2330 {
2331 struct brcmf_pciedev_info *devinfo = from_timer(devinfo, t, timer);
2332
2333 if (!devinfo->console_active)
2334 return;
2335
2336 brcmf_pcie_bus_console_read(devinfo, false);
2337
2338 /* Reschedule the timer if console interval is not zero */
2339 mod_timer(&devinfo->timer, jiffies + devinfo->console_interval);
2340 }
2341
brcmf_pcie_console_interval_get(void * data,u64 * val)2342 static int brcmf_pcie_console_interval_get(void *data, u64 *val)
2343 {
2344 struct brcmf_pciedev_info *devinfo = data;
2345
2346 *val = devinfo->console_interval;
2347
2348 return 0;
2349 }
2350
brcmf_pcie_console_interval_set(void * data,u64 val)2351 static int brcmf_pcie_console_interval_set(void *data, u64 val)
2352 {
2353 struct brcmf_pciedev_info *devinfo = data;
2354
2355 if (val > MAX_CONSOLE_INTERVAL)
2356 return -EINVAL;
2357
2358 devinfo->console_interval = val;
2359
2360 if (!val && devinfo->console_active)
2361 brcmf_pcie_fwcon_timer(devinfo, false);
2362 else if (val)
2363 brcmf_pcie_fwcon_timer(devinfo, true);
2364
2365 return 0;
2366 }
2367
2368 DEFINE_SIMPLE_ATTRIBUTE(brcmf_pcie_console_interval_fops,
2369 brcmf_pcie_console_interval_get,
2370 brcmf_pcie_console_interval_set,
2371 "%llu\n");
2372
brcmf_pcie_debugfs_create(struct device * dev)2373 static void brcmf_pcie_debugfs_create(struct device *dev)
2374 {
2375 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2376 struct brcmf_pub *drvr = bus_if->drvr;
2377 struct brcmf_pciedev *pcie_bus_dev = bus_if->bus_priv.pcie;
2378 struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo;
2379 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr);
2380
2381 if (IS_ERR_OR_NULL(dentry))
2382 return;
2383
2384 devinfo->console_interval = BRCMF_CONSOLE;
2385
2386 debugfs_create_file("console_interval", 0644, dentry, devinfo,
2387 &brcmf_pcie_console_interval_fops);
2388 }
2389
2390 #else
brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info * devinfo,bool active)2391 void brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info *devinfo, bool active)
2392 {
2393 }
2394
brcmf_pcie_debugfs_create(struct device * dev)2395 static void brcmf_pcie_debugfs_create(struct device *dev)
2396 {
2397 }
2398 #endif
2399
2400 struct brcmf_pcie_drvdata {
2401 enum brcmf_fwvendor vendor;
2402 bool fw_seed;
2403 };
2404
2405 enum {
2406 BRCMF_DRVDATA_CYW,
2407 BRCMF_DRVDATA_BCA,
2408 BRCMF_DRVDATA_WCC,
2409 BRCMF_DRVDATA_WCC_SEED,
2410 };
2411
2412 static const struct brcmf_pcie_drvdata drvdata[] = {
2413 [BRCMF_DRVDATA_CYW] = {
2414 .vendor = BRCMF_FWVENDOR_CYW,
2415 .fw_seed = false,
2416 },
2417 [BRCMF_DRVDATA_BCA] = {
2418 .vendor = BRCMF_FWVENDOR_BCA,
2419 .fw_seed = false,
2420 },
2421 [BRCMF_DRVDATA_WCC] = {
2422 .vendor = BRCMF_FWVENDOR_WCC,
2423 .fw_seed = false,
2424 },
2425 [BRCMF_DRVDATA_WCC_SEED] = {
2426 .vendor = BRCMF_FWVENDOR_WCC,
2427 .fw_seed = true,
2428 },
2429 };
2430
2431 /* Forward declaration for pci_match_id() call */
2432 static const struct pci_device_id brcmf_pcie_devid_table[];
2433
2434 static int
brcmf_pcie_probe(struct pci_dev * pdev,const struct pci_device_id * id)2435 brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2436 {
2437 int ret;
2438 struct brcmf_fw_request *fwreq;
2439 struct brcmf_pciedev_info *devinfo;
2440 struct brcmf_pciedev *pcie_bus_dev;
2441 struct brcmf_core *core;
2442 struct brcmf_bus *bus;
2443
2444 if (!id) {
2445 id = pci_match_id(brcmf_pcie_devid_table, pdev);
2446 if (!id) {
2447 pci_err(pdev, "Error could not find pci_device_id for %x:%x\n", pdev->vendor, pdev->device);
2448 return -ENODEV;
2449 }
2450 }
2451
2452 brcmf_dbg(PCIE, "Enter %x:%x\n", pdev->vendor, pdev->device);
2453
2454 ret = -ENOMEM;
2455 devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL);
2456 if (devinfo == NULL)
2457 return ret;
2458
2459 devinfo->pdev = pdev;
2460 pcie_bus_dev = NULL;
2461 devinfo->ci = brcmf_chip_attach(devinfo, pdev->device,
2462 &brcmf_pcie_buscore_ops);
2463 if (IS_ERR(devinfo->ci)) {
2464 ret = PTR_ERR(devinfo->ci);
2465 devinfo->ci = NULL;
2466 goto fail;
2467 }
2468
2469 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2);
2470 if (core->rev >= 64)
2471 devinfo->reginfo = &brcmf_reginfo_64;
2472 else
2473 devinfo->reginfo = &brcmf_reginfo_default;
2474
2475 pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL);
2476 if (pcie_bus_dev == NULL) {
2477 ret = -ENOMEM;
2478 goto fail;
2479 }
2480
2481 devinfo->settings = brcmf_get_module_param(&devinfo->pdev->dev,
2482 BRCMF_BUSTYPE_PCIE,
2483 devinfo->ci->chip,
2484 devinfo->ci->chiprev);
2485 if (!devinfo->settings) {
2486 ret = -ENOMEM;
2487 goto fail;
2488 }
2489 ret = PTR_ERR_OR_ZERO(devinfo->settings);
2490 if (ret < 0)
2491 goto fail;
2492
2493 bus = kzalloc(sizeof(*bus), GFP_KERNEL);
2494 if (!bus) {
2495 ret = -ENOMEM;
2496 goto fail;
2497 }
2498 bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL);
2499 if (!bus->msgbuf) {
2500 ret = -ENOMEM;
2501 kfree(bus);
2502 goto fail;
2503 }
2504
2505 /* hook it all together. */
2506 pcie_bus_dev->devinfo = devinfo;
2507 pcie_bus_dev->bus = bus;
2508 bus->dev = &pdev->dev;
2509 bus->bus_priv.pcie = pcie_bus_dev;
2510 bus->ops = &brcmf_pcie_bus_ops;
2511 bus->proto_type = BRCMF_PROTO_MSGBUF;
2512 bus->chip = devinfo->coreid;
2513 bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot);
2514 bus->fwvid = drvdata[id->driver_data].vendor;
2515 devinfo->fwseed = drvdata[id->driver_data].fw_seed;
2516 dev_set_drvdata(&pdev->dev, bus);
2517
2518 ret = brcmf_alloc(&devinfo->pdev->dev, devinfo->settings);
2519 if (ret)
2520 goto fail_bus;
2521
2522 ret = brcmf_pcie_read_otp(devinfo);
2523 if (ret) {
2524 brcmf_err(bus, "failed to parse OTP\n");
2525 goto fail_brcmf;
2526 }
2527
2528 #ifdef DEBUG
2529 /* Set up the fwcon timer */
2530 timer_setup(&devinfo->timer, brcmf_pcie_fwcon, 0);
2531 #endif
2532
2533 fwreq = brcmf_pcie_prepare_fw_request(devinfo);
2534 if (!fwreq) {
2535 ret = -ENOMEM;
2536 goto fail_brcmf;
2537 }
2538
2539 ret = brcmf_fw_get_firmwares(bus->dev, fwreq, brcmf_pcie_setup);
2540 if (ret < 0) {
2541 kfree(fwreq);
2542 goto fail_brcmf;
2543 }
2544 return 0;
2545
2546 fail_brcmf:
2547 brcmf_free(&devinfo->pdev->dev);
2548 fail_bus:
2549 kfree(bus->msgbuf);
2550 kfree(bus);
2551 fail:
2552 brcmf_err(NULL, "failed %x:%x\n", pdev->vendor, pdev->device);
2553 brcmf_pcie_release_resource(devinfo);
2554 if (devinfo->ci)
2555 brcmf_chip_detach(devinfo->ci);
2556 if (devinfo->settings)
2557 brcmf_release_module_param(devinfo->settings);
2558 kfree(pcie_bus_dev);
2559 kfree(devinfo);
2560 return ret;
2561 }
2562
2563
2564 static void
brcmf_pcie_remove(struct pci_dev * pdev)2565 brcmf_pcie_remove(struct pci_dev *pdev)
2566 {
2567 struct brcmf_pciedev_info *devinfo;
2568 struct brcmf_bus *bus;
2569
2570 brcmf_dbg(PCIE, "Enter\n");
2571
2572 bus = dev_get_drvdata(&pdev->dev);
2573 if (bus == NULL)
2574 return;
2575
2576 devinfo = bus->bus_priv.pcie->devinfo;
2577 brcmf_pcie_bus_console_read(devinfo, false);
2578 brcmf_pcie_fwcon_timer(devinfo, false);
2579
2580 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
2581 if (devinfo->ci)
2582 brcmf_pcie_intr_disable(devinfo);
2583
2584 brcmf_detach(&pdev->dev);
2585 brcmf_free(&pdev->dev);
2586
2587 kfree(bus->bus_priv.pcie);
2588 kfree(bus->msgbuf->flowrings);
2589 kfree(bus->msgbuf);
2590 kfree(bus);
2591
2592 brcmf_pcie_release_irq(devinfo);
2593 brcmf_pcie_release_scratchbuffers(devinfo);
2594 brcmf_pcie_release_ringbuffers(devinfo);
2595 brcmf_pcie_reset_device(devinfo);
2596 brcmf_pcie_release_resource(devinfo);
2597 release_firmware(devinfo->clm_fw);
2598 release_firmware(devinfo->txcap_fw);
2599
2600 if (devinfo->ci)
2601 brcmf_chip_detach(devinfo->ci);
2602 if (devinfo->settings)
2603 brcmf_release_module_param(devinfo->settings);
2604
2605 kfree(devinfo);
2606 dev_set_drvdata(&pdev->dev, NULL);
2607 }
2608
2609
2610 #ifdef CONFIG_PM
2611
2612
brcmf_pcie_pm_enter_D3(struct device * dev)2613 static int brcmf_pcie_pm_enter_D3(struct device *dev)
2614 {
2615 struct brcmf_pciedev_info *devinfo;
2616 struct brcmf_bus *bus;
2617
2618 brcmf_dbg(PCIE, "Enter\n");
2619
2620 bus = dev_get_drvdata(dev);
2621 devinfo = bus->bus_priv.pcie->devinfo;
2622
2623 brcmf_pcie_fwcon_timer(devinfo, false);
2624 brcmf_bus_change_state(bus, BRCMF_BUS_DOWN);
2625
2626 devinfo->mbdata_completed = false;
2627 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM);
2628
2629 wait_event_timeout(devinfo->mbdata_resp_wait, devinfo->mbdata_completed,
2630 BRCMF_PCIE_MBDATA_TIMEOUT);
2631 if (!devinfo->mbdata_completed) {
2632 brcmf_err(bus, "Timeout on response for entering D3 substate\n");
2633 brcmf_bus_change_state(bus, BRCMF_BUS_UP);
2634 return -EIO;
2635 }
2636
2637 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
2638
2639 return 0;
2640 }
2641
2642
brcmf_pcie_pm_leave_D3(struct device * dev)2643 static int brcmf_pcie_pm_leave_D3(struct device *dev)
2644 {
2645 struct brcmf_pciedev_info *devinfo;
2646 struct brcmf_bus *bus;
2647 struct pci_dev *pdev;
2648 int err;
2649
2650 brcmf_dbg(PCIE, "Enter\n");
2651
2652 bus = dev_get_drvdata(dev);
2653 devinfo = bus->bus_priv.pcie->devinfo;
2654 brcmf_dbg(PCIE, "Enter, dev=%p, bus=%p\n", dev, bus);
2655
2656 /* Check if device is still up and running, if so we are ready */
2657 if (brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->intmask) != 0) {
2658 brcmf_dbg(PCIE, "Try to wakeup device....\n");
2659 if (brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM))
2660 goto cleanup;
2661 brcmf_dbg(PCIE, "Hot resume, continue....\n");
2662 devinfo->state = BRCMFMAC_PCIE_STATE_UP;
2663 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
2664 brcmf_bus_change_state(bus, BRCMF_BUS_UP);
2665 brcmf_pcie_intr_enable(devinfo);
2666 brcmf_pcie_hostready(devinfo);
2667 brcmf_pcie_fwcon_timer(devinfo, true);
2668 return 0;
2669 }
2670
2671 cleanup:
2672 brcmf_chip_detach(devinfo->ci);
2673 devinfo->ci = NULL;
2674 pdev = devinfo->pdev;
2675 brcmf_pcie_remove(pdev);
2676
2677 err = brcmf_pcie_probe(pdev, NULL);
2678 if (err)
2679 __brcmf_err(NULL, __func__, "probe after resume failed, err=%d\n", err);
2680
2681 return err;
2682 }
2683
2684
2685 static const struct dev_pm_ops brcmf_pciedrvr_pm = {
2686 .suspend = brcmf_pcie_pm_enter_D3,
2687 .resume = brcmf_pcie_pm_leave_D3,
2688 .freeze = brcmf_pcie_pm_enter_D3,
2689 .restore = brcmf_pcie_pm_leave_D3,
2690 };
2691
2692
2693 #endif /* CONFIG_PM */
2694
2695
2696 #define BRCMF_PCIE_DEVICE(dev_id, fw_vend) \
2697 { \
2698 BRCM_PCIE_VENDOR_ID_BROADCOM, (dev_id), \
2699 PCI_ANY_ID, PCI_ANY_ID, \
2700 PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, \
2701 BRCMF_DRVDATA_ ## fw_vend \
2702 }
2703 #define BRCMF_PCIE_DEVICE_SUB(dev_id, subvend, subdev, fw_vend) \
2704 { \
2705 BRCM_PCIE_VENDOR_ID_BROADCOM, (dev_id), \
2706 (subvend), (subdev), \
2707 PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, \
2708 BRCMF_DRVDATA_ ## fw_vend \
2709 }
2710
2711 static const struct pci_device_id brcmf_pcie_devid_table[] = {
2712 BRCMF_PCIE_DEVICE(BRCM_PCIE_4350_DEVICE_ID, WCC),
2713 BRCMF_PCIE_DEVICE_SUB(0x4355, BRCM_PCIE_VENDOR_ID_BROADCOM, 0x4355, WCC),
2714 BRCMF_PCIE_DEVICE(BRCM_PCIE_4354_RAW_DEVICE_ID, WCC),
2715 BRCMF_PCIE_DEVICE(BRCM_PCIE_4355_DEVICE_ID, WCC_SEED),
2716 BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID, WCC),
2717 BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID, WCC),
2718 BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID, WCC),
2719 BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_RAW_DEVICE_ID, WCC),
2720 BRCMF_PCIE_DEVICE(BRCM_PCIE_4358_DEVICE_ID, WCC),
2721 BRCMF_PCIE_DEVICE(BRCM_PCIE_4359_DEVICE_ID, WCC),
2722 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID, WCC),
2723 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_2G_DEVICE_ID, WCC),
2724 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_5G_DEVICE_ID, WCC),
2725 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_RAW_DEVICE_ID, WCC),
2726 BRCMF_PCIE_DEVICE(BRCM_PCIE_4364_DEVICE_ID, WCC_SEED),
2727 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_DEVICE_ID, BCA),
2728 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_2G_DEVICE_ID, BCA),
2729 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_5G_DEVICE_ID, BCA),
2730 BRCMF_PCIE_DEVICE_SUB(0x4365, BRCM_PCIE_VENDOR_ID_BROADCOM, 0x4365, BCA),
2731 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_DEVICE_ID, BCA),
2732 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_2G_DEVICE_ID, BCA),
2733 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_5G_DEVICE_ID, BCA),
2734 BRCMF_PCIE_DEVICE(BRCM_PCIE_4371_DEVICE_ID, WCC),
2735 BRCMF_PCIE_DEVICE(BRCM_PCIE_43596_DEVICE_ID, CYW),
2736 BRCMF_PCIE_DEVICE(BRCM_PCIE_4377_DEVICE_ID, WCC_SEED),
2737 BRCMF_PCIE_DEVICE(BRCM_PCIE_4378_DEVICE_ID, WCC_SEED),
2738 BRCMF_PCIE_DEVICE(BRCM_PCIE_4387_DEVICE_ID, WCC_SEED),
2739 BRCMF_PCIE_DEVICE(BRCM_PCIE_43752_DEVICE_ID, WCC_SEED),
2740
2741 { /* end: all zeroes */ }
2742 };
2743
2744
2745 MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table);
2746
2747
2748 static struct pci_driver brcmf_pciedrvr = {
2749 .name = KBUILD_MODNAME,
2750 .id_table = brcmf_pcie_devid_table,
2751 .probe = brcmf_pcie_probe,
2752 .remove = brcmf_pcie_remove,
2753 #ifdef CONFIG_PM
2754 .driver.pm = &brcmf_pciedrvr_pm,
2755 #endif
2756 .driver.coredump = brcmf_dev_coredump,
2757 };
2758
2759
brcmf_pcie_register(void)2760 int brcmf_pcie_register(void)
2761 {
2762 brcmf_dbg(PCIE, "Enter\n");
2763 return pci_register_driver(&brcmf_pciedrvr);
2764 }
2765
2766
brcmf_pcie_exit(void)2767 void brcmf_pcie_exit(void)
2768 {
2769 brcmf_dbg(PCIE, "Enter\n");
2770 pci_unregister_driver(&brcmf_pciedrvr);
2771 }
2772