1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Eswin DWC Ethernet linux driver
4 *
5 * Copyright 2025, Beijing ESWIN Computing Technology Co., Ltd.
6 *
7 * Authors:
8 * Zhi Li <lizhi2@eswincomputing.com>
9 * Shuang Liang <liangshuang@eswincomputing.com>
10 * Shangjuan Wei <weishangjuan@eswincomputing.com>
11 */
12
13 #include <linux/platform_device.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/stmmac.h>
17 #include <linux/regmap.h>
18 #include <linux/of.h>
19
20 #include "stmmac_platform.h"
21
22 /* eth_phy_ctrl_offset eth0:0x100 */
23 #define EIC7700_ETH_TX_CLK_SEL BIT(16)
24 #define EIC7700_ETH_PHY_INTF_SELI BIT(0)
25
26 /* eth_axi_lp_ctrl_offset eth0:0x108 */
27 #define EIC7700_ETH_CSYSREQ_VAL BIT(0)
28
29 /*
30 * TX/RX Clock Delay Bit Masks:
31 * - TX Delay: bits [14:8] - TX_CLK delay (unit: 0.02ns per bit)
32 * - TX Invert : bit [15]
33 * - RX Delay: bits [30:24] - RX_CLK delay (unit: 0.02ns per bit)
34 * - RX Invert : bit [31]
35 */
36 #define EIC7700_ETH_TX_ADJ_DELAY GENMASK(14, 8)
37 #define EIC7700_ETH_RX_ADJ_DELAY GENMASK(30, 24)
38 #define EIC7700_ETH_TX_INV_DELAY BIT(15)
39 #define EIC7700_ETH_RX_INV_DELAY BIT(31)
40
41 #define EIC7700_MAX_DELAY_STEPS 0x7F
42 #define EIC7700_DELAY_STEP_PS 20
43 #define EIC7700_MAX_DELAY_PS \
44 (EIC7700_MAX_DELAY_STEPS * EIC7700_DELAY_STEP_PS)
45
46 static const char * const eic7700_clk_names[] = {
47 "tx", "axi", "cfg",
48 };
49
50 struct eic7700_dwmac_data {
51 bool rgmii_rx_clk_invert;
52 bool has_internal_tx_delay;
53 u32 tx_clk_inherent_skew_ps;
54 };
55
56 struct eic7700_qos_priv {
57 struct device *dev;
58 struct plat_stmmacenet_data *plat_dat;
59 struct regmap *eic7700_hsp_regmap;
60 u32 eth_axi_lp_ctrl_offset;
61 u32 eth_phy_ctrl_offset;
62 u32 eth_clk_offset;
63 u32 eth_txd_offset;
64 u32 eth_rxd_offset;
65 u32 eth_clk_dly_param;
66 bool has_txd_offset;
67 bool has_rxd_offset;
68 bool eth_rx_clk_inv;
69 };
70
eic7700_clks_config(void * priv,bool enabled)71 static int eic7700_clks_config(void *priv, bool enabled)
72 {
73 struct eic7700_qos_priv *dwc = (struct eic7700_qos_priv *)priv;
74 struct plat_stmmacenet_data *plat = dwc->plat_dat;
75 int ret = 0;
76
77 if (enabled)
78 ret = clk_bulk_prepare_enable(plat->num_clks, plat->clks);
79 else
80 clk_bulk_disable_unprepare(plat->num_clks, plat->clks);
81
82 return ret;
83 }
84
eic7700_dwmac_init(struct device * dev,void * priv)85 static int eic7700_dwmac_init(struct device *dev, void *priv)
86 {
87 struct eic7700_qos_priv *dwc = priv;
88 int ret;
89
90 ret = eic7700_clks_config(dwc, true);
91 if (ret)
92 return ret;
93
94 ret = regmap_set_bits(dwc->eic7700_hsp_regmap,
95 dwc->eth_phy_ctrl_offset,
96 EIC7700_ETH_TX_CLK_SEL |
97 EIC7700_ETH_PHY_INTF_SELI);
98 if (ret) {
99 eic7700_clks_config(dwc, false);
100 return ret;
101 }
102
103 regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_axi_lp_ctrl_offset,
104 EIC7700_ETH_CSYSREQ_VAL);
105
106 if (dwc->has_txd_offset)
107 regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_txd_offset, 0);
108
109 if (dwc->has_rxd_offset)
110 regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_rxd_offset, 0);
111
112 return 0;
113 }
114
eic7700_dwmac_exit(struct device * dev,void * priv)115 static void eic7700_dwmac_exit(struct device *dev, void *priv)
116 {
117 struct eic7700_qos_priv *dwc = priv;
118
119 eic7700_clks_config(dwc, false);
120 }
121
eic7700_dwmac_suspend(struct device * dev,void * priv)122 static int eic7700_dwmac_suspend(struct device *dev, void *priv)
123 {
124 return pm_runtime_force_suspend(dev);
125 }
126
eic7700_dwmac_resume(struct device * dev,void * priv)127 static int eic7700_dwmac_resume(struct device *dev, void *priv)
128 {
129 int ret;
130
131 ret = pm_runtime_force_resume(dev);
132 if (ret)
133 dev_err(dev, "%s failed: %d\n", __func__, ret);
134
135 return ret;
136 }
137
138 /*
139 * eth1 requires RX clock inversion at 1000Mbps due to silicon-inherent
140 * RX sampling skew at MAC input.
141 *
142 * The configuration is updated in fix_mac_speed() because the required
143 * sampling behavior depends on the negotiated link speed.
144 */
eic7700_dwmac_fix_speed(void * priv,phy_interface_t interface,int speed,unsigned int mode)145 static void eic7700_dwmac_fix_speed(void *priv, phy_interface_t interface,
146 int speed, unsigned int mode)
147 {
148 struct eic7700_qos_priv *dwc = (struct eic7700_qos_priv *)priv;
149 u32 dly_param = dwc->eth_clk_dly_param;
150
151 switch (speed) {
152 case SPEED_1000:
153 if (dwc->eth_rx_clk_inv)
154 dly_param |= EIC7700_ETH_RX_INV_DELAY;
155 break;
156 case SPEED_100:
157 case SPEED_10:
158 break;
159 default:
160 dev_warn(dwc->dev, "unsupported speed %u\n", speed);
161 return;
162 }
163
164 regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_clk_offset, dly_param);
165 }
166
eic7700_dwmac_probe(struct platform_device * pdev)167 static int eic7700_dwmac_probe(struct platform_device *pdev)
168 {
169 const struct eic7700_dwmac_data *data;
170 struct plat_stmmacenet_data *plat_dat;
171 struct stmmac_resources stmmac_res;
172 struct eic7700_qos_priv *dwc_priv;
173 u32 delay_ps, val;
174 int i, ret;
175
176 ret = stmmac_get_platform_resources(pdev, &stmmac_res);
177 if (ret)
178 return dev_err_probe(&pdev->dev, ret,
179 "failed to get resources\n");
180
181 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
182 if (IS_ERR(plat_dat))
183 return dev_err_probe(&pdev->dev, PTR_ERR(plat_dat),
184 "dt configuration failed\n");
185
186 dwc_priv = devm_kzalloc(&pdev->dev, sizeof(*dwc_priv), GFP_KERNEL);
187 if (!dwc_priv)
188 return -ENOMEM;
189
190 dwc_priv->dev = &pdev->dev;
191
192 data = device_get_match_data(&pdev->dev);
193 if (!data)
194 return dev_err_probe(&pdev->dev,
195 -EINVAL, "no match data found\n");
196
197 dwc_priv->eth_rx_clk_inv = data->rgmii_rx_clk_invert;
198 /*
199 * The MAC silicon unconditionally adds ~2 ns TX delay; prevent
200 * the PHY from also adding TX delay to avoid doubling it.
201 *
202 * DT specifies rgmii-id (TX from MAC silicon, RX from PHY);
203 * override to rgmii-rxid so the PHY only adds its RX delay.
204 */
205 if (data->has_internal_tx_delay) {
206 plat_dat->phy_interface =
207 phy_fix_phy_mode_for_mac_delays(plat_dat->phy_interface,
208 true, false);
209 if (plat_dat->phy_interface == PHY_INTERFACE_MODE_NA)
210 return dev_err_probe(&pdev->dev, -EINVAL,
211 "phy interface mode is NA\n");
212 }
213
214 /* Read rx-internal-delay-ps and update rx_clk delay */
215 if (!of_property_read_u32(pdev->dev.of_node,
216 "rx-internal-delay-ps", &delay_ps)) {
217 if (delay_ps % EIC7700_DELAY_STEP_PS)
218 return dev_err_probe(&pdev->dev, -EINVAL,
219 "rx delay must be multiple of %dps\n",
220 EIC7700_DELAY_STEP_PS);
221
222 if (delay_ps > EIC7700_MAX_DELAY_PS)
223 return dev_err_probe(&pdev->dev, -EINVAL,
224 "rx delay out of range\n");
225
226 val = delay_ps / EIC7700_DELAY_STEP_PS;
227
228 dwc_priv->eth_clk_dly_param &= ~EIC7700_ETH_RX_ADJ_DELAY;
229 dwc_priv->eth_clk_dly_param |=
230 FIELD_PREP(EIC7700_ETH_RX_ADJ_DELAY, val);
231 }
232
233 /* Read tx-internal-delay-ps and update tx_clk delay.
234 *
235 * For eswin,eic7700-qos-eth-clk-inversion, the DT property describes
236 * the effective TX delay at the MAC output, including the inherent
237 * silicon delay. Subtract the fixed component to obtain the
238 * programmable delay value.
239 */
240 if (!of_property_read_u32(pdev->dev.of_node,
241 "tx-internal-delay-ps", &delay_ps)) {
242 if (delay_ps % EIC7700_DELAY_STEP_PS)
243 return dev_err_probe(&pdev->dev, -EINVAL,
244 "tx delay must be multiple of %dps\n",
245 EIC7700_DELAY_STEP_PS);
246
247 if (delay_ps < data->tx_clk_inherent_skew_ps)
248 return dev_err_probe(&pdev->dev, -EINVAL,
249 "tx delay %ups below inherent skew %ups\n",
250 delay_ps, data->tx_clk_inherent_skew_ps);
251
252 delay_ps -= data->tx_clk_inherent_skew_ps;
253
254 if (delay_ps > EIC7700_MAX_DELAY_PS)
255 return dev_err_probe(&pdev->dev, -EINVAL,
256 "tx delay out of programmable range\n");
257
258 val = delay_ps / EIC7700_DELAY_STEP_PS;
259
260 dwc_priv->eth_clk_dly_param &= ~EIC7700_ETH_TX_ADJ_DELAY;
261 dwc_priv->eth_clk_dly_param |=
262 FIELD_PREP(EIC7700_ETH_TX_ADJ_DELAY, val);
263 }
264
265 dwc_priv->eic7700_hsp_regmap =
266 syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
267 "eswin,hsp-sp-csr");
268 if (IS_ERR(dwc_priv->eic7700_hsp_regmap))
269 return dev_err_probe(&pdev->dev,
270 PTR_ERR(dwc_priv->eic7700_hsp_regmap),
271 "Failed to get hsp-sp-csr regmap\n");
272
273 ret = of_property_read_u32_index(pdev->dev.of_node,
274 "eswin,hsp-sp-csr",
275 1, &dwc_priv->eth_phy_ctrl_offset);
276 if (ret)
277 return dev_err_probe(&pdev->dev, ret,
278 "can't get eth_phy_ctrl_offset\n");
279
280 ret = of_property_read_u32_index(pdev->dev.of_node,
281 "eswin,hsp-sp-csr",
282 2, &dwc_priv->eth_axi_lp_ctrl_offset);
283 if (ret)
284 return dev_err_probe(&pdev->dev, ret,
285 "can't get eth_axi_lp_ctrl_offset\n");
286
287 ret = of_property_read_u32_index(pdev->dev.of_node,
288 "eswin,hsp-sp-csr",
289 3, &dwc_priv->eth_clk_offset);
290 if (ret)
291 return dev_err_probe(&pdev->dev, ret,
292 "can't get eth_clk_offset\n");
293
294 ret = of_property_read_u32_index(pdev->dev.of_node,
295 "eswin,hsp-sp-csr",
296 4, &dwc_priv->eth_txd_offset);
297 if (!ret)
298 dwc_priv->has_txd_offset = true;
299
300 ret = of_property_read_u32_index(pdev->dev.of_node,
301 "eswin,hsp-sp-csr",
302 5, &dwc_priv->eth_rxd_offset);
303 if (!ret)
304 dwc_priv->has_rxd_offset = true;
305
306 plat_dat->num_clks = ARRAY_SIZE(eic7700_clk_names);
307 plat_dat->clks = devm_kcalloc(&pdev->dev,
308 plat_dat->num_clks,
309 sizeof(*plat_dat->clks),
310 GFP_KERNEL);
311 if (!plat_dat->clks)
312 return -ENOMEM;
313
314 for (i = 0; i < ARRAY_SIZE(eic7700_clk_names); i++)
315 plat_dat->clks[i].id = eic7700_clk_names[i];
316
317 ret = devm_clk_bulk_get_optional(&pdev->dev,
318 plat_dat->num_clks,
319 plat_dat->clks);
320 if (ret)
321 return dev_err_probe(&pdev->dev, ret,
322 "Failed to get clocks\n");
323
324 plat_dat->clk_tx_i = stmmac_pltfr_find_clk(plat_dat, "tx");
325 plat_dat->set_clk_tx_rate = stmmac_set_clk_tx_rate;
326 plat_dat->clks_config = eic7700_clks_config;
327 plat_dat->bsp_priv = dwc_priv;
328 dwc_priv->plat_dat = plat_dat;
329 plat_dat->init = eic7700_dwmac_init;
330 plat_dat->exit = eic7700_dwmac_exit;
331 plat_dat->suspend = eic7700_dwmac_suspend;
332 plat_dat->resume = eic7700_dwmac_resume;
333 plat_dat->fix_mac_speed = eic7700_dwmac_fix_speed;
334
335 return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);
336 }
337
338 static const struct eic7700_dwmac_data eic7700_dwmac_data = {
339 .rgmii_rx_clk_invert = false,
340 .has_internal_tx_delay = false,
341 .tx_clk_inherent_skew_ps = 0,
342 };
343
344 static const struct eic7700_dwmac_data eic7700_dwmac_data_clk_inversion = {
345 .rgmii_rx_clk_invert = true,
346 .has_internal_tx_delay = true,
347 .tx_clk_inherent_skew_ps = 2000,
348 };
349
350 static const struct of_device_id eic7700_dwmac_match[] = {
351 { .compatible = "eswin,eic7700-qos-eth",
352 .data = &eic7700_dwmac_data,
353 },
354 {
355 .compatible = "eswin,eic7700-qos-eth-clk-inversion",
356 .data = &eic7700_dwmac_data_clk_inversion,
357 },
358 { }
359 };
360 MODULE_DEVICE_TABLE(of, eic7700_dwmac_match);
361
362 static struct platform_driver eic7700_dwmac_driver = {
363 .probe = eic7700_dwmac_probe,
364 .driver = {
365 .name = "eic7700-eth-dwmac",
366 .pm = &stmmac_pltfr_pm_ops,
367 .of_match_table = eic7700_dwmac_match,
368 },
369 };
370 module_platform_driver(eic7700_dwmac_driver);
371
372 MODULE_AUTHOR("Zhi Li <lizhi2@eswincomputing.com>");
373 MODULE_AUTHOR("Shuang Liang <liangshuang@eswincomputing.com>");
374 MODULE_AUTHOR("Shangjuan Wei <weishangjuan@eswincomputing.com>");
375 MODULE_DESCRIPTION("Eswin eic7700 qos ethernet driver");
376 MODULE_LICENSE("GPL");
377