1 // SPDX-License-Identifier: GPL-2.0-or-later
2 // Copyright IBM Corp
3 // Copyright ASPEED Technology
4
5 #define pr_fmt(fmt) "clk-ast2600: " fmt
6
7 #include <linux/mfd/syscon.h>
8 #include <linux/of_address.h>
9 #include <linux/platform_device.h>
10 #include <linux/regmap.h>
11 #include <linux/slab.h>
12
13 #include <dt-bindings/clock/ast2600-clock.h>
14
15 #include "clk-aspeed.h"
16
17 /*
18 * This includes the gates (configured from aspeed_g6_gates), plus the
19 * explicitly-configured clocks (ASPEED_CLK_HPLL and up).
20 */
21 #define ASPEED_G6_NUM_CLKS 73
22
23 #define ASPEED_G6_SILICON_REV 0x014
24 #define CHIP_REVISION_ID GENMASK(23, 16)
25
26 #define ASPEED_G6_RESET_CTRL 0x040
27 #define ASPEED_G6_RESET_CTRL2 0x050
28
29 #define ASPEED_G6_CLK_STOP_CTRL 0x080
30 #define ASPEED_G6_CLK_STOP_CTRL2 0x090
31
32 #define ASPEED_G6_MISC_CTRL 0x0C0
33 #define UART_DIV13_EN BIT(12)
34
35 #define ASPEED_G6_CLK_SELECTION1 0x300
36 #define ASPEED_G6_CLK_SELECTION2 0x304
37 #define ASPEED_G6_CLK_SELECTION4 0x310
38 #define ASPEED_G6_CLK_SELECTION5 0x314
39 #define I3C_CLK_SELECTION_SHIFT 31
40 #define I3C_CLK_SELECTION BIT(31)
41 #define I3C_CLK_SELECT_HCLK (0 << I3C_CLK_SELECTION_SHIFT)
42 #define I3C_CLK_SELECT_APLL_DIV (1 << I3C_CLK_SELECTION_SHIFT)
43 #define APLL_DIV_SELECTION_SHIFT 28
44 #define APLL_DIV_SELECTION GENMASK(30, 28)
45 #define APLL_DIV_2 (0b001 << APLL_DIV_SELECTION_SHIFT)
46 #define APLL_DIV_3 (0b010 << APLL_DIV_SELECTION_SHIFT)
47 #define APLL_DIV_4 (0b011 << APLL_DIV_SELECTION_SHIFT)
48 #define APLL_DIV_5 (0b100 << APLL_DIV_SELECTION_SHIFT)
49 #define APLL_DIV_6 (0b101 << APLL_DIV_SELECTION_SHIFT)
50 #define APLL_DIV_7 (0b110 << APLL_DIV_SELECTION_SHIFT)
51 #define APLL_DIV_8 (0b111 << APLL_DIV_SELECTION_SHIFT)
52
53 #define ASPEED_HPLL_PARAM 0x200
54 #define ASPEED_APLL_PARAM 0x210
55 #define ASPEED_MPLL_PARAM 0x220
56 #define ASPEED_EPLL_PARAM 0x240
57 #define ASPEED_DPLL_PARAM 0x260
58
59 #define ASPEED_G6_STRAP1 0x500
60
61 #define ASPEED_MAC12_CLK_DLY 0x340
62 #define ASPEED_MAC34_CLK_DLY 0x350
63
64 /* Globally visible clocks */
65 static DEFINE_SPINLOCK(aspeed_g6_clk_lock);
66
67 /* Keeps track of all clocks */
68 static struct clk_hw_onecell_data *aspeed_g6_clk_data;
69
70 static void __iomem *scu_g6_base;
71 /* AST2600 revision: A0, A1, A2, etc */
72 static u8 soc_rev;
73
74 /*
75 * The majority of the clocks in the system are gates paired with a reset
76 * controller that holds the IP in reset; this is represented by the @reset_idx
77 * member of entries here.
78 *
79 * This borrows from clk_hw_register_gate, but registers two 'gates', one
80 * to control the clock enable register and the other to control the reset
81 * IP. This allows us to enforce the ordering:
82 *
83 * 1. Place IP in reset
84 * 2. Enable clock
85 * 3. Delay
86 * 4. Release reset
87 *
88 * Consequently, if reset_idx is set, reset control is implicit: the clock
89 * consumer does not need its own reset handling, as enabling the clock will
90 * also deassert reset.
91 *
92 * There are some gates that do not have an associated reset; these are
93 * handled by using -1 as the index for the reset, and the consumer must
94 * explicitly assert/deassert reset lines as required.
95 *
96 * Clocks marked with CLK_IS_CRITICAL:
97 *
98 * ref0 and ref1 are essential for the SoC to operate
99 * mpll is required if SDRAM is used
100 */
101 static const struct aspeed_gate_data aspeed_g6_gates[] = {
102 /* clk rst name parent flags */
103 [ASPEED_CLK_GATE_MCLK] = { 0, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
104 [ASPEED_CLK_GATE_ECLK] = { 1, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
105 [ASPEED_CLK_GATE_GCLK] = { 2, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
106 /* vclk parent - dclk/d1clk/hclk/mclk */
107 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
108 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */
109 /* From dpll */
110 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
111 [ASPEED_CLK_GATE_REF0CLK] = { 6, -1, "ref0clk-gate", "clkin", CLK_IS_CRITICAL },
112 [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */
113 /* Reserved 8 */
114 [ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */
115 /* From dpll/epll/40mhz usb p1 phy/gpioc6/dp phy pll */
116 [ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", "d1clk", 0 }, /* GFX CRT */
117 /* Reserved 11/12 */
118 [ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */
119 [ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */
120 [ASPEED_CLK_GATE_UART5CLK] = { 15, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */
121 /* Reserved 16/19 */
122 [ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac12", 0 }, /* MAC1 */
123 [ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac12", 0 }, /* MAC2 */
124 /* Reserved 22/23 */
125 [ASPEED_CLK_GATE_RSACLK] = { 24, 4, "rsaclk-gate", NULL, 0 }, /* HAC */
126 [ASPEED_CLK_GATE_RVASCLK] = { 25, 9, "rvasclk-gate", NULL, 0 }, /* RVAS */
127 /* Reserved 26 */
128 [ASPEED_CLK_GATE_EMMCCLK] = { 27, 16, "emmcclk-gate", NULL, 0 }, /* For card clk */
129 /* Reserved 28/29/30 */
130 [ASPEED_CLK_GATE_LCLK] = { 32, 32, "lclk-gate", NULL, 0 }, /* LPC */
131 [ASPEED_CLK_GATE_ESPICLK] = { 33, -1, "espiclk-gate", NULL, 0 }, /* eSPI */
132 [ASPEED_CLK_GATE_REF1CLK] = { 34, -1, "ref1clk-gate", "clkin", CLK_IS_CRITICAL },
133 /* Reserved 35 */
134 [ASPEED_CLK_GATE_SDCLK] = { 36, 56, "sdclk-gate", NULL, 0 }, /* SDIO/SD */
135 [ASPEED_CLK_GATE_LHCCLK] = { 37, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */
136 /* Reserved 38 RSA: no longer used */
137 /* Reserved 39 */
138 [ASPEED_CLK_GATE_I3C0CLK] = { 40, 40, "i3c0clk-gate", "i3cclk", 0 }, /* I3C0 */
139 [ASPEED_CLK_GATE_I3C1CLK] = { 41, 41, "i3c1clk-gate", "i3cclk", 0 }, /* I3C1 */
140 [ASPEED_CLK_GATE_I3C2CLK] = { 42, 42, "i3c2clk-gate", "i3cclk", 0 }, /* I3C2 */
141 [ASPEED_CLK_GATE_I3C3CLK] = { 43, 43, "i3c3clk-gate", "i3cclk", 0 }, /* I3C3 */
142 [ASPEED_CLK_GATE_I3C4CLK] = { 44, 44, "i3c4clk-gate", "i3cclk", 0 }, /* I3C4 */
143 [ASPEED_CLK_GATE_I3C5CLK] = { 45, 45, "i3c5clk-gate", "i3cclk", 0 }, /* I3C5 */
144 /* Reserved: 46 & 47 */
145 [ASPEED_CLK_GATE_UART1CLK] = { 48, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */
146 [ASPEED_CLK_GATE_UART2CLK] = { 49, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */
147 [ASPEED_CLK_GATE_UART3CLK] = { 50, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */
148 [ASPEED_CLK_GATE_UART4CLK] = { 51, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */
149 [ASPEED_CLK_GATE_MAC3CLK] = { 52, 52, "mac3clk-gate", "mac34", 0 }, /* MAC3 */
150 [ASPEED_CLK_GATE_MAC4CLK] = { 53, 53, "mac4clk-gate", "mac34", 0 }, /* MAC4 */
151 [ASPEED_CLK_GATE_UART6CLK] = { 54, -1, "uart6clk-gate", "uartx", 0 }, /* UART6 */
152 [ASPEED_CLK_GATE_UART7CLK] = { 55, -1, "uart7clk-gate", "uartx", 0 }, /* UART7 */
153 [ASPEED_CLK_GATE_UART8CLK] = { 56, -1, "uart8clk-gate", "uartx", 0 }, /* UART8 */
154 [ASPEED_CLK_GATE_UART9CLK] = { 57, -1, "uart9clk-gate", "uartx", 0 }, /* UART9 */
155 [ASPEED_CLK_GATE_UART10CLK] = { 58, -1, "uart10clk-gate", "uartx", 0 }, /* UART10 */
156 [ASPEED_CLK_GATE_UART11CLK] = { 59, -1, "uart11clk-gate", "uartx", 0 }, /* UART11 */
157 [ASPEED_CLK_GATE_UART12CLK] = { 60, -1, "uart12clk-gate", "uartx", 0 }, /* UART12 */
158 [ASPEED_CLK_GATE_UART13CLK] = { 61, -1, "uart13clk-gate", "uartx", 0 }, /* UART13 */
159 [ASPEED_CLK_GATE_FSICLK] = { 62, 59, "fsiclk-gate", "fsiclk", 0 }, /* FSI */
160 };
161
162 static const struct clk_div_table ast2600_eclk_div_table[] = {
163 { 0x0, 2 },
164 { 0x1, 2 },
165 { 0x2, 3 },
166 { 0x3, 4 },
167 { 0x4, 5 },
168 { 0x5, 6 },
169 { 0x6, 7 },
170 { 0x7, 8 },
171 { 0 }
172 };
173
174 static const struct clk_div_table ast2600_emmc_extclk_div_table[] = {
175 { 0x0, 2 },
176 { 0x1, 4 },
177 { 0x2, 6 },
178 { 0x3, 8 },
179 { 0x4, 10 },
180 { 0x5, 12 },
181 { 0x6, 14 },
182 { 0x7, 16 },
183 { 0 }
184 };
185
186 static const struct clk_div_table ast2600_mac_div_table[] = {
187 { 0x0, 4 },
188 { 0x1, 4 },
189 { 0x2, 6 },
190 { 0x3, 8 },
191 { 0x4, 10 },
192 { 0x5, 12 },
193 { 0x6, 14 },
194 { 0x7, 16 },
195 { 0 }
196 };
197
198 static const struct clk_div_table ast2600_div_table[] = {
199 { 0x0, 4 },
200 { 0x1, 8 },
201 { 0x2, 12 },
202 { 0x3, 16 },
203 { 0x4, 20 },
204 { 0x5, 24 },
205 { 0x6, 28 },
206 { 0x7, 32 },
207 { 0 }
208 };
209
210 /* For hpll/dpll/epll/mpll */
ast2600_calc_pll(const char * name,u32 val)211 static struct clk_hw *ast2600_calc_pll(const char *name, u32 val)
212 {
213 unsigned int mult, div;
214
215 if (val & BIT(24)) {
216 /* Pass through mode */
217 mult = div = 1;
218 } else {
219 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */
220 u32 m = val & 0x1fff;
221 u32 n = (val >> 13) & 0x3f;
222 u32 p = (val >> 19) & 0xf;
223 mult = (m + 1) / (n + 1);
224 div = (p + 1);
225 }
226 return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
227 mult, div);
228 };
229
ast2600_calc_apll(const char * name,u32 val)230 static struct clk_hw *ast2600_calc_apll(const char *name, u32 val)
231 {
232 unsigned int mult, div;
233
234 if (soc_rev >= 2) {
235 if (val & BIT(24)) {
236 /* Pass through mode */
237 mult = div = 1;
238 } else {
239 /* F = 25Mhz * [(m + 1) / (n + 1)] / (p + 1) */
240 u32 m = val & 0x1fff;
241 u32 n = (val >> 13) & 0x3f;
242 u32 p = (val >> 19) & 0xf;
243
244 mult = (m + 1);
245 div = (n + 1) * (p + 1);
246 }
247 } else {
248 if (val & BIT(20)) {
249 /* Pass through mode */
250 mult = div = 1;
251 } else {
252 /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */
253 u32 m = (val >> 5) & 0x3f;
254 u32 od = (val >> 4) & 0x1;
255 u32 n = val & 0xf;
256
257 mult = (2 - od) * (m + 2);
258 div = n + 1;
259 }
260 }
261 return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
262 mult, div);
263 };
264
get_bit(u8 idx)265 static u32 get_bit(u8 idx)
266 {
267 return BIT(idx % 32);
268 }
269
get_reset_reg(struct aspeed_clk_gate * gate)270 static u32 get_reset_reg(struct aspeed_clk_gate *gate)
271 {
272 if (gate->reset_idx < 32)
273 return ASPEED_G6_RESET_CTRL;
274
275 return ASPEED_G6_RESET_CTRL2;
276 }
277
get_clock_reg(struct aspeed_clk_gate * gate)278 static u32 get_clock_reg(struct aspeed_clk_gate *gate)
279 {
280 if (gate->clock_idx < 32)
281 return ASPEED_G6_CLK_STOP_CTRL;
282
283 return ASPEED_G6_CLK_STOP_CTRL2;
284 }
285
aspeed_g6_clk_is_enabled(struct clk_hw * hw)286 static int aspeed_g6_clk_is_enabled(struct clk_hw *hw)
287 {
288 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
289 u32 clk = get_bit(gate->clock_idx);
290 u32 rst = get_bit(gate->reset_idx);
291 u32 reg;
292 u32 enval;
293
294 /*
295 * If the IP is in reset, treat the clock as not enabled,
296 * this happens with some clocks such as the USB one when
297 * coming from cold reset. Without this, aspeed_clk_enable()
298 * will fail to lift the reset.
299 */
300 if (gate->reset_idx >= 0) {
301 regmap_read(gate->map, get_reset_reg(gate), ®);
302
303 if (reg & rst)
304 return 0;
305 }
306
307 regmap_read(gate->map, get_clock_reg(gate), ®);
308
309 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
310
311 return ((reg & clk) == enval) ? 1 : 0;
312 }
313
aspeed_g6_clk_enable(struct clk_hw * hw)314 static int aspeed_g6_clk_enable(struct clk_hw *hw)
315 {
316 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
317 unsigned long flags;
318 u32 clk = get_bit(gate->clock_idx);
319 u32 rst = get_bit(gate->reset_idx);
320
321 spin_lock_irqsave(gate->lock, flags);
322
323 if (aspeed_g6_clk_is_enabled(hw)) {
324 spin_unlock_irqrestore(gate->lock, flags);
325 return 0;
326 }
327
328 if (gate->reset_idx >= 0) {
329 /* Put IP in reset */
330 regmap_write(gate->map, get_reset_reg(gate), rst);
331 /* Delay 100us */
332 udelay(100);
333 }
334
335 /* Enable clock */
336 if (gate->flags & CLK_GATE_SET_TO_DISABLE) {
337 /* Clock is clear to enable, so use set to clear register */
338 regmap_write(gate->map, get_clock_reg(gate) + 0x04, clk);
339 } else {
340 /* Clock is set to enable, so use write to set register */
341 regmap_write(gate->map, get_clock_reg(gate), clk);
342 }
343
344 if (gate->reset_idx >= 0) {
345 /* A delay of 10ms is specified by the ASPEED docs */
346 mdelay(10);
347 /* Take IP out of reset */
348 regmap_write(gate->map, get_reset_reg(gate) + 0x4, rst);
349 }
350
351 spin_unlock_irqrestore(gate->lock, flags);
352
353 return 0;
354 }
355
aspeed_g6_clk_disable(struct clk_hw * hw)356 static void aspeed_g6_clk_disable(struct clk_hw *hw)
357 {
358 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
359 unsigned long flags;
360 u32 clk = get_bit(gate->clock_idx);
361
362 spin_lock_irqsave(gate->lock, flags);
363
364 if (gate->flags & CLK_GATE_SET_TO_DISABLE) {
365 regmap_write(gate->map, get_clock_reg(gate), clk);
366 } else {
367 /* Use set to clear register */
368 regmap_write(gate->map, get_clock_reg(gate) + 0x4, clk);
369 }
370
371 spin_unlock_irqrestore(gate->lock, flags);
372 }
373
374 static const struct clk_ops aspeed_g6_clk_gate_ops = {
375 .enable = aspeed_g6_clk_enable,
376 .disable = aspeed_g6_clk_disable,
377 .is_enabled = aspeed_g6_clk_is_enabled,
378 };
379
aspeed_g6_reset_deassert(struct reset_controller_dev * rcdev,unsigned long id)380 static int aspeed_g6_reset_deassert(struct reset_controller_dev *rcdev,
381 unsigned long id)
382 {
383 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
384 u32 rst = get_bit(id);
385 u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
386
387 /* Use set to clear register */
388 return regmap_write(ar->map, reg + 0x04, rst);
389 }
390
aspeed_g6_reset_assert(struct reset_controller_dev * rcdev,unsigned long id)391 static int aspeed_g6_reset_assert(struct reset_controller_dev *rcdev,
392 unsigned long id)
393 {
394 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
395 u32 rst = get_bit(id);
396 u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
397
398 return regmap_write(ar->map, reg, rst);
399 }
400
aspeed_g6_reset_status(struct reset_controller_dev * rcdev,unsigned long id)401 static int aspeed_g6_reset_status(struct reset_controller_dev *rcdev,
402 unsigned long id)
403 {
404 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
405 int ret;
406 u32 val;
407 u32 rst = get_bit(id);
408 u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
409
410 ret = regmap_read(ar->map, reg, &val);
411 if (ret)
412 return ret;
413
414 return !!(val & rst);
415 }
416
417 static const struct reset_control_ops aspeed_g6_reset_ops = {
418 .assert = aspeed_g6_reset_assert,
419 .deassert = aspeed_g6_reset_deassert,
420 .status = aspeed_g6_reset_status,
421 };
422
aspeed_g6_clk_hw_register_gate(struct device * dev,const char * name,const char * parent_name,unsigned long flags,struct regmap * map,u8 clock_idx,u8 reset_idx,u8 clk_gate_flags,spinlock_t * lock)423 static struct clk_hw *aspeed_g6_clk_hw_register_gate(struct device *dev,
424 const char *name, const char *parent_name, unsigned long flags,
425 struct regmap *map, u8 clock_idx, u8 reset_idx,
426 u8 clk_gate_flags, spinlock_t *lock)
427 {
428 struct aspeed_clk_gate *gate;
429 struct clk_init_data init;
430 struct clk_hw *hw;
431 int ret;
432
433 gate = kzalloc_obj(*gate);
434 if (!gate)
435 return ERR_PTR(-ENOMEM);
436
437 init.name = name;
438 init.ops = &aspeed_g6_clk_gate_ops;
439 init.flags = flags;
440 init.parent_names = parent_name ? &parent_name : NULL;
441 init.num_parents = parent_name ? 1 : 0;
442
443 gate->map = map;
444 gate->clock_idx = clock_idx;
445 gate->reset_idx = reset_idx;
446 gate->flags = clk_gate_flags;
447 gate->lock = lock;
448 gate->hw.init = &init;
449
450 hw = &gate->hw;
451 ret = clk_hw_register(dev, hw);
452 if (ret) {
453 kfree(gate);
454 hw = ERR_PTR(ret);
455 }
456
457 return hw;
458 }
459
460 static const char *const emmc_extclk_parent_names[] = {
461 "emmc_extclk_hpll_in",
462 "mpll",
463 };
464
465 static const char * const vclk_parent_names[] = {
466 "dpll",
467 "d1pll",
468 "hclk",
469 "mclk",
470 };
471
472 static const char * const d1clk_parent_names[] = {
473 "dpll",
474 "epll",
475 "usb-phy-40m",
476 "gpioc6_clkin",
477 "dp_phy_pll",
478 };
479
aspeed_g6_clk_probe(struct platform_device * pdev)480 static int aspeed_g6_clk_probe(struct platform_device *pdev)
481 {
482 struct device *dev = &pdev->dev;
483 struct aspeed_reset *ar;
484 struct regmap *map;
485 struct clk_hw *hw;
486 u32 val, rate;
487 int i, ret;
488
489 map = syscon_node_to_regmap(dev->of_node);
490 if (IS_ERR(map)) {
491 dev_err(dev, "no syscon regmap\n");
492 return PTR_ERR(map);
493 }
494
495 ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL);
496 if (!ar)
497 return -ENOMEM;
498
499 ar->map = map;
500
501 ar->rcdev.owner = THIS_MODULE;
502 ar->rcdev.nr_resets = 64;
503 ar->rcdev.ops = &aspeed_g6_reset_ops;
504 ar->rcdev.of_node = dev->of_node;
505
506 ret = devm_reset_controller_register(dev, &ar->rcdev);
507 if (ret) {
508 dev_err(dev, "could not register reset controller\n");
509 return ret;
510 }
511
512 /* UART clock div13 setting */
513 regmap_read(map, ASPEED_G6_MISC_CTRL, &val);
514 if (val & UART_DIV13_EN)
515 rate = 24000000 / 13;
516 else
517 rate = 24000000;
518 hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate);
519 if (IS_ERR(hw))
520 return PTR_ERR(hw);
521 aspeed_g6_clk_data->hws[ASPEED_CLK_UART] = hw;
522
523 /* UART6~13 clock div13 setting */
524 regmap_read(map, 0x80, &val);
525 if (val & BIT(31))
526 rate = 24000000 / 13;
527 else
528 rate = 24000000;
529 hw = clk_hw_register_fixed_rate(dev, "uartx", NULL, 0, rate);
530 if (IS_ERR(hw))
531 return PTR_ERR(hw);
532 aspeed_g6_clk_data->hws[ASPEED_CLK_UARTX] = hw;
533
534 /* EMMC ext clock */
535 hw = clk_hw_register_fixed_factor(dev, "emmc_extclk_hpll_in", "hpll",
536 0, 1, 2);
537 if (IS_ERR(hw))
538 return PTR_ERR(hw);
539
540 hw = clk_hw_register_mux(dev, "emmc_extclk_mux",
541 emmc_extclk_parent_names,
542 ARRAY_SIZE(emmc_extclk_parent_names), 0,
543 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 11, 1,
544 0, &aspeed_g6_clk_lock);
545 if (IS_ERR(hw))
546 return PTR_ERR(hw);
547
548 hw = clk_hw_register_gate(dev, "emmc_extclk_gate", "emmc_extclk_mux",
549 0, scu_g6_base + ASPEED_G6_CLK_SELECTION1,
550 15, 0, &aspeed_g6_clk_lock);
551 if (IS_ERR(hw))
552 return PTR_ERR(hw);
553
554 hw = clk_hw_register_divider_table(dev, "emmc_extclk",
555 "emmc_extclk_gate", 0,
556 scu_g6_base +
557 ASPEED_G6_CLK_SELECTION1, 12,
558 3, 0, ast2600_emmc_extclk_div_table,
559 &aspeed_g6_clk_lock);
560 if (IS_ERR(hw))
561 return PTR_ERR(hw);
562 aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw;
563
564 /* SD/SDIO clock divider and gate */
565 hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0,
566 scu_g6_base + ASPEED_G6_CLK_SELECTION4, 31, 0,
567 &aspeed_g6_clk_lock);
568 if (IS_ERR(hw))
569 return PTR_ERR(hw);
570 hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate",
571 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0,
572 ast2600_div_table,
573 &aspeed_g6_clk_lock);
574 if (IS_ERR(hw))
575 return PTR_ERR(hw);
576 aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw;
577
578 /* MAC1/2 RMII 50MHz RCLK */
579 hw = clk_hw_register_fixed_rate(dev, "mac12rclk", "hpll", 0, 50000000);
580 if (IS_ERR(hw))
581 return PTR_ERR(hw);
582
583 /* MAC1/2 AHB bus clock divider */
584 hw = clk_hw_register_divider_table(dev, "mac12", "hpll", 0,
585 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 16, 3, 0,
586 ast2600_mac_div_table,
587 &aspeed_g6_clk_lock);
588 if (IS_ERR(hw))
589 return PTR_ERR(hw);
590 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC12] = hw;
591
592 /* RMII1 50MHz (RCLK) output enable */
593 hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0,
594 scu_g6_base + ASPEED_MAC12_CLK_DLY, 29, 0,
595 &aspeed_g6_clk_lock);
596 if (IS_ERR(hw))
597 return PTR_ERR(hw);
598 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC1RCLK] = hw;
599
600 /* RMII2 50MHz (RCLK) output enable */
601 hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0,
602 scu_g6_base + ASPEED_MAC12_CLK_DLY, 30, 0,
603 &aspeed_g6_clk_lock);
604 if (IS_ERR(hw))
605 return PTR_ERR(hw);
606 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC2RCLK] = hw;
607
608 /* MAC1/2 RMII 50MHz RCLK */
609 hw = clk_hw_register_fixed_rate(dev, "mac34rclk", "hclk", 0, 50000000);
610 if (IS_ERR(hw))
611 return PTR_ERR(hw);
612
613 /* MAC3/4 AHB bus clock divider */
614 hw = clk_hw_register_divider_table(dev, "mac34", "hpll", 0,
615 scu_g6_base + 0x310, 24, 3, 0,
616 ast2600_mac_div_table,
617 &aspeed_g6_clk_lock);
618 if (IS_ERR(hw))
619 return PTR_ERR(hw);
620 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC34] = hw;
621
622 /* RMII3 50MHz (RCLK) output enable */
623 hw = clk_hw_register_gate(dev, "mac3rclk", "mac34rclk", 0,
624 scu_g6_base + ASPEED_MAC34_CLK_DLY, 29, 0,
625 &aspeed_g6_clk_lock);
626 if (IS_ERR(hw))
627 return PTR_ERR(hw);
628 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC3RCLK] = hw;
629
630 /* RMII4 50MHz (RCLK) output enable */
631 hw = clk_hw_register_gate(dev, "mac4rclk", "mac34rclk", 0,
632 scu_g6_base + ASPEED_MAC34_CLK_DLY, 30, 0,
633 &aspeed_g6_clk_lock);
634 if (IS_ERR(hw))
635 return PTR_ERR(hw);
636 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC4RCLK] = hw;
637
638 /* LPC Host (LHCLK) clock divider */
639 hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
640 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
641 ast2600_div_table,
642 &aspeed_g6_clk_lock);
643 if (IS_ERR(hw))
644 return PTR_ERR(hw);
645 aspeed_g6_clk_data->hws[ASPEED_CLK_LHCLK] = hw;
646
647 /* gfx d1clk : use dp clk */
648 regmap_update_bits(map, ASPEED_G6_CLK_SELECTION1, GENMASK(10, 8), BIT(10));
649 /* SoC Display clock selection */
650 hw = clk_hw_register_mux(dev, "d1clk", d1clk_parent_names,
651 ARRAY_SIZE(d1clk_parent_names), 0,
652 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 8, 3, 0,
653 &aspeed_g6_clk_lock);
654 if (IS_ERR(hw))
655 return PTR_ERR(hw);
656 aspeed_g6_clk_data->hws[ASPEED_CLK_D1CLK] = hw;
657
658 /* d1 clk div 0x308[17:15] x [14:12] - 8,7,6,5,4,3,2,1 */
659 regmap_write(map, 0x308, 0x12000); /* 3x3 = 9 */
660
661 /* P-Bus (BCLK) clock divider */
662 hw = clk_hw_register_divider_table(dev, "bclk", "epll", 0,
663 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
664 ast2600_div_table,
665 &aspeed_g6_clk_lock);
666 if (IS_ERR(hw))
667 return PTR_ERR(hw);
668 aspeed_g6_clk_data->hws[ASPEED_CLK_BCLK] = hw;
669
670 /* Video Capture clock selection */
671 hw = clk_hw_register_mux(dev, "vclk", vclk_parent_names,
672 ARRAY_SIZE(vclk_parent_names), 0,
673 scu_g6_base + ASPEED_G6_CLK_SELECTION2, 12, 3, 0,
674 &aspeed_g6_clk_lock);
675 if (IS_ERR(hw))
676 return PTR_ERR(hw);
677 aspeed_g6_clk_data->hws[ASPEED_CLK_VCLK] = hw;
678
679 /* Video Engine clock divider */
680 hw = clk_hw_register_divider_table(dev, "eclk", NULL, 0,
681 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 28, 3, 0,
682 ast2600_eclk_div_table,
683 &aspeed_g6_clk_lock);
684 if (IS_ERR(hw))
685 return PTR_ERR(hw);
686 aspeed_g6_clk_data->hws[ASPEED_CLK_ECLK] = hw;
687
688 for (i = 0; i < ARRAY_SIZE(aspeed_g6_gates); i++) {
689 const struct aspeed_gate_data *gd = &aspeed_g6_gates[i];
690 u32 gate_flags;
691
692 if (!gd->name)
693 continue;
694
695 /*
696 * Special case: the USB port 1 clock (bit 14) is always
697 * working the opposite way from the other ones.
698 */
699 gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE;
700 hw = aspeed_g6_clk_hw_register_gate(dev,
701 gd->name,
702 gd->parent_name,
703 gd->flags,
704 map,
705 gd->clock_idx,
706 gd->reset_idx,
707 gate_flags,
708 &aspeed_g6_clk_lock);
709 if (IS_ERR(hw))
710 return PTR_ERR(hw);
711 aspeed_g6_clk_data->hws[i] = hw;
712 }
713
714 return 0;
715 };
716
717 static const struct of_device_id aspeed_g6_clk_dt_ids[] = {
718 { .compatible = "aspeed,ast2600-scu" },
719 { }
720 };
721
722 static struct platform_driver aspeed_g6_clk_driver = {
723 .probe = aspeed_g6_clk_probe,
724 .driver = {
725 .name = "ast2600-clk",
726 .of_match_table = aspeed_g6_clk_dt_ids,
727 .suppress_bind_attrs = true,
728 },
729 };
730 builtin_platform_driver(aspeed_g6_clk_driver);
731
732 static const u32 ast2600_a0_axi_ahb_div_table[] = {
733 2, 2, 3, 5,
734 };
735
736 static const u32 ast2600_a1_axi_ahb_div0_tbl[] = {
737 3, 2, 3, 4,
738 };
739
740 static const u32 ast2600_a1_axi_ahb_div1_tbl[] = {
741 3, 4, 6, 8,
742 };
743
744 static const u32 ast2600_a1_axi_ahb200_tbl[] = {
745 3, 4, 3, 4, 2, 2, 2, 2,
746 };
747
aspeed_g6_cc(struct regmap * map)748 static void __init aspeed_g6_cc(struct regmap *map)
749 {
750 struct clk_hw *hw;
751 u32 val, div, divbits, axi_div, ahb_div;
752
753 clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, 25000000);
754
755 /*
756 * High-speed PLL clock derived from the crystal. This the CPU clock,
757 * and we assume that it is enabled
758 */
759 regmap_read(map, ASPEED_HPLL_PARAM, &val);
760 aspeed_g6_clk_data->hws[ASPEED_CLK_HPLL] = ast2600_calc_pll("hpll", val);
761
762 regmap_read(map, ASPEED_MPLL_PARAM, &val);
763 aspeed_g6_clk_data->hws[ASPEED_CLK_MPLL] = ast2600_calc_pll("mpll", val);
764
765 regmap_read(map, ASPEED_DPLL_PARAM, &val);
766 aspeed_g6_clk_data->hws[ASPEED_CLK_DPLL] = ast2600_calc_pll("dpll", val);
767
768 regmap_read(map, ASPEED_EPLL_PARAM, &val);
769 aspeed_g6_clk_data->hws[ASPEED_CLK_EPLL] = ast2600_calc_pll("epll", val);
770
771 regmap_read(map, ASPEED_APLL_PARAM, &val);
772 aspeed_g6_clk_data->hws[ASPEED_CLK_APLL] = ast2600_calc_apll("apll", val);
773
774 /* Strap bits 12:11 define the AXI/AHB clock frequency ratio (aka HCLK)*/
775 regmap_read(map, ASPEED_G6_STRAP1, &val);
776 if (val & BIT(16))
777 axi_div = 1;
778 else
779 axi_div = 2;
780
781 divbits = (val >> 11) & 0x3;
782 if (soc_rev >= 1) {
783 if (!divbits) {
784 ahb_div = ast2600_a1_axi_ahb200_tbl[(val >> 8) & 0x3];
785 if (val & BIT(16))
786 ahb_div *= 2;
787 } else {
788 if (val & BIT(16))
789 ahb_div = ast2600_a1_axi_ahb_div1_tbl[divbits];
790 else
791 ahb_div = ast2600_a1_axi_ahb_div0_tbl[divbits];
792 }
793 } else {
794 ahb_div = ast2600_a0_axi_ahb_div_table[(val >> 11) & 0x3];
795 }
796
797 hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, axi_div * ahb_div);
798 aspeed_g6_clk_data->hws[ASPEED_CLK_AHB] = hw;
799
800 regmap_read(map, ASPEED_G6_CLK_SELECTION1, &val);
801 val = (val >> 23) & 0x7;
802 div = 4 * (val + 1);
803 hw = clk_hw_register_fixed_factor(NULL, "apb1", "hpll", 0, 1, div);
804 aspeed_g6_clk_data->hws[ASPEED_CLK_APB1] = hw;
805
806 regmap_read(map, ASPEED_G6_CLK_SELECTION4, &val);
807 val = (val >> 9) & 0x7;
808 div = 2 * (val + 1);
809 hw = clk_hw_register_fixed_factor(NULL, "apb2", "ahb", 0, 1, div);
810 aspeed_g6_clk_data->hws[ASPEED_CLK_APB2] = hw;
811
812 /* USB 2.0 port1 phy 40MHz clock */
813 hw = clk_hw_register_fixed_rate(NULL, "usb-phy-40m", NULL, 0, 40000000);
814 aspeed_g6_clk_data->hws[ASPEED_CLK_USBPHY_40M] = hw;
815
816 /* i3c clock: source from apll, divide by 8 */
817 regmap_update_bits(map, ASPEED_G6_CLK_SELECTION5,
818 I3C_CLK_SELECTION | APLL_DIV_SELECTION,
819 I3C_CLK_SELECT_APLL_DIV | APLL_DIV_8);
820
821 hw = clk_hw_register_fixed_factor(NULL, "i3cclk", "apll", 0, 1, 8);
822 aspeed_g6_clk_data->hws[ASPEED_CLK_I3C] = hw;
823
824 hw = clk_hw_register_fixed_factor(NULL, "fsiclk", "apll", 0, 1, 4);
825 aspeed_g6_clk_data->hws[ASPEED_CLK_FSI] = hw;
826 };
827
aspeed_g6_cc_init(struct device_node * np)828 static void __init aspeed_g6_cc_init(struct device_node *np)
829 {
830 struct regmap *map;
831 int ret;
832 int i;
833
834 scu_g6_base = of_iomap(np, 0);
835 if (!scu_g6_base)
836 return;
837
838 soc_rev = (readl(scu_g6_base + ASPEED_G6_SILICON_REV) & CHIP_REVISION_ID) >> 16;
839
840 aspeed_g6_clk_data = kzalloc_flex(*aspeed_g6_clk_data, hws,
841 ASPEED_G6_NUM_CLKS);
842 if (!aspeed_g6_clk_data)
843 return;
844 aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS;
845
846 /*
847 * This way all clocks fetched before the platform device probes,
848 * except those we assign here for early use, will be deferred.
849 */
850 for (i = 0; i < ASPEED_G6_NUM_CLKS; i++)
851 aspeed_g6_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
852
853 /*
854 * We check that the regmap works on this very first access,
855 * but as this is an MMIO-backed regmap, subsequent regmap
856 * access is not going to fail and we skip error checks from
857 * this point.
858 */
859 map = syscon_node_to_regmap(np);
860 if (IS_ERR(map)) {
861 pr_err("no syscon regmap\n");
862 return;
863 }
864
865 aspeed_g6_cc(map);
866 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_g6_clk_data);
867 if (ret)
868 pr_err("failed to add DT provider: %d\n", ret);
869 };
870 CLK_OF_DECLARE_DRIVER(aspeed_cc_g6, "aspeed,ast2600-scu", aspeed_g6_cc_init);
871