1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Bitmain BM1880 SoC clock driver
4 *
5 * Copyright (c) 2019 Linaro Ltd.
6 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
7 */
8
9 #include <linux/clk-provider.h>
10 #include <linux/io.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/slab.h>
15
16 #include <dt-bindings/clock/bm1880-clock.h>
17
18 #define BM1880_CLK_MPLL_CTL 0x00
19 #define BM1880_CLK_SPLL_CTL 0x04
20 #define BM1880_CLK_FPLL_CTL 0x08
21 #define BM1880_CLK_DDRPLL_CTL 0x0c
22
23 #define BM1880_CLK_ENABLE0 0x00
24 #define BM1880_CLK_ENABLE1 0x04
25 #define BM1880_CLK_SELECT 0x20
26 #define BM1880_CLK_DIV0 0x40
27 #define BM1880_CLK_DIV1 0x44
28 #define BM1880_CLK_DIV2 0x48
29 #define BM1880_CLK_DIV3 0x4c
30 #define BM1880_CLK_DIV4 0x50
31 #define BM1880_CLK_DIV5 0x54
32 #define BM1880_CLK_DIV6 0x58
33 #define BM1880_CLK_DIV7 0x5c
34 #define BM1880_CLK_DIV8 0x60
35 #define BM1880_CLK_DIV9 0x64
36 #define BM1880_CLK_DIV10 0x68
37 #define BM1880_CLK_DIV11 0x6c
38 #define BM1880_CLK_DIV12 0x70
39 #define BM1880_CLK_DIV13 0x74
40 #define BM1880_CLK_DIV14 0x78
41 #define BM1880_CLK_DIV15 0x7c
42 #define BM1880_CLK_DIV16 0x80
43 #define BM1880_CLK_DIV17 0x84
44 #define BM1880_CLK_DIV18 0x88
45 #define BM1880_CLK_DIV19 0x8c
46 #define BM1880_CLK_DIV20 0x90
47 #define BM1880_CLK_DIV21 0x94
48 #define BM1880_CLK_DIV22 0x98
49 #define BM1880_CLK_DIV23 0x9c
50 #define BM1880_CLK_DIV24 0xa0
51 #define BM1880_CLK_DIV25 0xa4
52 #define BM1880_CLK_DIV26 0xa8
53 #define BM1880_CLK_DIV27 0xac
54 #define BM1880_CLK_DIV28 0xb0
55
56 #define to_bm1880_pll_clk(_hw) container_of(_hw, struct bm1880_pll_hw_clock, hw)
57 #define to_bm1880_div_clk(_hw) container_of(_hw, struct bm1880_div_hw_clock, hw)
58
59 static DEFINE_SPINLOCK(bm1880_clk_lock);
60
61 struct bm1880_clock_data {
62 void __iomem *pll_base;
63 void __iomem *sys_base;
64 struct clk_hw_onecell_data hw_data;
65 };
66
67 struct bm1880_gate_clock {
68 unsigned int id;
69 const char *name;
70 const char *parent;
71 u32 gate_reg;
72 s8 gate_shift;
73 unsigned long flags;
74 };
75
76 struct bm1880_mux_clock {
77 unsigned int id;
78 const char *name;
79 const char * const *parents;
80 s8 num_parents;
81 u32 reg;
82 s8 shift;
83 unsigned long flags;
84 };
85
86 struct bm1880_div_clock {
87 unsigned int id;
88 const char *name;
89 u32 reg;
90 u8 shift;
91 u8 width;
92 u32 initval;
93 const struct clk_div_table *table;
94 unsigned long flags;
95 };
96
97 struct bm1880_div_hw_clock {
98 struct bm1880_div_clock div;
99 void __iomem *base;
100 spinlock_t *lock;
101 struct clk_hw hw;
102 struct clk_init_data init;
103 };
104
105 struct bm1880_composite_clock {
106 unsigned int id;
107 const char *name;
108 const char *parent;
109 const char * const *parents;
110 unsigned int num_parents;
111 unsigned long flags;
112
113 u32 gate_reg;
114 u32 mux_reg;
115 u32 div_reg;
116
117 s8 gate_shift;
118 s8 mux_shift;
119 s8 div_shift;
120 s8 div_width;
121 s16 div_initval;
122 const struct clk_div_table *table;
123 };
124
125 struct bm1880_pll_clock {
126 unsigned int id;
127 const char *name;
128 u32 reg;
129 unsigned long flags;
130 };
131
132 struct bm1880_pll_hw_clock {
133 struct bm1880_pll_clock pll;
134 void __iomem *base;
135 struct clk_hw hw;
136 struct clk_init_data init;
137 };
138
139 static const struct clk_ops bm1880_pll_ops;
140 static const struct clk_ops bm1880_clk_div_ops;
141
142 #define GATE_DIV(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \
143 _div_shift, _div_width, _div_initval, _table, \
144 _flags) { \
145 .id = _id, \
146 .parent = _parent, \
147 .name = _name, \
148 .gate_reg = _gate_reg, \
149 .gate_shift = _gate_shift, \
150 .div_reg = _div_reg, \
151 .div_shift = _div_shift, \
152 .div_width = _div_width, \
153 .div_initval = _div_initval, \
154 .table = _table, \
155 .mux_shift = -1, \
156 .flags = _flags, \
157 }
158
159 #define GATE_MUX(_id, _name, _parents, _gate_reg, _gate_shift, \
160 _mux_reg, _mux_shift, _flags) { \
161 .id = _id, \
162 .parents = _parents, \
163 .num_parents = ARRAY_SIZE(_parents), \
164 .name = _name, \
165 .gate_reg = _gate_reg, \
166 .gate_shift = _gate_shift, \
167 .div_shift = -1, \
168 .mux_reg = _mux_reg, \
169 .mux_shift = _mux_shift, \
170 .flags = _flags, \
171 }
172
173 #define CLK_PLL(_id, _name, _parent, _reg, _flags) { \
174 .pll.id = _id, \
175 .pll.name = _name, \
176 .pll.reg = _reg, \
177 .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, \
178 &bm1880_pll_ops, \
179 _flags), \
180 }
181
182 #define CLK_DIV(_id, _name, _parent, _reg, _shift, _width, _initval, \
183 _table, _flags) { \
184 .div.id = _id, \
185 .div.name = _name, \
186 .div.reg = _reg, \
187 .div.shift = _shift, \
188 .div.width = _width, \
189 .div.initval = _initval, \
190 .div.table = _table, \
191 .hw.init = CLK_HW_INIT_HW(_name, _parent, \
192 &bm1880_clk_div_ops, \
193 _flags), \
194 }
195
196 static struct clk_parent_data bm1880_pll_parent[] = {
197 { .fw_name = "osc", .name = "osc" },
198 };
199
200 /*
201 * All PLL clocks are marked as CRITICAL, hence they are very crucial
202 * for the functioning of the SoC
203 */
204 static struct bm1880_pll_hw_clock bm1880_pll_clks[] = {
205 CLK_PLL(BM1880_CLK_MPLL, "clk_mpll", bm1880_pll_parent,
206 BM1880_CLK_MPLL_CTL, 0),
207 CLK_PLL(BM1880_CLK_SPLL, "clk_spll", bm1880_pll_parent,
208 BM1880_CLK_SPLL_CTL, 0),
209 CLK_PLL(BM1880_CLK_FPLL, "clk_fpll", bm1880_pll_parent,
210 BM1880_CLK_FPLL_CTL, 0),
211 CLK_PLL(BM1880_CLK_DDRPLL, "clk_ddrpll", bm1880_pll_parent,
212 BM1880_CLK_DDRPLL_CTL, 0),
213 };
214
215 /*
216 * Clocks marked as CRITICAL are needed for the proper functioning
217 * of the SoC.
218 */
219 static const struct bm1880_gate_clock bm1880_gate_clks[] = {
220 { BM1880_CLK_AHB_ROM, "clk_ahb_rom", "clk_mux_axi6",
221 BM1880_CLK_ENABLE0, 2, 0 },
222 { BM1880_CLK_AXI_SRAM, "clk_axi_sram", "clk_axi1",
223 BM1880_CLK_ENABLE0, 3, 0 },
224 /*
225 * Since this clock is sourcing the DDR memory, let's mark it as
226 * critical to avoid gating.
227 */
228 { BM1880_CLK_DDR_AXI, "clk_ddr_axi", "clk_mux_axi6",
229 BM1880_CLK_ENABLE0, 4, CLK_IS_CRITICAL },
230 { BM1880_CLK_APB_EFUSE, "clk_apb_efuse", "clk_mux_axi6",
231 BM1880_CLK_ENABLE0, 6, 0 },
232 { BM1880_CLK_AXI5_EMMC, "clk_axi5_emmc", "clk_axi5",
233 BM1880_CLK_ENABLE0, 7, 0 },
234 { BM1880_CLK_AXI5_SD, "clk_axi5_sd", "clk_axi5",
235 BM1880_CLK_ENABLE0, 10, 0 },
236 { BM1880_CLK_AXI4_ETH0, "clk_axi4_eth0", "clk_axi4",
237 BM1880_CLK_ENABLE0, 14, 0 },
238 { BM1880_CLK_AXI4_ETH1, "clk_axi4_eth1", "clk_axi4",
239 BM1880_CLK_ENABLE0, 16, 0 },
240 { BM1880_CLK_AXI1_GDMA, "clk_axi1_gdma", "clk_axi1",
241 BM1880_CLK_ENABLE0, 17, 0 },
242 /* Don't gate GPIO clocks as it is not owned by the GPIO driver */
243 { BM1880_CLK_APB_GPIO, "clk_apb_gpio", "clk_mux_axi6",
244 BM1880_CLK_ENABLE0, 18, CLK_IGNORE_UNUSED },
245 { BM1880_CLK_APB_GPIO_INTR, "clk_apb_gpio_intr", "clk_mux_axi6",
246 BM1880_CLK_ENABLE0, 19, CLK_IGNORE_UNUSED },
247 { BM1880_CLK_AXI1_MINER, "clk_axi1_miner", "clk_axi1",
248 BM1880_CLK_ENABLE0, 21, 0 },
249 { BM1880_CLK_AHB_SF, "clk_ahb_sf", "clk_mux_axi6",
250 BM1880_CLK_ENABLE0, 22, 0 },
251 /*
252 * Not sure which module this clock is sourcing but gating this clock
253 * prevents the system from booting. So, let's mark it as critical.
254 */
255 { BM1880_CLK_SDMA_AXI, "clk_sdma_axi", "clk_axi5",
256 BM1880_CLK_ENABLE0, 23, CLK_IS_CRITICAL },
257 { BM1880_CLK_APB_I2C, "clk_apb_i2c", "clk_mux_axi6",
258 BM1880_CLK_ENABLE0, 25, 0 },
259 { BM1880_CLK_APB_WDT, "clk_apb_wdt", "clk_mux_axi6",
260 BM1880_CLK_ENABLE0, 26, 0 },
261 { BM1880_CLK_APB_JPEG, "clk_apb_jpeg", "clk_axi6",
262 BM1880_CLK_ENABLE0, 27, 0 },
263 { BM1880_CLK_AXI5_NF, "clk_axi5_nf", "clk_axi5",
264 BM1880_CLK_ENABLE0, 29, 0 },
265 { BM1880_CLK_APB_NF, "clk_apb_nf", "clk_axi6",
266 BM1880_CLK_ENABLE0, 30, 0 },
267 { BM1880_CLK_APB_PWM, "clk_apb_pwm", "clk_mux_axi6",
268 BM1880_CLK_ENABLE1, 0, 0 },
269 { BM1880_CLK_RV, "clk_rv", "clk_mux_rv",
270 BM1880_CLK_ENABLE1, 1, 0 },
271 { BM1880_CLK_APB_SPI, "clk_apb_spi", "clk_mux_axi6",
272 BM1880_CLK_ENABLE1, 2, 0 },
273 { BM1880_CLK_UART_500M, "clk_uart_500m", "clk_div_uart_500m",
274 BM1880_CLK_ENABLE1, 4, 0 },
275 { BM1880_CLK_APB_UART, "clk_apb_uart", "clk_axi6",
276 BM1880_CLK_ENABLE1, 5, 0 },
277 { BM1880_CLK_APB_I2S, "clk_apb_i2s", "clk_axi6",
278 BM1880_CLK_ENABLE1, 6, 0 },
279 { BM1880_CLK_AXI4_USB, "clk_axi4_usb", "clk_axi4",
280 BM1880_CLK_ENABLE1, 7, 0 },
281 { BM1880_CLK_APB_USB, "clk_apb_usb", "clk_axi6",
282 BM1880_CLK_ENABLE1, 8, 0 },
283 { BM1880_CLK_12M_USB, "clk_12m_usb", "clk_div_12m_usb",
284 BM1880_CLK_ENABLE1, 11, 0 },
285 { BM1880_CLK_APB_VIDEO, "clk_apb_video", "clk_axi6",
286 BM1880_CLK_ENABLE1, 12, 0 },
287 { BM1880_CLK_APB_VPP, "clk_apb_vpp", "clk_axi6",
288 BM1880_CLK_ENABLE1, 15, 0 },
289 { BM1880_CLK_AXI6, "clk_axi6", "clk_mux_axi6",
290 BM1880_CLK_ENABLE1, 21, 0 },
291 };
292
293 static const char * const clk_a53_parents[] = { "clk_spll", "clk_mpll" };
294 static const char * const clk_rv_parents[] = { "clk_div_1_rv", "clk_div_0_rv" };
295 static const char * const clk_axi1_parents[] = { "clk_div_1_axi1", "clk_div_0_axi1" };
296 static const char * const clk_axi6_parents[] = { "clk_div_1_axi6", "clk_div_0_axi6" };
297
298 static const struct bm1880_mux_clock bm1880_mux_clks[] = {
299 { BM1880_CLK_MUX_RV, "clk_mux_rv", clk_rv_parents, 2,
300 BM1880_CLK_SELECT, 1, 0 },
301 { BM1880_CLK_MUX_AXI6, "clk_mux_axi6", clk_axi6_parents, 2,
302 BM1880_CLK_SELECT, 3, 0 },
303 };
304
305 static const struct clk_div_table bm1880_div_table_0[] = {
306 { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
307 { 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 },
308 { 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 },
309 { 12, 13 }, { 13, 14 }, { 14, 15 }, { 15, 16 },
310 { 16, 17 }, { 17, 18 }, { 18, 19 }, { 19, 20 },
311 { 20, 21 }, { 21, 22 }, { 22, 23 }, { 23, 24 },
312 { 24, 25 }, { 25, 26 }, { 26, 27 }, { 27, 28 },
313 { 28, 29 }, { 29, 30 }, { 30, 31 }, { 31, 32 },
314 { 0, 0 }
315 };
316
317 static const struct clk_div_table bm1880_div_table_1[] = {
318 { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
319 { 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 },
320 { 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 },
321 { 12, 13 }, { 13, 14 }, { 14, 15 }, { 15, 16 },
322 { 16, 17 }, { 17, 18 }, { 18, 19 }, { 19, 20 },
323 { 20, 21 }, { 21, 22 }, { 22, 23 }, { 23, 24 },
324 { 24, 25 }, { 25, 26 }, { 26, 27 }, { 27, 28 },
325 { 28, 29 }, { 29, 30 }, { 30, 31 }, { 31, 32 },
326 { 127, 128 }, { 0, 0 }
327 };
328
329 static const struct clk_div_table bm1880_div_table_2[] = {
330 { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
331 { 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 },
332 { 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 },
333 { 12, 13 }, { 13, 14 }, { 14, 15 }, { 15, 16 },
334 { 16, 17 }, { 17, 18 }, { 18, 19 }, { 19, 20 },
335 { 20, 21 }, { 21, 22 }, { 22, 23 }, { 23, 24 },
336 { 24, 25 }, { 25, 26 }, { 26, 27 }, { 27, 28 },
337 { 28, 29 }, { 29, 30 }, { 30, 31 }, { 31, 32 },
338 { 127, 128 }, { 255, 256 }, { 0, 0 }
339 };
340
341 static const struct clk_div_table bm1880_div_table_3[] = {
342 { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
343 { 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 },
344 { 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 },
345 { 12, 13 }, { 13, 14 }, { 14, 15 }, { 15, 16 },
346 { 16, 17 }, { 17, 18 }, { 18, 19 }, { 19, 20 },
347 { 20, 21 }, { 21, 22 }, { 22, 23 }, { 23, 24 },
348 { 24, 25 }, { 25, 26 }, { 26, 27 }, { 27, 28 },
349 { 28, 29 }, { 29, 30 }, { 30, 31 }, { 31, 32 },
350 { 127, 128 }, { 255, 256 }, { 511, 512 }, { 0, 0 }
351 };
352
353 static const struct clk_div_table bm1880_div_table_4[] = {
354 { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
355 { 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 },
356 { 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 },
357 { 12, 13 }, { 13, 14 }, { 14, 15 }, { 15, 16 },
358 { 16, 17 }, { 17, 18 }, { 18, 19 }, { 19, 20 },
359 { 20, 21 }, { 21, 22 }, { 22, 23 }, { 23, 24 },
360 { 24, 25 }, { 25, 26 }, { 26, 27 }, { 27, 28 },
361 { 28, 29 }, { 29, 30 }, { 30, 31 }, { 31, 32 },
362 { 127, 128 }, { 255, 256 }, { 511, 512 }, { 65535, 65536 },
363 { 0, 0 }
364 };
365
366 /*
367 * Clocks marked as CRITICAL are needed for the proper functioning
368 * of the SoC.
369 */
370 static struct bm1880_div_hw_clock bm1880_div_clks[] = {
371 CLK_DIV(BM1880_CLK_DIV_0_RV, "clk_div_0_rv", &bm1880_pll_clks[1].hw,
372 BM1880_CLK_DIV12, 16, 5, 1, bm1880_div_table_0, 0),
373 CLK_DIV(BM1880_CLK_DIV_1_RV, "clk_div_1_rv", &bm1880_pll_clks[2].hw,
374 BM1880_CLK_DIV13, 16, 5, 1, bm1880_div_table_0, 0),
375 CLK_DIV(BM1880_CLK_DIV_UART_500M, "clk_div_uart_500m", &bm1880_pll_clks[2].hw,
376 BM1880_CLK_DIV15, 16, 7, 3, bm1880_div_table_1, 0),
377 CLK_DIV(BM1880_CLK_DIV_0_AXI1, "clk_div_0_axi1", &bm1880_pll_clks[0].hw,
378 BM1880_CLK_DIV21, 16, 5, 2, bm1880_div_table_0,
379 0),
380 CLK_DIV(BM1880_CLK_DIV_1_AXI1, "clk_div_1_axi1", &bm1880_pll_clks[2].hw,
381 BM1880_CLK_DIV22, 16, 5, 3, bm1880_div_table_0,
382 0),
383 CLK_DIV(BM1880_CLK_DIV_0_AXI6, "clk_div_0_axi6", &bm1880_pll_clks[2].hw,
384 BM1880_CLK_DIV27, 16, 5, 15, bm1880_div_table_0,
385 0),
386 CLK_DIV(BM1880_CLK_DIV_1_AXI6, "clk_div_1_axi6", &bm1880_pll_clks[0].hw,
387 BM1880_CLK_DIV28, 16, 5, 11, bm1880_div_table_0,
388 0),
389 CLK_DIV(BM1880_CLK_DIV_12M_USB, "clk_div_12m_usb", &bm1880_pll_clks[2].hw,
390 BM1880_CLK_DIV18, 16, 7, 125, bm1880_div_table_1, 0),
391 };
392
393 /*
394 * Clocks marked as CRITICAL are all needed for the proper functioning
395 * of the SoC.
396 */
397 static struct bm1880_composite_clock bm1880_composite_clks[] = {
398 /*
399 * Since clk_a53 and clk_50m_a53 clocks are sourcing the CPU core,
400 * let's mark them as critical to avoid gating.
401 */
402 GATE_MUX(BM1880_CLK_A53, "clk_a53", clk_a53_parents,
403 BM1880_CLK_ENABLE0, 0, BM1880_CLK_SELECT, 0,
404 CLK_IS_CRITICAL),
405 GATE_DIV(BM1880_CLK_50M_A53, "clk_50m_a53", "clk_fpll",
406 BM1880_CLK_ENABLE0, 1, BM1880_CLK_DIV0, 16, 5, 30,
407 bm1880_div_table_0, CLK_IS_CRITICAL),
408 GATE_DIV(BM1880_CLK_EFUSE, "clk_efuse", "clk_fpll",
409 BM1880_CLK_ENABLE0, 5, BM1880_CLK_DIV1, 16, 7, 60,
410 bm1880_div_table_1, 0),
411 GATE_DIV(BM1880_CLK_EMMC, "clk_emmc", "clk_fpll",
412 BM1880_CLK_ENABLE0, 8, BM1880_CLK_DIV2, 16, 5, 15,
413 bm1880_div_table_0, 0),
414 GATE_DIV(BM1880_CLK_100K_EMMC, "clk_100k_emmc", "clk_div_12m_usb",
415 BM1880_CLK_ENABLE0, 9, BM1880_CLK_DIV3, 16, 8, 120,
416 bm1880_div_table_2, 0),
417 GATE_DIV(BM1880_CLK_SD, "clk_sd", "clk_fpll",
418 BM1880_CLK_ENABLE0, 11, BM1880_CLK_DIV4, 16, 5, 15,
419 bm1880_div_table_0, 0),
420 GATE_DIV(BM1880_CLK_100K_SD, "clk_100k_sd", "clk_div_12m_usb",
421 BM1880_CLK_ENABLE0, 12, BM1880_CLK_DIV5, 16, 8, 120,
422 bm1880_div_table_2, 0),
423 GATE_DIV(BM1880_CLK_500M_ETH0, "clk_500m_eth0", "clk_fpll",
424 BM1880_CLK_ENABLE0, 13, BM1880_CLK_DIV6, 16, 5, 3,
425 bm1880_div_table_0, 0),
426 GATE_DIV(BM1880_CLK_500M_ETH1, "clk_500m_eth1", "clk_fpll",
427 BM1880_CLK_ENABLE0, 15, BM1880_CLK_DIV7, 16, 5, 3,
428 bm1880_div_table_0, 0),
429 /* Don't gate GPIO clocks as it is not owned by the GPIO driver */
430 GATE_DIV(BM1880_CLK_GPIO_DB, "clk_gpio_db", "clk_div_12m_usb",
431 BM1880_CLK_ENABLE0, 20, BM1880_CLK_DIV8, 16, 16, 120,
432 bm1880_div_table_4, CLK_IGNORE_UNUSED),
433 GATE_DIV(BM1880_CLK_SDMA_AUD, "clk_sdma_aud", "clk_fpll",
434 BM1880_CLK_ENABLE0, 24, BM1880_CLK_DIV9, 16, 7, 61,
435 bm1880_div_table_1, 0),
436 GATE_DIV(BM1880_CLK_JPEG_AXI, "clk_jpeg_axi", "clk_fpll",
437 BM1880_CLK_ENABLE0, 28, BM1880_CLK_DIV10, 16, 5, 4,
438 bm1880_div_table_0, 0),
439 GATE_DIV(BM1880_CLK_NF, "clk_nf", "clk_fpll",
440 BM1880_CLK_ENABLE0, 31, BM1880_CLK_DIV11, 16, 5, 30,
441 bm1880_div_table_0, 0),
442 GATE_DIV(BM1880_CLK_TPU_AXI, "clk_tpu_axi", "clk_spll",
443 BM1880_CLK_ENABLE1, 3, BM1880_CLK_DIV14, 16, 5, 1,
444 bm1880_div_table_0, 0),
445 GATE_DIV(BM1880_CLK_125M_USB, "clk_125m_usb", "clk_fpll",
446 BM1880_CLK_ENABLE1, 9, BM1880_CLK_DIV16, 16, 5, 12,
447 bm1880_div_table_0, 0),
448 GATE_DIV(BM1880_CLK_33K_USB, "clk_33k_usb", "clk_div_12m_usb",
449 BM1880_CLK_ENABLE1, 10, BM1880_CLK_DIV17, 16, 9, 363,
450 bm1880_div_table_3, 0),
451 GATE_DIV(BM1880_CLK_VIDEO_AXI, "clk_video_axi", "clk_fpll",
452 BM1880_CLK_ENABLE1, 13, BM1880_CLK_DIV19, 16, 5, 4,
453 bm1880_div_table_0, 0),
454 GATE_DIV(BM1880_CLK_VPP_AXI, "clk_vpp_axi", "clk_fpll",
455 BM1880_CLK_ENABLE1, 14, BM1880_CLK_DIV20, 16, 5, 4,
456 bm1880_div_table_0, 0),
457 GATE_MUX(BM1880_CLK_AXI1, "clk_axi1", clk_axi1_parents,
458 BM1880_CLK_ENABLE1, 15, BM1880_CLK_SELECT, 2, 0),
459 GATE_DIV(BM1880_CLK_AXI2, "clk_axi2", "clk_fpll",
460 BM1880_CLK_ENABLE1, 17, BM1880_CLK_DIV23, 16, 5, 3,
461 bm1880_div_table_0, 0),
462 GATE_DIV(BM1880_CLK_AXI3, "clk_axi3", "clk_mux_rv",
463 BM1880_CLK_ENABLE1, 18, BM1880_CLK_DIV24, 16, 5, 2,
464 bm1880_div_table_0, 0),
465 GATE_DIV(BM1880_CLK_AXI4, "clk_axi4", "clk_fpll",
466 BM1880_CLK_ENABLE1, 19, BM1880_CLK_DIV25, 16, 5, 6,
467 bm1880_div_table_0, 0),
468 GATE_DIV(BM1880_CLK_AXI5, "clk_axi5", "clk_fpll",
469 BM1880_CLK_ENABLE1, 20, BM1880_CLK_DIV26, 16, 5, 15,
470 bm1880_div_table_0, 0),
471 };
472
bm1880_pll_rate_calc(u32 regval,unsigned long parent_rate)473 static unsigned long bm1880_pll_rate_calc(u32 regval, unsigned long parent_rate)
474 {
475 u64 numerator;
476 u32 fbdiv, refdiv;
477 u32 postdiv1, postdiv2, denominator;
478
479 fbdiv = (regval >> 16) & 0xfff;
480 refdiv = regval & 0x1f;
481 postdiv1 = (regval >> 8) & 0x7;
482 postdiv2 = (regval >> 12) & 0x7;
483
484 numerator = parent_rate * fbdiv;
485 denominator = refdiv * postdiv1 * postdiv2;
486 do_div(numerator, denominator);
487
488 return (unsigned long)numerator;
489 }
490
bm1880_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)491 static unsigned long bm1880_pll_recalc_rate(struct clk_hw *hw,
492 unsigned long parent_rate)
493 {
494 struct bm1880_pll_hw_clock *pll_hw = to_bm1880_pll_clk(hw);
495 unsigned long rate;
496 u32 regval;
497
498 regval = readl(pll_hw->base + pll_hw->pll.reg);
499 rate = bm1880_pll_rate_calc(regval, parent_rate);
500
501 return rate;
502 }
503
504 static const struct clk_ops bm1880_pll_ops = {
505 .recalc_rate = bm1880_pll_recalc_rate,
506 };
507
bm1880_clk_register_pll(struct bm1880_pll_hw_clock * pll_clk,void __iomem * sys_base)508 static struct clk_hw *bm1880_clk_register_pll(struct bm1880_pll_hw_clock *pll_clk,
509 void __iomem *sys_base)
510 {
511 struct clk_hw *hw;
512 int err;
513
514 pll_clk->base = sys_base;
515 hw = &pll_clk->hw;
516
517 err = clk_hw_register(NULL, hw);
518 if (err)
519 return ERR_PTR(err);
520
521 return hw;
522 }
523
bm1880_clk_register_plls(struct bm1880_pll_hw_clock * clks,int num_clks,struct bm1880_clock_data * data)524 static int bm1880_clk_register_plls(struct bm1880_pll_hw_clock *clks,
525 int num_clks,
526 struct bm1880_clock_data *data)
527 {
528 struct clk_hw *hw;
529 void __iomem *pll_base = data->pll_base;
530 int i;
531
532 for (i = 0; i < num_clks; i++) {
533 struct bm1880_pll_hw_clock *bm1880_clk = &clks[i];
534
535 hw = bm1880_clk_register_pll(bm1880_clk, pll_base);
536 if (IS_ERR(hw)) {
537 pr_err("%s: failed to register clock %s\n",
538 __func__, bm1880_clk->pll.name);
539 goto err_clk;
540 }
541
542 data->hw_data.hws[clks[i].pll.id] = hw;
543 }
544
545 return 0;
546
547 err_clk:
548 while (i--)
549 clk_hw_unregister(data->hw_data.hws[clks[i].pll.id]);
550
551 return PTR_ERR(hw);
552 }
553
bm1880_clk_register_mux(const struct bm1880_mux_clock * clks,int num_clks,struct bm1880_clock_data * data)554 static int bm1880_clk_register_mux(const struct bm1880_mux_clock *clks,
555 int num_clks,
556 struct bm1880_clock_data *data)
557 {
558 struct clk_hw *hw;
559 void __iomem *sys_base = data->sys_base;
560 int i;
561
562 for (i = 0; i < num_clks; i++) {
563 hw = clk_hw_register_mux(NULL, clks[i].name,
564 clks[i].parents,
565 clks[i].num_parents,
566 clks[i].flags,
567 sys_base + clks[i].reg,
568 clks[i].shift, 1, 0,
569 &bm1880_clk_lock);
570 if (IS_ERR(hw)) {
571 pr_err("%s: failed to register clock %s\n",
572 __func__, clks[i].name);
573 goto err_clk;
574 }
575
576 data->hw_data.hws[clks[i].id] = hw;
577 }
578
579 return 0;
580
581 err_clk:
582 while (i--)
583 clk_hw_unregister_mux(data->hw_data.hws[clks[i].id]);
584
585 return PTR_ERR(hw);
586 }
587
bm1880_clk_div_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)588 static unsigned long bm1880_clk_div_recalc_rate(struct clk_hw *hw,
589 unsigned long parent_rate)
590 {
591 struct bm1880_div_hw_clock *div_hw = to_bm1880_div_clk(hw);
592 struct bm1880_div_clock *div = &div_hw->div;
593 void __iomem *reg_addr = div_hw->base + div->reg;
594 unsigned int val;
595 unsigned long rate;
596
597 if (!(readl(reg_addr) & BIT(3))) {
598 val = div->initval;
599 } else {
600 val = readl(reg_addr) >> div->shift;
601 val &= clk_div_mask(div->width);
602 }
603
604 rate = divider_recalc_rate(hw, parent_rate, val, div->table,
605 div->flags, div->width);
606
607 return rate;
608 }
609
bm1880_clk_div_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)610 static int bm1880_clk_div_determine_rate(struct clk_hw *hw,
611 struct clk_rate_request *req)
612 {
613 struct bm1880_div_hw_clock *div_hw = to_bm1880_div_clk(hw);
614 struct bm1880_div_clock *div = &div_hw->div;
615 void __iomem *reg_addr = div_hw->base + div->reg;
616
617 if (div->flags & CLK_DIVIDER_READ_ONLY) {
618 u32 val;
619
620 val = readl(reg_addr) >> div->shift;
621 val &= clk_div_mask(div->width);
622
623 return divider_ro_determine_rate(hw, req, div->table,
624 div->width, div->flags, val);
625 }
626
627 return divider_determine_rate(hw, req, div->table, div->width, div->flags);
628 }
629
bm1880_clk_div_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)630 static int bm1880_clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
631 unsigned long parent_rate)
632 {
633 struct bm1880_div_hw_clock *div_hw = to_bm1880_div_clk(hw);
634 struct bm1880_div_clock *div = &div_hw->div;
635 void __iomem *reg_addr = div_hw->base + div->reg;
636 unsigned long flags = 0;
637 int value;
638 u32 val;
639
640 value = divider_get_val(rate, parent_rate, div->table,
641 div->width, div_hw->div.flags);
642 if (value < 0)
643 return value;
644
645 if (div_hw->lock)
646 spin_lock_irqsave(div_hw->lock, flags);
647 else
648 __acquire(div_hw->lock);
649
650 val = readl(reg_addr);
651 val &= ~(clk_div_mask(div->width) << div_hw->div.shift);
652 val |= (u32)value << div->shift;
653 writel(val, reg_addr);
654
655 if (div_hw->lock)
656 spin_unlock_irqrestore(div_hw->lock, flags);
657 else
658 __release(div_hw->lock);
659
660 return 0;
661 }
662
663 static const struct clk_ops bm1880_clk_div_ops = {
664 .recalc_rate = bm1880_clk_div_recalc_rate,
665 .determine_rate = bm1880_clk_div_determine_rate,
666 .set_rate = bm1880_clk_div_set_rate,
667 };
668
bm1880_clk_register_div(struct bm1880_div_hw_clock * div_clk,void __iomem * sys_base)669 static struct clk_hw *bm1880_clk_register_div(struct bm1880_div_hw_clock *div_clk,
670 void __iomem *sys_base)
671 {
672 struct clk_hw *hw;
673 int err;
674
675 div_clk->div.flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO;
676 div_clk->base = sys_base;
677 div_clk->lock = &bm1880_clk_lock;
678
679 hw = &div_clk->hw;
680 err = clk_hw_register(NULL, hw);
681 if (err)
682 return ERR_PTR(err);
683
684 return hw;
685 }
686
bm1880_clk_register_divs(struct bm1880_div_hw_clock * clks,int num_clks,struct bm1880_clock_data * data)687 static int bm1880_clk_register_divs(struct bm1880_div_hw_clock *clks,
688 int num_clks,
689 struct bm1880_clock_data *data)
690 {
691 struct clk_hw *hw;
692 void __iomem *sys_base = data->sys_base;
693 unsigned int i, id;
694
695 for (i = 0; i < num_clks; i++) {
696 struct bm1880_div_hw_clock *bm1880_clk = &clks[i];
697
698 hw = bm1880_clk_register_div(bm1880_clk, sys_base);
699 if (IS_ERR(hw)) {
700 pr_err("%s: failed to register clock %s\n",
701 __func__, bm1880_clk->div.name);
702 goto err_clk;
703 }
704
705 id = clks[i].div.id;
706 data->hw_data.hws[id] = hw;
707 }
708
709 return 0;
710
711 err_clk:
712 while (i--)
713 clk_hw_unregister(data->hw_data.hws[clks[i].div.id]);
714
715 return PTR_ERR(hw);
716 }
717
bm1880_clk_register_gate(const struct bm1880_gate_clock * clks,int num_clks,struct bm1880_clock_data * data)718 static int bm1880_clk_register_gate(const struct bm1880_gate_clock *clks,
719 int num_clks,
720 struct bm1880_clock_data *data)
721 {
722 struct clk_hw *hw;
723 void __iomem *sys_base = data->sys_base;
724 int i;
725
726 for (i = 0; i < num_clks; i++) {
727 hw = clk_hw_register_gate(NULL, clks[i].name,
728 clks[i].parent,
729 clks[i].flags,
730 sys_base + clks[i].gate_reg,
731 clks[i].gate_shift, 0,
732 &bm1880_clk_lock);
733 if (IS_ERR(hw)) {
734 pr_err("%s: failed to register clock %s\n",
735 __func__, clks[i].name);
736 goto err_clk;
737 }
738
739 data->hw_data.hws[clks[i].id] = hw;
740 }
741
742 return 0;
743
744 err_clk:
745 while (i--)
746 clk_hw_unregister_gate(data->hw_data.hws[clks[i].id]);
747
748 return PTR_ERR(hw);
749 }
750
bm1880_clk_register_composite(struct bm1880_composite_clock * clks,void __iomem * sys_base)751 static struct clk_hw *bm1880_clk_register_composite(struct bm1880_composite_clock *clks,
752 void __iomem *sys_base)
753 {
754 struct clk_hw *hw;
755 struct clk_mux *mux = NULL;
756 struct clk_gate *gate = NULL;
757 struct bm1880_div_hw_clock *div_hws = NULL;
758 struct clk_hw *mux_hw = NULL, *gate_hw = NULL, *div_hw = NULL;
759 const struct clk_ops *mux_ops = NULL, *gate_ops = NULL, *div_ops = NULL;
760 const char * const *parent_names;
761 const char *parent;
762 int num_parents;
763 int ret;
764
765 if (clks->mux_shift >= 0) {
766 mux = kzalloc_obj(*mux);
767 if (!mux)
768 return ERR_PTR(-ENOMEM);
769
770 mux->reg = sys_base + clks->mux_reg;
771 mux->mask = 1;
772 mux->shift = clks->mux_shift;
773 mux_hw = &mux->hw;
774 mux_ops = &clk_mux_ops;
775 mux->lock = &bm1880_clk_lock;
776
777 parent_names = clks->parents;
778 num_parents = clks->num_parents;
779 } else {
780 parent = clks->parent;
781 parent_names = &parent;
782 num_parents = 1;
783 }
784
785 if (clks->gate_shift >= 0) {
786 gate = kzalloc_obj(*gate);
787 if (!gate) {
788 ret = -ENOMEM;
789 goto err_out;
790 }
791
792 gate->reg = sys_base + clks->gate_reg;
793 gate->bit_idx = clks->gate_shift;
794 gate->lock = &bm1880_clk_lock;
795
796 gate_hw = &gate->hw;
797 gate_ops = &clk_gate_ops;
798 }
799
800 if (clks->div_shift >= 0) {
801 div_hws = kzalloc_obj(*div_hws);
802 if (!div_hws) {
803 ret = -ENOMEM;
804 goto err_out;
805 }
806
807 div_hws->base = sys_base;
808 div_hws->div.reg = clks->div_reg;
809 div_hws->div.shift = clks->div_shift;
810 div_hws->div.width = clks->div_width;
811 div_hws->div.table = clks->table;
812 div_hws->div.initval = clks->div_initval;
813 div_hws->lock = &bm1880_clk_lock;
814 div_hws->div.flags = CLK_DIVIDER_ONE_BASED |
815 CLK_DIVIDER_ALLOW_ZERO;
816
817 div_hw = &div_hws->hw;
818 div_ops = &bm1880_clk_div_ops;
819 }
820
821 hw = clk_hw_register_composite(NULL, clks->name, parent_names,
822 num_parents, mux_hw, mux_ops, div_hw,
823 div_ops, gate_hw, gate_ops,
824 clks->flags);
825
826 if (IS_ERR(hw)) {
827 ret = PTR_ERR(hw);
828 goto err_out;
829 }
830
831 return hw;
832
833 err_out:
834 kfree(div_hws);
835 kfree(gate);
836 kfree(mux);
837
838 return ERR_PTR(ret);
839 }
840
bm1880_clk_register_composites(struct bm1880_composite_clock * clks,int num_clks,struct bm1880_clock_data * data)841 static int bm1880_clk_register_composites(struct bm1880_composite_clock *clks,
842 int num_clks,
843 struct bm1880_clock_data *data)
844 {
845 struct clk_hw *hw;
846 void __iomem *sys_base = data->sys_base;
847 int i;
848
849 for (i = 0; i < num_clks; i++) {
850 struct bm1880_composite_clock *bm1880_clk = &clks[i];
851
852 hw = bm1880_clk_register_composite(bm1880_clk, sys_base);
853 if (IS_ERR(hw)) {
854 pr_err("%s: failed to register clock %s\n",
855 __func__, bm1880_clk->name);
856 goto err_clk;
857 }
858
859 data->hw_data.hws[clks[i].id] = hw;
860 }
861
862 return 0;
863
864 err_clk:
865 while (i--)
866 clk_hw_unregister_composite(data->hw_data.hws[clks[i].id]);
867
868 return PTR_ERR(hw);
869 }
870
bm1880_clk_probe(struct platform_device * pdev)871 static int bm1880_clk_probe(struct platform_device *pdev)
872 {
873 struct bm1880_clock_data *clk_data;
874 void __iomem *pll_base, *sys_base;
875 struct device *dev = &pdev->dev;
876 int num_clks, i;
877
878 pll_base = devm_platform_ioremap_resource(pdev, 0);
879 if (IS_ERR(pll_base))
880 return PTR_ERR(pll_base);
881
882 sys_base = devm_platform_ioremap_resource(pdev, 1);
883 if (IS_ERR(sys_base))
884 return PTR_ERR(sys_base);
885
886 num_clks = ARRAY_SIZE(bm1880_pll_clks) +
887 ARRAY_SIZE(bm1880_div_clks) +
888 ARRAY_SIZE(bm1880_mux_clks) +
889 ARRAY_SIZE(bm1880_composite_clks) +
890 ARRAY_SIZE(bm1880_gate_clks);
891
892 clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws,
893 num_clks), GFP_KERNEL);
894 if (!clk_data)
895 return -ENOMEM;
896
897 clk_data->pll_base = pll_base;
898 clk_data->sys_base = sys_base;
899
900 for (i = 0; i < num_clks; i++)
901 clk_data->hw_data.hws[i] = ERR_PTR(-ENOENT);
902
903 clk_data->hw_data.num = num_clks;
904
905 bm1880_clk_register_plls(bm1880_pll_clks,
906 ARRAY_SIZE(bm1880_pll_clks),
907 clk_data);
908
909 bm1880_clk_register_divs(bm1880_div_clks,
910 ARRAY_SIZE(bm1880_div_clks),
911 clk_data);
912
913 bm1880_clk_register_mux(bm1880_mux_clks,
914 ARRAY_SIZE(bm1880_mux_clks),
915 clk_data);
916
917 bm1880_clk_register_composites(bm1880_composite_clks,
918 ARRAY_SIZE(bm1880_composite_clks),
919 clk_data);
920
921 bm1880_clk_register_gate(bm1880_gate_clks,
922 ARRAY_SIZE(bm1880_gate_clks),
923 clk_data);
924
925 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
926 &clk_data->hw_data);
927 }
928
929 static const struct of_device_id bm1880_of_match[] = {
930 { .compatible = "bitmain,bm1880-clk", },
931 {}
932 };
933 MODULE_DEVICE_TABLE(of, bm1880_of_match);
934
935 static struct platform_driver bm1880_clk_driver = {
936 .driver = {
937 .name = "bm1880-clk",
938 .of_match_table = bm1880_of_match,
939 },
940 .probe = bm1880_clk_probe,
941 };
942 module_platform_driver(bm1880_clk_driver);
943
944 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
945 MODULE_DESCRIPTION("Clock driver for Bitmain BM1880 SoC");
946