1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013-2014 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. 7 */ 8 9 #include "adreno_gpu.h" 10 11 bool hang_debug = false; 12 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)"); 13 module_param_named(hang_debug, hang_debug, bool, 0600); 14 15 bool snapshot_debugbus = false; 16 MODULE_PARM_DESC(snapshot_debugbus, "Include debugbus sections in GPU devcoredump (if not fused off)"); 17 module_param_named(snapshot_debugbus, snapshot_debugbus, bool, 0600); 18 19 int enable_preemption = -1; 20 MODULE_PARM_DESC(enable_preemption, "Enable preemption (A7xx+ only) (1=on , 0=disable, -1=auto (default))"); 21 module_param(enable_preemption, int, 0600); 22 23 bool disable_acd; 24 MODULE_PARM_DESC(disable_acd, "Forcefully disable GPU ACD"); 25 module_param_unsafe(disable_acd, bool, 0400); 26 27 static bool skip_gpu; 28 MODULE_PARM_DESC(no_gpu, "Disable GPU driver register (0=enable GPU driver register (default), 1=skip GPU driver register"); 29 module_param(skip_gpu, bool, 0400); 30 31 extern const struct adreno_gpulist a2xx_gpulist; 32 extern const struct adreno_gpulist a3xx_gpulist; 33 extern const struct adreno_gpulist a4xx_gpulist; 34 extern const struct adreno_gpulist a5xx_gpulist; 35 extern const struct adreno_gpulist a6xx_gpulist; 36 extern const struct adreno_gpulist a7xx_gpulist; 37 extern const struct adreno_gpulist a8xx_gpulist; 38 39 static const struct adreno_gpulist *gpulists[] = { 40 &a2xx_gpulist, 41 &a3xx_gpulist, 42 &a4xx_gpulist, 43 &a5xx_gpulist, 44 &a6xx_gpulist, 45 &a7xx_gpulist, 46 &a8xx_gpulist, 47 }; 48 49 static const struct adreno_info *adreno_info(uint32_t chip_id) 50 { 51 /* identify gpu: */ 52 for (int i = 0; i < ARRAY_SIZE(gpulists); i++) { 53 for (int j = 0; j < gpulists[i]->gpus_count; j++) { 54 const struct adreno_info *info = &gpulists[i]->gpus[j]; 55 56 if (info->machine && !of_machine_is_compatible(info->machine)) 57 continue; 58 59 for (int k = 0; info->chip_ids[k]; k++) 60 if (info->chip_ids[k] == chip_id) 61 return info; 62 } 63 } 64 65 return NULL; 66 } 67 68 struct msm_gpu *adreno_load_gpu(struct drm_device *dev) 69 { 70 struct msm_drm_private *priv = dev->dev_private; 71 struct platform_device *pdev = priv->gpu_pdev; 72 struct msm_gpu *gpu = NULL; 73 struct adreno_gpu *adreno_gpu; 74 int ret; 75 76 if (pdev) 77 gpu = dev_to_gpu(&pdev->dev); 78 79 if (!gpu) { 80 dev_err_once(dev->dev, "no GPU device was found\n"); 81 return NULL; 82 } 83 84 adreno_gpu = to_adreno_gpu(gpu); 85 86 /* 87 * The number one reason for HW init to fail is if the firmware isn't 88 * loaded yet. Try that first and don't bother continuing on 89 * otherwise 90 */ 91 92 ret = adreno_load_fw(adreno_gpu); 93 if (ret) 94 return NULL; 95 96 if (gpu->funcs->ucode_load) { 97 ret = gpu->funcs->ucode_load(gpu); 98 if (ret) 99 return NULL; 100 } 101 102 /* 103 * Now that we have firmware loaded, and are ready to begin 104 * booting the gpu, go ahead and enable runpm: 105 */ 106 pm_runtime_enable(&pdev->dev); 107 108 ret = pm_runtime_get_sync(&pdev->dev); 109 if (ret < 0) { 110 pm_runtime_put_noidle(&pdev->dev); 111 DRM_DEV_ERROR(dev->dev, "Couldn't power up the GPU: %d\n", ret); 112 goto err_disable_rpm; 113 } 114 115 mutex_lock(&gpu->lock); 116 ret = msm_gpu_hw_init(gpu); 117 mutex_unlock(&gpu->lock); 118 if (ret) { 119 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret); 120 goto err_put_rpm; 121 } 122 123 pm_runtime_put_autosuspend(&pdev->dev); 124 125 #ifdef CONFIG_DEBUG_FS 126 if (gpu->funcs->debugfs_init) { 127 gpu->funcs->debugfs_init(gpu, dev->primary); 128 gpu->funcs->debugfs_init(gpu, dev->render); 129 } 130 #endif 131 132 return gpu; 133 134 err_put_rpm: 135 pm_runtime_put_sync_suspend(&pdev->dev); 136 err_disable_rpm: 137 pm_runtime_disable(&pdev->dev); 138 139 return NULL; 140 } 141 142 static int find_chipid(struct device_node *node, uint32_t *chipid) 143 { 144 const char *compat; 145 int ret; 146 147 /* first search the compat strings for qcom,adreno-XYZ.W: */ 148 ret = of_property_read_string_index(node, "compatible", 0, &compat); 149 if (ret == 0) { 150 unsigned int r, patch; 151 152 if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 || 153 sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) { 154 uint32_t core, major, minor; 155 156 core = r / 100; 157 r %= 100; 158 major = r / 10; 159 r %= 10; 160 minor = r; 161 162 *chipid = (core << 24) | 163 (major << 16) | 164 (minor << 8) | 165 patch; 166 167 return 0; 168 } 169 170 if (sscanf(compat, "qcom,adreno-%08x", chipid) == 1) 171 return 0; 172 } 173 174 /* and if that fails, fall back to legacy "qcom,chipid" property: */ 175 ret = of_property_read_u32(node, "qcom,chipid", chipid); 176 if (ret) { 177 DRM_ERROR("%pOF: could not parse qcom,chipid: %d\n", 178 node, ret); 179 return ret; 180 } 181 182 pr_warn("%pOF: Using legacy qcom,chipid binding!\n", node); 183 184 return 0; 185 } 186 187 bool adreno_has_gpu(struct device_node *node) 188 { 189 const struct adreno_info *info; 190 uint32_t chip_id; 191 int ret; 192 193 if (skip_gpu) 194 return false; 195 196 ret = find_chipid(node, &chip_id); 197 if (ret) 198 return false; 199 200 info = adreno_info(chip_id); 201 if (!info) { 202 pr_warn("%pOF: Unknown GPU revision: %"ADRENO_CHIPID_FMT"\n", 203 node, ADRENO_CHIPID_ARGS(chip_id)); 204 return false; 205 } 206 207 return true; 208 } 209 210 static int adreno_bind(struct device *dev, struct device *master, void *data) 211 { 212 static struct adreno_platform_config config = {}; 213 const struct adreno_info *info; 214 struct msm_drm_private *priv = dev_get_drvdata(master); 215 struct drm_device *drm = priv->dev; 216 struct msm_gpu *gpu; 217 int ret; 218 219 ret = find_chipid(dev->of_node, &config.chip_id); 220 /* We shouldn't have gotten this far if we can't parse the chip_id */ 221 if (WARN_ON(ret)) 222 return ret; 223 224 dev->platform_data = &config; 225 priv->gpu_pdev = to_platform_device(dev); 226 227 info = adreno_info(config.chip_id); 228 /* We shouldn't have gotten this far if we don't recognize the GPU: */ 229 if (WARN_ON(!info)) 230 return -ENXIO; 231 232 config.info = info; 233 234 DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.chip_id)); 235 236 priv->is_a2xx = info->family < ADRENO_3XX; 237 priv->has_cached_coherent = 238 !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT); 239 240 gpu = info->funcs->init(drm); 241 if (IS_ERR(gpu)) { 242 dev_warn(drm->dev, "failed to load adreno gpu\n"); 243 return PTR_ERR(gpu); 244 } 245 246 ret = dev_pm_opp_of_find_icc_paths(dev, NULL); 247 if (ret) 248 return ret; 249 250 return 0; 251 } 252 253 static int adreno_system_suspend(struct device *dev); 254 static void adreno_unbind(struct device *dev, struct device *master, 255 void *data) 256 { 257 struct msm_drm_private *priv = dev_get_drvdata(master); 258 struct msm_gpu *gpu = dev_to_gpu(dev); 259 260 if (pm_runtime_enabled(dev)) 261 WARN_ON_ONCE(adreno_system_suspend(dev)); 262 gpu->funcs->destroy(gpu); 263 264 priv->gpu_pdev = NULL; 265 } 266 267 static const struct component_ops a3xx_ops = { 268 .bind = adreno_bind, 269 .unbind = adreno_unbind, 270 }; 271 272 static int adreno_probe(struct platform_device *pdev) 273 { 274 if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon") || 275 msm_gpu_no_components()) 276 return msm_gpu_probe(pdev, &a3xx_ops); 277 278 return component_add(&pdev->dev, &a3xx_ops); 279 } 280 281 static void adreno_remove(struct platform_device *pdev) 282 { 283 struct msm_drm_private *priv = platform_get_drvdata(pdev); 284 285 if (priv->kms_init) 286 component_del(&pdev->dev, &a3xx_ops); 287 else 288 msm_gpu_remove(pdev, &a3xx_ops); 289 } 290 291 static void adreno_shutdown(struct platform_device *pdev) 292 { 293 WARN_ON_ONCE(adreno_system_suspend(&pdev->dev)); 294 } 295 296 static const struct of_device_id dt_match[] = { 297 { .compatible = "qcom,adreno" }, 298 { .compatible = "qcom,adreno-3xx" }, 299 /* for compatibility with imx5 gpu: */ 300 { .compatible = "amd,imageon" }, 301 /* for backwards compat w/ downstream kgsl DT files: */ 302 { .compatible = "qcom,kgsl-3d0" }, 303 {} 304 }; 305 MODULE_DEVICE_TABLE(of, dt_match); 306 307 static int adreno_runtime_resume(struct device *dev) 308 { 309 struct msm_gpu *gpu = dev_to_gpu(dev); 310 int ret = gpu->funcs->pm_resume(gpu); 311 if (!ret) 312 ret = msm_perfcntr_resume(gpu); 313 return ret; 314 } 315 316 static int adreno_runtime_suspend(struct device *dev) 317 { 318 struct msm_gpu *gpu = dev_to_gpu(dev); 319 320 /* 321 * We should be holding a runpm ref, which will prevent 322 * runtime suspend. In the system suspend path, we've 323 * already waited for active jobs to complete. 324 */ 325 WARN_ON_ONCE(gpu->active_submits); 326 327 msm_perfcntr_suspend(gpu); 328 329 return gpu->funcs->pm_suspend(gpu); 330 } 331 332 static void suspend_scheduler(struct msm_gpu *gpu) 333 { 334 int i; 335 336 /* 337 * Shut down the scheduler before we force suspend, so that 338 * suspend isn't racing with scheduler kthread feeding us 339 * more work. 340 * 341 * Note, we just want to park the thread, and let any jobs 342 * that are already on the hw queue complete normally, as 343 * opposed to the drm_sched_stop() path used for handling 344 * faulting/timed-out jobs. We can't really cancel any jobs 345 * already on the hw queue without racing with the GPU. 346 */ 347 for (i = 0; i < gpu->nr_rings; i++) { 348 struct drm_gpu_scheduler *sched = &gpu->rb[i]->sched; 349 350 drm_sched_wqueue_stop(sched); 351 } 352 } 353 354 static void resume_scheduler(struct msm_gpu *gpu) 355 { 356 int i; 357 358 for (i = 0; i < gpu->nr_rings; i++) { 359 struct drm_gpu_scheduler *sched = &gpu->rb[i]->sched; 360 361 drm_sched_wqueue_start(sched); 362 } 363 } 364 365 static int adreno_system_suspend(struct device *dev) 366 { 367 struct msm_gpu *gpu = dev_to_gpu(dev); 368 int remaining, ret; 369 370 if (!gpu) 371 return 0; 372 373 suspend_scheduler(gpu); 374 375 remaining = wait_event_timeout(gpu->retire_event, 376 gpu->active_submits == 0, 377 msecs_to_jiffies(1000)); 378 if (remaining == 0) { 379 dev_err(dev, "Timeout waiting for GPU to suspend\n"); 380 ret = -EBUSY; 381 goto out; 382 } 383 384 ret = pm_runtime_force_suspend(dev); 385 out: 386 if (ret) 387 resume_scheduler(gpu); 388 389 return ret; 390 } 391 392 static int adreno_system_resume(struct device *dev) 393 { 394 struct msm_gpu *gpu = dev_to_gpu(dev); 395 396 if (!gpu) 397 return 0; 398 399 resume_scheduler(gpu); 400 return pm_runtime_force_resume(dev); 401 } 402 403 static const struct dev_pm_ops adreno_pm_ops = { 404 SYSTEM_SLEEP_PM_OPS(adreno_system_suspend, adreno_system_resume) 405 RUNTIME_PM_OPS(adreno_runtime_suspend, adreno_runtime_resume, NULL) 406 }; 407 408 static struct platform_driver adreno_driver = { 409 .probe = adreno_probe, 410 .remove = adreno_remove, 411 .shutdown = adreno_shutdown, 412 .driver = { 413 .name = "adreno", 414 .of_match_table = dt_match, 415 .pm = &adreno_pm_ops, 416 }, 417 }; 418 419 void __init adreno_register(void) 420 { 421 if (skip_gpu) 422 return; 423 424 platform_driver_register(&adreno_driver); 425 } 426 427 void __exit adreno_unregister(void) 428 { 429 if (skip_gpu) 430 return; 431 432 platform_driver_unregister(&adreno_driver); 433 } 434